Chip performance dynamic trimming control method and system based on cave and reinforcement learning
By combining CAVE with reinforcement learning, a dynamic chip performance tuning method is developed, which solves the problem of low chip tuning efficiency, achieves a high-precision and high-efficiency tuning process, and improves chip performance consistency and automation.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- ANQING NORMAL UNIV
- Filing Date
- 2026-03-09
- Publication Date
- 2026-06-26
AI Technical Summary
Existing chip trimming technology is inefficient and struggles to handle nonlinear response relationships and multi-factor coupled control structures, resulting in low trimming efficiency, limited accuracy, and a lack of versatility and automation capabilities.
A dynamic chip performance tuning method based on CAVE and reinforcement learning is adopted. The performance deviation is measured by chip testing hardware, the tuning factor is generated by conditional variational autoencoder, and the tuning strategy is optimized by reinforcement learning to achieve closed-loop tuning.
Significantly improves tuning accuracy and efficiency, enhances robustness to dynamic environments, and improves chip performance consistency and production yield.
Smart Images
Figure CN122285594A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of integrated circuit testing technology, specifically to a method and system for dynamic chip performance tuning and control based on CAVE and reinforcement learning. Background Technology
[0002] With the widespread application of integrated circuits (ICs) in smart terminals, automotive electronics, and industrial control, the requirements for performance stability and manufacturing consistency are increasingly stringent. While the continuous evolution of advanced process nodes has significantly enhanced chip integration and functional complexity, it has also exacerbated sensitivity to process fluctuations. Even minor parameter deviations during manufacturing can lead to performance imbalances in critical analog modules (such as bandgap reference sources, current references, and gain amplifiers), thereby affecting the overall functional integrity and yield of the chip. To improve electrical performance consistency, chip trimming technology is widely adopted to fine-tune and compensate for sensitive parameters during post-processing testing, ensuring compliance with design specifications.
[0003] Existing tuning techniques mainly include laser tuning, fuse tuning, and EEPROM digital tuning, combined with traditional exhaustive search, lookup table, and binary search strategies to determine suitable control parameters. However, these methods generally rely on the following assumptions: ① there is a monotonic or approximately linear relationship between the control variables and performance indicators; ② the control variables have a low dimensionality, suitable for full-space traversal or strategy search. When faced with complex tuning tasks such as nonlinear response relationships and multi-factor coupled control structures, these methods are inefficient, have limited tuning accuracy, and lack good versatility and automation capabilities. The control structures, variable forms, and feedback paths vary significantly between different tuning tasks, making it difficult for existing tuning methods to cope with highly dynamic and complex tuning environments, resulting in low tuning efficiency. Summary of the Invention
[0004] The technical problem to be solved by this invention is how to solve the problem of low adjustment efficiency of existing chips.
[0005] This invention solves the above-mentioned technical problems through the following technical means: a chip performance dynamic tuning and control method based on CAVE and reinforcement learning, comprising:
[0006] S1. Measure the initial actual performance indicators of the chip under test using chip testing hardware, and calculate the performance deviation by combining it with the preset target performance indicators. S2. Input the performance deviation into the pre-trained Conditional Variational Autoencoder (CVAE) model, and generate a tuning factor from the CVAE model; S3. Convert the adjustment factor into a driving instruction and drive the adjustment execution hardware to perform adjustment operations on the chip under test. S4. Measure the actual performance indicators after adjustment using chip testing hardware, and calculate the new performance deviation. S5. Input the new performance deviation into the reinforcement learning model. The reinforcement learning model optimizes the adjustment strategy through reward value until the performance of the chip under test meets the preset tolerance requirement or reaches the preset maximum number of adjustments, thus completing the dynamic adjustment of chip performance.
[0007] This invention first collects the initial actual performance indicators of the chip under test through chip testing hardware and calculates the performance deviation. The performance deviation is then input into a pre-trained Conditional Variational Autoencoder (CVAE) model to generate a trimming factor, which is then converted into driving instructions to drive the trimming execution hardware to complete the trimming. Afterward, the actual performance indicators after trimming are measured again and a new performance deviation is calculated. This deviation is then input into a reinforcement learning model to iteratively optimize the trimming strategy with a reward value until the performance meets the target or the maximum number of trimming attempts is reached. Compared with the traditional single trimming method, this invention adopts a closed-loop trimming architecture that combines the rapid generation of initial trimming factors by the CVAE model with the online dynamic optimization of the trimming strategy by reinforcement learning. This ensures both the initial accuracy and generation efficiency of the trimming, and can adaptively correct subsequent trimming behavior based on real-time trimming results. This significantly improves the accuracy, efficiency, and stability of chip performance trimming, reduces the number of invalid trimming attempts, and achieves adaptive adaptation to different performance deviation scenarios, effectively improving chip performance consistency and production yield.
[0008] Furthermore, in S1, the performance deviation is the difference between the target performance index of the chip and the initial measured performance index, defined as follows: ,in, Due to performance deviation, The preset target performance indicators, These are the initial actual performance indicators; the performance indicators include at least one of the chip's reference voltage, current, and frequency.
[0009] Furthermore, the CVAE model construction in S2 addresses performance deviations. To the adjustment factor mapping function CVAE model building and generation model Introducing latent variables Then, where k is a hyperparameter of the model, the modeling of the generative model satisfies:
[0010] in, For encoder, For decoder, For the standard normal prior, Let KL divergence be the KL divergence. To adjust the variables, This is a performance deviation. The process of generating adjustment factors in the CVAE model includes two stages: the model training stage and the inference stage.
[0011] Furthermore, the model training phase specifically involves: adjusting variables... With performance deviation The concatenated data is input into the encoder, which outputs a latent variable. mean Sum of logarithmic variance Differentiable latent variable samples are obtained through reparameterization techniques. :
[0012] in, , For element-wise multiplication, It is the identity matrix; The encoder mapping relationship is Latent variables With performance deviation After concatenation, the data is input into the decoder to generate a reconstructed result with adjusted variables. The decoding mapping relationship is as follows: ; The loss function used in the training process is:
[0013] in, For adjustable weighting parameters, The reconstructed mean square error of the adjustment variable. This is the reconstruction result of the modulated variables output by the decoder.
[0014] Furthermore, the reasoning stage specifically includes: The initial measured performance index and target performance index of the chip under test are used to calculate the performance deviation. The performance deviation is then input into the pre-trained CVAE model, and the decoder derives the tuning factor. The derivation formula is as follows: .
[0015] Furthermore, the new performance deviation in S4 is expressed by the formula The calculation yielded that, For new performance deviations, These are the actual performance indicators after adjustment. The target performance index is preset; the reward value is expressed by the formula. Calculated.
[0016] Furthermore, the adjustment execution hardware is at least one of a digital adjustment mechanism, a laser adjustment mechanism, a fuse adjustment mechanism, and a memristor / memory type adjustment mechanism; the adjustment factor is a control parameter corresponding one-to-one with the adjustment execution hardware, specifically including: The digital adjustment code corresponding to the digital adjustment mechanism; The laser etching position coordinates and etching length parameters corresponding to the laser trimming mechanism; The fuse failure combination parameters corresponding to the fuse adjustment mechanism; Pulse control parameters corresponding to memristor / storage type tuning mechanisms.
[0017] This invention also provides a chip performance dynamic tuning control system based on CAVE and reinforcement learning, including: A chip under test (DUT) carrier module, comprising a DUT chip, a probe station, and a test fixture; The test module, which is an ATE (Automatic Test Equipment) controller, includes measurement instruments and a timing source. The test module is electrically connected to the chip-under-test (DUT) carrier module and is used to acquire the initial actual performance indicators of the DUT. and actual performance indicators after adjustment The collected performance metrics are then sent to the processing module. The adjustment execution module is connected to both the chip under test (DUT) carrier module and the processing module. It receives drive signals sent by the processing module, where the drive signals correspond to adjustment variables. Mapping adjustment factor Perform digital trimming, laser trimming, fuse trimming, or memristor / memory type trimming operations on the chip under test; The processing module is electrically connected to the testing module, the tuning and execution module, and the storage module. The processing module pre-stores pre-trained CVAE models and reinforcement learning models, and is used to receive performance parameters sent by the testing module and to handle performance deviations. , The calculation generates adjustment factors through CVAE model inference. The reinforcement learning model updates the adjustment strategy based on the reward value and generates a corresponding driving signal to be sent to the adjustment execution module. Storage module, the storage module being used to store target performance parameters The system includes preset tolerance, preset maximum number of adjustments, CVAE model parameters, reinforcement learning model parameters, adjustment data, adjustment logs, and model version information; the adjustment data includes adjustment variables. , The corresponding performance parameters of the chip under test , and performance deviation , .
[0018] The present invention also provides a processing device, including at least one processor and at least one memory communicatively connected to the processor, wherein: the memory stores program instructions executable by the processor, and the processor can execute the above-described method steps by calling the program instructions.
[0019] The present invention also provides a computer-readable storage medium storing computer instructions that cause the computer to perform the above-described method steps.
[0020] The advantages of this invention are: This invention achieves performance deviation-driven dynamic feedback tuning by using performance deviation as a conditional variational autoencoder (CVAE) to generate tuning factors and introducing reinforcement learning (RL) to dynamically optimize the tuning strategy based on real-time performance feedback. This invention effectively models the complex nonlinear mapping between tuning variables and performance indicators, automatically adjusting the tuning operation through multi-round iterative feedback, significantly improving tuning accuracy and efficiency. Simultaneously, the reinforcement learning reward mechanism ensures adaptive optimization of the tuning process, enhancing robustness to dynamic environments and performance deviations, thereby reducing manual intervention and improving the automation and intelligence level of chip tuning. Attached Figure Description
[0021] Figure 1 This is a flowchart of the chip performance dynamic tuning control method based on CAVE and reinforcement learning according to Embodiment 1 of the present invention; Figure 2 This is a flowchart of the CVAE model inference stage in Embodiment 1 of the present invention; Figure 3 The figure shows the experimental results of the method and the dichotomy method of the present invention in Embodiment 1 of the present invention. Detailed Implementation
[0022] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below in conjunction with the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0023] Example 1 like Figure 1 As shown, the chip performance dynamic tuning and control method based on CAVE and reinforcement learning includes: S1. Measure the initial actual performance indicators of the chip under test using chip testing hardware, and calculate the performance deviation by combining it with the preset target performance indicators.
[0024] Specifically, the performance deviation calculation determines the direction and magnitude of the subsequent adjustment strategy generation.
[0025] Obtaining the initial actual performance indicators of a chip: Measuring the initial actual performance indicators of a certain parameter of the chip under test using chip testing hardware. Such as voltage, current, frequency and other related indicators. The preset target performance index is usually determined based on design requirements. Performance deviation is calculated using the following formula. This deviation value will determine the adjustment of subsequent tuning parameters:
[0026] in, Performance deviation represents the difference between the actual value of a parameter of the chip under test and a preset target value. This performance deviation is calculated... This provides a basis for subsequent revision decisions and clarifies the direction and extent of revisions.
[0027] S2. Input the performance deviation into the pre-trained conditional variational autoencoder (CVAE) model to generate a tuning factor.
[0028] Specifically, in recent years, deep learning methods have been widely applied in fields such as analog circuit modeling and performance prediction due to their powerful end-to-end modeling and nonlinear mapping capabilities. Among them, Conditional Variational Autoencoders (CVAEs), as a typical probabilistic generative model, not only have good training characteristics but also can capture complex dependencies between inputs and outputs by introducing conditional variables. Compared with traditional methods such as Multilayer Perceptrons (MLPs), Gaussian Processes (GPs), or Generative Adversarial Networks (GANs), CVAEs have advantages in modeling stability, expressive power, and conditional control capabilities, making them particularly suitable for modeling complex nonlinear mapping processes of "tuning variables-performance indicators." Although CVAEs are powerful nonlinear modeling tools, their core is static; once training is complete, the model parameters are fixed and cannot automatically adapt to new inputs or environmental changes. To address the feedback optimization problem in dynamic tuning processes, this method introduces reinforcement learning (RL) techniques on top of the original CVAE, optimizing the tuning strategy through real-time feedback, thereby effectively dealing with performance deviations and complex dynamic environments during the tuning process.
[0029] This method combines reinforcement learning (RL) with conditional variational autoencoder (CVAE) to implement a performance bias-driven dynamic feedback tuning approach. The CVAE learns the relationship between tuning factors and performance bias, such as tuning codes, laser paths, etching directions, and lengths. The RL dynamically selects the optimal tuning strategy based on real-time performance feedback. Reinforcement learning optimizes the tuning strategy through a reward mechanism, gradually approaching the target performance.
[0030] Based on calculated performance deviation An adaptive tuning factor is generated using a conditional variational autoencoder (CVAE) model. These factors can dynamically adjust the electrical or physical properties of the chip based on performance deviations to ensure that performance targets are met.
[0031] This method aims to learn a performance deviation. To the adjustment factor mapping function The reverse derivation to achieve the performance target is as follows:
[0032] Make the application Afterwards, the chip performance can approach the target specifications. That is, minimize .
[0033] CVAE Inverse Modeling Framework To achieve the aforementioned goal of inverse modeling from performance deviation to adjustment factor, this method introduces a conditional variational autoencoder (CVAE) to construct a generative model. Introducing latent variables The post-modeling is as follows:
[0034] in, For the encoder, the output latent variable's Gaussian distribution parameters, including mean and variance, are... For the decoder, based on the sampled With performance deviation Generate repair and adjustment. For the standard normal prior, This represents the KL divergence, used to constrain the similarity between the posterior and prior.
[0035] (1) Model training phase Adjust variables With performance deviation The concatenated data is input into the encoder, which outputs a latent variable. mean Sum of logarithmic variance Differentiable latent variable samples are obtained through reparameterization techniques. :
[0036] in, , For element-wise multiplication, It is an identity matrix.
[0037] The encoder mapping relationship is Latent variables With performance deviation After concatenation, the data is input into the decoder to generate a reconstructed result with adjusted variables. The decoding mapping relationship is as follows: .
[0038] The training objective is to minimize the sum of the reconstruction error and the KL divergence.
[0039] in, For adjustable weighting parameters, The mean squared error of the reconstruction of the trimmed variables is used to measure the reconstruction result of the trimmed variables generated by the decoder. With real adjustment variables The difference between them is the Mean Squared Error (MSE).
[0040] (2) Reasoning stage In the reasoning stage, such as Figure 2 As shown, the initial measured performance index and target performance index of the chip under test are used to calculate the performance deviation. The performance bias is input into the pre-trained CVAE model, and the decoder derives the tuning factor. :
[0041] Unlike traditional multi-round trial-and-error adjustment methods, this method, given the initial actual performance index and target performance index of the chip, inputs the performance deviation and quickly outputs a set of feasible adjustment factors. This method achieves precise compensation of performance indicators without manual intervention or multiple rounds of trial and error. It has broad applicability in tuning structures such as laser etching, resistance adjustment, and digital code configuration.
[0042] S3. Convert the adjustment factor into a driving instruction and drive the adjustment execution hardware to perform adjustment operations on the chip under test.
[0043] Specifically, adjustment operations are performed based on the adjustment factors generated by CVAE, and the performance after adjustment is measured using a testing system. Performance measurement feedback is used to determine whether the adjustment results meet the target requirements. After performing the adjustment operation, the actual performance of the chip is measured as the basis for further feedback and optimization.
[0044] Perform trimming operations: Trimming the chip based on the trimming factor generated by CVAE. Specific operations may include: modifying the chip's trimming code; adjusting the laser etching path and length; adjusting the etching direction, etc.
[0045] S4. Measure the actual performance indicators after adjustment using chip testing hardware, and calculate the new performance deviation.
[0046] Specifically, performance measurement: After tuning, the actual performance indicators of the chip under test are remeasured using chip testing hardware. For example, voltage, current, frequency, etc.
[0047] By adjusting the chip's performance and measuring the results after adjustment, data is provided for the next step of performance deviation calculation and feedback.
[0048] S5. Input the new performance deviation into the reinforcement learning model. The reinforcement learning model optimizes the adjustment strategy through the reward value until the performance of the chip under test meets the preset tolerance requirements or reaches the preset maximum number of adjustments, thus completing the dynamic adjustment of chip performance.
[0049] Specifically, reinforcement learning (RL) is used to evaluate the tuning results and optimize the tuning strategy based on real-time performance feedback. The reinforcement learning model optimizes the selection of tuning factors based on the performance deviation after tuning, gradually approaching the target performance. The tuning strategy is optimized through the reward mechanism of reinforcement learning, dynamically adjusting the tuning factors to ensure that the tuning process always moves towards the target performance.
[0050] Based on the adjusted performance values Calculate the new performance deviation:
[0051] Calculate the reward value based on the new performance deviation. The calculation formula is as follows:
[0052] A higher reward indicates a better tuning effect and a smaller performance deviation.
[0053] Update reinforcement learning strategy: The reinforcement learning model adjusts the selection strategy of adjustment factors based on the reward signal to optimize the next round of adjustment process.
[0054] Multi-round tuning and iterative optimization: The tuning process is continuously optimized through multiple rounds of tuning. After each round, the tuning strategy is adjusted based on feedback from performance deviations until the target performance requirements are met or the maximum number of tuning rounds is reached. Through multiple rounds of tuning, performance deviations are gradually reduced, ensuring that the tuning process is efficient and accurate.
[0055] Check performance deviations: If the performance deviations after adjustment are... Meet the target requirements (i.e.) If the performance deviation still does not meet the target requirements, the adjustment factor is optimized through reinforcement learning, and the process enters the next round of adjustment.
[0056] Set maximum number of adjustments: To prevent endless adjustments, set a maximum number of adjustments. If the requirements are not met after reaching the maximum number of adjustments, the adjustment will stop.
[0057] For different types of tuning structures, this set of control variables can be specifically mapped to the following operation instructions: For digital tuning structures (such as EEPROM configurable resistor arrays): the tuning factor of the output. The corresponding trimming code is loaded into the target chip via a digital interface, and the corresponding resistor, capacitor values or bias circuits are automatically configured.
[0058] For laser-adjustable structures: the adjustment factor can correspond to the specific etching path and position coordinates ( , Laser length or direction, etc., are used to precisely etch thin film resistors through a laser control system.
[0059] For fuse trimming structures: the trimming factor can be mapped to the fusing combination of a specific fuse, and the fusing operation can be performed directly.
[0060] For memory-type regulation structures (such as memristors or non-volatile devices): the tuning factor can be used to generate regulation pulses or control signals to update the device's conductance state.
[0061] To verify the effectiveness of the proposed chip performance dynamic trimming control method based on CAVE and reinforcement learning in practical applications, it is compared with the widely used traditional binary search method to demonstrate that the proposed method has significant advantages in reducing the number of trimming iterations and improving trimming efficiency.
[0062] The experimental data came from 1000 sets of actual tuning data from a certain model of chip, including tuning codes and corresponding frequency parameters. The first 800 sets of data were used as the training set to construct the CVAE-RL tuning model, and the last 200 sets of data were used as the test set to verify the performance of the proposed method. The target frequency was set to 62.5kHz. The experimental results are as follows: Figure 3 As shown in Table 1, the experimental data indicates that the traditional binary search method requires an average of 5.34 iterations, while this method requires only 3.63 iterations. Since each code adjustment requires actual testing to verify its effectiveness, the efficiency improvement reaches 59.73%.
[0063] Table 1 Partial Experimental Results
[0064] Example 2 Based on Embodiment 1, Embodiment 2 of the present invention also provides a chip performance dynamic tuning control system based on CAVE and reinforcement learning, including: The chip under test (DUT) carrier module includes the DUT, a probe station, and a test fixture.
[0065] The test module is an ATE controller, including measurement instruments and timing sources. The test module is electrically connected to the chip under test (DUT) carrier module and is used to acquire the initial actual performance indicators of the DUT. and actual performance indicators after adjustment The collected performance metrics are then sent to the processing module.
[0066] The adjustment execution module is connected to both the chip under test (DUT) carrier module and the processing module. It receives drive signals sent by the processing module, and the drive signals correspond to adjustment variables. Mapping adjustment factor It performs digital trimming, laser trimming, fuse trimming, or memristor / memory type trimming operations on the chip under test.
[0067] The processing module is electrically connected to the testing module, the tuning and execution module, and the storage module. The processing module pre-stores pre-trained CVAE models and reinforcement learning models, and is used to receive performance parameters sent by the testing module and to handle performance deviations. , The calculation generates adjustment factors through CVAE model inference. The reinforcement learning model updates the adjustment strategy based on the reward value and generates a corresponding driving signal to be sent to the adjustment execution module.
[0068] Specifically, performance deviation is the difference between the chip's target performance index and the initial measured performance index, defined as follows: ,in, Due to performance deviation, The preset target performance indicators, These are the initial actual performance indicators; performance indicators include at least one of the chip's reference voltage, current, and frequency.
[0069] CVAE model construction from performance deviation To the adjustment factor mapping function CVAE model building and generation model Introducing latent variables Then, where k is the hyperparameter of the model, the modeling of the generated model satisfies:
[0070] in, For encoder, For decoder, For the standard normal prior, Let KL divergence be the KL divergence. To adjust the control variable vector, This is a performance deviation. The process of generating tuning factors in a CVAE model includes two stages: model training and inference.
[0071] The model training phase specifically involves adjusting variables. With performance deviation The concatenated data is input into the encoder, which outputs a latent variable. mean Sum of logarithmic variance Differentiable latent variable samples are obtained through reparameterization techniques. :
[0072] in, , For element-wise multiplication, It is an identity matrix.
[0073] The encoder mapping relationship is Latent variables With performance deviation After concatenation, the data is input into the decoder to generate a reconstructed result with adjusted variables. The decoding mapping relationship is as follows: .
[0074] The loss function used in the training process is:
[0075] in, For adjustable weighting parameters, The reconstructed mean square error of the adjustment variable. This is the reconstruction result of the modulated variables output by the decoder.
[0076] The reasoning stage specifically includes: The initial measured performance index and target performance index of the chip under test are used to calculate the performance deviation. The performance deviation is then input into the pre-trained CVAE model, and the decoder derives the tuning factor. The derivation formula is as follows: .
[0077] New performance deviations are expressed by the formula The calculation yielded that, For new performance deviations, These are the actual performance indicators after adjustment. The preset target performance indicators; the reward value is calculated using the formula. Calculated.
[0078] Storage module, used to store target performance parameters The system includes preset tolerance, preset maximum number of adjustments, CVAE model parameters, reinforcement learning model parameters, adjustment data, adjustment logs, and model version information; the adjustment data includes adjustment variables. , The corresponding performance parameters of the chip under test , and performance deviation , .
[0079] Example 3 Based on Embodiment 1, Embodiment 3 of the present invention also provides a processing device, including at least one processor and at least one memory communicatively connected to the processor, wherein: the memory stores program instructions executable by the processor, and the processor can execute the method steps of Embodiment 1 by calling the program instructions.
[0080] Example 4 Based on Embodiment 1, Embodiment 4 of the present invention also provides a computer-readable storage medium storing computer instructions that cause the computer to perform the steps of the method described in Embodiment 1.
[0081] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims
1. A chip performance dynamic tuning and control method based on CAVE and reinforcement learning, characterized in that, include: S1. Measure the initial actual performance indicators of the chip under test using chip testing hardware, and calculate the performance deviation by combining it with the preset target performance indicators. S2. Input the performance deviation into the pre-trained Conditional Variational Autoencoder (CVAE) model, and generate a tuning factor from the CVAE model. S3. Convert the adjustment factor into a driving instruction and drive the adjustment execution hardware to perform adjustment operations on the chip under test. S4. Measure the actual performance indicators after adjustment using chip testing hardware, and calculate the new performance deviation. S5. Input the new performance deviation into the reinforcement learning model. The reinforcement learning model optimizes the adjustment strategy through reward value until the performance of the chip under test meets the preset tolerance requirement or reaches the preset maximum number of adjustments, thus completing the dynamic adjustment of chip performance.
2. The chip performance dynamic tuning and control method based on CAVE and reinforcement learning according to claim 1, characterized in that, In S1, the performance deviation is the difference between the chip's target performance index and the initial measured performance index, defined as follows: ,in, Due to performance deviation, The preset target performance indicators, These are the initial actual performance indicators; the performance indicators include at least one of the chip's reference voltage, current, and frequency.
3. The chip performance dynamic tuning and control method based on CAVE and reinforcement learning according to claim 1, characterized in that, The CVAE model construction in S2 is based on performance deviations. To the adjustment factor mapping function ; CVAE model building and generation model Introducing latent variables Then, where k is a hyperparameter of the model, the modeling of the generative model satisfies: in, For encoder, For decoder, For the standard normal prior, Let KL divergence be the KL divergence. To adjust the variables, This is a performance deviation. The process of generating adjustment factors in the CVAE model includes two stages: the model training stage and the inference stage.
4. The chip performance dynamic tuning and control method based on CAVE and reinforcement learning according to claim 3, characterized in that, The model training phase specifically involves: adjusting variables... With performance deviation The concatenated data is input into the encoder, which outputs a latent variable. mean Sum of logarithmic variance Differentiable latent variable samples are obtained through reparameterization techniques. : in, , For element-wise multiplication, It is the identity matrix; The encoder mapping relationship is Latent variables With performance deviation After concatenation, the data is input into the decoder to generate a reconstructed result with adjusted variables. The decoding mapping relationship is as follows: ; The loss function used in the training process is: in, For adjustable weighting parameters, The reconstructed mean square error of the adjustment variable. This is the reconstruction result of the modulated variables output by the decoder.
5. The chip performance dynamic tuning and control method based on CAVE and reinforcement learning according to claim 3, characterized in that, The reasoning stage specifically includes: The initial measured performance index and target performance index of the chip under test are used to calculate the performance deviation. The performance deviation is then input into the pre-trained CVAE model, and the decoder derives the tuning factor. The derivation formula is as follows: .
6. The chip performance dynamic tuning and control method based on CAVE and reinforcement learning according to claim 1, characterized in that, The new performance deviation in S4 is expressed by the formula The calculation yielded that, For new performance deviations, These are the actual performance indicators after adjustment. The target performance index is preset; the reward value is expressed by the formula. Calculated.
7. The chip performance dynamic tuning and control method based on CAVE and reinforcement learning according to claim 1, characterized in that, The tuning execution hardware is at least one of a digital tuning mechanism, a laser tuning mechanism, a fuse tuning mechanism, and a memristor / memory type tuning mechanism; the tuning factor is a control parameter corresponding one-to-one with the tuning execution hardware, specifically including: The digital adjustment code corresponding to the digital adjustment mechanism; The laser etching position coordinates and etching length parameters corresponding to the laser trimming mechanism; The fuse failure combination parameters corresponding to the fuse adjustment mechanism; Pulse control parameters corresponding to memristor / storage type tuning mechanisms.
8. A chip performance dynamic adjustment control system based on CAVE and reinforcement learning, characterized in that, include: A chip under test (DUT) carrier module, comprising a DUT chip, a probe station, and a test fixture; The test module, which is an ATE controller, includes measurement instruments and a timing source. The test module is electrically connected to the chip-under-test (DUT) carrier module and is used to acquire the initial actual performance indicators of the DUT. and actual performance indicators after adjustment The collected performance metrics are then sent to the processing module. The adjustment execution module is connected to both the chip under test (DUT) carrier module and the processing module. It receives drive signals sent by the processing module, where the drive signals correspond to adjustment variables. Mapping adjustment factor Perform digital trimming, laser trimming, fuse trimming, or memristor / memory type trimming operations on the chip under test; The processing module is electrically connected to the testing module, the tuning and execution module, and the storage module. The processing module pre-stores pre-trained CVAE models and reinforcement learning models, and is used to receive performance parameters sent by the testing module and to handle performance deviations. , The calculation generates adjustment factors through CVAE model inference. The reinforcement learning model updates the adjustment strategy based on the reward value and generates a corresponding driving signal to be sent to the adjustment execution module. Storage module, the storage module being used to store target performance parameters The system includes preset tolerance, preset maximum number of adjustments, CVAE model parameters, reinforcement learning model parameters, adjustment data, adjustment logs, and model version information; the adjustment data includes adjustment variables. , The corresponding performance parameters of the chip under test , and performance deviation , .
9. A processing device, characterized in that, The method includes at least one processor and at least one memory communicatively connected to the processor, wherein the memory stores program instructions executable by the processor, and the processor can execute the method as described in any one of claims 1 to 7 by invoking the program instructions.
10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions that cause the computer to perform the method as described in any one of claims 1 to 7.