A dead time control circuit, PCB board and controller

Abstract

This invention discloses a dead-time control circuit, PCB board, and controller, including a low-side dead-time setting unit, a high-side dead-time setting unit, a valley detection unit, and a trigger switch. The output terminals of the low-side and high-side dead-time setting units are respectively connected to the input terminal of the valley detection unit, and the output terminal of the valley detection unit is connected to the input terminal of the trigger switch. The low-side dead-time setting unit is used to delay the external low-side input signal; the high-side dead-time setting unit is used to delay the external high-side input signal; the valley detection unit is used to determine the lowest voltage moment of the switching node based on the output signals of the low-side and high-side dead-time setting units, and sends a control signal to the trigger switch based on the lowest voltage moment. By introducing the valley detection mechanism, the dead-time control is transformed from static preset to dynamic sensing and response, which is beneficial for optimizing switching losses.

Description

Technical Field

[0001] This invention relates to the field of dead-time control circuit technology, and particularly to a dead-time control circuit, PCB board and controller. Background Technology

[0002] In a half-bridge or full-bridge circuit, two switching transistors (typically an NMOS and a PMOS, or two NMOS transistors) are connected in series. When one is on, the other is off. Dead time refers to the short delay inserted between the drive signals controlling these two switching transistors. Its purpose is to ensure that one switching transistor is completely off before the other begins to conduct, thus preventing a short circuit caused by both transistors conducting simultaneously. A short circuit would generate a huge current spike and damage the device.

[0003] In existing technologies, the traditional method uses a fixed dead time, that is, the dead time is set to a certain fixed value during the HVIC design phase. Usually, it is based on the worst-case scenario, such as the environmental conditions of the highest junction temperature and the maximum load current, and a sufficiently long dead time is set. However, under most non-worst-case operating conditions, this fixed time is too long, which will lead to an increase in the conduction time of the switching transistor, thereby generating additional conduction losses and reverse recovery losses, and reducing system efficiency.

[0004] It is evident that existing technologies still need improvement and enhancement. Summary of the Invention

[0005] In view of the shortcomings of the prior art, the purpose of the present invention is to provide a dead time control circuit, which uses a valley detection unit to monitor the voltage of the switching node in real time. When it is determined that one switching transistor is completely turned off and its body diode has completed freewheeling, another switching transistor is turned on to achieve the effect of circuit self-adaptation and realize dynamic and flexible adjustment.

[0006] To achieve the above objectives, the present invention adopts the following technical solution: A dead-time control circuit includes a low-side dead-time setting unit, a high-side dead-time setting unit, a valley detection unit, and a trigger switch. The output terminals of the low-side dead-time setting unit and the high-side dead-time setting unit are respectively connected to the input terminal of the valley detection unit, and the output terminal of the valley detection unit is connected to the input terminal of the trigger switch. The low-side dead-time setting unit is used to delay external low-side input signals; the high-side dead-time setting unit is used to delay external high-side input signals; the valley detection unit is used to determine the lowest voltage moment of the switching node based on the output signals of the low-side dead-time setting unit and the high-side dead-time setting unit, and sends a control signal to the trigger switch based on the lowest voltage moment.

[0007] In the dead-time control circuit, the low-side dead-time setting unit includes a first level conversion unit, a first delay unit, and a first drive output unit. The input terminal of the first level conversion unit is connected to an external low-side input signal terminal, and the output terminal of the first level conversion unit is connected to the input terminal of the first delay unit. The input terminal of the first drive output unit is connected to the output terminal of the first delay unit and an external high-side input signal terminal, and the output terminal of the first drive output unit is connected to the input terminal of the valley detection unit. The first level conversion unit is used to shape the external low-side input signal; the first delay unit is used to delay the low-side shaped signal; and the first drive output unit is used to amplify the external high-side input signal based on the low-side delayed signal.

[0008] In the aforementioned dead-time control circuit, the first level conversion section includes a first field-effect transistor M1 and a second field-effect transistor M2; the first delay section includes a first resistor R1, a first capacitor C1, a third field-effect transistor M3, a fourth field-effect transistor M4, a fifth field-effect transistor M5, and a sixth field-effect transistor M6; the gates of the first field-effect transistor M1 and the second field-effect transistor M2 are connected to an external low-side input signal terminal, the sources of the first field-effect transistor M1, the third field-effect transistor M3, and the fifth field-effect transistor M5 are connected to an external power supply terminal, and the sources of the second field-effect transistor M2 and the sixth field-effect transistor M6 are grounded. The drain of field-effect transistor M1 is connected to one end of the first resistor R1, one end of the first capacitor C1, the gate of the third field-effect transistor M3, and the gate of the fourth field-effect transistor M4. The drain of the second field-effect transistor M2 is connected to the other end of the first resistor R1. The other end of the first capacitor C1 is connected to the source of the fourth field-effect transistor M4. The drains of the third field-effect transistor M3 and the fourth field-effect transistor M4 are connected to the drains of the fifth field-effect transistor M5 and the sixth field-effect transistor M6. The drains of the fifth field-effect transistor M5 and the sixth field-effect transistor M6 are connected to the input terminal of the first drive output section.

[0009] In the dead-time control circuit, the first drive output section includes a seventh field-effect transistor (FET) M7, an eighth field-effect transistor (FET) M8, a ninth field-effect transistor (FET) M9, a tenth field-effect transistor (FET) M10, an eleventh field-effect transistor (FET) M11, a twelfth field-effect transistor (FET) M12, and a thirteenth field-effect transistor (FET) M13. The gates of the seventh and tenth FETs are connected to the drains of the fifth and sixth FETs, respectively. The source of the seventh FET is connected to an external power supply terminal, and the drain of the seventh FET is connected to the source of the eighth FET M8. The gates of the eighth and eleventh FETs are connected to an external enable control terminal. The drain of the eighth field-effect transistor M8 is connected to the source of the ninth field-effect transistor M9. The gates of the ninth field-effect transistor M9 and the twelfth field-effect transistor M12 are connected to the external high-side input signal terminal. The drain of the ninth field-effect transistor M9 is connected to the drains of the tenth field-effect transistor M10, the eleventh field-effect transistor M11, and the twelfth field-effect transistor M12. The connection node of the drains of the ninth field-effect transistor M9, the tenth field-effect transistor M10, the eleventh field-effect transistor M11, and the twelfth field-effect transistor M12 is connected to the input terminal of the valley detection unit. The source of the twelfth field-effect transistor M12 is connected to the source of the tenth field-effect transistor M10 and the eleventh field-effect transistor M11.

[0010] In the dead-time control circuit, the high-side dead-time setting unit includes a second level conversion section, a second delay section, and a second drive output section. The input terminal of the second level conversion section is connected to an external high-side input signal terminal, and the output terminal of the second level conversion section is connected to the input terminal of the second delay section. The input terminal of the second drive output section is connected to the output terminal of the second delay section and an external low-side input signal terminal, and the output terminal of the second drive output section is connected to the input terminal of the valley detection unit. The second level conversion section is used to shape the external high-side input signal; the second delay section is used to delay the high-side shaped signal; and the second drive output section is used to amplify the external low-side input signal based on the high-side delayed signal.

[0011] In the dead-time control circuit, the second level conversion section includes a thirteenth field-effect transistor M13 and a fourteenth field-effect transistor M14; the second delay section includes a second resistor R2, a second capacitor C2, a fifteenth field-effect transistor M15, a sixteenth field-effect transistor M16, a seventeenth field-effect transistor M17, and an eighteenth field-effect transistor M18; the gates of the thirteenth field-effect transistor M13 and the fourteenth field-effect transistor M14 are connected to the external high-side input signal terminal, the sources of the thirteenth field-effect transistor M13, the fifteenth field-effect transistor M15, and the seventeenth field-effect transistor M17 are connected to the external power supply terminal, and the sources of the fourteenth field-effect transistor M14 and the eighteenth field-effect transistor M18 are grounded. The drain of the thirteenth field-effect transistor M13 is connected to one end of the second resistor R2, one end of the second capacitor C2, the gate of the fifteenth field-effect transistor M15, and the gate of the sixteenth field-effect transistor M16. The drain of the fourteenth field-effect transistor M14 is connected to the other end of the second resistor R2. The other end of the second capacitor C2 is connected to the source of the sixteenth field-effect transistor M16. The drains of the fifteenth and sixteenth field-effect transistors M15 and M16 are connected to the drains of the seventeenth and eighteenth field-effect transistors M17 and M18. The drains of the seventeenth and eighteenth field-effect transistors M17 and M18 are connected to the input terminal of the second drive output section.

[0012] In the dead-time control circuit, the second drive output section includes a nineteenth field-effect transistor M19, a twentieth field-effect transistor M20, a twenty-first field-effect transistor M21, a twenty-second field-effect transistor M22, a twenty-third field-effect transistor M23, and a twenty-fourth field-effect transistor M24. The gates of the nineteenth field-effect transistor M19 and the twenty-second field-effect transistor M22 are connected to the drains of the seventeenth field-effect transistor M17 and the eighteenth field-effect transistor M18. The source of the nineteenth field-effect transistor M19 is connected to an external power supply terminal. The drain of the nineteenth field-effect transistor M19 is connected to the source of the twentieth field-effect transistor M20. The gates of the twentieth field-effect transistor M20 and the twenty-third field-effect transistor M23 are connected to an external low-side input signal terminal. The drain of field-effect transistor M20 is connected to the source of the 21st field-effect transistor M21. The gates of the 21st field-effect transistor M21 and the 24th field-effect transistor M24 are connected to an external enable control terminal. The drain of the 21st field-effect transistor M21 is connected to the drains of the 22nd, 23rd, and 24th field-effect transistors M22 and M23 respectively. The connection node of the drains of the 21st, 22nd, 23rd, and 24th field-effect transistors M24 is connected to the input terminal of the valley detection unit. The source of the 24th field-effect transistor M24 is connected to the sources of the 22nd and 23rd field-effect transistors M22 and M23 respectively.

[0013] In the dead time control circuit, the valley detection unit includes an XOR gate and a D flip-flop. The two inputs of the XOR gate are connected to the outputs of the high-side dead time setting unit and the low-side dead time setting unit, respectively. The output of the XOR gate is connected to the D port of the D flip-flop, and the Q port of the D flip-flop is connected to the enable terminal of the trigger switch.

[0014] This application also provides a PCB board printed with the dead time control circuit described above.

[0015] This application also provides a controller that uses the dead-time control circuit described above for operation control.

[0016] Beneficial effects: This invention provides a dead-time control circuit that, by introducing a valley detection mechanism, transforms dead-time control from static preset to dynamic sensing and response. While ensuring the safe operation of the bridge arm and avoiding shoot-through risks, it allows for more precise control of the dead-time window, which helps optimize switching losses and thus improves the efficiency of the power conversion circuit to a certain extent. Attached Figure Description Figure 1A circuit block diagram of the dead time control circuit provided by the present invention; Figure 2 The circuit structure diagram of the low-side dead time setting unit in the dead time control circuit provided by the present invention; Figure 3 The circuit structure diagram of the high-side dead time setting unit in the dead time control circuit provided by the present invention.

[0017] Explanation of key component symbols: 1-Low-side dead time setting unit, 2-High-side dead time setting unit, 3-Valley detection unit, 4-Trigger switch. Detailed Implementation

[0018] This invention provides a dead-time control circuit, a PCB board, and a controller. To make the objectives, technical solutions, and effects of this invention clearer and more explicit, the invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only for explaining the invention and are not intended to limit the invention.

[0019] In the description of this invention, it should be understood that the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated.

[0020] Please see Figures 1 to 3 This invention provides a dead-time control circuit, including a low-side dead-time setting unit 1, a high-side dead-time setting unit 2, a valley detection unit 3, and a trigger switch 4. The outputs of the low-side dead-time setting unit 1 and the high-side dead-time setting unit 2 are respectively connected to the input of the valley detection unit 3, and the output of the valley detection unit 3 is connected to the input of the trigger switch 4. Specifically, the low-side dead-time setting unit 1 is used to delay the low-side input signal from an external source; the high-side dead-time setting unit 2 is used to delay the high-side input signal from an external source; the valley detection unit 3 is used to determine the voltage change of the circuit switching node based on the output signals of the low-side dead-time setting unit 1 and the high-side dead-time setting unit 2, and capture the lowest point (valley) moment during the voltage drop process. Then, based on this determined lowest moment, it sends a corresponding control signal to the trigger switch 4 to control the conduction timing of another switching transistor, thereby forming an adaptive dead-time.

[0021] In this embodiment, dynamic adaptation of dead time is achieved through valley detection. Compared with the traditional fixed dead time scheme, this scheme can automatically adjust the dead time based on the actual operating state of the circuit in each switching cycle (such as the influence of load current, junction temperature, etc. on switching speed and voltage oscillation waveform). Under most non-extreme operating conditions, this scheme can effectively shorten unnecessary dead time, allowing the switching transistor to be turned on faster after the body diode completes freewheeling, thereby reducing the conduction time of the switching transistor's body diode and the reverse recovery loss it causes. It also helps to reduce the conduction loss of the switching transistor itself, which has a positive significance for improving the overall system efficiency. Secondly, this scheme does not sacrifice system reliability while pursuing dynamic optimization. The basic fixed delay provided by the low-side and high-side dead time setting unit 2 can serve as a safety baseline, ensuring that even in the abnormal situation where the valley detection circuit fails to work accurately, there is still a minimum dead time barrier to prevent shoot-through short circuits and enhance the robustness of the circuit.

[0022] The working principle of this application is as follows: The low-side and high-side input signals from external input are first sent to the low-side dead-time setting unit 1 and the high-side dead-time setting unit 2, respectively. Each of these units performs a preset and fixed delay on the received input signal. This fixed delay constitutes a basic and minimized dead-time guarantee, aiming to ensure that, under any circumstances, there is a mandatory overlap prohibition zone between the drive signals of the two switching transistors at the initial stage of signal switching, thus providing a basic protection against shoot-through risk from the source of circuit logic. When the valley detection unit 3 receives the output signals from the two setting units, these output signals are not simply delayed signals, but rather a logical result combining the local delayed signal and the original input signal from the opposite path. Their signal change characteristics are related to the actual behavior of the switching node (SW) voltage. When the control signal switches, a switching transistor (e.g., the low-side transistor) is driven by a turn-off command and enters the turn-off process. Its parasitic diode begins to conduct freewheeling. At this time, the switching node voltage will experience an oscillating and decaying decrease due to parasitic inductance, capacitance, and other components in the circuit. The lowest voltage point during this process is the "valley". Valley detection unit 3 continuously compares the states of the two input signals, using its internal logic (e.g., utilizing signal edge differences) to identify and lock the time period from the start of the drop in the switching node voltage to reaching the valley. Once the valley moment is detected, valley detection unit 3 immediately sends a control signal to trigger switch 4. Only after receiving this control signal does trigger switch 4 finally allow the drive signal of the other switch (e.g., the high-side transistor) to pass through and output, thus turning it on. This means that the turn-on time of the other switch is no longer determined solely by the initial fixed delay, but is triggered by the detected "valley" signal that characterizes the actual end of the commutation in the current cycle. Therefore, the actual dead time is dynamically adjusted to be the time from when the first switch is commanded to turn off until the switching node voltage oscillates to the valley and the body diode naturally ends commutation. This is the shortest safe time required to avoid bridge arm shoot-through.

[0023] Further, in one embodiment of the present invention, the low-side dead time setting unit 1 includes a first level conversion unit, a first delay unit, and a first drive output unit. The input terminal of the first level conversion unit is used to receive an external low-side input signal, and its output terminal is connected to the input terminal of the first delay unit. The first drive output unit has two input terminals, respectively connected to the output terminal of the first delay unit and an external high-side input signal terminal, and its output terminal is connected to the input terminal of the valley detection unit 3. The first level conversion unit mainly performs waveform shaping on the externally input low-side signal to obtain a more regular internal control signal. The first delay unit receives the shaped low-side signal and performs a preset delay processing on it, which constitutes the basic fixed dead time. The first drive output unit comprehensively processes the delayed low-side signal and the external high-side input signal, and outputs it to the valley detection unit 3 after power amplification. This output signal reflects the expected turn-off state of the low-side switch under the intervention of the basic dead time.

[0024] Specifically, the first level conversion section includes a first field-effect transistor (FET) M1 and a second FET M2. The first delay section includes a first resistor R1, a first capacitor C1, a third FET M3, a fourth FET M4, a fifth FET M5, and a sixth FET M6. The gates of the first FET M1 and the second FET M2 are connected to an external low-side input signal terminal for receiving input signals. The sources of the first FET M1, the third FET M3, and the fifth FET M5 are all connected to an external power supply terminal to obtain the operating voltage. The sources of the second FET M2 and the sixth FET M6 are grounded. The drain of the first FET M1 is connected to one end of the first resistor R1, one end of the first capacitor C1, the gate of the third FET M3, and the gate of the fourth FET M4. The drain of the second FET M2 is connected to the other end of the first resistor R1. The other end of the first capacitor C1 is connected to the source of the fourth FET M4. The drains of the third field-effect transistor M3 and the fourth field-effect transistor M4 are connected, and this connection node is further connected to the drains of the fifth field-effect transistor M5 and the sixth field-effect transistor M6. The drains of the fifth field-effect transistor M5 and the sixth field-effect transistor M6 are shared and serve as the output of the first delay section, connected to the input terminal of the subsequent first drive output section. When the low-side input signal changes, it undergoes initial shaping through the inverter composed of the first field-effect transistor M1 and the second field-effect transistor M2. Subsequently, the signal generates the required delay through the circuit composed of the first resistor R1, the first capacitor C1, and the third to sixth field-effect transistors M3 to M6.

[0025] Further, the first drive output section includes a seventh field-effect transistor (FET) M7, an eighth field-effect transistor (FET) M8, a ninth field-effect transistor (FET) M9, a tenth field-effect transistor (FET) M10, an eleventh field-effect transistor (FET) M11, a twelfth field-effect transistor (FET) M12, and a thirteenth field-effect transistor (FET) M13. The gates of the seventh and tenth FETs are connected to the drains of the fifth and sixth FETs M5 and M6, respectively, to receive the delayed low-side control signal. The source of the seventh FET M7 is connected to an external power supply terminal, and its drain is connected to the source of the eighth FET M8. The gates of the eighth and eleventh FETs M11 are connected to an external enable control terminal to receive an enable signal. The drain of the eighth FET M8 is connected to the source of the ninth FET M9. The gates of the ninth and twelfth FETs M9 are connected to an external high-side input signal terminal. The drain of the ninth field-effect transistor M9 is connected to the drains of the tenth, eleventh, and twelfth field-effect transistors M10, M11, and M12. The node where the drains of these transistors are connected is the output terminal of the first drive output section, which is connected to the valley detection unit 3. The source of the twelfth field-effect transistor M12 is connected to the sources of the tenth and eleventh field-effect transistors M10 and M11. This circuit, through the cascading and combination of the seventh to thirteenth field-effect transistors M7 and M13, performs logic synthesis and drive amplification of the delayed low-side signal and the original high-side input signal. The state of its output signal is determined by these two input signals, representing the theoretical state of the switching node voltage during the basic dead time.

[0026] The low-side dead time setting unit 1, through the coordinated operation of its three functional units, achieves shaping, fixed delay, and logic synthesis with the high-side input signal of the external low-side input signal. The specific working principle is as follows: The first level conversion section consists of an inverter formed by a first field-effect transistor M1 and a second field-effect transistor M2. When an external low-side input signal arrives, the inverter performs preliminary waveform shaping and level conversion on it, outputting an internal signal that is inversely phase but with a steeper edge. This process helps to organize potentially noisy or slowly varying input signals into well-formed signals suitable for subsequent digital logic circuit processing, providing a clean starting point for delay processing and improving the anti-interference capability of the entire timing link.

[0027] After level conversion, the transition edge of the signal passes through an RC network consisting of a first resistor R1 and a first capacitor C1. The values ​​of the first resistor R1 and the first capacitor C1 together determine the charging or discharging time constant of this RC network, thus creating a delayed voltage change at the gate nodes of the third field-effect transistor M3 and the fourth field-effect transistor M4. Subsequently, the amplification and shaping circuit consisting of the third field-effect transistor M3 to the sixth field-effect transistor M6 converts this slowly changing voltage back into a delayed digital signal with clearly defined high and low levels. This time difference from the input edge to the output edge is the preset basic fixed dead time. This fixed delay, as a basic safety measure, ensures that under any circumstances, there is a minimum time interval between the low-side transistor receiving the turn-off command and the system considering its possible re-conduction, providing the first line of defense against bridge arm shoot-through.

[0028] The first drive output receives two signals: a low-side control signal from the first delay unit with a fixed delay, and the original high-side input signal from the outside without delay. This circuit, through the interconnection of the seventh MOSFET M7 to the thirteenth MOSFET M13, implements a logical function: the state of its final output signal is not solely determined by the delayed low-side signal, but rather by both the delayed low-side signal and the original high-side input signal. Specifically, when the high-side input signal is active, the output is forced into a state representing "high-side active, low-side should not interfere"; while when the high-side input signal is inactive, the output reflects the state of the delayed low-side signal. This design allows the output signal to more accurately represent the expected theoretical state of the switching node (SW) voltage after considering the basic fixed dead time, providing the subsequent valley detection unit 3 with an input signal that reflects the interaction between the upper and lower transistor drive commands and has a clear timing logic relationship, rather than a simple delayed copy. The eighth and eleventh field-effect transistors, M8 and M11, are high-side drive transistors, controlled by the enable signal output from an external enable control terminal. The enable signal controls the subsequent MOSFETs, ensuring that the drive signal can only be delivered to the output stage when the enable is active. This can force the output to shut down for emergency stops or initialization.

[0029] Correspondingly, the high-side dead-time setting unit 2 is structurally symmetrical to the low-side unit, and includes a second level conversion section, a second delay section, and a second drive output section. The input terminal of the second level conversion section is connected to an external high-side input signal terminal, and its output terminal is connected to the input terminal of the second delay section. The second drive output section has two input terminals, respectively connected to the output terminal of the second delay section and the external low-side input signal terminal, and its output terminal is connected to the other input terminal of the valley detection unit 3. The second level conversion section shapes the external high-side input signal, the second delay section delays the shaped high-side signal, and the second drive output section generates a drive signal based on the delayed high-side signal and the external low-side input signal and outputs it to the valley detection unit 3.

[0030] Specifically, the second level conversion section includes a thirteenth field-effect transistor (FET) M13 and a fourteenth field-effect transistor (FET) M14. The second delay section includes a second resistor R2, a second capacitor C2, a fifteenth field-effect transistor (FET) M15, a sixteenth field-effect transistor (FET) M16, a seventeenth field-effect transistor (FET) M17, and an eighteenth field-effect transistor (FET) M18. The gates of the thirteenth and fourteenth FETs M13 and M14 are connected to an external high-side input signal terminal. The sources of the thirteenth, fifteenth, and seventeenth FETs M17 are connected to an external power supply. The sources of the fourteenth and eighteenth FETs M14 are grounded. The drain of the thirteenth FET M13 is connected to one end of the second resistor R2, one end of the second capacitor C2, the gate of the fifteenth FET M15, and the gate of the sixteenth FET M16. The drain of the fourteenth FET M14 is connected to the other end of the second resistor R2. The other end of the second capacitor C2 is connected to the source of the sixteenth FET M16. The drains of the fifteenth field-effect transistor M15 and the sixteenth field-effect transistor M16 are connected, and further connected to the drains of the seventeenth field-effect transistor M17 and the eighteenth field-effect transistor M18. The common connection point of the drains of the seventeenth field-effect transistor M17 and the eighteenth field-effect transistor M18 serves as the output of the second delay section and is connected to the second drive output section. Its operating principle is similar to that of the low-side delay section, realizing a fixed delay for the high-side signal.

[0031] Further, the second drive output section includes a nineteenth field-effect transistor M19, a twentieth field-effect transistor M20, a twenty-first field-effect transistor M21, a twenty-second field-effect transistor M22, a twenty-third field-effect transistor M23, and a twenty-fourth field-effect transistor M24. The gates of the nineteenth field-effect transistor M19 and the twenty-second field-effect transistor M22 are connected to the drains of the seventeenth field-effect transistor M17 and the eighteenth field-effect transistor M18. The source of the nineteenth field-effect transistor M19 is connected to an external power supply, and its drain is connected to the source of the twentieth field-effect transistor M20. The gates of the twentieth field-effect transistor M20 and the twenty-third field-effect transistor M23 are connected to an external low-side input signal terminal. The drain of the twentieth field-effect transistor M20 is connected to the source of the twenty-first field-effect transistor M21. The gates of the twenty-first field-effect transistor M21 and the twenty-fourth field-effect transistor M24 are connected to an external enable control terminal. The drain of the 21st field-effect transistor M21 is connected to the drains of the 22nd, 23rd, and 24th field-effect transistors M22 and M23, respectively. This connection node serves as the output terminal of the second drive output section, connected to the valley detection unit 3. The source of the 24th field-effect transistor M24 is connected to the sources of the 22nd and 23rd field-effect transistors M22 and M23, respectively. Its function is to synthesize and process the delayed high-side signal and the original low-side input signal, and output a drive signal.

[0032] To ensure stable and reliable detection and determination of the switching node voltage valley, the valley detection unit 3 includes an XOR gate and a D flip-flop. The two inputs of the XOR gate are connected to the output of the high-side dead-time setting unit 2 (i.e., the output of the second drive output) and the output of the low-side dead-time setting unit 1 (i.e., the output of the first drive output), respectively. The output of the XOR gate is connected to the D input of the D flip-flop. The Q output of the D flip-flop is connected to the enable control terminal of the trigger switch 4. Its operating logic is as follows: the output signals of the low-side and high-side setting units represent the theoretical state of the switching node voltage under their respective base delays. When the drive signals of the upper and lower transistors switch, after one transistor is turned off, its body diode begins freewheeling, causing a change in the switching node voltage. By comparing the output signals of the two units, the XOR gate can generate a pulse signal with a pulse width related to the time from the start of the switching node voltage change to reaching the valley. This pulse signal is sent to the D flip-flop. Under the control of the clock signal, the D flip-flop generates a rising edge at the moment the pulse ends (i.e., the voltage valley is detected), which is sent as a control signal to the trigger switch 4, thereby triggering the drive signal of another switching transistor to achieve precise turn-on.

[0033] The trigger switch 4 activates after receiving the control signal from the valley detection unit 3, and finally outputs the high-side and low-side drive signals after adaptive dead time adjustment, so as to control the high-side and low-side switching transistors in the half-bridge or full-bridge circuit respectively.

[0034] In one embodiment of the present invention, the trigger switch 4 may be specifically implemented by a digital logic gate circuit. One feasible implementation is that the trigger switch 4 includes an AND gate and an inverter (INV).

[0035] Specifically, the trigger switch 4 has two input terminals and one output terminal. Its first input terminal is connected to the output terminal of the valley detection unit 3 (e.g., the Q terminal of a D flip-flop) to receive the valley detection control signal (DET). Its second input terminal is connected to the original drive signal source of the corresponding switching transistor; for example, for a low-side drive channel, this second input terminal is connected to an external low-side input signal (L_IN); for a high-side drive channel, it is connected to an external high-side input signal (H_IN). The output terminal of the trigger switch 4 outputs the final drive signal (such as LO or HO) to the gate of the power switching transistor.

[0036] One input terminal of the AND gate and the input terminal of the inverter together serve as the first input terminal of the trigger switch 4, receiving the valley detection control signal (DET). The output terminal of the inverter is connected to the other input terminal of the AND gate. The output terminal of the AND gate serves as the output terminal of the trigger switch 4. Simultaneously, the second input terminal of the trigger switch 4 (i.e., the original drive signal input terminal) is connected to a node before or after one input terminal of the AND gate (specifically, the path connected to the inverter output terminal) to introduce the original drive signal into the logic judgment. A direct connection method is to also connect the original drive signal (such as L_IN) to this input terminal of the AND gate, meaning this input terminal simultaneously receives the signal from the inverter and the original drive signal. This can be achieved in a practical circuit by adding an AND gate input terminal, forming a multi-input AND gate logic relationship.

[0037] Its working principle is as follows: When the valley detection unit 3 determines that the current time does not meet the turn-on condition (i.e., the switching node voltage has not reached the valley), its output control signal DET is low. This low-level signal directly makes one input of the AND gate low. At the same time, this low level is converted to a high level by an inverter and sent to the other input of the AND gate. However, since one input of the AND gate has been pulled low by DET, according to the characteristic that the AND gate is only high when all inputs are high, regardless of the state of the original drive signal (L_IN or H_IN) at this time, the output of the AND gate, that is, the final drive signal, will be forcibly locked at a low level (off state). This ensures that the switching transistor will not be accidentally turned on during the dead time.

[0038] When the valley detection unit 3 detects that the voltage at the switching node has reached the valley, its output control signal DET jumps to a high level. This high-level signal satisfies one input condition of the AND gate. Simultaneously, this high level is inverted and sent to the other input of the AND gate. At this point, the final output state of the AND gate will be completely determined by the original drive signal (L_IN or H_IN): if the original drive signal is high (turn-on command), since one input of the AND gate is high (from DET) and the other input is also high (original signal), the output is high, driving the switching transistor to turn on; if the original drive signal is low (turn-off command), the output remains low. In this way, the moment the switching transistor turns on is allowed to occur at the instant the valley appears, thus achieving dynamic cutoff of the dead time.

[0039] The working process of this invention is briefly described as follows: The externally input high-side and low-side raw drive signals enter the high-side and low-side dead-time setting units 1, respectively. These two units first shape the signals and apply a fixed base delay, and then combine them with the other raw signal to generate two intermediate signals, which are output to the valley detection unit 3. The valley detection unit 3 compares these two intermediate signals in real time. Utilizing the characteristic that the voltage drop at the switching node is caused by the freewheeling current of the body diode after the switching transistor is turned off, it accurately detects the moment when the voltage at the switching node reaches its lowest point through a combination of XOR gates and D flip-flops. Once this valley moment is detected, it indicates that the body diode of the turned-off switching transistor has completed its freewheeling, and the voltage resonates and swings back. At this time, turning on the other switching transistor can safely avoid shoot-through. The valley detection unit 3 then outputs a control signal to trigger the final drive signal output. In this way, the dead time is no longer fixed, but dynamically adjusted according to the actual changes in the voltage at the switching node in each switching cycle. Under the premise of avoiding shoot-through between the upper and lower transistors, unnecessary dead time can be effectively shortened, thereby helping to reduce the conduction loss and reverse recovery loss of the switching devices, and having a positive effect on improving the overall efficiency of the circuit.

[0040] In summary, by introducing a valley detection mechanism, the control of dead time is transformed from static preset to dynamic sensing and response. Under the premise of ensuring the safe operation of the bridge arm and avoiding shoot-through risks, the dead window can be managed more precisely, which helps to optimize switching losses and thus improve the efficiency of the power conversion circuit to a certain extent.

[0041] This application also provides a PCB board printed with the dead time control circuit described above.

[0042] This application also provides a controller that uses the dead-time control circuit described above for operation control.

[0043] It is understood that those skilled in the art can make equivalent substitutions or modifications to the technical solution and inventive concept of the present invention, and all such substitutions or modifications should fall within the protection scope of the appended claims.

Claims

1. A dead-time control circuit, characterized in that, The device includes a low-side dead time setting unit, a high-side dead time setting unit, a valley detection unit, and a trigger switch. The outputs of the low-side dead time setting unit and the high-side dead time setting unit are respectively connected to the input of the valley detection unit, and the output of the valley detection unit is connected to the input of the trigger switch. The low-side dead time setting unit is used to delay external low-side input signals; the high-side dead time setting unit is used to delay external high-side input signals; the valley detection unit is used to determine the lowest voltage moment of the switching node based on the output signals of the low-side dead time setting unit and the high-side dead time setting unit, and sends a control signal to the trigger switch based on the lowest voltage moment.

2. The dead-time control circuit according to claim 1, characterized in that, The low-side dead time setting unit includes a first level conversion section, a first delay section, and a first drive output section. The input terminal of the first level conversion section is connected to an external low-side input signal terminal, the output terminal of the first level conversion section is connected to the input terminal of the first delay section, the input terminal of the first drive output section is connected to the output terminal of the first delay section and an external high-side input signal terminal, and the output terminal of the first drive output section is connected to the input terminal of the valley detection unit. The first level conversion unit is used to shape the external low-side input signal; the first delay unit is used to delay the low-side shaped signal; and the first drive output unit is used to amplify the external high-side input signal based on the low-side delayed signal.

3. The dead-time control circuit according to claim 2, characterized in that, The first level conversion section includes a first field-effect transistor (FET) M1 and a second field-effect transistor (FET) M2; the first delay section includes a first resistor R1, a first capacitor C1, a third field-effect transistor (FET) M3, a fourth field-effect transistor (FET) M4, a fifth field-effect transistor (FET) M5, and a sixth field-effect transistor (FET) M6; the gates of the first FET M1 and the second FET M2 are connected to an external low-side input signal terminal, the sources of the first FET M1, the third FET M3, and the fifth FET M5 are connected to an external power supply terminal, the sources of the second FET M2 and the sixth FET M6 are grounded, and the first FET M1... The drain of transistor M1 is connected to one end of the first resistor R1, one end of the first capacitor C1, the gate of the third field-effect transistor M3, and the gate of the fourth field-effect transistor M4. The drain of the second field-effect transistor M2 is connected to the other end of the first resistor R1. The other end of the first capacitor C1 is connected to the source of the fourth field-effect transistor M4. The drains of the third field-effect transistor M3 and the fourth field-effect transistor M4 are connected to the drains of the fifth field-effect transistor M5 and the sixth field-effect transistor M6. The drains of the fifth field-effect transistor M5 and the sixth field-effect transistor M6 are connected to the input terminal of the first drive output section.

4. The dead-time control circuit according to claim 3, characterized in that, The first drive output section includes a seventh field-effect transistor (FET) M7, an eighth field-effect transistor (FET) M8, a ninth field-effect transistor (FET) M9, a tenth field-effect transistor (FET) M10, an eleventh field-effect transistor (FET) M11, a twelfth field-effect transistor (FET) M12, and a thirteenth field-effect transistor (FET) M13. The gates of the seventh and tenth FETs are connected to the drains of the fifth and sixth FETs, respectively. The source of the seventh FET M7 is connected to an external power supply terminal, and the drain of the seventh FET M7 is connected to the source of the eighth FET M8. The gates of the eighth and eleventh FETs are connected to an external enable control terminal. The drain of transistor 8 is connected to the source of transistor M9. The gates of transistors M9 and M12 are connected to the external high-side input signal terminal. The drain of transistor M9 is connected to the drains of transistors M10, M11, and M12. The connection node of the drains of transistors M9, M10, M11, and M12 is connected to the input terminal of the valley detection unit. The source of transistor M12 is connected to the source of transistors M10 and M11.

5. The dead-time control circuit according to claim 1, characterized in that, The high-side dead time setting unit includes a second level conversion section, a second delay section, and a second drive output section. The input terminal of the second level conversion section is connected to an external high-side input signal terminal, and the output terminal of the second level conversion section is connected to the input terminal of the second delay section. The input terminal of the second drive output section is connected to the output terminal of the second delay section and an external low-side input signal terminal, and the output terminal of the second drive output section is connected to the input terminal of the valley detection unit. The second level conversion section is used to shape the external high-side input signal; the second delay section is used to delay the high-side shaped signal; and the second drive output section is used to amplify the external low-side input signal based on the high-side delayed signal.

6. The dead-time control circuit according to claim 5, characterized in that, The second level conversion section includes a thirteenth field-effect transistor (FET) M13 and a fourteenth field-effect transistor (FET) M14; the second delay section includes a second resistor R2, a second capacitor C2, a fifteenth field-effect transistor (FET) M15, a sixteenth field-effect transistor (FET) M16, a seventeenth field-effect transistor (FET) M17, and an eighteenth field-effect transistor (FET) M18; the gates of the thirteenth and fourteenth FETs M13 and M14 are connected to an external high-side input signal terminal, the sources of the thirteenth, fifteenth, and seventeenth FETs M17 are connected to an external power supply terminal, and the sources of the fourteenth and eighteenth FETs M14 are grounded. The drain of transistor M13 is connected to one end of the second resistor R2, one end of the second capacitor C2, the gate of the fifteenth field-effect transistor M15, and the gate of the sixteenth field-effect transistor M16. The drain of the fourteenth field-effect transistor M14 is connected to the other end of the second resistor R2. The other end of the second capacitor C2 is connected to the source of the sixteenth field-effect transistor M16. The drains of the fifteenth and sixteenth field-effect transistors M15 and M16 are connected to the drains of the seventeenth and eighteenth field-effect transistors M17 and M18. The drains of the seventeenth and eighteenth field-effect transistors M17 and M18 are connected to the input terminal of the second drive output section.

7. The dead-time control circuit according to claim 6, characterized in that, The second drive output section includes a nineteenth field-effect transistor (FET) M19, a twentieth field-effect transistor (FET) M20, a twenty-first field-effect transistor (FET) M21, a twenty-second field-effect transistor (FET) M22, a twenty-third field-effect transistor (FET) M23, and a twenty-fourth field-effect transistor (FET) M24. The gates of the nineteenth FET M19 and the twenty-second FET M22 are connected to the drains of the seventeenth FET M17 and the eighteenth FET M18. The source of the nineteenth FET M19 is connected to an external power supply terminal. The drain of the nineteenth FET M19 is connected to the source of the twentieth FET M20. The gates of the twentieth FET M20 and the twenty-third FET M23 are connected to an external low-side input signal terminal. The twentieth FET M20... The drain of the 21st field-effect transistor M21 is connected to the source of the 21st field-effect transistor M21. The gates of the 21st field-effect transistor M21 and the 24th field-effect transistor M24 are connected to an external enable control terminal. The drain of the 21st field-effect transistor M21 is connected to the drains of the 22nd, 23rd, and 24th field-effect transistors M22 and M23. The connection node of the drains of the 21st, 22nd, 23rd, and 24th field-effect transistors M24 is connected to the input terminal of the valley detection unit. The source of the 24th field-effect transistor M24 is connected to the sources of the 22nd and 23rd field-effect transistors M22 and M23, respectively.

8. The dead-time control circuit according to claim 1, characterized in that, The valley detection unit includes an XOR gate and a D flip-flop. The two inputs of the XOR gate are connected to the outputs of the high-side dead time setting unit and the low-side dead time setting unit, respectively. The output of the XOR gate is connected to the D port of the D flip-flop, and the Q port of the D flip-flop is connected to the enable terminal of the trigger switch.

9. A PCB board, characterized in that, The PCB board is printed with a dead time control circuit as described in any one of claims 1-8.

10. A controller, characterized in that, The controller employs a dead-time control circuit as described in any one of claims 1-8.

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