Evaluation method and apparatus for parasitic capacitance in injection-locked circuits

Abstract

This invention discloses a method and apparatus for evaluating the parasitic capacitance of an injection-locked circuit. The evaluation method includes: determining the device parameters of an LC resonator based on a target operating frequency range, and simulating the LC resonator with the device parameters applied to obtain a first simulation result; loading an injection structure at the first and second simulation interface terminals of the LC resonator to obtain a first circuit, simulating the first circuit to obtain a second simulation result, and adjusting the second simulation result based on the first simulation result to determine the first parasitic capacitance of the injection structure; loading a locking structure between the first and second simulation interface terminals of the first circuit to obtain a second circuit, simulating the second circuit to obtain a third simulation result, and adjusting the third simulation result based on the target operating frequency range to determine the second parasitic capacitance of the locking structure. Thus, this solution achieves accurate evaluation of the parasitic capacitance of the injection-locked circuit.

Description

Technical Field

[0001] The present invention relates to the field of injection locking technology, and in particular to a method and apparatus for evaluating the parasitic capacitance of an injection locking circuit. Background Technology

[0002] Injection-locked technology is widely used in millimeter-wave local oscillator systems due to its high efficiency and flexibility. This technology can be used to design injection-locked frequency multipliers, injection-locked frequency dividers, and injection-locked amplifiers, and can be applied to voltage-controlled oscillators operating in low-noise, wide-bandwidth environments to improve frequency, bandwidth, and output power. However, the key design aspect of injection-locked modules lies in determining a suitable LC resonant cavity to ensure that the phase response of the cavity input impedance is near 0° and covers as wide a frequency range as possible to achieve the desired operating frequency range.

[0003] Currently, the optimal operating frequency range can be evaluated based on the relationship between the capacitance, inductance, coupling coefficient, and phase response of an LC resonator. However, because the input impedance phase of an LC resonator is particularly sensitive to changes in capacitance, especially at higher harmonic frequencies, the low injection current component can lead to a very small phase at the lock-in phase edge. Currently, there is a lack of effective methods for accurately evaluating the parasitic capacitance of the injection device. If the parasitic capacitance cannot be accurately evaluated, the injection-locked circuit may fail to lock, the lock-in bandwidth may be too narrow, or even if the chip is locked, instability may occur in complex external environments. Summary of the Invention

[0004] This invention provides a method and apparatus for evaluating the parasitic capacitance of an injection-locked circuit, so as to accurately evaluate the parasitic capacitance of the injection-locked circuit.

[0005] In a first aspect, embodiments of the present invention provide a method for evaluating the parasitic capacitance of an injection-locked circuit, the method comprising: The device parameters of the LC resonator are determined according to the target operating frequency range, and the LC resonator with the device parameters loaded is simulated to obtain a first simulation result. The LC resonator includes a first inductor, a second inductor, a first capacitor, two second capacitors, and a resistor. The first end of the first inductor and the first end of the first capacitor are both connected to the first end of the resistor. The second end of the resistor is grounded. The second end of the first inductor and the second end of the first capacitor are grounded together. The first inductor and the second inductor are coupled. The first end of the second inductor is connected to the first end of the first second capacitor and serves as the first simulation interface of the LC resonator. The second end of the first second capacitor is connected to the first end of the second second capacitor. The second end of the second inductor is connected to the second end of the second second capacitor and serves as the second simulation interface of the LC resonator. An injection structure is loaded at the first simulation interface and the second simulation interface of the LC resonant cavity to obtain a first circuit. The first circuit is simulated to obtain a second simulation result. The second simulation result is adjusted according to the first simulation result to determine the first parasitic capacitance of the injection structure. A locking structure is loaded between the first simulation interface and the second simulation interface of the first circuit to obtain a second circuit. The second circuit is simulated to obtain a third simulation result. The third simulation result is adjusted according to the target operating frequency range to determine the second parasitic capacitance of the locking structure.

[0006] Optionally, the first simulation result includes a first phase-output frequency simulation line; The device parameters include a first inductance value, a second inductance value, a first capacitance value, a second capacitance value, and a coupling coefficient between the first inductance and the second inductance.

[0007] Optionally, the step of simulating the LC resonant cavity with the device parameters loaded to obtain the first simulation result includes: Input a first impedance at the first simulation interface terminal and the second simulation interface terminal to obtain the first phase-output frequency simulation line.

[0008] Optionally, the step of simulating the first circuit to obtain the second simulation result includes: A second impedance is input at the first simulation interface terminal with the injection structure loaded and the second simulation interface terminal with the injection structure loaded, so as to obtain the second simulation result; The injection structure includes a third capacitor, a first transistor, and a second transistor; The first terminal of the third capacitor serves as the input terminal of the first circuit. The second terminal of the third capacitor is connected to the control terminal of the first transistor. The first electrode of the first transistor is grounded. The second electrode of the first transistor and the first electrode of the second transistor are connected. The control terminal of the second transistor is connected to the first potential. The second electrode of the second transistor is connected to either the first simulation interface terminal or the second simulation interface terminal.

[0009] Optionally, the second simulation result includes a second phase-output frequency simulation line; The step of determining the first parasitic capacitance of the injection structure includes: Adjust the capacitance value of each of the second capacitors until the second phase-output frequency simulation line and the first phase-output frequency simulation line coincide, and record the capacitance value of the second capacitor as the first adjustment capacitance value; The first parasitic capacitance of the injection structure is determined based on the first adjustment capacitance value and the second capacitance value.

[0010] Optionally, determining the first parasitic capacitance of the injection structure based on the first adjustment capacitance value and the second capacitance value includes: The first parasitic capacitance of the injection structure is equal to the difference between the second capacitance value and the first adjustment capacitance value.

[0011] Optionally, the step of simulating the second circuit to obtain the third simulation result includes: A third impedance is input to the first simulation interface terminal and the second simulation interface terminal of the first circuit where the locking structure is loaded, in order to obtain the third simulation result; The locking structure includes a third transistor, a fourth transistor, and a fifth transistor; The control terminal of the fifth transistor is connected to the second potential, the first terminal of the fifth transistor is grounded, the first terminals of the third transistor and the fourth transistor are both connected to the second terminal of the fifth transistor, the second terminal of the third transistor and the control terminal of the fourth transistor are both connected to the first simulation interface terminal, and the second terminal of the fourth transistor and the control terminal of the third transistor are both connected to the second simulation interface terminal.

[0012] Optionally, the third simulation result includes a third phase-output frequency simulation line; The step of determining the second parasitic capacitance of the locking structure includes: The initial target operating frequency is obtained based on the target operating frequency range; Adjust the capacitance value of the second capacitor until the zero-crossing frequency of the third phase-output frequency simulation line is equal to the initial target operating frequency, and record the capacitance value of the second capacitor as the second adjustment capacitor value; The second parasitic capacitance of the locking structure is determined based on the first adjustment capacitance value and the second adjustment capacitance value.

[0013] Optionally, determining the second parasitic capacitance of the locking structure based on the first adjustment capacitance value and the second adjustment capacitance value includes: The second parasitic capacitance of the locking structure is equal to the difference between the first adjustment capacitance value and the second adjustment capacitance value.

[0014] Secondly, embodiments of the present invention also provide an evaluation apparatus for the parasitic capacitance of an injection-locked circuit, the evaluation apparatus comprising: The first simulation module is used to determine the device parameters of the LC resonator according to the target operating frequency range, and to simulate the LC resonator with the device parameters loaded to obtain a first simulation result. The LC resonator includes a first inductor, a second inductor, a first capacitor, two second capacitors, and a resistor. The first end of the first inductor and the first end of the first capacitor are both connected to the first end of the resistor. The second end of the resistor is grounded. The second end of the first inductor and the second end of the first capacitor share a common ground. The first inductor and the second inductor are coupled. The first end of the second inductor is connected to the first end of the first second capacitor and serves as the first simulation interface of the LC resonator. The second end of the first second capacitor is connected to the first end of the second second capacitor. The second end of the second inductor is connected to the second end of the second second capacitor and serves as the second simulation interface of the LC resonator. The first parasitic capacitance determination module is used to load an injection structure onto the first simulation interface and the second simulation interface of the LC resonant cavity to obtain a first circuit, simulate the first circuit to obtain a second simulation result, and adjust the second simulation result according to the first simulation result to determine the first parasitic capacitance of the injection structure. The second parasitic capacitance determination module is used to load a locking structure between the first simulation interface terminal and the second simulation interface terminal of the first circuit to obtain a second circuit, simulate the second circuit to obtain a third simulation result, and adjust the third simulation result according to the target operating frequency range to determine the second parasitic capacitance of the locking structure.

[0015] This invention determines the device parameters of an LC resonator based on a target operating frequency range, and simulates the LC resonator with the device parameters applied to obtain a first simulation result, which serves as a benchmark result. An injection structure is loaded at the first and second simulation interface terminals of the LC resonator to obtain a first circuit. The first circuit is simulated to obtain a second simulation result, and the second simulation result is adjusted based on the first simulation result to ensure consistency between the first and second simulation results. The first parasitic capacitance of the injection structure is then determined based on the adjustment result. A locking structure is loaded between the first and second simulation interface terminals of the first circuit to obtain a second circuit. The second circuit is simulated to obtain a third simulation result. The zero-crossing point of the third simulation result is adjusted to equal the initial target operating frequency of the target operating frequency range, and the second parasitic capacitance of the locking structure is then determined based on the adjustment result. Thus, this solution achieves accurate evaluation of the parasitic capacitance of the injection-locked circuit. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 A flowchart illustrating a method for evaluating the parasitic capacitance of an injection-locked circuit, provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of the structure of an LC resonant cavity provided in an embodiment of the present invention; Figure 3 A schematic diagram of the structure of a first circuit provided in an embodiment of the present invention; Figure 4 A schematic diagram of a second circuit provided in an embodiment of the present invention; Figure 5 for Figure 2 A schematic diagram of the simulation line of the first phase-output frequency of the LC resonant cavity is shown. Figure 6 for Figure 3 A schematic diagram of the second phase-output frequency simulation line of the first circuit shown; Figure 7 for Figure 4 A schematic diagram of the simulation line of the third phase-output frequency of the second circuit shown. Figure 8 A schematic diagram of the structure of an evaluation device for parasitic capacitance of an injection locking circuit provided in an embodiment of the present invention; Figure 9 This is a schematic diagram of a multi-cavity structure for an injection-locked amplifier proposed in an embodiment of the present invention; Figure 10 for Figure 9 The diagram shows the relationship between the inductance value and the output frequency of the injection-locked amplifier. Figure 11 for Figure 9 The diagram shows the relationship between the inductor configuration factor and coupling coefficient of the injection-locked amplifier and the output frequency. Figure 12 for Figure 9 The amplitude response diagrams of the high-frequency and low-frequency subbands of the injection-locked amplifier at the multi-cavity input are shown. Figure 13 for Figure 9 The phase response diagrams of the high-frequency and low-frequency subbands of the injection-locked amplifier at the multi-cavity input are shown. Detailed Implementation

[0018] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0019] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0020] Because the input impedance phase of an LC resonator is particularly sensitive to changes in capacitance, especially when designing high-order harmonic harmonics, the low injection current component results in a very small lock-in phase edge. If parasitic capacitance is not accurately evaluated, the circuit may fail to lock, have an excessively narrow lock-in bandwidth, or even if it does lock, it may become unstable in complex external environments. Therefore, this application proposes a method for evaluating the parasitic capacitance of an injection-locked circuit to accurately assess its parasitic capacitance.

[0021] Figure 1 This is a flowchart illustrating a method for evaluating the parasitic capacitance of an injection-locked circuit according to an embodiment of the present invention. This embodiment is applicable to evaluating the parasitic capacitance of the injection-locked circuit in an injection-locked technology device. The method can be executed by an evaluation device for the parasitic capacitance of the injection-locked circuit, which can be implemented in hardware and / or software. The method specifically includes the following steps: S110. Determine the device parameters of the LC resonator according to the target operating frequency range, and simulate the LC resonator with the device parameters applied to obtain the first simulation result.

[0022] For example, Figure 2 This is a schematic diagram of the structure of an LC resonant cavity provided in an embodiment of the present invention, as shown below. Figure 2As shown, the LC resonant cavity includes a first inductor L1, a second inductor L2, a first capacitor C1, two second capacitors C2, and a resistor R. The first ends of the first inductor L1 and the first capacitor C1 are both connected to the first end of the resistor R. The second end of the resistor R is grounded. The second ends of the first inductor L1 and the first capacitor C1 share a common ground. The first inductor L1 and the second inductor L2 are coupled. The first end of the second inductor L2 is connected to the first end of the first second capacitor C2 and serves as the first simulation interface of the LC resonant cavity. The second end of the first second capacitor C2 is connected to the first end of the second second capacitor C2. The second end of the second inductor L2 is connected to the second end of the second second capacitor C2 and serves as the second simulation interface of the LC resonant cavity.

[0023] The target operating frequency range is the frequency range covered by the phase response of the resonant cavity input impedance near 0°. The device parameters of the LC resonant cavity include the parameters of each component, such as the inductance values ​​of the first and second inductors, the capacitance values ​​of the first and second capacitors, and the coupling coefficient between the first and second inductors. The device parameters are then applied to the LC resonant cavity, i.e., the specific inductance values ​​of the first and second inductors, the capacitance values ​​of the first and second capacitors, and the capacitance values ​​of the second capacitor are set. The LC resonant cavity with the device parameters applied is then simulated by inputting a first impedance at both the first and second simulation interface terminals to obtain the first simulation result (the relationship between the phase of the input impedance and the output frequency). A large value is chosen for the first impedance to effectively create an open circuit between the first and second simulation interface terminals, thus avoiding any influence from either terminal on the LC resonant cavity.

[0024] S120. An injection structure is loaded at the first simulation interface and the second simulation interface of the LC resonant cavity to obtain a first circuit. The first circuit is simulated to obtain a second simulation result. The second simulation result is adjusted according to the first simulation result to determine the first parasitic capacitance of the injection structure.

[0025] The injection structure is a common-source, common-gate structure composed of transistors, which can increase the injection current injected into the LC resonant cavity and improve the isolation between the LC resonant cavity and adjacent connected devices.

[0026] For example, Figure 3 A schematic diagram of a first circuit provided in an embodiment of the present invention, as shown below. Figure 3As shown, the first circuit includes an LC resonant cavity and two injection structures; one injection structure is connected to the first simulation interface terminal, and the other injection structure is connected to the second simulation interface terminal. Specifically, the injection structure includes a third capacitor C3, a first transistor M1, and a second transistor M2; the first terminal of the third capacitor C3 serves as the input terminal of the first circuit, the second terminal of the third capacitor C3 is connected to the control terminal of the first transistor M1, the first electrode of the first transistor M1 is grounded, the second electrode of the first transistor M1 is connected to the first electrode of the second transistor M2, the control terminal of the second transistor M2 is connected to the first potential V1, and the second electrode of the second transistor M2 is connected to either the first simulation interface terminal or the second simulation interface terminal.

[0027] The first circuit is simulated to obtain the second simulation result, that is, a second impedance is input at the first simulation interface terminal with the injection structure and the second simulation interface terminal with the injection structure to obtain the second simulation result (the relationship between the phase of the input impedance and the output frequency). The value of the second impedance is selected to be large so that the first simulation interface terminal and the second simulation interface terminal are equivalent to an open circuit, so as to avoid the influence of the first simulation interface terminal and the second simulation interface terminal on the first circuit.

[0028] Furthermore, the specific process of adjusting the second simulation result based on the first simulation result to determine the first parasitic capacitance of the injection structure is as follows: Since an injection structure is loaded at the first simulation interface and the second simulation interface of the LC resonant cavity, the first parasitic capacitance of the injection structure will be increased in the LC resonant cavity. In order to make the capacitance of the first circuit equal to the capacitance of the LC resonant cavity, the capacitance value of the second capacitor needs to be reduced, so that the second simulation result moves toward the first simulation result until the second simulation result is consistent with the first simulation result. Thus, the adjustment amplitude of the capacitance value of the second capacitor is the first parasitic capacitance of the injection structure.

[0029] S130. A locking structure is loaded between the first simulation interface and the second simulation interface of the first circuit to obtain a second circuit. The second circuit is simulated to obtain a third simulation result. The third simulation result is adjusted according to the target operating frequency range to determine the second parasitic capacitance of the locking structure.

[0030] The locking structure is a cross-coupled structure composed of transistors, which can amplify the injected signal. For example, Figure 4 This is a schematic diagram of a second circuit provided in an embodiment of the present invention. Figure 4As shown, the second circuit includes an LC resonant cavity, two injection structures, and a locking structure; the locking structure is located between the first and second simulation interface terminals. Specifically, the locking structure includes a third transistor M3, a fourth transistor M4, and a fifth transistor M5; the control terminal of the fifth transistor M5 is connected to the second potential V2, the first terminal of the fifth transistor M5 is grounded, the first terminals of the third transistor M3 and the fourth transistor M4 are both connected to the second terminal of the fifth transistor M5, the second terminal of the third transistor M3 and the control terminal of the fourth transistor M4 are both connected to the first simulation interface terminal, and the second terminal of the fourth transistor M4 and the control terminal of the third transistor M3 are both connected to the second simulation interface terminal.

[0031] The second circuit is simulated to obtain the third simulation result. Specifically, a third impedance is input to the first and second simulation interface terminals of the first circuit, which are loaded with a locking structure, to obtain the third simulation result (the relationship between the phase of the input impedance and the output frequency). The value of the third impedance is selected to be large so that the first and second simulation interface terminals are equivalent to an open circuit, so as to avoid the influence of the first and second simulation interface terminals on the second circuit.

[0032] In addition, the specific process of adjusting the third simulation results to determine the second parasitic capacitance of the locking structure according to the target operating frequency range is as follows: Since the locking structure is loaded between the first simulation interface and the second simulation interface of the first circuit, the first circuit will have an additional second parasitic capacitance of the locking structure. In order to make the capacitance of the second circuit equal to the capacitance of the first circuit, the capacitance value of the second capacitor needs to be reduced so that the zero-crossing frequency of the third simulation result is equal to the initial target operating frequency of the target operating frequency range, and the second parasitic capacitance of the locking structure is determined according to the adjustment amplitude of the capacitance value of the second capacitor.

[0033] This invention determines the device parameters of an LC resonator based on a target operating frequency range, and simulates the LC resonator with the device parameters applied to obtain a first simulation result, which serves as a benchmark result. An injection structure is loaded at the first and second simulation interface terminals of the LC resonator to obtain a first circuit. The first circuit is simulated to obtain a second simulation result, and the second simulation result is adjusted based on the first simulation result to ensure consistency between the first and second simulation results. The first parasitic capacitance of the injection structure is then determined based on the adjustment result. A locking structure is loaded between the first and second simulation interface terminals of the first circuit to obtain a second circuit. The second circuit is simulated to obtain a third simulation result. The zero-crossing point of the third simulation result is adjusted to equal the initial target operating frequency of the target operating frequency range, and the second parasitic capacitance of the locking structure is then determined based on the adjustment result. Thus, this solution achieves accurate evaluation of the parasitic capacitance of the injection-locked circuit.

[0034] Based on the above embodiments, optionally, the first simulation result includes a first phase-output frequency simulation line; the device parameters include a first inductance value, a second inductance value, a first capacitance value, a second capacitance value, and a coupling coefficient between the first inductance and the second inductance.

[0035] For example, if the target operating frequency range is 35 GHz to 45 GHz, that is, the phase response of the input impedance is near 0° between 35 GHz and 45 GHz; in this case, the device parameters of the LC resonant cavity are as follows: the first inductance value of the first inductor is 160 pH, the second inductance value of the second inductor is 306 pH, the first capacitance value of the first capacitor is 154 fF, the second capacitance value of the second capacitor is 128 fF, and the coupling coefficient between the first inductor and the second inductor is 0.6.

[0036] Specifically, the simulation of the LC resonant cavity with loaded device parameters is used to obtain the first simulation result, including: inputting the first impedance at the first simulation interface terminal and the second simulation interface terminal to obtain the first phase-output frequency simulation line.

[0037] For example, if the first inductance value of the first inductor is 160 pH, the second inductance value of the second inductor is 306 pH, the first capacitance value of the first capacitor is 154 fF, the second capacitance value of the second capacitor is 128 fF, and the coupling coefficient between the first and second inductors is 0.6; and a first impedance of 50000 ohms is selected, effectively creating an open circuit between the first and second simulation interface terminals, thus avoiding any impact from the first and second simulation interface terminals on the LC resonant cavity. Figure 5 for Figure 2 The diagram shows a simulation line of the first phase-output frequency of the LC resonant cavity. Figure 5 As shown, the phase response of the input impedance is near 0° between 35 GHz and 45 GHz. It should be noted that the first phase-output frequency simulation line obtained above is based on an initialized LC resonant cavity including the parasitic capacitance of the injection-locked circuit.

[0038] Based on the above embodiments, optionally, the first circuit is simulated to obtain a second simulation result, including: inputting a second impedance at the first simulation interface terminal with the injection structure and the second simulation interface terminal with the injection structure to obtain the second simulation result.

[0039] Specifically, the second simulation results include the second phase-output frequency simulation line; The steps for determining the first parasitic capacitance of the injection structure include: adjusting the capacitance value of each second capacitor until the second phase-output frequency simulation line and the first phase-output frequency simulation line coincide, recording the capacitance value of the second capacitor as the first adjustment capacitance value; and determining the first parasitic capacitance of the injection structure based on the first adjustment capacitance value and the second capacitance value.

[0040] The first parasitic capacitance of the injection structure is equal to the difference between the second capacitance value and the first adjustment capacitance value.

[0041] For example, Figure 6 for Figure 3 A schematic diagram of the second phase-output frequency simulation line of the first circuit shown. Figure 6 As shown, the phase response of the second impedance is represented by the blue curve. Compared to the black curve, the blue curve shows a downward drift, indicating a narrowing of the target operating frequency range. To address this, the capacitance value of the second capacitor is gradually decreased to gradually adjust the phase response of the second impedance. For example, when the capacitance value of the second capacitor is adjusted to 105 fF (the first adjustment capacitance value), the blue curve matches the black curve. Therefore, the first parasitic capacitance introduced into the LC resonant cavity by the injection structure is 23 fF (first parasitic capacitance 23 fF = second capacitance value 128 fF - first adjustment capacitance value 105 fF).

[0042] Optionally, based on the above embodiments, the second circuit is simulated to obtain a third simulation result, including: inputting a third impedance at the first simulation interface terminal and the second simulation interface terminal of the first circuit with a locking structure to obtain the third simulation result.

[0043] Specifically, the third simulation result includes the third phase-output frequency simulation line; The steps for determining the second parasitic capacitance of the locking structure include: obtaining an initial target operating frequency based on the target operating frequency range; adjusting the capacitance value of the second capacitor until the zero-crossing frequency of the third phase-output frequency simulation line is equal to the initial target operating frequency, recording the capacitance value of the second capacitor as the second adjustment capacitance value; and determining the second parasitic capacitance of the locking structure based on the first adjustment capacitance value and the second adjustment capacitance value.

[0044] In this case, the second parasitic capacitance of the locking structure is equal to the difference between the first adjustment capacitance value and the second adjustment capacitance value.

[0045] For example, Figure 7 for Figure 4 A schematic diagram of the simulation line for the third phase-output frequency of the second circuit shown. Figure 7As shown, the capacitance value of the second capacitor is the actual capacitance value after the second circuit eliminates the first parasitic capacitance. The phase response of the third impedance is represented by the green curve, with a steep phase curve that rapidly crosses zero near 25 GHz, a frequency point that is significantly off from the desired target operating frequency range. To address this, the capacitance value of the second capacitor is reduced, gradually adjusting the phase response of the third impedance. For example, when the capacitance value of the second capacitor is adjusted to 18 fF (the second adjustment capacitance value), the phase response of the green curve will shift to the position of the blue curve and change the zero-crossing point to 35 GHz (the initial target operating frequency). Therefore, the second parasitic capacitance of the locked structure is 87 fF (second parasitic capacitance 87 fF = first adjustment capacitance value 105 fF - second adjustment capacitance value 18 fF).

[0046] Figure 8 This is a schematic diagram of the structure of an evaluation device for the parasitic capacitance of an injection-locked circuit provided in an embodiment of the present invention, as shown below. Figure 8 As shown, the evaluation apparatus for the parasitic capacitance of the injection lock circuit includes: The first simulation module 10 is used to determine the device parameters of the LC resonator according to the target operating frequency range, and to simulate the LC resonator with the device parameters loaded to obtain the first simulation result. The LC resonator includes a first inductor, a second inductor, a first capacitor, two second capacitors and a resistor. The first end of the first inductor and the first end of the first capacitor are both connected to the first end of the resistor. The second end of the resistor is grounded. The second end of the first inductor and the second end of the first capacitor are grounded together. The first inductor and the second inductor are coupled. The first end of the second inductor is connected to the first end of the first second capacitor and serves as the first simulation interface of the LC resonator. The second end of the first second capacitor is connected to the first end of the second second capacitor. The second end of the second inductor is connected to the second end of the second second capacitor and serves as the second simulation interface of the LC resonator. The first parasitic capacitance determination module 20 is used to load an injection structure at the first simulation interface and the second simulation interface of the LC resonant cavity to obtain a first circuit, simulate the first circuit to obtain a second simulation result, and adjust the second simulation result according to the first simulation result to determine the first parasitic capacitance of the injection structure. The second parasitic capacitance determination module 30 is used to load a locking structure between the first simulation interface terminal and the second simulation interface terminal of the first circuit to obtain the second circuit, simulate the second circuit to obtain the third simulation result, and adjust the third simulation result according to the target operating frequency range to determine the second parasitic capacitance of the locking structure.

[0047] In this embodiment of the invention, the first simulation module 10 determines the device parameters of the LC resonator based on the target operating frequency range, and simulates the LC resonator with the device parameters applied to obtain a first simulation result, which serves as a benchmark result. The first parasitic capacitance determination module 20 loads an injection structure at the first and second simulation interface terminals of the LC resonator to obtain a first circuit, simulates the first circuit to obtain a second simulation result, and adjusts the second simulation result based on the first simulation result to make the first simulation result consistent with the second simulation result, thereby determining the first parasitic capacitance of the injection structure based on the adjustment result. The second parasitic capacitance determination module 30 loads a locking structure between the first and second simulation interface terminals of the first circuit to obtain a second circuit, simulates the second circuit to obtain a third simulation result, and adjusts the zero-crossing point of the third simulation result to be equal to the initial target operating frequency of the target operating frequency range, thereby determining the second parasitic capacitance of the locking structure based on the adjustment result. Thus, this solution achieves accurate evaluation of the parasitic capacitance of the injection-locked circuit.

[0048] Based on the above embodiments, optionally, the first simulation result includes a first phase-output frequency simulation line; the device parameters include a first inductance value, a second inductance value, a first capacitance value, a second capacitance value, and a coupling coefficient between the first inductance and the second inductance.

[0049] Based on the above embodiments, optionally, the first simulation module is specifically used to input a first impedance at the first simulation interface terminal and the second simulation interface terminal to obtain a first phase-output frequency simulation line.

[0050] Based on the above embodiments, optionally, the second simulation result includes a second phase-output frequency simulation line; The first parasitic capacitance determination module is specifically used for: A second impedance is input at the first simulation interface terminal with the injection structure loaded and the second simulation interface terminal with the injection structure loaded to obtain the second simulation result; Adjust the capacitance value of each second capacitor until the second phase-output frequency simulation line coincides with the first phase-output frequency simulation line, and record the capacitance value of the second capacitor as the first adjustment capacitor value. The first parasitic capacitance of the injection structure is determined based on the first adjustment capacitance value and the second capacitance value. The first parasitic capacitance of the injection structure is equal to the difference between the second capacitance value and the first adjustment capacitance value.

[0051] Based on the above embodiments, optionally, the third simulation result includes a third phase-output frequency simulation line; The second parasitic capacitance determination module is specifically used for: A third impedance is input at the first simulation interface terminal and the second simulation interface terminal of the first circuit with a locking structure to obtain a third simulation result. Obtain the initial target operating frequency based on the target operating frequency range; Adjust the capacitance value of the second capacitor until the zero-crossing frequency of the third phase-output frequency simulation line equals the initial target operating frequency, and record the capacitance value of the second capacitor as the second adjustment capacitor value. The second parasitic capacitance of the locking structure is determined based on the first adjustment capacitance value and the second adjustment capacitance value. The second parasitic capacitance of the locking structure is equal to the difference between the first adjustment capacitance value and the second adjustment capacitance value.

[0052] For example, Figure 9 This is a schematic diagram of a multi-cavity structure for an injection-locked amplifier according to an embodiment of the present invention. Figure 10 for Figure 9 The graph shown illustrates the relationship between the inductance value and the output frequency of the injection-locked amplifier. Figure 11 for Figure 9 The diagram shows the relationship between the inductor configuration factor and coupling coefficient of the injection-locked amplifier and the output frequency. Figure 12 for Figure 9 The amplitude response diagrams of the high-frequency and low-frequency subbands at the input of the injection-locked amplifier are shown. Figure 13 for Figure 9 The phase response diagrams of the high-frequency and low-frequency subbands of the injection-locked amplifier at the multi-cavity input are shown.

[0053] Figure 9 For the optimized fourth-order resonant cavity layout, metals 7 and 8 are made of copper with thicknesses of 0.9 μm and 3.3 μm, respectively, and metal 9 is made of aluminum with a thickness of 1.325 μm. The ratio of primary to secondary coils is 2:1. The two coils are coupled in a stacked manner, and the coupling coefficient is 0.59 at 40 GHz. The resonant cavity is a regular octagon with a maximum diameter of 68 μm. Figure 10 To simulate the relationship between the inductance values ​​of inductors L1 and L2 and the frequency in a resonant cavity. Figure 11 To simulate the configuration factor and coupling coefficient of the resonant cavity, the configuration factor of inductor L1 reaches a maximum of 17 at 30 GHz, and the configuration factor of inductor L2 reaches a maximum of 15.2 at 45 GHz.

[0054] To achieve dual-band amplification output for millimeter-wave 5G, the lock-in amplifier was designed with a lock-in range of 24-45 GHz during simulation to avoid narrowing of the lock-in range due to inter-stage matching or process variations. For a fourth-order resonant cavity, the input impedance phase response has a limited span near 0°, and designing only one lock-in sub-band cannot fully cover the 5G millimeter-wave frequency band. Therefore, switched capacitors C1 and C3 were added across the resonator inductors L1 and L2, switching them to achieve different lock-in bands. When C1 and C3 are off, the simulated amplitude and phase response of the resonant cavity input impedance are as follows: Figure 12 and Figure 13 The black curve is designed to meet the output power amplification requirements of 24-30GHz. When switched capacitors C1 and C3 are turned on, the amplitude and phase response of the resonant cavity input impedance increase due to parasitic expansion. Figure 12 and Figure 13 The red curve is used to meet the output power amplification requirements of 30-45GHz.

[0055] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0056] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A method for evaluating the parasitic capacitance of an injection-locked circuit, characterized in that, include: The device parameters of the LC resonator are determined according to the target operating frequency range, and the LC resonator with the device parameters loaded is simulated to obtain the first simulation result; The LC resonant cavity includes a first inductor, a second inductor, a first capacitor, two second capacitors, and a resistor. The first end of the first inductor and the first end of the first capacitor are both connected to the first end of the resistor. The second end of the resistor is grounded. The second end of the first inductor and the second end of the first capacitor share a common ground. The first inductor and the second inductor are coupled. The first end of the second inductor is connected to the first end of the first second capacitor and serves as the first simulation interface of the LC resonant cavity. The second end of the first second capacitor is connected to the first end of the second second capacitor. The second end of the second inductor is connected to the second end of the second second capacitor and serves as the second simulation interface of the LC resonant cavity. An injection structure is loaded at the first simulation interface and the second simulation interface of the LC resonant cavity to obtain a first circuit. The first circuit is simulated to obtain a second simulation result. The second simulation result is adjusted according to the first simulation result to determine the first parasitic capacitance of the injection structure. A locking structure is loaded between the first simulation interface and the second simulation interface of the first circuit to obtain a second circuit. The second circuit is simulated to obtain a third simulation result. The third simulation result is adjusted according to the target operating frequency range to determine the second parasitic capacitance of the locking structure.

2. The method for evaluating the parasitic capacitance of the injection-locked circuit according to claim 1, characterized in that, The first simulation result includes the first phase-output frequency simulation line; The device parameters include a first inductance value, a second inductance value, a first capacitance value, a second capacitance value, and a coupling coefficient between the first inductance and the second inductance.

3. The method for evaluating the parasitic capacitance of the injection-locked circuit according to claim 2, characterized in that, The step of simulating the LC resonant cavity with the device parameters loaded to obtain the first simulation result includes: Input a first impedance at the first simulation interface terminal and the second simulation interface terminal to obtain the first phase-output frequency simulation line.

4. The method for evaluating the parasitic capacitance of the injection-locked circuit according to claim 2, characterized in that, The step of simulating the first circuit to obtain the second simulation result includes: A second impedance is input at the first simulation interface terminal with the injection structure loaded and the second simulation interface terminal with the injection structure loaded, so as to obtain the second simulation result; The injection structure includes a third capacitor, a first transistor, and a second transistor; The first terminal of the third capacitor serves as the input terminal of the first circuit. The second terminal of the third capacitor is connected to the control terminal of the first transistor. The first electrode of the first transistor is grounded. The second electrode of the first transistor and the first electrode of the second transistor are connected. The control terminal of the second transistor is connected to the first potential. The second electrode of the second transistor is connected to either the first simulation interface terminal or the second simulation interface terminal.

5. The method for evaluating the parasitic capacitance of the injection-locked circuit according to claim 2, characterized in that, The second simulation result includes the second phase-output frequency simulation line; The step of determining the first parasitic capacitance of the injection structure includes: Adjust the capacitance value of each of the second capacitors until the second phase-output frequency simulation line and the first phase-output frequency simulation line coincide, and record the capacitance value of the second capacitor as the first adjustment capacitance value; The first parasitic capacitance of the injection structure is determined based on the first adjustment capacitance value and the second capacitance value.

6. The method for evaluating the parasitic capacitance of the injection-locked circuit according to claim 5, characterized in that, Determining the first parasitic capacitance of the injection structure based on the first adjustment capacitance value and the second capacitance value includes: The first parasitic capacitance of the injection structure is equal to the difference between the second capacitance value and the first adjustment capacitance value.

7. The method for evaluating the parasitic capacitance of the injection-locked circuit according to claim 2, characterized in that, The step of simulating the second circuit to obtain the third simulation result includes: A third impedance is input to the first simulation interface terminal and the second simulation interface terminal of the first circuit where the locking structure is loaded, in order to obtain the third simulation result; The locking structure includes a third transistor, a fourth transistor, and a fifth transistor; The control terminal of the fifth transistor is connected to the second potential, the first terminal of the fifth transistor is grounded, the first terminals of the third transistor and the fourth transistor are both connected to the second terminal of the fifth transistor, the second terminal of the third transistor and the control terminal of the fourth transistor are both connected to the first simulation interface terminal, and the second terminal of the fourth transistor and the control terminal of the third transistor are both connected to the second simulation interface terminal.

8. The method for evaluating the parasitic capacitance of the injection-locked circuit according to claim 5, characterized in that, The third simulation result includes the third phase-output frequency simulation line; The step of determining the second parasitic capacitance of the locking structure includes: The initial target operating frequency is obtained based on the target operating frequency range; Adjust the capacitance value of the second capacitor until the zero-crossing frequency of the third phase-output frequency simulation line is equal to the initial target operating frequency, and record the capacitance value of the second capacitor as the second adjustment capacitor value; The second parasitic capacitance of the locking structure is determined based on the first adjustment capacitance value and the second adjustment capacitance value.

9. The method for evaluating the parasitic capacitance of the injection-locked circuit according to claim 8, characterized in that, Determining the second parasitic capacitance of the locking structure based on the first adjustment capacitance value and the second adjustment capacitance value includes: The second parasitic capacitance of the locking structure is equal to the difference between the first adjustment capacitance value and the second adjustment capacitance value.

10. An evaluation device for parasitic capacitance of an injection-locked circuit, characterized in that, include: The first simulation module is used to determine the device parameters of the LC resonator according to the target operating frequency range, and to simulate the LC resonator with the device parameters loaded to obtain a first simulation result. The LC resonator includes a first inductor, a second inductor, a first capacitor, two second capacitors, and a resistor. The first end of the first inductor and the first end of the first capacitor are both connected to the first end of the resistor. The second end of the resistor is grounded. The second end of the first inductor and the second end of the first capacitor share a common ground. The first inductor and the second inductor are coupled. The first end of the second inductor is connected to the first end of the first second capacitor and serves as the first simulation interface of the LC resonator. The second end of the first second capacitor is connected to the first end of the second second capacitor. The second end of the second inductor is connected to the second end of the second second capacitor and serves as the second simulation interface of the LC resonator. The first parasitic capacitance determination module is used to load an injection structure onto the first simulation interface and the second simulation interface of the LC resonant cavity to obtain a first circuit, simulate the first circuit to obtain a second simulation result, and adjust the second simulation result according to the first simulation result to determine the first parasitic capacitance of the injection structure. The second parasitic capacitance determination module is used to load a locking structure between the first simulation interface terminal and the second simulation interface terminal of the first circuit to obtain a second circuit, simulate the second circuit to obtain a third simulation result, and adjust the third simulation result according to the target operating frequency range to determine the second parasitic capacitance of the locking structure.

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