Nitride semiconductor epitaxial wafer, method for manufacturing the same, and optoelectronic device

Abstract

This invention relates to a nitride semiconductor epitaxial wafer, its fabrication method, and optoelectronic devices. The nitride semiconductor epitaxial wafer comprises a growth substrate, an n-type nitride layer, a nitride diffusion layer, a composite light-emitting layer, a nitride barrier layer, and a p-type nitride layer, stacked sequentially. The composite light-emitting layer comprises spaced nanopillar spacers and light-emitting units disposed between adjacent nanopillar spacers. The nanopillar spacers separate the light-emitting units, making the light-emitting units nanostructured. This not only reduces the stress in the light-emitting layer within the light-emitting units and improves the composition incorporation and uniformity of the epitaxial layer, but also utilizes the quantum size confinement effect to reduce QCSE, improve the radiative recombination efficiency of electrons and holes, and reduce the carrier trapping effect caused by sidewall damage. This improves the luminous efficiency and brightness of the nitride semiconductor epitaxial wafer, reduces the full width at half maximum (FWHM) of the emission wavelength, and enhances the color purity for display applications.

Description

Technical Field

[0001] This invention belongs to the field of optoelectronic device technology, and relates to an epitaxial wafer structure, particularly to a nitride semiconductor epitaxial wafer, its preparation method, and an optoelectronic device. Background Technology

[0002] Micro-LEDs (Micro Light Emitting Diodes) consist of micrometer-scale arrays of semiconductor light-emitting units. They offer advantages such as small size, high resolution, and high reliability, and are widely used in visible light communication, large flat panel displays, virtual reality and wearable displays, televisions, lighting, optogenetics, and neural interface light sources. For nitride Micro-LEDs, a combination of standard photolithography and dry etching is typically used for fabrication. However, the dry etching process inevitably causes surface damage to the Micro-LED chip, increasing the surface nonradiative recombination rate and reducing the internal quantum efficiency, which in turn reduces the chip's external quantum efficiency. Furthermore, due to the small size of Micro-LEDs, surface damage caused by dry etching has a more significant impact on the chip's photoelectric performance, severely affecting its luminous efficiency. Simultaneously, the nitride emissive layer requires a heterostructure as the quantum well and quantum barrier. The large lattice and thermal expansion mismatch between the quantum well and quantum barrier leads to a high dislocation density and high stress in the nitride emissive layer, resulting in high nonradiative recombination and severely impacting the brightness and luminous efficiency of the Micro-LED.

[0003] Therefore, there is an urgent need for an epitaxial wafer with high luminous brightness and luminous efficiency. Summary of the Invention

[0004] The purpose of this invention is to provide a nitride semiconductor epitaxial wafer, its preparation method, and an optoelectronic device. This invention reduces the stress in the light-emitting structural units of the nitride semiconductor epitaxial wafer, improves component integration and uniformity, and can also utilize the quantum size confinement effect to reduce the Stark effect (QCSE), reduce the stress distribution in the light-emitting structural units, improve the radiative recombination efficiency of electrons and holes in the light-emitting structural units, and reduce the carrier trapping effect caused by sidewall damage. This improves the luminous efficiency and brightness of the nitride semiconductor epitaxial wafer, and can also improve color purity by reducing the half-width at half-maximum (WHM) of the emission wavelength.

[0005] To achieve this objective, the present invention adopts the following technical solution:

[0006] In a first aspect, the present invention provides a nitride semiconductor epitaxial wafer, the nitride semiconductor epitaxial wafer comprising a growth substrate, an n-type nitride layer, a nitride diffusion layer, a composite light-emitting layer, a nitride barrier layer and a p-type nitride layer stacked sequentially.

[0007] The composite light-emitting layer includes spaced nanopillar spacer units and light-emitting units disposed between adjacent nanopillar spacer units.

[0008] The nanopillar spacer unit includes a nanopillar, a top unit disposed on the top surface of the nanopillar, and a side unit disposed on the sidewall of the nanopillar. The surface of the nanopillar in contact with the top unit is a horizontal plane.

[0009] The light-emitting unit includes at least a first light-emitting structural unit and a second light-emitting structural unit stacked together, wherein the first light-emitting structural unit is used to perform lattice modulation on the nitride diffusion layer and the second light-emitting structural unit.

[0010] The p-type nitride layer is disposed on the surface of the nitride barrier layer.

[0011] The nitride semiconductor epitaxial wafer provided by this invention, through the arrangement of nanopillar spacers, enables the nanopillar spacers to separate the light-emitting units, making the light-emitting units nanostructured. On the one hand, this reduces the stress in the light-emitting units and improves the composition incorporation and uniformity of the epitaxial layer. On the other hand, it utilizes the quantum size confinement effect to reduce QCSE, decrease the stress distribution in the light-emitting units, improve the radiative recombination efficiency of electrons and holes in the light-emitting units, and reduce the carrier trapping effect caused by sidewall damage, thereby improving the luminous efficiency and brightness of the nitride semiconductor epitaxial wafer. In addition, it can also reduce the full width at half maximum (FWHM) of the emission wavelength and improve color purity.

[0012] Preferably, the nitride semiconductor epitaxial wafer further includes a nitride merging layer, which covers the second light-emitting structural unit and merges above the nanopillar spacer unit, with a gap between the nitride merging layer and the nanopillar spacer unit.

[0013] Preferably, the nitride barrier layer includes a first nitride barrier layer closest to the nitride diffusion layer and a second nitride barrier layer furthest from the nitride diffusion layer; the first nitride barrier layer covers the nitride merging layer.

[0014] Preferably, the nanopillars are made of silicon.

[0015] Preferably, the top unit is made of aluminum oxide.

[0016] Preferably, the side unit is made of silicon oxide.

[0017] Preferably, the height of the nanopillars is 10 nm to 200 nm.

[0018] Preferably, the height of the nanopillar is not higher than the height of the first light-emitting structural unit.

[0019] Preferably, the distance between any two adjacent nanopillar spacer units is 100 nm to 500 nm.

[0020] Secondly, the present invention provides a method for preparing a nitride semiconductor epitaxial wafer, the method comprising the following steps:

[0021] An n-type nitride layer, a nitride diffusion layer, a composite light-emitting layer, and a nitride barrier layer are sequentially fabricated on the surface of a growth substrate. The composite light-emitting layer includes spaced nanopillar spacers and light-emitting units disposed between adjacent nanopillar spacers. Each nanopillar spacer includes a nanopillar, a top unit disposed on the top surface of the nanopillar, and a side unit disposed on the sidewall of the nanopillar. The surface of the nanopillar in contact with the top unit is horizontal. Each light-emitting unit includes at least a first light-emitting structural unit and a second light-emitting structural unit stacked together. The first light-emitting structural unit is used to modulate the lattice of the nitride diffusion layer and the second light-emitting structural unit.

[0022] A p-type nitride layer is prepared on the surface of the nitride barrier layer.

[0023] Preferably, the nitride merging layer covers the second luminescent structural unit and is merged above the nanopillar spacer unit.

[0024] Preferably, the nitride barrier layer includes a first nitride barrier layer and a second nitride barrier layer.

[0025] The method for preparing the nitride barrier layer includes:

[0026] The first nitride barrier layer is prepared on the nitride merging layer.

[0027] The second nitride barrier layer is prepared on the first nitride barrier layer.

[0028] Preferably, the method for preparing the nitride merging layer includes: introducing a Ga source with a flow rate of 10 sccm to 60 sccm and an N source with a flow rate of 40 sccm to 100 sccm at a temperature of 1100°C to 1250°C and a pressure of 50 to 100 torr, to grow a layer with a thickness of 40 nm to 120 nm and a Mg doping concentration of 2 × 10⁻⁶. 19 cm -3 Up to 7×10 20 cm -3 The nitride merging layer.

[0029] Preferably, the method for preparing the first nitride barrier layer includes: introducing an aluminum source with a flow rate of 20 sccm to 200 sccm and a nitrogen source with a flow rate of 1 slm to 10 slm under conditions of a temperature of 950°C to 1050°C and a pressure of 50 torr to 150 torr, and growing a first nitride barrier layer with a thickness of 2 nm to 5 nm.

[0030] Preferably, the method for preparing the second nitride barrier layer includes: introducing a Ga source with a flow rate of 30 sccm to 150 sccm, an aluminum source with a flow rate of 20 sccm to 200 sccm, and a nitrogen source with a flow rate of 20 slm to 50 slm at a temperature of 950°C to 1050°C and a pressure of 100 torr to 300 torr, to grow a second nitride barrier layer with a thickness of 5 nm to 20 nm.

[0031] Preferably, the composite light-emitting layer includes spaced nanopillar spacer units and light-emitting units disposed between adjacent nanopillar spacer units.

[0032] The method for preparing the composite light-emitting layer includes:

[0033] The nanopillar spacer unit is prepared on the surface of the nitride diffusion layer.

[0034] The light-emitting unit is prepared between adjacent nanopillar spacer units.

[0035] Preferably, the fabrication of the light-emitting unit between adjacent nanopillar spacer units includes:

[0036] A first luminescent structural unit is grown on the surface of the nitride diffusion layer between the nanopillar spacer units.

[0037] A second light-emitting structural unit is grown on the surface of the first light-emitting structural unit to obtain the light-emitting unit.

[0038] Preferably, a first light-emitting structural unit is grown on the surface of the nitride diffusion layer between the nanopillar spacer units, comprising:

[0039] A11. Under conditions of temperature of 800℃ to 950℃ and pressure of 200 torr to 400 torr, a gallium source with a flow rate of 100 sccm to 500 sccm, an indium source with a flow rate of 500 sccm to 2000 sccm, and a nitrogen source with a flow rate of 50 slm to 100 slm are introduced to grow a first quantum well layer with a thickness of 2 nm to 5 nm.

[0040] A12. Under conditions of temperature of 800℃ to 950℃ and pressure of 200 torr to 400 torr, a gallium source with a flow rate of 100 sccm to 500 sccm and a nitrogen source with a flow rate of 50 slm to 100 slm are introduced to grow a first quantum barrier layer with a thickness of 3 nm to 25 nm.

[0041] A13. The first light-emitting structural unit is obtained by periodically and alternately executing A11 and A12 2 to 8 times.

[0042] Preferably, the step of setting the second light-emitting structural unit on the surface of the first light-emitting structural unit includes:

[0043] A21. Under conditions of temperature from 650°C to 850°C and pressure from 200 to 400 tor, a gallium source with a flow rate of 100 to 500 tor, an indium source with a flow rate of 500 to 2000 sccm, and a nitrogen source with a flow rate of 50 slm to 100 slm are introduced to grow a second quantum well layer with a thickness of 2 nm to 5 nm.

[0044] A22. Under conditions of temperature of 750℃ to 950℃ and pressure of 200 torr to 400 torr, a gallium source with a flow rate of 100 sccm to 500 sccm and a nitrogen source with a flow rate of 50 slm to 100 slm are introduced to grow a second quantum barrier layer with a thickness of 3 nm to 15 nm.

[0045] A23. The second light-emitting structural unit is obtained by periodically and alternately executing A21 and A22 2 to 15 times.

[0046] Preferably, the fabrication of the nanopillar spacer unit on the surface of the nitride diffusion layer includes:

[0047] S1. An aluminum metal layer with a thickness of 10 nm to 100 nm is grown on the surface of the nitride diffusion layer. Then, the aluminum metal layer is annealed for 60 s to 300 s at a temperature of 700 °C to 1000 °C and a pressure of 50 to 150 to 150 to 150 to form nanospheres with a spacing of 100 nm to 500 nm and a diameter of 10 nm to 100 nm.

[0048] S2. The nanospheres are subjected to heat treatment for 5 to 60 minutes at a temperature of 700°C to 1000°C and a pressure of 200 to 600 tor, and then the heat treatment is interrupted for 100 to 600 seconds to obtain the microsphere structure.

[0049] S3. Growing nanopillars based on the microsphere structure.

[0050] S4. Post-process the nanopillars to obtain the nanopillar spacer units.

[0051] Preferably, the growth of nanopillars based on the microsphere structure includes:

[0052] S31. Under conditions of temperature of 700°C to 1000°C and pressure of 400 torr to 600 torr, a silicon source is introduced into the surface of the microsphere structure at a flow rate of 200 sccm to 800 sccm for 10 to 100 seconds.

[0053] S32, interrupt the silicon source supply for 10s to 180s.

[0054] S33, and S31 and S32 are periodically alternated to obtain the nanopillar.

[0055] Preferably, the top unit is an aluminum oxide layer, the side units are silicon oxide layers, and the post-processing of the nanopillars to obtain the nanopillar spacer units includes:

[0056] S41. Under conditions of 400°C to 800°C and 200 torr to 600 torr, perform oxygen treatment for 60 to 120 seconds to form an aluminum oxide layer on the top surface of the nanopillar and a silicon oxide layer on the sidewall of the nanopillar.

[0057] S42. Under conditions of temperature of 400°C to 800°C and pressure of 200 torr to 600 torr, perform hydrogen treatment for 20 to 60 seconds to decompose the oxygen element on the surface of the nitride diffusion layer between adjacent nanopillar spacer units.

[0058] S43, S41 and S42 are periodically cyclically alternated 20 to 100 times to obtain the nanopillar spacer unit.

[0059] Preferably, the method for preparing the n-type nitride layer includes:

[0060] Under conditions of temperature ranging from 1070°C to 1250°C and pressure ranging from 100 to 300 torr, a Si doping concentration of 1 × 10⁻⁶ m thick is grown on the growth substrate. 18 Up to 5×10 19 cm -3 The n-type nitride layer.

[0061] Preferably, the method for preparing the nitride diffusion layer includes:

[0062] A nitride diffusion layer with a thickness of 10 nm to 50 nm is grown on the n-type nitride layer under conditions of temperature of 1020 °C to 1220 °C and pressure of 100 torr to 300 torr.

[0063] The method for preparing the p-type nitride layer includes:

[0064] Under conditions of 850°C to 1050°C and 200 torr to 500 torr, a gallium source with a flow rate of 100 sccm to 1000 sccm and a nitrogen source with a flow rate of 20 slm to 80 slm are introduced to grow a nitride barrier layer with a thickness of 20 nm to 200 nm and a Mg doping concentration of 1 × 10⁻⁶. 19 cm -3 Up to 5×10 20 cm -3 The p-type nitride layer.

[0065] Preferably, the silicon source in this invention can be SiH4, the nitrogen source can be NH3, the gallium source can be trimethylgallium (TMGa), and the indium source can be trimethylindium (TMIn).

[0066] Thirdly, the present invention provides an optoelectronic device, the optoelectronic device comprising the nitride semiconductor epitaxial wafer described in the first aspect, or comprising the nitride semiconductor epitaxial wafer prepared by the preparation method described in the second aspect.

[0067] Compared with the prior art, the present invention has the following beneficial effects:

[0068] The nitride semiconductor epitaxial wafer provided by this invention, through the arrangement of nanopillar spacers, enables the nanopillar spacers to separate the light-emitting units, making the light-emitting units nanostructured. On the one hand, this reduces the stress in the light-emitting units and improves the composition incorporation and uniformity of the epitaxial layer. On the other hand, it utilizes the quantum size confinement effect to reduce QCSE, decrease the stress distribution in the light-emitting units, improve the radiative recombination efficiency of electrons and holes in the light-emitting units, and reduce the carrier trapping effect caused by sidewall damage, thereby improving the luminous efficiency and brightness of the nitride semiconductor epitaxial wafer. In addition, it can also reduce the full width at half maximum (FWHM) of the emission wavelength and improve color purity. Attached Figure Description

[0069] Figure 1 This is a schematic diagram of the structure of the nitride semiconductor epitaxial wafer provided in Embodiment 1 of the present invention.

[0070] Figure 2 This is a schematic diagram of the structure of the nitride semiconductor epitaxial wafer provided in Comparative Example 3 of the present invention.

[0071] Wherein: 1, growth substrate; 2, n-type nitride layer; 3, nitride diffusion layer; 4, first light-emitting structural unit; 5, second light-emitting structural unit; 6, first nitride barrier layer; 7, second nitride barrier layer; 8, p-type nitride layer; 9, nanopillar; 10, side unit; 11, top unit; 12, nitride merging layer. Detailed Implementation

[0072] The technical solution of the present invention will be further illustrated below through specific embodiments. Those skilled in the art should understand that the embodiments described are merely illustrative of the present invention and should not be construed as limiting the invention in any way.

[0073] The present invention provides a nitride semiconductor epitaxial wafer, which includes a growth substrate, an n-type nitride layer, a nitride diffusion layer, a composite light-emitting layer, a nitride barrier layer and a p-type nitride layer stacked sequentially.

[0074] The composite light-emitting layer includes spaced nanopillar spacer units and light-emitting units disposed between adjacent nanopillar spacer units.

[0075] The nanopillar spacer unit includes a nanopillar, a top unit disposed on the top surface of the nanopillar, and a side unit disposed on the sidewall of the nanopillar. The surface in contact between the nanopillar and the top unit is a horizontal plane.

[0076] The light-emitting unit includes at least a first light-emitting structural unit and a second light-emitting structural unit stacked together, wherein the first light-emitting structural unit is used to perform lattice modulation on the nitride diffusion layer and the second light-emitting structural unit.

[0077] The p-type nitride layer is disposed on the surface of the nitride barrier layer.

[0078] The nitride semiconductor epitaxial wafer provided by this invention, through the arrangement of nanopillar spacers, enables the nanopillar spacers to separate the light-emitting units, making the light-emitting units nanostructured. On the one hand, this reduces the stress in the light-emitting units and improves the composition incorporation and uniformity of the epitaxial layer. On the other hand, it utilizes the quantum size confinement effect to reduce QCSE, decrease the stress distribution in the light-emitting units, improve the radiative recombination efficiency of electrons and holes in the light-emitting units, and reduce the carrier trapping effect caused by sidewall damage, thereby improving the luminous efficiency and brightness of the nitride semiconductor epitaxial wafer. In addition, it can also reduce the full width at half maximum (FWHM) of the emission wavelength and improve color purity.

[0079] In the nitride semiconductor epitaxial wafer provided by the present invention, the nitride diffusion layer enables Si atoms on the surface of the nitride diffusion layer between adjacent nanopillar spacer units to form a uniform diffusion in the nitride diffusion layer.

[0080] In some embodiments, the nitride semiconductor epitaxial wafer further includes a nitride merging layer that covers the second light-emitting structural unit and is merged above the nanopillar spacer unit, with a gap between the nitride merging layer and the nanopillar spacer unit.

[0081] In some embodiments, the nitride barrier layer includes a first nitride barrier layer closest to the nitride diffusion layer and a second nitride barrier layer furthest from the nitride diffusion layer; the first nitride barrier layer covers the nitride merging layer.

[0082] In this invention, the first nitride barrier layer provides a template for the growth of the second nitride barrier layer; while the second nitride barrier layer prevents the recombination luminescence that occurs when the charge carriers overflow across the second luminescent structural unit to the p-type nitride layer, thereby improving the confinement capability of the charge carriers in the second luminescent structural unit.

[0083] In some embodiments, the nanopillars are made of silicon.

[0084] In some embodiments, the top unit is made of aluminum oxide.

[0085] In some embodiments, the side unit is made of silicon oxide.

[0086] In some embodiments, the height of the nanopillars is from 10 nm to 200 nm, for example, it can be 10 nm, 30 nm, 50 nm, 75 nm, 100 nm, 125 nm, 150 nm, 175 nm or 200 nm, but is not limited to the listed values, and other unlisted values ​​within the range are also applicable.

[0087] In some embodiments, the height of the nanopillars is not higher than the height of the first light-emitting structural unit.

[0088] During the epitaxial growth of nitride materials, it is difficult to completely cover the sidewalls of the nanopillars with nitride. Therefore, the first light-emitting structure in contact with the SiN sidewall capping layer will form a carrier trapping center. In this invention, the height of the nanopillars is no higher than the height of the first light-emitting structural unit, which can reduce the sidewall carrier trapping effect of the second light-emitting structural unit as the main light-emitting structural unit, and is beneficial to improving the brightness and luminous efficiency of the nitride semiconductor epitaxial wafer.

[0089] In some embodiments, the distance between any two adjacent nanopillar spacers is 100 nm to 500 nm, for example, it can be 100 nm, 150 nm, 200 nm, 250 nm, 300 nm, 350 nm, 400 nm, 450 nm or 500 nm, but is not limited to the listed values. Other unlisted values ​​within the range are also applicable.

[0090] The present invention also provides a method for preparing a nitride semiconductor epitaxial wafer, the method comprising the following steps:

[0091] S11: An n-type nitride layer, a nitride diffusion layer, a composite light-emitting layer, and a nitride barrier layer are sequentially prepared on the surface of the growth substrate.

[0092] The composite light-emitting layer includes spaced nanopillar spacer units and light-emitting units disposed between adjacent nanopillar spacer units. Each nanopillar spacer unit includes a nanopillar, a top unit disposed on the top surface of the nanopillar, and side units disposed on the sidewalls of the nanopillar. The surface of the nanopillar in contact with the top unit is horizontal. Each light-emitting unit includes at least a first light-emitting structural unit and a second light-emitting structural unit stacked together. The first light-emitting structural unit is used to modulate the lattice of the nitride diffusion layer and the second light-emitting structural unit.

[0093] S12: Prepare a p-type nitride layer on the surface of the nitride barrier layer.

[0094] In some embodiments, the method for preparing the n-type nitride layer includes: growing a layer with a thickness of 1 μm to 5 μm and a Si doping concentration of 1 × 10⁻⁶ on a growth substrate at a temperature of 1070°C to 1250°C and a pressure of 100 torr to 300 torr. 18 cm -3 Up to 5×10 19 cm -3 The n-type nitride layer.

[0095] The temperature for preparing the n-type nitride layer is between 1070℃ and 1250℃, for example, 1070℃, 1100℃, 1150℃, 1200℃ or 1250℃.

[0096] The pressure for preparing the n-type nitride layer is 100 torr to 300 torr, for example, it can be 100 torr, 150 torr, 200 torr, 250 torr or 300 torr.

[0097] The thickness of the prepared n-type nitride layer is 1 μm to 5 μm, for example, it can be 1 μm, 2 μm, 3 μm, 4 μm or 5 μm.

[0098] The Si doping concentration in the preparation of the n-type nitride layer is 1×10⁻⁶. 18 cm -3 Up to 5×10 19 cm -3 For example, it could be 1×10 18 cm -3 5×10 18 cm -3 1×10 19 cm -3 2×1019 cm -3 3×10 19 cm -3 4×10 19 cm -3 Or 5×10 19 cm -3 wait.

[0099] In some embodiments, the method for preparing the nitride diffusion layer includes growing a nitride diffusion layer with a thickness of 10 nm to 50 nm on an n-type nitride layer at a temperature of 1020 °C to 1220 °C and a pressure of 100 torr to 300 torr.

[0100] The temperature for preparing the nitride diffusion layer is between 1020℃ and 1220℃, for example, 1020℃, 1050℃, 1100℃, 1150℃, 1200℃ or 1220℃.

[0101] The pressure for preparing the nitride diffusion layer is 100 torr to 300 torr, for example, it can be 100 torr, 150 torr, 200 torr, 250 torr or 300 torr.

[0102] The thickness of the nitride diffusion layer is 10 nm to 50 nm, for example, it can be 10 nm, 20 nm, 30 nm, 40 nm or 50 nm.

[0103] In some embodiments, the composite light-emitting layer includes spaced nanopillar spacers and light-emitting units disposed between adjacent nanopillar spacers; the method for preparing the composite light-emitting layer includes: preparing nanopillar spacers on the surface of a nitride diffusion layer; and preparing light-emitting units between adjacent nanopillar spacers.

[0104] In some embodiments, nanopillar spacer units are fabricated on the surface of the nitride diffusion layer, including:

[0105] S1. An aluminum metal layer with a thickness of 10 μm to 100 nm is grown on the surface of the nitride diffusion layer. Then, the aluminum metal layer is annealed for 60 to 300 s at a temperature of 700 °C to 1000 °C and a pressure of 50 to 150 to 150 to 150 to form nanospheres with a spacing of 100 nm to 500 nm and a diameter of 10 nm to 100 nm.

[0106] The thickness of the aluminum metal layer is 10nm to 100nm, for example, it can be 10nm, 30nm, 50nm, 80nm or 100nm.

[0107] The annealing temperature is between 700℃ and 1000℃, for example, 700℃, 750℃, 800℃, 850℃, 900℃, 950℃, or 1000℃. The annealing pressure is between 50 torr and 150 torr, for example, 50 torr, 80 torr, 100 torr, 120 torr, or 150 torr. The annealing time is between 60s and 300s, for example, 60s, 100s, 150s, 200s, 250s, or 300s.

[0108] The spacing between the formed nanospheres is from 100 nm to 500 nm, for example, 100 nm, 200 nm, 300 nm, 400 nm, or 500 nm; in this invention, the spacing between the nanospheres refers to the closest distance between any two adjacent nanospheres. The diameter of the formed nanospheres is from 10 nm to 100 nm, for example, 10 nm, 20 nm, 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, or 100 nm.

[0109] S2. The nanospheres are heat-treated for 5 to 60 minutes at a temperature of 700℃ to 1000℃ and a pressure of 200 to 600 tor, and then the heat treatment is interrupted for 100 to 600 seconds to obtain the microsphere structure.

[0110] The heat treatment temperature is between 700℃ and 1000℃, for example, 700℃, 750℃, 800℃, 850℃, 900℃, 950℃, or 1000℃. The heat treatment pressure is between 200 torr and 600 torr, for example, 200 torr, 300 torr, 400 torr, 500 torr, or 600 torr. The heat treatment time is between 5 minutes and 60 minutes, for example, 5 minutes, 10 minutes, 20 minutes, 30 minutes, 40 minutes, or 60 minutes.

[0111] The interruption time for heat treatment is 100s to 600s, for example, it can be 100s, 200s, 300s, 500s or 600s.

[0112] Furthermore, the heat treatment can be Si heat treatment, and the microsphere structure is a metal-Si eutectic structure, that is, Si deposition is formed on the surface of the nanospheres. Interrupting the introduction of silicon source can form a metal-Si eutectic structure, which serves as a growth template for nanopillars.

[0113] S3. Nanopillars grown based on microsphere structure.

[0114] The nanopillars can be Si nanopillars. Si atoms required for Si nanopillars are introduced into the surface of the microsphere structure. The Si atoms dissolve and precipitate in the microsphere structure and grow axially to form Si nanopillars.

[0115] This invention utilizes the characteristic of silicon atoms dissolving and precipitating in micro / nano liquid metal structures, and then growing axially to form nanostructures. Si atoms are introduced onto the surface of the microsphere structure. These Si atoms dissolve under heat treatment, and with continued treatment, they undergo non-equilibrium diffusion growth on the surface of the microsphere structure, forming Si nanopillars. On one hand, a high concentration of Si atoms accumulates on the surface of the liquid metal structure, creating a large concentration difference between the surface and interior, meaning the surface has a high diffusion potential energy. Consequently, Si atoms continuously diffuse and precipitate from the high diffusion energy direction to the low diffusion energy direction along the concentration difference. On the other hand, Si atoms require higher saturation to precipitate from other locations on the surface, while precipitation at the interface between the liquid metal structure and the solid Si nanopillars precipitated at the bottom has the lowest diffusion energy. Therefore, Si atoms continuously diffuse along the concentration difference direction, precipitating from the bottom of the liquid metal, ultimately forming a bottom liquid-solid interface instead of forming liquid-solid interfaces in other directions to precipitate Si.

[0116] In some embodiments, the growth of nanopillars based on microsphere structures includes:

[0117] S31. Under conditions of temperature of 700℃ to 1000℃ and pressure of 400 torr to 600 torr, a silicon source is introduced into the surface of the microsphere structure at a flow rate of 200 sccm to 800 sccm for 10 s to 100 s.

[0118] The temperature can be 700℃, 800℃, 900℃ or 1000℃, etc., and the pressure can be 400 torr, 450 torr, 500 torr, 550 torr or 600 torr, etc.

[0119] The silicon source can be SiH4, and the flow rate of the silicon source can be 200 sccm, 300 sccm, 400 sccm, 500 sccm, 600 sccm, 700 sccm, or 800 sccm, etc. The time for introducing the silicon source can be 10s, 30s, 50s, 80s, or 100s, etc.

[0120] S32, interrupt the silicon source supply for 10s to 180s.

[0121] The interruption time of the silicon source can be 10s, 50s, 80s, 100s, 120s, 150s or 180s, etc.

[0122] S33, and S31 and S32 are periodically alternated to obtain nanopillars.

[0123] This invention does not specifically limit the number of times S31 and S32 are repeated, as long as the required height of the nanopillar can be obtained; for example, the number of repetitions of S31 and S32 can be 100-300 times.

[0124] During the periodic and alternating formation of nanopillars, the interruption of the silicon source allows silicon atoms to fully dissolve on the surface of the microsphere structure, resulting in the continuous and uniform precipitation of silicon atoms. This process achieves two main benefits: firstly, it produces nanopillars with smooth surfaces, ensuring the stability of the microsphere structure on the nanopillars; secondly, it enables uniform diffusion of silicon atoms on the surface of the nitride diffusion layer between adjacent nanopillars, reducing the phenomenon of silicon atoms absorbing light as impurities; and thirdly, it enhances the lateral expansion capability of charge carriers in the nitride semiconductor epitaxial wafer, improves the uniformity of charge carrier injection, and increases the brightness of the nitride semiconductor epitaxial wafer.

[0125] S4. Post-process the nanopillars to obtain nanopillar spacer units.

[0126] In some embodiments, the top unit is an aluminum oxide layer, the side units are silicon oxide layers, and post-processing of the nanopillars yields nanopillar spacer units, including:

[0127] S41. Under conditions of 400°C to 800°C and 200 torr to 600 torr, perform oxygen treatment for 60 to 120 seconds to form an aluminum oxide layer on the top surface of the nanopillar and a silicon oxide layer on the sidewall of the nanopillar.

[0128] Temperatures can be 400℃, 450℃, 500℃, 550℃, 600℃, 650℃, 700℃, 750℃, or 800℃, etc. Pressures can be 200 torr, 300 torr, 400 torr, 500 torr, or 600 torr, etc.

[0129] The oxygen treatment time can be 60s, 80s, 90s, 100s, or 120s, etc.

[0130] S42. Under conditions of 400°C to 800°C and 200 torr to 600 torr, perform hydrogen treatment for 20 to 60 seconds to decompose the oxygen element on the surface of the nitride diffusion layer between adjacent nanopillar spacer units.

[0131] Temperatures can be 400℃, 450℃, 500℃, 550℃, 600℃, 650℃, 700℃, 750℃, or 800℃, etc. Pressures can be 200 torr, 300 torr, 400 torr, 500 torr, or 600 torr, etc.

[0132] The hydrogen treatment time can be 20s, 30s, 40s, 50s, or 60s, etc.

[0133] Hydrogen treatment decomposes the oxygen elements on the surface of the nitride diffusion layer between adjacent nanopillar spacer units, preventing the formation of oxygen impurities in the nitride diffusion layer, reducing the light absorption of oxygen impurities, improving the crystal quality of the nitride diffusion layer, reducing the extension of dislocations into the light-emitting unit, and improving the radiative recombination efficiency in the light-emitting unit.

[0134] S43, and S41 and S42, which are periodically cyclically alternated 20 to 100 times, yield nanopillar spacer units.

[0135] The number of cyclical alternations ranges from 20 to 100 times, for example, 20, 40, 50, 60, 80, or 100 times.

[0136] This invention utilizes oxygen treatment to oxidize the nanopillars, ultimately forming nanopillar spacers with aluminum oxide top units and silicon oxide side units. Silicon exhibits strong absorption of visible light and has a high refractive index, severely reducing forward light emission. The top and side units, with their relatively low refractive indices, can increase total internal reflection of light from the light-emitting units towards the growth substrate, reducing light absorption and improving the brightness and luminous efficiency of the nitride semiconductor epitaxial wafer.

[0137] In some embodiments, the light-emitting unit is prepared between adjacent nanopillar spacer units, including: growing a first light-emitting structural unit on the surface of a nitride diffusion layer between the nanopillar spacer units; and growing a second light-emitting structural unit on the surface of the first light-emitting structural unit to obtain the light-emitting unit.

[0138] In this invention, the first light-emitting structural unit is not the main light-emitting structure. It mainly plays a role in lattice modulation between the nitride diffusion layer and the second light-emitting structural unit, which can release the stress of the second light-emitting structural unit, improve the crystal quality of the second light-emitting structural unit, and increase the radiative recombination efficiency. As a preferred technical solution of this invention, the height of the first light-emitting structural unit is not less than the height of the nanopillar, which can reduce the sidewall carrier trapping effect of the second light-emitting structural unit as the main light-emitting structural unit, and is beneficial to improving the brightness and luminous efficiency of the nitride semiconductor epitaxial wafer.

[0139] In some embodiments, a first light-emitting structural unit is grown on the surface of the nitride diffusion layer between the nanopillar spacer units, including:

[0140] A11. Under conditions of temperature of 800℃ to 950℃ and pressure of 200 torr to 400 torr, a gallium source with a flow rate of 100 sccm to 500 sccm, an indium source with a flow rate of 500 sccm to 2000 sccm, and a nitrogen source with a flow rate of 50 slm to 100 slm are introduced to grow a first quantum well layer with a thickness of 2 nm to 5 nm.

[0141] The gallium source can be TMGa, and the nitrogen source can be NH3.

[0142] The temperature for growing the first quantum well layer is between 800°C and 950°C, for example, it can be 800°C, 820°C, 850°C, 880°C, 900°C, 920°C or 950°C.

[0143] The pressure for growing the first quantum well layer is between 200 torr and 400 torr, for example, it can be 200 torr, 250 torr, 300 torr, 350 torr or 400 torr.

[0144] The gallium source flux for growing the first quantum well layer is 100 sccm to 500 sccm, for example, it can be 100 sccm, 200 sccm, 300 sccm, 400 sccm or 500 sccm.

[0145] The indium source flux for growing the first quantum well layer is between 500 sccm and 2000 sccm, for example, it can be 500 sccm, 800 sccm, 1000 sccm, 1200 sccm, 1500 sccm, 1800 sccm or 2000 sccm, etc.

[0146] The nitrogen source flux for growing the first quantum well layer is 50 slm to 100 slm, for example, it can be 50 slm, 60 slm, 70 slm, 80 slm, 90 slm or 100 slm, etc.

[0147] The thickness of the first quantum well layer is 2nm to 5nm, for example, it can be 2nm, 2.5nm, 3nm, 3.5nm, 4nm or 5nm, etc.

[0148] A12. Under conditions of temperature of 800℃ to 950℃ and pressure of 200 torr to 400 torr, a gallium source with a flow rate of 100 sccm to 500 sccm and a nitrogen source with a flow rate of 50 slm to 100 slm are introduced to grow a first quantum barrier layer with a thickness of 3 nm to 25 nm.

[0149] The temperature for growing the first quantum barrier layer is between 800°C and 950°C, for example, it can be 800°C, 820°C, 850°C, 880°C, 900°C, 920°C or 950°C.

[0150] The pressure for growing the first quantum barrier layer is between 200 torr and 400 torr, for example, it can be 200 torr, 250 torr, 300 torr, 350 torr or 400 torr.

[0151] The gallium source flux for growing the first quantum barrier layer is 100 sccm to 500 sccm, for example, it can be 100 sccm, 200 sccm, 300 sccm, 400 sccm or 500 sccm.

[0152] The nitrogen source flux for growing the first quantum barrier layer is 50 slm to 100 slm, for example, it can be 50 slm, 60 slm, 70 slm, 80 slm, 90 slm or 100 slm, etc.

[0153] The thickness of the first quantum barrier layer is 3nm to 25nm, for example, it can be 3nm, 5nm, 8nm, 10nm, 15nm, 18nm, 20nm, 22nm or 25nm, etc.

[0154] A13, and A11 and A12 are periodically and alternately executed 2 to 8 times to obtain the first light-emitting structural unit.

[0155] The number of times A11 and A12 are executed alternately is 2 to 8 times, for example, 2, 4, 5, 6 or 8 times.

[0156] In some embodiments, a second light-emitting structural unit is disposed on the surface of the first light-emitting structural unit, including:

[0157] A21. Under conditions of temperature from 650°C to 850°C and pressure from 200 to 400 tor, a gallium source with a flow rate of 100 to 500 tor, an indium source with a flow rate of 500 to 2000 sccm, and a nitrogen source with a flow rate of 50 slm to 100 slm are introduced to grow a second quantum well layer with a thickness of 2 nm to 5 nm.

[0158] The indium source can be TMIn.

[0159] The temperature for growing the second quantum well layer is between 650°C and 850°C, for example, it can be 650°C, 700°C, 750°C, 800°C or 850°C.

[0160] The pressure for growing the second quantum well layer is between 200 torr and 400 torr, for example, it can be 200 torr, 250 torr, 300 torr, 350 torr or 400 torr.

[0161] The gallium source flux for growing the second quantum well layer is 100 torr to 500 torr, for example, it can be 100 torr, 200 torr, 300 torr, 400 torr or 500 torr.

[0162] The indium source flux for growing the second quantum well layer is from 500 sccm to 2000 sccm, for example, it can be 500 sccm, 600 sccm, 800 sccm, 1000 sccm, 1200 sccm, 1500 sccm, 1800 sccm or 2000 sccm, etc.

[0163] The nitrogen source flux for growing the second quantum well layer is 50 slm to 100 slm, for example, it can be 50 slm, 60 slm, 80 slm, 90 slm or 100 slm.

[0164] The thickness of the second quantum well layer is 2nm to 5nm, for example, it can be 2nm, 3nm, 4nm or 5nm.

[0165] A22. Under conditions of temperature of 750℃ to 950℃ and pressure of 200 torr to 400 torr, a gallium source with a flow rate of 100 sccm to 500 sccm and a nitrogen source with a flow rate of 50 slm to 100 slm are introduced to grow a second quantum barrier layer with a thickness of 3 nm to 15 nm.

[0166] The temperature for growing the second quantum barrier layer is between 750°C and 950°C, for example, it can be 750°C, 800°C, 850°C, 900°C or 950°C.

[0167] The pressure for growing the second quantum barrier layer is 200 torr to 400 torr, for example, it can be 200 torr, 250 torr, 300 torr, 350 torr or 400 torr.

[0168] The gallium source flux for growing the second quantum barrier layer is 100 torr to 500 torr, for example, it can be 100 torr, 200 torr, 300 torr, 400 torr or 500 torr.

[0169] The nitrogen source flux for growing the second quantum barrier layer is 50 slm to 100 slm, for example, it can be 50 slm, 60 slm, 80 slm, 90 slm or 100 slm.

[0170] The thickness of the second quantum barrier layer is 3nm to 15nm, for example, it can be 3nm, 5nm, 6nm, 8nm, 10nm, 12nm or 15nm, etc.

[0171] A23. The second light-emitting structural unit is obtained by periodically alternating between A21 and A22 2 to 15 times.

[0172] The number of times A21 and A22 are executed alternately is 2 to 15 times, for example, 2, 4, 5, 6, 8, 10, 12 or 15 times.

[0173] In some embodiments, the nitride semiconductor epitaxial wafer further includes a nitride merging layer that covers the second light-emitting structural unit and is merged above the nanopillar spacer unit, with a gap between the nitride merging layer and the nanopillar spacer unit.

[0174] Furthermore, the method for preparing the nitride merged layer includes: introducing a Ga source with a flow rate of 10 sccm to 60 sccm and an N source with a flow rate of 40 sccm to 100 sccm at a temperature of 1100℃ to 1250℃ and a pressure of 50 to 100 torr, to grow a layer with a thickness of 40 nm to 120 nm and a Mg doping concentration of 2 × 10⁻⁶. 19 cm -3 Up to 7×10 20 cm -3 The nitride merging layer.

[0175] The temperature for preparing the nitride merging layer is 1100℃ to 1250℃, for example, 1100℃, 1150℃, 1200℃ or 1250℃.

[0176] The pressure for preparing the nitride merging layer is 50 torr to 100 torr, for example, it can be 50 torr, 60 torr, 70 torr, 80 torr, 90 torr or 100 torr, etc.

[0177] The Ga source flux for preparing the nitride merging layer is from 10 sccm to 60 sccm, for example, it can be 10 sccm, 20 sccm, 30 sccm, 40 sccm, 50 sccm or 60 sccm.

[0178] The N source flux for preparing the nitride merging layer is 40 sccm to 100 sccm, for example, it can be 40 sccm, 50 sccm, 60 sccm, 80 sccm or 100 sccm.

[0179] The thickness of the nitride merging layer is 40nm to 120nm, for example, it can be 40nm, 50nm, 60nm, 80nm, 100nm or 120nm.

[0180] The Mg doping concentration of the nitride merging layer is 2 × 10⁻⁶. 19 cm -3 Up to 7×1020 cm -3 For example, it could be 2×10 19 cm -3 5×10 19 cm -3 1×10 20 cm -3 3×10 20 cm -3 5×10 20 cm -3 Or 7×10 20 cm -3 wait.

[0181] This invention enhances the lateral growth of the nitride merging layer by optimizing the fabrication process of the nitride merging layer (using high temperature, low pressure, low Ga source, and high N source). The final nitride merging layer is formed on the second light-emitting structural unit and merged above the nanopillar spacer unit, forming a void between the nitride merging layer and the nanopillar spacer unit. Compared with nitride materials, the void and the top unit have a lower refractive index, which can enhance the total internal reflection of the light emitted laterally from the light-emitting unit. After reflection, the lateral light has more opportunities to be emitted in the forward direction, thus improving the light emission efficiency.

[0182] In some embodiments, the nitride barrier layer includes a first nitride barrier layer and a second nitride barrier layer, and the method for preparing the nitride barrier layer includes: preparing the first nitride barrier layer on the nitride merging layer; and preparing the second nitride barrier layer on the first nitride barrier layer.

[0183] In this invention, the first nitride barrier layer covers the nitride merging layer, which can provide a template for the growth of the second nitride barrier layer; the second nitride barrier layer can block carriers that cross the second light-emitting unit from entering the p-type nitride layer, thereby improving the carrier confinement capability of the second light-emitting structural unit.

[0184] In some embodiments, the method for preparing the first nitride barrier layer includes: introducing an aluminum source with a flow rate of 20 sccm to 200 sccm and a nitrogen source with a flow rate of 1 slm to 10 slm at a temperature of 950°C to 1050°C and a pressure of 50 torr to 150 torr to grow a first nitride barrier layer with a thickness of 2 nm to 5 nm.

[0185] The aluminum source can be TMAl.

[0186] The temperature for preparing the first nitride barrier layer is between 950°C and 1050°C, for example, it can be 950°C, 980°C, 1000°C, 1020°C or 1050°C.

[0187] The pressure used to prepare the first nitride barrier layer is between 50 torr and 150 torr, for example, it can be 50 torr, 80 torr, 100 torr, 120 torr or 150 torr.

[0188] The aluminum source flow rate during the preparation of the first nitride barrier layer is 20 sccm to 200 sccm, for example, it can be 20 sccm, 50 sccm, 80 sccm, 100 sccm, 150 sccm or 200 sccm.

[0189] The nitrogen source flux during the preparation of the first nitride barrier layer is 1 slm to 10 slm, for example, it can be 1 slm, 3 slm, 5 slm, 6 slm, 8 slm or 10 slm, etc.

[0190] The thickness of the first nitride barrier layer is 2 nm to 5 nm, for example, it can be 2 nm, 3 nm, 4 nm or 5 nm.

[0191] In some embodiments, the method for preparing the second nitride barrier layer includes: introducing a Ga source with a flow rate of 30 sccm to 150 sccm, an aluminum source with a flow rate of 20 sccm to 200 sccm, and a nitrogen source with a flow rate of 20 slm to 50 slm at a temperature of 950°C to 1050°C and a pressure of 100 torr to 300 torr, to grow a second nitride barrier layer with a thickness of 5 nm to 20 nm.

[0192] The temperature for preparing the second nitride barrier layer is between 950°C and 1050°C, for example, 950°C, 980°C, 1000°C, 1020°C, or 1050°C.

[0193] The pressure used to prepare the second nitride barrier layer is between 100 torr and 300 torr, for example, it can be 100 torr, 150 torr, 200 torr, 250 torr or 300 torr.

[0194] The Ga source flux during the preparation of the second nitride barrier layer is 30 sccm to 150 sccm, for example, it can be 30 sccm, 50 sccm, 60 sccm, 80 sccm, 100 sccm, 120 sccm or 150 sccm.

[0195] The aluminum source flow rate during the preparation of the second nitride barrier layer is 20 sccm to 200 sccm, for example, it can be 20 sccm, 50 sccm, 100 sccm, 120 sccm, 150 sccm, 180 sccm or 200 sccm.

[0196] The nitrogen source flux during the preparation of the second nitride barrier layer is 20 slm to 50 slm, for example, it can be 20 slm, 25 slm, 30 slm, 35 slm, 40 slm, 45 slm or 50 slm, etc.

[0197] The thickness of the second nitride barrier layer is 5 nm to 20 nm, for example, it can be 5 nm, 8 nm, 10 nm, 12 nm, 15 nm, 18 nm or 20 nm.

[0198] In some embodiments, the method for preparing a p-type nitride layer includes: introducing a gallium source with a flow rate of 100 sccm to 1000 sccm and a nitrogen source with a flow rate of 20 slm to 80 slm on the surface of the nitride barrier layer at a temperature of 850°C to 1050°C and a pressure of 200 torr to 500 torr, thereby growing a 20 nm to 200 nm thick Mg doping concentration of 1 × 10⁻⁶ on the surface of the nitride barrier layer. 19 cm -3 Up to 5×10 20 cm -3 The p-type nitride layer.

[0199] The temperature for preparing the p-type nitride layer is between 850°C and 1050°C, for example, 850°C, 900°C, 950°C, 1000°C, or 1050°C.

[0200] The pressure for preparing the p-type nitride layer is 200 torr to 500 torr, for example, it can be 200 torr, 250 torr, 300 torr, 350 torr, 400 torr, 450 torr or 500 torr, etc.

[0201] The gallium source flux during the preparation of the p-type nitride layer is 100 sccm to 1000 sccm, for example, it can be 100 sccm, 300 sccm, 500 sccm, 800 sccm or 1000 sccm.

[0202] The nitrogen source flow rate for preparing the p-type nitride layer is 20 slm to 80 slm, for example, it can be 20 slm, 40 slm, 50 slm, 60 slm or 80 slm.

[0203] The thickness of the p-type nitride layer is 20 nm to 200 nm, for example, it can be 20 nm, 50 nm, 80 nm, 100 nm, 120 nm, 150 nm, 180 nm or 200 nm.

[0204] An embodiment of the present invention provides an optoelectronic device, which includes a nitride semiconductor epitaxial wafer as described in any embodiment, or a nitride semiconductor epitaxial wafer prepared by the preparation method provided in any embodiment.

[0205] Example 1

[0206] This embodiment provides a method such as Figure 1 The nitride semiconductor epitaxial wafer shown includes a growth substrate 1, an n-type nitride layer 2, a nitride diffusion layer 3, a composite light-emitting layer, a nitride merging layer 12, a nitride barrier layer, and a p-type nitride layer 8, which are stacked sequentially.

[0207] The composite light-emitting layer includes spaced nanopillar spacers and light-emitting units disposed between adjacent nanopillar spacers. Each nanopillar spacer includes a nanopillar 9 (made of silicon), a top unit 11 (made of aluminum oxide) disposed on the top surface of the nanopillar 9, and side units 10 (made of silicon oxide) disposed on the sidewalls of the nanopillar 9. The surface of the nanopillar 9 in contact with the top unit 11 is horizontal. Each light-emitting unit includes a first light-emitting structure 4 and a second light-emitting structure 5 stacked together. The first light-emitting structure 4 is used to modulate the lattice of the second light-emitting structure 5.

[0208] The nitride merging layer 12 covers the second light-emitting structural unit 5 and is merged above the nanopillar spacer unit, with a gap between the nitride merging layer 12 and the nanopillar spacer unit; the nitride barrier layer includes a first nitride barrier layer 6 closest to the nitride diffusion layer 3 and a second nitride barrier layer 7 furthest from the nitride diffusion layer 3; the first nitride barrier layer 6 covers the nitride merging layer 12; the second nitride barrier layer 7 covers the first nitride barrier layer 6.

[0209] p-type nitride layer 8 is disposed on the surface of the second nitride barrier layer 7.

[0210] The method for preparing a nitride semiconductor epitaxial wafer provided in this embodiment includes the following steps:

[0211] (1) Provide a 4-inch sapphire crystal as the growth substrate 1.

[0212] (2) Under the conditions of 1150℃ and 200 torr, a GaN material with a Si doping concentration of 1×10⁻⁶ was grown on growth substrate 1 with a thickness of 3μm. 19 cm -3 n-type nitride layer 2.

[0213] (3) A nitride diffusion layer 3 with a thickness of 30 nm and made of GaN was grown on the n-type nitride layer 2 under the conditions of temperature of 1120℃ and pressure of 200 torr.

[0214] (4) Fabricating nanopillar spacer units on the surface of nitride diffusion layer 3, including the following steps:

[0215] S41. An aluminum metal layer with a thickness of 50 nm is grown on the surface of the nitride diffusion layer 3. Then, the aluminum metal layer is annealed for 200 s at a temperature of 850 °C and a pressure of 100 torr to form nanospheres with a spacing of 300 nm and a diameter of 50 nm.

[0216] S42. Under the conditions of 850℃ and 400 torr, the nanospheres were subjected to Si heat treatment for 30 min, and then the Si heat treatment was interrupted for 300 s to obtain the microsphere structure.

[0217] S43. Under the conditions of temperature of 850℃ and pressure of 500 torr, SiH4 is introduced into the surface of the microsphere structure at a flow rate of 500 sccm for 50s.

[0218] S44, interrupt the flow of SiH4 for 100s.

[0219] S45. Periodically and alternately execute S43 and S44 until a nanopillar 9 with a height of 100 nm is obtained.

[0220] S46. Under conditions of 600℃ and 400 torr, perform oxygen treatment for 90s to form an aluminum oxide layer of Al2O3 on the top surface of the nanopillar 9 and a silicon oxide layer of SiO2 on the sidewall of the nanopillar 9.

[0221] S47. Under conditions of 600℃ and 400 torr, perform hydrogen treatment for 40s to decompose the oxygen element on the surface of the nitride diffusion layer 3 between adjacent nanopillar spacer units.

[0222] S48, S46 and S47 are periodically cyclically alternated 50 times to obtain nanopillar spacer units.

[0223] (5) Growing a first light-emitting structure 4 unit on the surface of the nitride diffusion layer 3 between the nanopillar spacer units, including the following steps:

[0224] A11. Under conditions of 900℃ and 300 torr, a first quantum well layer with a thickness of 3nm is grown by introducing TMGa at a flow rate of 300 sccm, TMIn at a flow rate of 1000 sccm, and NH3 at a flow rate of 80 slm.

[0225] A12. Under conditions of 900℃ and 300 torr, TMGa with a flow rate of 300 sccm and NH3 with a flow rate of 80 slm are introduced to grow a first quantum barrier layer with a thickness of 20 nm.

[0226] A13, and A11 and A12 are periodically and alternately executed 5 times to obtain the first light-emitting structure 4 units.

[0227] (6) Depositing a second light-emitting structure unit 5 on the surface of the first light-emitting structure unit 4 includes the following steps:

[0228] A21. Under conditions of 750℃ and 300 torr, a second quantum well layer with a thickness of 4nm is grown by introducing TMGa at a flow rate of 300 torr, TMIn at a flow rate of 1000 sccm, and NH3 at a flow rate of 80 slm.

[0229] A22. Under conditions of 900℃ and 300 torr, a second quantum barrier layer with a thickness of 10 nm is grown by introducing TMGa at a flow rate of 300 sccm and NH3 at a flow rate of 80 slm.

[0230] A23, A21 and A22 are periodically and alternately executed 8 times to obtain the second light-emitting structural unit 5.

[0231] (7) Under conditions of 1200℃ and 80 torr, TMGa with a flow rate of 40 sccm and NH3 with a flow rate of 60 sccm are introduced to grow a thickness of 80 nm with a Mg doping concentration of 1×10⁻⁶. 20 cm -3 p-type nitride merging layer 12.

[0232] (8) Under the conditions of 1000℃ and 100 torr, TMAl with a flow rate of 100 sccm and NH3 with a flow rate of 5 slm are introduced to grow a first nitride barrier layer 6 with a thickness of 4 nm and made of AlN on the p-type nitride merging layer 12.

[0233] (9) Under the conditions of 1000℃ and 200 torr, TMGa with a flow rate of 100 sccm, TMAl with a flow rate of 100 sccm and NH3 with a flow rate of 35 slm are introduced to grow a second nitride barrier layer 7 with a thickness of 10 nm and made of AlGaN on the first nitride barrier layer 6.

[0234] (10) Under conditions of 950℃ and 350 torr, TMGa with a flow rate of 500 sccm and NH3 with a flow rate of 50 slm were introduced to grow a 100 nm thick Mg doping concentration of 1×10 on the surface of the second nitride barrier layer 7. 20 cm -3 p-type nitride layer 8.

[0235] Example 2

[0236] This embodiment provides a nitride semiconductor epitaxial wafer, comprising a growth substrate, an n-type nitride layer, a nitride diffusion layer, a composite light-emitting layer, a nitride merging layer, a nitride barrier layer, and a p-type nitride layer stacked sequentially.

[0237] The composite light-emitting layer includes spaced nanopillar spacer units and light-emitting units disposed between adjacent nanopillar spacer units. Each nanopillar spacer unit includes a nanopillar (made of silicon), a top unit (made of aluminum oxide) disposed on the top surface of the nanopillar, and side units (made of silicon oxide) disposed on the sidewalls of the nanopillar. The surface in contact between the nanopillar and the top unit is horizontal. Each light-emitting unit includes a first light-emitting structural unit and a second light-emitting structural unit stacked together. The first light-emitting structural unit is used to modulate the lattice of the second light-emitting structural unit.

[0238] The nitride merging layer covers the second luminescent structural unit and is merged above the nanopillar spacer unit, with a gap between the nitride merging layer and the nanopillar spacer unit; the nitride barrier layer includes a first nitride barrier layer closest to the nitride diffusion layer and a second nitride barrier layer furthest from the nitride diffusion layer; the first nitride barrier layer covers the nitride merging layer; the second nitride barrier layer covers the first nitride barrier layer.

[0239] The p-type nitride layer is disposed on the surface of the second nitride barrier layer.

[0240] The method for preparing a nitride semiconductor epitaxial wafer provided in this embodiment includes the following steps:

[0241] (1) Provide 4-inch sapphire as the growth substrate.

[0242] (2) Under the conditions of 1070℃ and 100 torr, a GaN material with a Si doping concentration of 1×10⁻⁶ was grown on a growth substrate with a thickness of 1 μm. 18 cm -3 The n-type nitride layer.

[0243] (3) A nitride diffusion layer with a thickness of 10 nm and made of GaN was grown on an n-type nitride layer under the conditions of a temperature of 1020℃ and a pressure of 100 torr.

[0244] (4) Fabricating nanopillar spacer units on the surface of the nitride diffusion layer, including the following steps:

[0245] S41. An aluminum metal layer with a thickness of 10 nm is grown on the surface of the nitride diffusion layer. Then, the aluminum metal layer is annealed for 60 s at a temperature of 700 °C and a pressure of 50 torr to form nanospheres with a spacing of 100 nm and a diameter of 10 nm.

[0246] S42. The nanospheres were heat-treated for 5 minutes at a temperature of 700℃ and a pressure of 200 torr, and then the heat treatment was interrupted for 100 seconds to obtain the microsphere structure.

[0247] S43. Under the conditions of 700℃ and 400 torr, SiH4 is introduced into the surface of the microsphere structure at a flow rate of 20 sccm for 10 s.

[0248] S44, interrupt the flow of SiH4 for 10 seconds.

[0249] S45. Periodically and alternately execute S43 and S44 until a nanopillar with a height of 10 nm is obtained.

[0250] S46. Under conditions of 400℃ and 200 torr, perform oxygen treatment for 60s to form an aluminum oxide layer of Al2O3 on the top surface of the nanopillar and a silicon oxide layer of SiO2 on the sidewall of the nanopillar.

[0251] S47. Under conditions of 400℃ and 200 torr, perform hydrogen treatment for 20s to decompose the oxygen element on the surface of the nitride diffusion layer between adjacent nanopillar spacer units.

[0252] S48, S46 and S47 are periodically cyclically alternated 20 times to obtain nanopillar spacer units.

[0253] (5) Growing a first light-emitting structural unit on the surface of the nitride diffusion layer between the nanopillar spacer units, including the following steps:

[0254] A11. Under conditions of 800℃ and 200 torr, a first quantum well layer with a thickness of 3nm is grown by introducing TMGa at a flow rate of 100 sccm, TMIn at a flow rate of 500 sccm, and NH3 at a flow rate of 50 slm.

[0255] A12. Under conditions of 800℃ and 200 torr, TMGa with a flow rate of 100 sccm and NH3 with a flow rate of 50 slm are introduced to grow a first quantum barrier layer with a thickness of 15 nm.

[0256] A13, and A11 and A12 are periodically and alternately executed twice to obtain the first light-emitting structural unit.

[0257] (6) Depositing a second light-emitting structure unit on the surface of the first light-emitting structure unit includes the following steps:

[0258] A21. Under conditions of 650℃ and 200 torr, a second quantum well layer with a thickness of 2nm is grown by introducing TMGa at a flow rate of 100 torr, TMIn at a flow rate of 500 sccm, and NH3 at a flow rate of 50 slm.

[0259] A22. Under conditions of 800℃ and 200 torr, a second quantum barrier layer with a thickness of 6nm is grown by introducing TMGa at a flow rate of 100 sccm and NH3 at a flow rate of 50 slm.

[0260] A23, A21 and A22 are periodically and alternately executed 15 times to obtain the second light-emitting structural unit.

[0261] (7) Under conditions of 1100℃ and 50 torr, TMGa with a flow rate of 10 sccm and NH3 with a flow rate of 40 sccm are introduced to grow a 40 nm thick material with a Mg doping concentration of 2 × 10⁻⁶. 19 cm -3 p-type nitride merging layers.

[0262] (8) Under the conditions of 950℃ and 50 torr, TMAl with a flow rate of 20 sccm and NH3 with a flow rate of 1 slm are introduced to grow a first nitride barrier layer with a thickness of 2 nm and made of AlN on the p-type nitride merging layer.

[0263] (9) Under the conditions of 950℃ and 100 torr, TMGa with a flow rate of 30 sccm, TMAl with a flow rate of 20 sccm and NH3 with a flow rate of 20 slm are introduced to grow a second nitride barrier layer with a thickness of 5 nm and made of AlGaN on the first nitride barrier layer.

[0264] (10) Under conditions of 850℃ and 200 torr, TMGa with a flow rate of 100 sccm and NH3 with a flow rate of 20 slm were introduced to grow a 20 nm thick Mg doping concentration of 1×10 on the surface of the second nitride barrier layer. 19 cm -3 The p-type nitride layer.

[0265] Example 3

[0266] This embodiment provides a nitride semiconductor epitaxial wafer, comprising a growth substrate, an n-type nitride layer, a nitride diffusion layer, a composite light-emitting layer, a nitride merging layer, a nitride barrier layer, and a p-type nitride layer stacked sequentially.

[0267] The composite light-emitting layer includes spaced nanopillar spacer units and light-emitting units disposed between adjacent nanopillar spacer units. Each nanopillar spacer unit includes a nanopillar (made of silicon), a top unit (made of aluminum oxide) disposed on the top surface of the nanopillar, and side units (made of silicon oxide) disposed on the sidewalls of the nanopillar. The surface in contact between the nanopillar and the top unit is horizontal. Each light-emitting unit includes a first light-emitting structural unit and a second light-emitting structural unit stacked together. The first light-emitting structural unit is used to modulate the lattice of the second light-emitting structural unit.

[0268] The nitride merging layer covers the second luminescent structural unit and merges above the nanopillar spacer unit, with a gap between the nitride merging layer and the nanopillar spacer unit; the nitride barrier layer includes a first nitride barrier layer closest to the nitride diffusion layer and a second nitride barrier layer furthest from the nitride diffusion layer; the first nitride barrier layer covers the nitride merging layer; the second nitride barrier layer covers the first nitride barrier layer.

[0269] The p-type nitride layer is disposed on the surface of the second nitride barrier layer.

[0270] The method for preparing a nitride semiconductor epitaxial wafer provided in this embodiment includes the following steps:

[0271] (1) Provide 4-inch sapphire as the growth substrate.

[0272] (2) Under the conditions of 1250℃ and 300 torr, a GaN material with a Si doping concentration of 5×10⁻⁶ was grown on a growth substrate with a thickness of 5μm. 19 cm -3 The n-type nitride layer.

[0273] (3) A nitride diffusion layer with a thickness of 50 nm and made of GaN was grown on an n-type nitride layer under the conditions of temperature of 1220℃ and pressure of 300 torr.

[0274] (4) Fabricating nanopillar spacer units on the surface of the nitride diffusion layer, including the following steps:

[0275] S41. An aluminum metal layer with a thickness of 100 nm is grown on the surface of the nitride diffusion layer. Then, the aluminum metal layer is annealed for 300 s at a temperature of 1000 °C and a pressure of 150 torr to form nanospheres with a spacing of 500 nm and a diameter of 100 nm.

[0276] S42. The nanospheres were heat-treated for 60 minutes at a temperature of 100℃ and a pressure of 600 torr, and then the heat treatment was interrupted for 600 seconds to obtain the microsphere structure.

[0277] S43. Under the conditions of 1000℃ and 600 torr, SiH4 is introduced into the surface of the microsphere structure at a flow rate of 200 sccm for 10 s.

[0278] S44, interrupt the flow of SiH4 for 100s.

[0279] S45, and S43 and S44 are periodically alternated until a nanopillar with a height of 200 nm is obtained.

[0280] S46. Under conditions of 800℃ and 600 torr, perform oxygen treatment for 120s to form an aluminum oxide layer of Al2O3 on the top surface of the nanopillar and a silicon oxide layer of SiO2 on the sidewall of the nanopillar.

[0281] S47. Under conditions of 800℃ and 600 torr, perform hydrogen treatment for 60s to decompose the oxygen element on the surface of the nitride diffusion layer between adjacent nanopillar spacer units.

[0282] S48, S46 and S47 are periodically cyclically alternated 100 times to obtain nanopillar spacer units.

[0283] (5) Growing a first light-emitting structural unit on the surface of the nitride diffusion layer between the nanopillar spacer units, including the following steps:

[0284] A11. Under conditions of 950℃ and 400 torr, a first quantum well layer with a thickness of 3nm is grown by introducing TMGa at a flow rate of 500 sccm, TMIn at a flow rate of 2000 sccm, and NH3 at a flow rate of 100 slm.

[0285] A12. Under conditions of 950℃ and 400 torr, a gallium source (TMGa) with a flow rate of 500 sccm and a nitrogen source (NH3) with a flow rate of 100 slm are introduced to grow a first quantum barrier layer with a thickness of 25 nm.

[0286] A13, and A11 and A12 are periodically and alternately executed 8 times to obtain the first light-emitting structural unit.

[0287] (6) Depositing a second light-emitting structure unit on the surface of the first light-emitting structure unit includes the following steps:

[0288] A21. Under conditions of 850℃ and 400 torr, a second quantum well layer with a thickness of 5nm is grown by introducing TMGa at a flow rate of 500 torr, TMIn at a flow rate of 2000 sccm, and NH3 at a flow rate of 100 slm.

[0289] A22. Under conditions of 950℃ and 400 torr, a second quantum barrier layer with a thickness of 15nm is grown by introducing TMGa at a flow rate of 500 sccm and NH3 at a flow rate of 100 slm.

[0290] A23, and A21 and A22 are periodically and alternately executed twice to obtain the second light-emitting structural unit.

[0291] (7) Under conditions of 1250℃ and 100 torr, TMGa with a flow rate of 60 sccm and NH3 with a flow rate of 100 sccm are introduced to grow a 120 nm thick material with a Mg doping concentration of 7 × 10⁻⁶. 20 cm -3 p-type nitride merging layers.

[0292] (8) Under the conditions of temperature of 1050℃ and pressure of 300 torr, TMAl with a flow rate of 200 sccm and NH3 with a flow rate of 10 slm are introduced to grow a first nitride barrier layer with a thickness of 5 nm and material of AlN on the p-type nitride merging layer.

[0293] (9) Under the conditions of 1050℃ and 300 torr, TMGa with a flow rate of 150 sccm, TMAl with a flow rate of 200 sccm and NH3 with a flow rate of 50 slm are introduced to grow a second nitride barrier layer with a thickness of 20 nm and made of AlGaN on the first nitride barrier layer.

[0294] (10) Under conditions of 1050℃ and 500 torr, TMGa with a flow rate of 1000 sccm and NH3 with a flow rate of 80 slm were introduced to grow a 200 nm thick Mg doping concentration of 5 × 10⁻⁶ on the surface of the second nitride barrier layer. 20 cm -3 The p-type nitride layer.

[0295] Comparative Example 1

[0296] This comparative example provides a nitride semiconductor epitaxial wafer. Except for not performing steps S46-S48, i.e. not performing oxygen and hydrogen treatment on the nanopillars, not forming an aluminum oxide layer on the top surface of the nanopillars, and not forming a silicon oxide layer on the sidewalls of the nanopillar body, everything else is the same as in Example 1, and will not be repeated here.

[0297] Comparative Example 2

[0298] This comparative example provides a nitride semiconductor epitaxial wafer, which is the same as Example 1 except that no nitride diffusion layer is provided and the composite light-emitting layer is directly prepared on the surface of the n-type nitride layer. It will not be described again here.

[0299] Comparative Example 3

[0300] This comparative example provides a way to... Figure 2 The nitride semiconductor epitaxial wafer shown includes a growth substrate 1, an n-type nitride layer 2, a nitride diffusion layer 3, a light-emitting unit, a nitride barrier layer, and a p-type nitride layer 8, which are stacked sequentially.

[0301] The light-emitting unit includes a first light-emitting structural unit 4 and a second light-emitting structural unit 5 stacked together. The first light-emitting structural unit 4 is used to perform lattice modulation on the nitride diffusion layer 3 and the second light-emitting structural unit 5.

[0302] The nitride barrier layer includes a first nitride barrier layer 6 that is closest to the nitride diffusion layer 3 and a second nitride barrier layer 7 that is furthest from the nitride diffusion layer 3; the first nitride barrier layer 6 covers the exposed surfaces of the second light-emitting structural unit 5 and the nitride diffusion layer 3.

[0303] p-type nitride layer 8 is disposed on the surface of the second nitride barrier layer 7.

[0304] The method for preparing the nitride semiconductor epitaxial wafer provided in this comparative example includes the following steps:

[0305] (1) Provide a 4-inch sapphire crystal as the growth substrate 1.

[0306] (2) Under the conditions of 1150℃ and 200 torr, a GaN material with a Si doping concentration of 1×10⁻⁶ was grown on growth substrate 1 with a thickness of 3μm. 19 cm -3 n-type nitride layer 2.

[0307] (3) A nitride diffusion layer 3 with a thickness of 30 nm and made of GaN was grown on the n-type nitride layer 2 under the conditions of temperature of 1120℃ and pressure of 200 torr.

[0308] (4) Growing a first light-emitting structural unit 4 on the surface of the nitride diffusion layer 3 includes the following steps:

[0309] A11. Under conditions of 900℃ and 300 torr, a first quantum well layer with a thickness of 3nm is grown by introducing TMGa at a flow rate of 300 sccm, TMIn at a flow rate of 1000 sccm, and NH3 at a flow rate of 80 slm.

[0310] A12. Under conditions of 900℃ and 300 torr, TMGa with a flow rate of 300 sccm and NH3 with a flow rate of 80 slm are introduced to grow a first quantum barrier layer with a thickness of 20 nm.

[0311] A13, A11 and A12 are periodically and alternately executed 5 times to obtain the first light-emitting structural unit 4.

[0312] (5) Depositing a second light-emitting structure unit 5 on the surface of the first light-emitting structure unit 4 includes the following steps:

[0313] A21. Under conditions of 750℃ and 300 torr, a second quantum well layer with a thickness of 4nm is grown by introducing TMGa at a flow rate of 300 torr, TMIn at a flow rate of 1000 sccm, and NH3 at a flow rate of 80 slm.

[0314] A22. Under conditions of 900℃ and 300 torr, a second quantum barrier layer with a thickness of 10 nm is grown by introducing TMGa at a flow rate of 300 sccm and NH3 at a flow rate of 80 slm.

[0315] A23, A21 and A22 are periodically and alternately executed 8 times to obtain the second light-emitting structural unit 5.

[0316] (6) Under the conditions of 1000℃ and 100 torr, TMAl with a flow rate of 100 sccm and NH3 with a flow rate of 5 slm are introduced to grow a first nitride barrier layer 6 with a thickness of 4 nm and made of AlN on the second light-emitting structural unit 5 and the nitride diffusion layer 3.

[0317] (7) Under the conditions of 1000℃ and 200 torr, TMGa with a flow rate of 100 sccm, TMAl with a flow rate of 100 sccm and NH3 with a flow rate of 35 slm are introduced to grow a second nitride barrier layer 7 with a thickness of 10 nm and made of AlGaN on the first nitride barrier layer 6.

[0318] (8) Under conditions of 950℃ and 350 torr, TMGa with a flow rate of 500 sccm and NH3 with a flow rate of 50 slm were introduced to grow a 100 nm thick Mg doping concentration of 1×10⁻⁶ on the surface of the second nitride barrier layer 7. 20 cm -3 p-type nitride layer 8.

[0319] Comparative Example 4

[0320] This comparative example provides a nitride semiconductor epitaxial wafer. Except for skipping steps S44 and S45, and instead directly growing nanopillars with a height of 100 nm on the surface of a microsphere structure, the rest is the same as in Example 1, and will not be repeated here.

[0321] Performance Characterization

[0322] The long-wavelength orange (585nm±1nm) nitride epitaxial wafers obtained in the above embodiments and comparative examples were subjected to performance testing. The wavelength uniformity (std / nm) and full width at half maximum (HW / nm) of the epitaxial wafers prepared in the above embodiments and comparative examples were tested by photoluminescence (PL). Then, Micro-LEDs were fabricated using the same preparation process and tested using an LED optoelectronic performance tester, including luminous intensity (Lop / mW) under a 2mA current injection condition, and ESD yield and leakage current yield IR performance tests under reverse breakdown voltage of 2000V and reverse voltage of 7V. The results are shown in Table 1.

[0323] Table 1

[0324] WLD / nm std / nm HW / nm Lop / mW / 2mA ESD / % IR / % Example 1 585.1 1.0 55.8 13.7 99.8 99.9 Example 2 585.4 0.9 54.8 13.5 99.9 99.9 Example 3 585.1 1.1 55.9 13.7 99.8 99.8 Comparative Example 1 585.7 1.4 57.7 10.1 97.1 96.7 Comparative Example 2 585.4 1.3 59.1 9.8 89.3 91.3 Comparative Example 3 585.2 3.1 69.9 6.1 93.1 94.6 Comparative Example 4 585.2 1.6 58.6 11.1 96.7 96.9

[0325] As can be seen from the table above, Examples 1-3 exhibit low wavelength std, low full width at half maximum (HW), high brightness, and high ESD and IR yield performance. In Comparative Example 1, the nanopillars were not subjected to oxygen and hydrogen treatment, thus failing to utilize the total internal reflection effect caused by the low refractive index of the top unit of the aluminum oxide and the side unit of the silicon oxide formed after oxidation. More light was absorbed in the epitaxial layer, and the nanopillars and the epitaxial layer in contact with them formed an alloy meltback, introducing high-density defects into the epitaxial layer. Dislocation extension increased non-radiative recombination and compositional fluctuations in the light-emitting unit, and increased leakage channels. In Comparative Example 2, no nitrides were incorporated. During the formation of nanopillars, the diffusion layer causes the accumulation of Si atom impurities on the surface of the n-type nitride layer, increasing light absorption. Furthermore, the diffusion of Si atoms into the light-emitting unit increases non-radiative recombination and leakage channels. In Comparative Example 3, the absence of nanopillar spacer units leads to increased stress in the light-emitting unit and the inability to utilize the quantum size confinement effect, resulting in reduced electron-hole recombination efficiency. In Comparative Example 4, the lack of a cyclic process for the nanopillars causes uneven Si atom precipitation, affecting the uniformity of the nanopillars and thus deteriorating the thickness, compositional uniformity, and carrier injection uniformity of the light-emitting unit.

[0326] In summary, the nitride semiconductor epitaxial wafer provided by this invention, through the arrangement of nanopillar spacers, enables the nanopillar spacers to separate the light-emitting units, making the light-emitting units nanostructured. On the one hand, this reduces the stress in the light-emitting units, improves the composition incorporation and uniformity of the epitaxial layer, and on the other hand, utilizes the quantum size confinement effect to reduce QCSE, reduce stress distribution in the light-emitting units, improve the radiative recombination efficiency of electrons and holes in the light-emitting units, and reduce the carrier trapping effect caused by sidewall damage, thereby improving the luminous efficiency and brightness of the nitride semiconductor epitaxial wafer. In addition, it can also reduce the full width at half maximum (FWHM) of the emission wavelength and improve color purity. In the nitride semiconductor epitaxial wafer provided by this invention, the arrangement of the nitride diffusion layer enables Si atoms on the surface of the nitride diffusion layer between adjacent nanopillar spacers to form a uniform diffusion in the nitride diffusion layer.

[0327] The above description is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Those skilled in the art should understand that any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention fall within the protection and disclosure scope of the present invention.

Claims

1. A nitride semiconductor epitaxial wafer, characterized in that, The nitride semiconductor epitaxial wafer includes a growth substrate, an n-type nitride layer, a nitride diffusion layer, a composite light-emitting layer, a nitride barrier layer, and a p-type nitride layer stacked sequentially. The composite light-emitting layer includes spaced nanopillar spacer units and light-emitting units disposed between adjacent nanopillar spacer units; The nanopillar spacer unit includes a nanopillar, a top unit disposed on the top surface of the nanopillar, and a side unit disposed on the sidewall of the nanopillar. The surface of the nanopillar in contact with the top unit is a horizontal plane. The light-emitting unit includes at least a first light-emitting structural unit and a second light-emitting structural unit stacked together, wherein the first light-emitting structural unit is used to perform lattice modulation on the nitride diffusion layer and the second light-emitting structural unit; The p-type nitride layer is disposed on the surface of the nitride barrier layer.

2. The nitride semiconductor epitaxial wafer according to claim 1, characterized in that, The nitride semiconductor epitaxial wafer further includes a nitride merging layer, which covers the second light-emitting structure unit and is merged above the nanopillar spacer unit, with a gap between the nitride merging layer and the nanopillar spacer unit; Preferably, the nitride barrier layer includes a first nitride barrier layer closest to the nitride diffusion layer and a second nitride barrier layer furthest from the nitride diffusion layer; the first nitride barrier layer covers the nitride merging layer; Preferably, the nanopillars are made of silicon; Preferably, the material of the top unit includes aluminum oxide; Preferably, the side unit is made of silicon oxide; Preferably, the height of the nanopillars is 10 nm to 200 nm; Preferably, the height of the nanopillar is not higher than the height of the first light-emitting structural unit; Preferably, the distance between any two adjacent nanopillar spacer units is 100 nm to 500 nm.

3. A method for preparing a nitride semiconductor epitaxial wafer, characterized in that, The preparation method includes the following steps: An n-type nitride layer, a nitride diffusion layer, a composite light-emitting layer, and a nitride barrier layer are sequentially fabricated on the surface of a growth substrate. The composite light-emitting layer includes spaced nanopillar spacer units and light-emitting units disposed between adjacent nanopillar spacer units. Each nanopillar spacer unit includes a nanopillar, a top unit disposed on the top surface of the nanopillar, and side units disposed on the sidewalls of the nanopillar. The surface of the nanopillar in contact with the top unit is a horizontal plane. Each light-emitting unit includes at least a first light-emitting structural unit and a second light-emitting structural unit stacked together. The first light-emitting structural unit is used to modulate the lattice of the nitride diffusion layer and the second light-emitting structural unit. A p-type nitride layer is prepared on the surface of the nitride barrier layer.

4. The preparation method according to claim 3, characterized in that, The nitride semiconductor epitaxial wafer further includes a nitride merging layer, which covers the second light-emitting structure unit and is merged above the nanopillar spacer unit, with a gap between the nitride merging layer and the nanopillar spacer unit; Preferably, the nitride barrier layer includes a first nitride barrier layer and a second nitride barrier layer; The method for preparing the nitride barrier layer includes: The first nitride barrier layer is prepared on the nitride merging layer; The second nitride barrier layer is prepared on the first nitride barrier layer.

5. The preparation method according to claim 4, characterized in that, The method for preparing the nitride merged layer includes: introducing a Ga source with a flow rate of 10 sccm to 60 sccm and an N source with a flow rate of 40 sccm to 100 sccm at a temperature of 1100°C to 1250°C and a pressure of 50 to 100 torr, to grow a layer with a thickness of 40 nm to 120 nm and a Mg doping concentration of 2 × 10⁻⁶. 19 cm -3 Up to 7×10 20 cm -3 The nitride merging layer; Preferably, the method for preparing the first nitride barrier layer includes: introducing an aluminum source with a flow rate of 20 sccm to 200 sccm and a nitrogen source with a flow rate of 1 slm to 10 slm under conditions of a temperature of 950°C to 1050°C and a pressure of 50 torr to 150 torr, and growing a first nitride barrier layer with a thickness of 2 nm to 5 nm. Preferably, the method for preparing the second nitride barrier layer includes: introducing a Ga source with a flow rate of 30 sccm to 150 sccm, an aluminum source with a flow rate of 20 sccm to 200 sccm, and a nitrogen source with a flow rate of 20 slm to 50 slm at a temperature of 950°C to 1050°C and a pressure of 100 torr to 300 torr, to grow a second nitride barrier layer with a thickness of 5 nm to 20 nm.

6. The preparation method according to claim 3, characterized in that, The composite light-emitting layer includes spaced nanopillar spacer units and light-emitting units disposed between adjacent nanopillar spacer units; The method for preparing the composite light-emitting layer includes: The nanopillar spacer unit is prepared on the surface of the nitride diffusion layer; The light-emitting unit is prepared between adjacent nanopillar spacer units.

7. The preparation method according to claim 6, characterized in that, The fabrication of the light-emitting unit between adjacent nanopillar spacer units includes: A first light-emitting structural unit is grown on the surface of the nitride diffusion layer between the nanopillar spacer units; A second light-emitting structural unit is grown on the surface of the first light-emitting structural unit to obtain the light-emitting unit; Preferably, a first light-emitting structural unit is grown on the surface of the nitride diffusion layer between the nanopillar spacer units, comprising: A11. Under conditions of temperature of 800℃ to 950℃ and pressure of 200 torr to 400 torr, a gallium source with a flow rate of 100 sccm to 500 sccm, an indium source with a flow rate of 500 sccm to 2000 sccm, and a nitrogen source with a flow rate of 50 slm to 100 slm are introduced to grow a first quantum well layer with a thickness of 2 nm to 5 nm. A12. Under conditions of temperature of 800℃ to 950℃ and pressure of 200 torr to 400 torr, a gallium source with a flow rate of 100 sccm to 500 sccm and a nitrogen source with a flow rate of 50 slm to 100 slm are introduced to grow a first quantum barrier layer with a thickness of 3 nm to 25 nm. A13. Periodically and alternately execute A11 and A12 2 to 8 times to obtain the first light-emitting structural unit; Preferably, the step of setting the second light-emitting structural unit on the surface of the first light-emitting structural unit includes: A21. Under conditions of temperature of 650℃ to 850℃ and pressure of 200 torr to 400 torr, a gallium source with a flow rate of 100 torr to 500 torr, an indium source with a flow rate of 500 sccm to 2000 sccm, and a nitrogen source with a flow rate of 50 slm to 100 slm are introduced to grow a second quantum well layer with a thickness of 2 nm to 5 nm. A22. Under conditions of temperature of 750℃ to 950℃ and pressure of 200 torr to 400 torr, a gallium source with a flow rate of 100 sccm to 500 sccm and a nitrogen source with a flow rate of 50 slm to 100 slm are introduced to grow a second quantum barrier layer with a thickness of 3 nm to 15 nm. A23. The second light-emitting structural unit is obtained by periodically and alternately executing A21 and A22 2 to 15 times.

8. The preparation method according to claim 6, characterized in that, The fabrication of the nanopillar spacer units on the surface of the nitride diffusion layer includes: S1. An aluminum metal layer with a thickness of 10 nm to 100 nm is grown on the surface of the nitride diffusion layer. Then, the aluminum metal layer is annealed for 60 s to 300 s at a temperature of 700 °C to 1000 °C and a pressure of 50 to 150 to 150 to 150 to form nanospheres with a spacing of 100 nm to 500 nm and a diameter of 10 nm to 100 nm. S2. The nanospheres are subjected to heat treatment for 5 min to 60 min at a temperature of 700℃ to 1000℃ and a pressure of 200 to 600 tor, and then the heat treatment is interrupted for 100 s to 600 s to obtain the microsphere structure. S3. Growing nanopillars based on the microsphere structure; S4. Post-process the nanopillars to obtain the nanopillar spacer units; Preferably, the growth of nanopillars based on the microsphere structure includes: S31. Under conditions of temperature of 700°C to 1000°C and pressure of 400 torr to 600 torr, a silicon source is introduced into the surface of the microsphere structure at a flow rate of 200 sccm to 800 sccm for 10 to 100 seconds. S32, interrupt the silicon source supply for 10s to 180s; S33, and S31 and S32 are periodically alternated to obtain the nanopillar. Preferably, the top unit is an aluminum oxide layer, the side units are silicon oxide layers, and the post-processing of the nanopillars to obtain the nanopillar spacer units includes: S41. Under conditions of temperature of 400°C to 800°C and pressure of 200 torr to 600 torr, perform oxygen treatment for 60 to 120 seconds to form an aluminum oxide layer on the top surface of the nanopillar and a silicon oxide layer on the sidewall of the nanopillar. S42. Under conditions of temperature of 400°C to 800°C and pressure of 200 torr to 600 torr, perform hydrogen treatment for 20 to 60 seconds to decompose the oxygen element on the surface of the nitride diffusion layer between adjacent nanopillar spacer units. S43, S41 and S42 are periodically cyclically alternated 20 to 100 times to obtain the nanopillar spacer unit.

9. The preparation method according to any one of claims 4 to 8, characterized in that, The method for preparing the n-type nitride layer includes: Under conditions of temperature ranging from 1070°C to 1250°C and pressure ranging from 100 to 300 torr, a Si doping concentration of 1 × 10⁻⁶ m thick is grown on the growth substrate. 18 Up to 5×10 19 cm -3 n-type nitride layer; Preferably, the method for preparing the nitride diffusion layer includes: A nitride diffusion layer with a thickness of 10 nm to 50 nm is grown on the n-type nitride layer under conditions of temperature of 1020 °C to 1220 °C and pressure of 100 torr to 300 torr. The method for preparing the p-type nitride layer includes: Under conditions of 850°C to 1050°C and 200 torr to 500 torr, a gallium source with a flow rate of 100 sccm to 1000 sccm and a nitrogen source with a flow rate of 20 slm to 80 slm are introduced to grow a nitride barrier layer with a thickness of 20 nm to 200 nm and a Mg doping concentration of 1 × 10⁻⁶. 19 cm -3 Up to 5×10 20 cm -3 The p-type nitride layer.

10. An optoelectronic device, characterized in that, The optoelectronic device includes the nitride semiconductor epitaxial wafer as described in claim 1 or 2, or the nitride semiconductor epitaxial wafer prepared by the preparation method described in any one of claims 3 to 9.

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