A method for manufacturing a back contact solar cell with high double-sided rate and a BC module containing the same

Abstract

The application belongs to the technical field of solar cells, and discloses a preparation method of a high-bifaciality back contact solar cell and a BC module containing the same. The preparation method comprises the following steps: firstly, ICP etching is performed on the front surface of a silicon wafer by dynamically adjusting the flow ratio of sulfur hexafluoride to oxygen in three stages to form a gradient composite textured surface; then, a mask layer is deposited on the back surface, and a complementary nano-pillar array microstructure is prepared through nano-imprinting and etching; finally, based on the spectral characteristics of the front and back surfaces, a matching gradient antireflection film and a light transmission film are respectively deposited. The application effectively reduces light reflection loss through the morphology coordination of the front gradient textured surface and the back microstructure, and the optical matching of the front and back film systems. The prepared cell has a front surface reflectivity of ≤3%, a back surface reflectivity of ≤4%, a bifaciality of ≥92%, and excellent stability. The BC module prepared by using the same is stable and reliable in long-term use.

Description

Technical Field

[0001] This invention belongs to the field of solar cell technology, specifically relating to a method for preparing a high bifaciality back-contact solar cell and a BC module containing it. Background Technology

[0002] Back-contact solar cells, due to their unobstructed front surface and uniform, aesthetically pleasing appearance, have become a key development direction for distributed photovoltaics and the high-end market. Bifaciality, the ratio of the photoelectric conversion efficiency on the back side of the cell to that on the front side, is a core indicator determining the power generation gain of BC modules (back-contact solar cell modules). Studies show that for every 1% increase in bifaciality, the levelized cost of electricity (LCOE) for ground-mounted power plants can decrease by 0.3%-0.5%. However, currently, the bifaciality of mass-produced BC modules in the industry is generally between 85% and 88%, failing to fully realize their theoretical potential, indicating significant room for improvement.

[0003] In the existing technology, a large number of studies are dedicated to improving the bifaciality of BC modules, but their solutions still have many shortcomings, which can be mainly summarized into three categories: (1) Optimization technology with single front and back morphology. This type of technology only optimizes the morphology of the front textured surface or the back microstructure by improving the etching or imprinting process, aiming to reduce light reflection at a specific angle. For example, a textured surface of a specific size is prepared by adjusting the etching parameters. However, such methods have an inherent "spectral blind zone". For example, the optimized textured surface may only be effective in the visible light band, while the anti-reflection effect in the near-infrared band is not good. More importantly, it does not take into account the deposition of subsequent functional film layers. Irregular or overly sharp morphology will lead to uneven film layer coverage and stress concentration points, which will cause film layer cracking or decreased adhesion, posing a hidden danger to long-term reliability. (2) Single film layer improvement technology. This type of technology focuses on designing and depositing multiple antireflection films or light-transmitting films on the front and back of the battery, using the interference effect and refractive index matching between film layers to improve light transmittance. However, its design is often based on an ideal flat surface, which cannot effectively solve the complex light scattering problem caused by the presence of textured or microstructures on the surface, and the design of film parameters is somewhat blind. At the same time, this type of technology usually optimizes the front or back side in isolation, and cannot maximize the utilization of secondary light. (3) Simple superposition technology of front and back morphology and film layer. This type of technology attempts to simply superimpose the above two paths, that is, first prepare textured / microstructure, and then deposit film layer; but the two are only superimposed at the physical level. For example, the thickness and refractive index of the film layer are not customized for the specific three-dimensional morphology below it, resulting in inconsistent optical effects of the film layer at the slope, valley and other positions of the morphology, resulting in additional interface reflection loss.

[0004] Therefore, there is an urgent need to provide a method that can fully utilize the unique characteristics of BC modules—"no grid lines on the front and integrated on the back"—to enable independent and collaborative optical design, and effectively improve the dihedral ratio of BC modules. Summary of the Invention

[0005] This invention aims to at least solve one of the technical problems existing in the prior art. To this end, this invention proposes a method for fabricating a high bifaciality back-contact solar cell and a BC module containing the same. The method provided by this invention can significantly improve the bifaciality and long-term stability of back-contact solar cell modules.

[0006] This invention provides a method for fabricating a back-contact solar cell with high bifaciality.

[0007] Specifically, a method for fabricating a high bifaciality back-contact solar cell includes the following steps: S1. On the pre-treated silicon wafer, an inductively coupled plasma etching process is used to prepare a gradient-size textured surface on the front side, forming a gradient-size composite textured surface structure with a large bottom pyramid and a small top pyramid on the front side of the silicon wafer. S2. Mask layer deposition, nanoimprint patterning and plasma etching are performed sequentially on the back side of the silicon wafer to prepare the back microstructure; S3. Deposit a gradient antireflection film on the front side and a light-transmitting film on the back side, and finally perform post-processing to obtain a back contact solar cell; The steps for preparing the front gradient size velvet surface include the following three stages: In the first stage, sulfur hexafluoride and oxygen with a flow rate ratio of (3.8-4.2):1 were introduced and etched for 0.8-1.2 minutes at an RF power of 140-160W, a bias power of 25-35W, and a temperature of 50-70℃. In the second stage, sulfur hexafluoride and oxygen were introduced at a flow rate ratio of (3.3-3.7):(1.3-1.7), and etching was performed for 0.8-1.2 minutes under the same power and temperature conditions. In the third stage, sulfur hexafluoride and oxygen were introduced at a flow rate ratio of (2.8-3.2):(1.8-2.2), and etching was performed for 0.8-1.2 minutes under the same power and temperature conditions.

[0008] In some embodiments of the present invention, in the first stage, the flow rate of sulfur hexafluoride is 80-90 sccm; in the second stage, the flow rate of sulfur hexafluoride is 70-79 sccm; and in the third stage, the flow rate of sulfur hexafluoride is 60-69 sccm.

[0009] In some embodiments of the present invention, the pretreatment process in step S1 includes chemical cleaning and edge passivation etching steps.

[0010] The chemical cleaning process is as follows: First, the silicon wafer is immersed in a mixed solution of ammonia, hydrogen peroxide, and deionized water at 70-80℃ for 8-12 minutes; then, it is immersed in a mixed solution of hydrochloric acid, hydrogen peroxide, and deionized water at 65-75℃ for 6-10 minutes; finally, it is cleaned and dried. The volume ratio of ammonia to hydrogen peroxide to deionized water is 1:(0.8-1.2):(4-6), and the volume ratio of hydrochloric acid to hydrogen peroxide to deionized water is 1:(0.8-1.2):(5-7). The single-stage cleaning process achieves gentle cleaning, suitable for non-destructive processing of ultra-thin silicon wafers below 120μm, efficiently removing organic matter, and adaptable to batch production needs. Processing time is reduced by 20%, organic contaminant removal rate is ≥99.5%, and no corrosion marks are found on the silicon wafer surface. The secondary treatment process is mainly used to remove metallic impurities, with residual amounts of Fe, Cu, Al, and other metallic impurities ≤1×10⁻⁶. 10 atoms / cm 2 It can meet the needs of high-purity silicon wafers, improve metal removal efficiency by 15%, and reduce process energy consumption.

[0011] The edge passivation etching process is as follows: Plasma is used to etch (i.e., chamfer) the edges of the silicon wafer until the chamfer radius reaches 0.5-1 mm. This eliminates edge stress in subsequent processes, preventing film cracking and microstructure damage caused by stress concentration. The etching process conditions are: argon flow rate 40-60 sccm, power 100-140 W, etching time 2-5 min. This process achieves rapid chamfering, an edge stress release rate of no less than 90%, a 5% increase in film adhesion area, and an edge flatness Ra ≤ 0.3 μm.

[0012] In some embodiments of the present invention, in step S2, the mask layer deposition process is as follows: using SiH4 and nitrous oxide (N2O) as precursors, a SiO2 film layer is deposited on the back side of the silicon wafer using plasma-enhanced chemical vapor deposition (PECVD). Preferably, the flow rate ratio of SiH4 to N2O is 1:(12-18). The PCVD process conditions are: RF power 90-110W, temperature 260-300℃, and time 5-7min. These process conditions can control the film thickness to 90-110nm and the refractive index to 1.45-1.47, ensuring a pure SiO2 film layer. The SiO2 film layer is uniform and dense, and can serve as a good mask for subsequent pattern transfer and etching.

[0013] In some embodiments of the present invention, in step S2, the nanoimprint patterning process is as follows: a nanopillar template matching the size of the front textured surface is prepared, the template is pressed onto the SiO2 film layer, cured by ultraviolet light, and a patterned mask is formed after demolding.

[0014] In some embodiments of the present invention, in step S2, the plasma etching process is as follows: the pattern of the patterned mask is etched into the silicon wafer using inductively coupled plasma (ICP) etching to form a nanopillar array on the back side. Preferably, the process conditions for the inductively coupled plasma (ICP) etching are: SF6 and CHF3 with a flow rate ratio of (2-4):1, RF power of 180-220W, bias voltage of 18-22W, temperature of 45-55℃, and time of 2-5min.

[0015] Preferably, the period of the nanopillar array is 1.8-2.2 μm, the pillar diameter is 400-600 nm, and the etching depth is 500-700 nm. This size design matches the period of the small pyramid on the front side to achieve complementarity of the light scattering paths on the front and back sides.

[0016] In some embodiments of the present invention, step S2 further includes a defect passivation process after the plasma etching step. Specifically, the defect passivation process involves immersing the plasma-etched silicon wafer in a 1% (w / w) HF solution, followed by oxygen plasma treatment to repair sidewall defects. This defect passivation process effectively cleans etching residues and passivates surface defects, improving optical and electrical performance.

[0017] In some embodiments of the present invention, in step S3, the front gradient antireflective film sequentially comprises: a bottom alumina film, a middle titanium oxide film, and a surface gradient silicon nitride film; the thickness of the bottom alumina film is 14-16 nm, and the refractive index is 1.60-1.64; the thickness of the middle titanium oxide film is 7-9 nm, and the refractive index is 2.30-2.40; the thickness of the surface gradient silicon nitride film is 65-75 nm, and the refractive index gradually changes from 1.75-1.85 to 1.95-2.05.

[0018] In some embodiments of the present invention, in step S3, the preparation process of the front-side gradient antireflection film is as follows: First, an underlying alumina film is deposited using 99.999% pure trimethylaluminum (TMA) as the aluminum source and deionized water (H2O) as the oxygen source. At a deposition temperature of 170-190°C, using process parameters of TMA pulse time 0.08-0.12s, water pulse time 0.04-0.06s, and pulse interval 2-3s, a high-purity film with a thickness of 14-16nm and a refractive index of 1.60-1.64 (measured by an ellipsometer) is formed after 55-65 deposition cycles. The first layer has a refractive index that smoothly transitions to the textured silicon surface (refractive index 3.45) to reduce interface reflection. Furthermore, the oxygen vacancies in Al2O3 passivate dangling bonds on the silicon wafer surface and reduce recombination losses, thus providing both passivation and antireflection functions. Next, a middle titanium oxide film is deposited, using 99.99% pure titanium tetraisopropoxide (TTIP) as the titanium source and 99.999% pure oxygen (O2) as the oxygen source, to meet the antireflection requirements in the 700-900nm wavelength range. At a deposition temperature of 190-210℃, the TTIP pulse time is 0.18-0.22s, and the oxygen pulse time is 0.09-0.11s. With a pulse interval of 3-4 seconds, a high refractive index film with a thickness of 7-9 nm and a refractive index of 2.30-2.40 (measured by an ellipsometer) is formed after 25-35 deposition cycles. This film is designed for the optical path difference in the 700-900 nm wavelength band, and it forms interference superposition with the upper and lower films, reducing the reflectivity in this band by 40%-50%, accurately compensating for the reflection peak of the back microstructure. Finally, a graded silicon nitride film is deposited on the surface, using 99.999% pure silane (SiH4) as the silicon source and 99.999% pure ammonia (NH3) as the nitrogen source, at 240-260℃. At deposition temperature and 170-190W RF power, with a fixed silane flow rate of 20-25 sccm, the ammonia flow rate is increased from 8-12 sccm to 28-32 sccm in a gradient of 2 sccm every 5 cycles. After 130-150 total deposition cycles, a film with a thickness of 65-75 nm is formed, with its refractive index gradually changing from 1.75-1.85 to 1.95-2.05 (measured by an ellipsometer). The gradient design can cover the anti-reflection requirements of the entire 300-1100nm wavelength band and avoid the spectral blind zone of a single refractive index film. At the same time, the high refractive index of the surface layer can enhance the wear resistance of the film.

[0019] If necessary, after the front gradient antireflection film is prepared, post-treatment of the film layer can be performed. Specifically, the post-treatment process is as follows: the silicon wafer after the front gradient antireflection film has been deposited is placed in a plasma annealing device, and high-purity nitrogen gas (N2, purity 99.999%) is introduced (power 100W, temperature 300℃, time 5min) to improve the film layer density and adhesion. In some embodiments of the present invention, in step S3, the back-side light-transmitting film comprises: a bottom silicon dioxide film and a surface graded silicon nitride film; the thickness of the bottom silicon dioxide film is 45-55 nm and the refractive index is 1.44-1.47; the thickness of the surface graded silicon nitride film is 85-95 nm and the refractive index gradually changes from 1.48-1.52 to 1.92-1.98.

[0020] In some embodiments of the present invention, the preparation process of the back-side light-transmitting film in step S3 is as follows: Plasma-enhanced chemical vapor deposition (PECVD) was used to deposit a SiO2 film. The underlying SiO2 film used silane (SiH4, 99.999% purity) and nitrous oxide (N2O, 99.99% purity) as precursors, with a flow ratio controlled at 1:(20-30) (SiH4 15-25 sccm, N2O 3 75-600 sccm). The RF power was set at 110-130 W, the deposition temperature at 260-300℃, and deposition was continued for 9-11 minutes, forming a dense film layer with a thickness of 45-55 nm (refractive index 1.44-1.47 as measured by ellipsometer). This film layer can fill the gaps in the back-side microstructure, improving the interface passivation effect, while its low refractive index characteristic lays the foundation for long-wavelength light transmission. Subsequently, a gradient surface layer was deposited. Silicon nitride film was deposited by maintaining a constant SiH4 flow rate of 18-22 sccm, gradually decreasing the N2O flow rate from 180-220 sccm to 35-45 sccm, and gradually increasing the ammonia (99.999% purity) flow rate from 4-6 sccm to 23-27 sccm (adjusting the flow rate every 2 minutes of deposition). The RF power was set to 190-210 W and the deposition temperature to 310-330℃. The deposition was carried out for 14-16 minutes to form a gradient film with a thickness of 85-95 nm. The refractive index smoothly transitioned from 1.48-1.52 to 1.92-1.98 (measured by an ellipsometer). Through the refractive index gradient design adapted to the long wavelength band, the transmittance in the 900-1100 nm band was increased to over 94%. As needed, the back-side translucent film can be planarized using a chemical mechanical polishing (CMP) process. For example, SiO2 colloidal polishing slurry (particle size 50-100nm) can be selected, and the polishing pressure can be controlled at 2.5-3.5MPa, the polishing disc speed at 30-40rpm, and the polishing time at 1.5-2.5min. After testing with an atomic force microscope (AFM), the surface roughness of the microstructure Ra≤0.6nm can be effectively avoided due to surface unevenness, ensuring uniform incidence and absorption of light on the back side.

[0021] In some embodiments of the present invention, after depositing the front gradient antireflection film and the back light-transmitting film, the method further includes testing the combined spectral response of the front and back sides of the battery, and performing feedback and fine-tuning of the film layer parameters of the front gradient antireflection film and the back light-transmitting film according to preset optical performance thresholds. The logic of the fine-tuning is as follows: if the transmittance in the 400-600nm band is lower than a first preset threshold (e.g., transmittance < 94%), the thickness of the middle titanium oxide film in the front gradient antireflection film in step S3 is adjusted; if the transmittance in the 900-1100nm band is lower than a second preset threshold (e.g., transmittance < 92%), the deposition process parameters of the surface gradient silicon nitride film in the back light-transmitting film in step S3 are adjusted to increase its thickness.

[0022] In some embodiments of the present invention, in step S3, the post-processing involves depositing an anti-corrosion layer on the surface of the back transparent film. The anti-corrosion layer is a tin or tin alloy layer deposited by magnetron sputtering, with a thickness of 1.5-2.5 μm.

[0023] The present invention also provides a back-contact solar cell, which is prepared by the above-described preparation method.

[0024] The present invention also provides a BC module (back contact solar cell module) comprising at least one of the aforementioned back contact solar cells. Preferably, the BC module has a front reflectivity ≤3%, a back reflectivity ≤4%, an average transmittance across the entire wavelength range ≥93%, and a bifaciality ≥92%.

[0025] Compared with the prior art, the beneficial effects of the present invention are as follows: The back-contact solar cell fabricated in this invention utilizes a staged adjustment of the gas flow ratio to create a gradient textured surface structure on the front side, combining a large bottom pyramid with a small top pyramid. Simultaneously, a nanopillar array with complementary optical properties is fabricated on the back side. Based on the reflectance spectrum of the back-side microstructure and the transmission spectrum of the front side, a gradient antireflection film on the front side and a transparent film on the back side are specifically designed and deposited. This ingenious design reduces the front reflectance to below 3%, the back reflectance to below 4%, the average transmittance across the entire wavelength range to over 93%, the front photoelectric conversion efficiency to over 26.8%, and the bifaciality to over 92%. Furthermore, the back-contact solar cell provided by this invention exhibits excellent environmental stability, and the BC modules fabricated using it demonstrate stable and reliable long-term operation. Detailed Implementation

[0026] To enable those skilled in the art to more clearly understand the technical solutions described in this invention, the following embodiments are provided for illustration. It should be noted that the following embodiments do not constitute a limitation on the scope of protection claimed by this invention.

[0027] Unless otherwise specified, the raw materials, reagents or devices used in the following examples are available from conventional commercial sources or can be obtained by existing known methods.

[0028] Example 1 A method for fabricating a high bifaciality back-contact solar cell includes the following steps: S1. Pre-treatment of silicon wafers: First, immerse the silicon wafer in a mixed solution of ammonia, hydrogen peroxide, and deionized water with a volume ratio of 1:1:5 and treat it once at 75°C for 10 minutes. Then, immerse it in a mixed solution of hydrochloric acid, hydrogen peroxide, and deionized water with a volume ratio of 1:1:6 and treat it a second time at 70°C for 8 minutes. After cleaning and drying, perform edge passivation etching (i.e., chamfering). Use plasma to etch the edges of the silicon wafer with an argon flow rate of 50 sccm and a power of 120W for 3 minutes until the radius of the chamfered edge of the silicon wafer reaches 0.8 mm. This eliminates edge stress in subsequent processes and avoids film cracking and microstructure damage caused by edge stress concentration. After treatment, the edge flatness Ra ≤ 0.3 μm, the edge stress release rate is not less than 90%, and the film adhesion area is increased by 5%.

[0029] The pretreated silicon wafer is fixed in the vacuum reaction chamber of an inductively coupled plasma (ICP) etching machine, and the vacuum is evacuated to at least 5 × 10⁻⁶. -4 Pa; Preparation of gradient-sized textured surfaces: 1. First-stage etching (forming the bottom of the large pyramid): A mixture of sulfur hexafluoride and oxygen is introduced into the reaction chamber, with an initial flow ratio set to 4:1 (where the flow rate of sulfur hexafluoride is 84 sccm). The RF power is set to 150W, the bias power to 30W, and the etching temperature is controlled at 60℃. Etching is continued for 1 min. In this stage, sulfur hexafluoride is used as the main etching gas, and F is generated through plasma dissociation. - Ions perform anisotropic etching on the silicon wafer surface. A high proportion of sulfur hexafluoride ensures an etching rate of 900 nm / min, enabling rapid formation of the bottom basic structure. A low proportion of oxygen forms a thin oxide layer on the silicon wafer surface, slightly inhibiting sidewall etching and laying the outline for the large pyramid structure. After this stage, a preliminary pyramid shape with a height of 3.5 μm is formed on the silicon wafer surface. 2. Second stage etching: A mixture of sulfur hexafluoride and oxygen gas is introduced into the reaction chamber, with an initial flow ratio set at 3.5:1.5 (the flow rate of sulfur hexafluoride is 72.5 sccm). The RF power is set to 15W, the bias power to 30W, and the etching temperature is controlled at 60℃. Etching is carried out continuously for 1 minute at an etching rate of 650 nm / min. In this stage, sulfur hexafluoride serves as the main etching gas, generating F through plasma dissociation. -Ions are used to anisotropically etch the silicon wafer surface, increasing the pyramid height to 4.8 μm and refining the sidewall structure. 3. Third-stage etching (forming the top of the small pyramid): Maintaining stable power and temperature parameters, the flow ratio of sulfur hexafluoride to oxygen is further adjusted to 3:2 (sulfur hexafluoride flow rate is 63 sccm), and etching continues for 1 min. The high oxygen ratio increases the thickness of the oxide layer on the silicon wafer surface, significantly enhancing the sidewall protection. The etching rate is further reduced to 450 nm / min, with the etching process concentrated at the top of the pyramid and the corner areas. Through refined etching, a small pyramid structure with a height of approximately 2 μm is formed at the top of the large bottom pyramid (approximately 4.8 μm), ultimately forming a gradient-sized composite textured surface of "a large bottom pyramid of 4.8 μm + a small top pyramid of 2 μm".

[0030] S2. Backside Microstructure Fabrication: 1. The silicon wafer with the front surface textured finish is flipped and fixed in the plasma-enhanced chemical vapor deposition (PECVD) reaction chamber. The chamber is closed and evacuated to 5 × 10⁻⁶. -4 Pa, using silane (SiH4) and nitrous oxide (N2O) as precursors. The precursor flow ratio was controlled at 1:15 (SiH4 flow rate of 20 sccm, N2O flow rate of 300 sccm), with RF power set at 100W, deposition temperature at 280℃, and continuous deposition for 6 minutes (the mask layer thickness was controlled to be 100nm through real-time feedback from a film thickness monitor). 2. After deposition, the refractive index of the film was measured to be 1.46 (standard SiO2 refractive index range) using an ellipsometry to ensure film purity. This mask layer will serve as a hard mask for subsequent nanoimprinting and ICP etching, protecting the non-etched areas of the silicon wafer from damage. 3. Nanoimprinting transfer of microstructure patterns: A nanopillar template matching the size of the front textured surface was prepared: template period = side length of the front small pyramid (2μm), nanopillar diameter 500nm, height 800nm ​​(ensuring that the optical scattering characteristics of the back microstructure are complementary to those of the front textured surface). 4. Ultraviolet Nanoimprinting: The template is pressed onto the back SiO2 mask layer, a pressure of 8MPa is applied, and it is exposed to 365nm ultraviolet light for 30s (light intensity 100mW / cm²). 25. ICP etching to prepare the back-side nanopillar microstructure: Etching gas: SF6 / CHF3 = 3:1 (flow ratio), RF power 200W, bias power 20W, etching temperature 50℃, time 2.5min. 6. Morphology control: Etching depth 600nm, nanopillar array period 2μm, sidewall perpendicularity ≥85°, forming a composite structure of subwavelength microstructure + SiO2 mask residue layer, the back-side reflectivity is initially reduced to below 6%. 7. Microstructure defect passivation: The silicon wafer is immersed in 1% HF solution (time 5s) to remove the residual polymer from the etching, and then treated with oxygen plasma (power 60W, time 2min) to passivate the sidewall defects of the microstructure.

[0031] S3. First, deposit a gradient antireflection film on the front side. Then, place the silicon wafer with the back microstructure fabricated in an ultraviolet-visible-near-infrared spectrophotometer (Agilent Cary 7000) and test the reflectance spectrum of the back microstructure in the full wavelength range of 300-1100nm. Through spectral curve fitting, it was determined that the back microstructure has a reflectance peak (4.5%-5.5%) in the near-infrared band of 700-900nm, while the reflectance in the visible band of 400-600nm is as low as 3%-4%. Therefore, the core design goal of the gradient antireflection film on the front side is to enhance the antireflection in the 700-900nm band while maintaining the low reflectance characteristics in the visible band. An atomic layer deposition (ALD) system (ASMIntelliGap) was employed to precisely control the thickness and refractive index of each film layer by controlling the deposition process atomically. First, an alumina film was deposited using 99.999% pure trimethylaluminum (TMA) as the aluminum source and deionized water (H2O) as the oxygen source. At a deposition temperature of 180℃, with process parameters of 0.10s TMA pulse time, 0.05s water pulse time, and 3s pulse interval, a film with a thickness of 15nm and a refractive index of 1.62 was formed after 60 deposition cycles. The high-purity film layer (tested with an ellipsometry) has a refractive index that smoothly transitions to the textured silicon surface (refractive index 3.45) to reduce interface reflection. Furthermore, the oxygen vacancies in Al2O3 can passivate dangling bonds on the silicon wafer surface and reduce recombination losses, thus providing both passivation and antireflection functions. Next, a middle titanium oxide film is deposited, using 99.99% pure titanium tetraisopropoxide (TTIP) as the titanium source and 99.999% pure oxygen (O2) as the oxygen source, to meet the antireflection requirements in the 700-900nm wavelength range. At a deposition temperature of 200℃, the TTIP pulse duration is measured. With parameters set at 0.20s, oxygen pulse time of 0.10s, and pulse interval of 3s, a high refractive index film with a thickness of 8nm and a refractive index of 2.35 (measured by an ellipsometer) was formed after 30 deposition cycles. This film was designed for the optical path difference in the 700-900nm wavelength band, and its interference superposition with the upper and lower layers reduced the reflectivity in this band by 40%-50%, precisely compensating for the reflection peak of the back-side microstructure. Finally, a graded silicon nitride film was deposited on the surface, using 99.999% pure silane (SiH4) as the silicon source. Using ammonia as the nitrogen source, at a deposition temperature of 250℃ and an RF power of 180W, the silane flow rate was fixed at 23 sccm. The ammonia flow rate was increased from 10 sccm to 30 sccm in a gradient of 2 sccm every 5 cycles. After 140 total deposition cycles, a film with a thickness of 70 nm was formed. Its refractive index gradually changed from 1.80 to 2.00 (measured by an ellipsometry). The gradient design can cover the anti-reflection requirements of the entire 300-1100nm wavelength band and avoid the spectral blind zone of a single refractive index film. At the same time, the high refractive index of the surface layer can enhance the wear resistance of the film.The silicon wafer with the three gradient films deposited is placed in a plasma annealing equipment and high-purity nitrogen gas (N2, purity 99.999%) is introduced (power 100W, temperature 300℃, time 5min) to improve the film density and adhesion.

[0032] A back-side transparent film is then deposited. Based on the transmission spectrum of the front-side antireflection film, the back-side film layer is adjusted in reverse. A bottom silica film and a surface graded silicon nitride film are deposited using plasma-enhanced chemical vapor deposition (PECVD). The bottom silica film uses silane (SiH4, 99.999% purity) and nitrous oxide (N2O, 99.99% purity) as precursors, with a controlled flow ratio of 1:25 (SiH4 20 sccm, N2O). At a deposition rate of 500 sccm, with an RF power of 120 W and a deposition temperature of 280 °C, deposition was carried out for 10 minutes to form a dense film with a thickness of approximately 50 nm (refractive index 1.46 as measured by ellipsometer). This film can fill the gaps in the back microstructure, improve the interface passivation effect, and its low refractive index characteristic lays the foundation for long-wavelength light transmission. Subsequently, a gradient silicon nitride film was deposited on the surface, keeping the SiH4 flow rate constant at 20 sccm, gradually decreasing the N2O flow rate from 200 sccm to 40 sccm, and gradually increasing the ammonia (purity 99.999%) flow rate from 5 sccm to 25 sccm (adjusting the flow rate every 2 minutes of deposition). The RF power was set to 200 W and the deposition temperature to 320 °C, and deposition was carried out continuously. After 15 minutes, a gradient film with a thickness of 90 nm was formed, with its refractive index smoothly transitioning from 1.50 to 1.95 (measured by an ellipsometry). Through a refractive index gradient design adapted for long wavelengths, the transmittance in the 900-1100 nm wavelength range was increased to over 94%. Finally, chemical mechanical polishing (CMP) was used to planarize the film. SiO2 colloidal polishing slurry (particle size 50-100 nm) was selected, and the polishing pressure was controlled at 3.0 MPa, the polishing disc speed at 35 rpm, and the polishing time at 2.0 min. Atomic force microscopy (AFM) testing showed that the surface roughness Ra of the microstructure was ≤0.6 nm, effectively avoiding light scattering loss caused by surface unevenness and ensuring uniform incident and absorption of light from the back side.

[0033] Finally, post-processing was performed, using magnetron sputtering plasma tin plating to modify the surface of the back transparent film for corrosion protection: a tin target with a purity of 99.99% was used as the sputtering source, and high-purity argon gas (purity of 99.999%) was introduced as the working gas. The argon gas flow rate was controlled at 35 sccm, the sputtering power was set to 80W, the deposition temperature was set to 165℃, and the deposition was carried out continuously for 3.0 min, forming a dense tin-based anti-corrosion layer with a thickness of 2.0μm on the surface of the back transparent film. This coating can effectively block the penetration of corrosive media such as moisture and salt in the air, and improve the long-term environmental stability of the film layer.

[0034] Example 2 The difference between Example 2 and Example 1 is as follows: In step S1, the silicon wafer is first treated with a mixed solution of ammonia, hydrogen peroxide, and deionized water in a volume ratio of 1:1:4 at 80°C for 8 minutes. Then, a mixed solution of hydrochloric acid, hydrogen peroxide, and deionized water in a volume ratio of 1:1:5 is used for a second treatment at 75°C for 6 minutes. Finally, plasma etching is performed on the edges of the silicon wafer at an argon flow rate of 60 sccm and a power of 140 W for 2 minutes.

[0035] In step S1, during the fabrication of the front gradient textured surface: 1. First-stage etching: The flow ratio of sulfur hexafluoride (SF6) to oxygen is 4:1, the SF6 flow rate is 80 sccm, the RF power is set to 140 W, the bias power to 25 W, the etching temperature is controlled at 55°C, the etching rate is 850 nm / min, and the etching is continued for 1.2 min. After this stage, a preliminary pyramid shape with a height of 3.8 μm is formed on the silicon wafer surface. 2. Second-stage etching: The flow ratio of SF6 to oxygen is 3.5:1.5, the SF6 flow rate is 70 sccm, the RF power is set to 140 W, the bias power to 25 W, the etching temperature is controlled at 55°C, and the etching is continued for 1.2 min at an etching rate of 600 nm / min, increasing the pyramid height to 5.0 μm and refining the sidewall structure. 3. Third-stage etching: Maintaining stable power and temperature parameters, the flow ratio of sulfur hexafluoride to oxygen was further adjusted to 3:2, with a sulfur hexafluoride flow rate of 60 sccm. Etching was carried out continuously for 1.2 min at an etching rate of 400 nm / min. This resulted in the formation of a small pyramid structure with a height of approximately 2 μm at the top of the large bottom pyramid (approximately 5 μm in size), ultimately creating a gradient-sized composite textured surface consisting of a 5.0 μm large bottom pyramid and a 2 μm small top pyramid.

[0036] The remaining preparation process is the same as in Example 1.

[0037] Example 3 The difference between Example 3 and Example 1 is as follows: In step S1, the silicon wafer is first treated with a mixed solution of ammonia, hydrogen peroxide, and deionized water in a volume ratio of 1:1:6 at 70°C for 12 minutes. Then, a mixed solution of hydrochloric acid, hydrogen peroxide, and deionized water in a volume ratio of 1:1:7 is used for a second treatment at 65°C for 10 minutes. Finally, plasma etching is performed on the edges of the silicon wafer at an argon flow rate of 40 sccm and a power of 100 W for 4 minutes.

[0038] In step S1, during the fabrication of the front gradient textured surface: 1. First-stage etching: The flow ratio of sulfur hexafluoride (SF6) to oxygen is 4:1, the SF6 flow rate is 85 sccm, the RF power is set to 160 W, the bias power to 35 W, the etching temperature is controlled at 65°C, the etching rate is 950 nm / min, and the etching is continued for 0.8 min. After this stage, a preliminary pyramid shape with a height of 3.2 μm is formed on the silicon wafer surface. 2. Second-stage etching: The flow ratio of SF6 to oxygen is 3.5:1.5, the SF6 flow rate is 75 sccm, the RF power is set to 160 W, the bias power to 35 W, the etching temperature is controlled at 65°C, and the etching is continued for 0.8 min at an etching rate of 700 nm / min, increasing the pyramid height to 4.5 μm and refining the sidewall structure. 3. Third-stage etching: Maintaining stable power and temperature parameters, the flow ratio of sulfur hexafluoride to oxygen was further adjusted to 3:2, with a sulfur hexafluoride flow rate of 65 sccm. Etching was carried out continuously for 0.8 min at an etching rate of 500 nm / min. This resulted in the formation of a small pyramid structure with a height of approximately 2.1 μm at the top of the large bottom pyramid (approximately 4.5 μm in size), ultimately creating a gradient-sized composite textured surface consisting of a 4.5 μm large bottom pyramid and a 2.1 μm small top pyramid.

[0039] The remaining preparation process is the same as in Example 1.

[0040] Comparative Example 1 The difference between Comparative Example 1 and Example 1 is as follows: In step S1, during the fabrication of the front gradient-sized textured surface, the first-stage etching and the second-stage etching processes are combined. The first-stage etching conditions are used directly to form a preliminary pyramid with a height of 4.8 μm on the silicon wafer surface. Then, a small pyramid structure with a height of approximately 2.0 μm is formed at the top using the third-stage etching conditions described in Example 1.

[0041] The remaining preparation process is the same as in Example 1.

[0042] Comparative Example 2 The difference between Comparative Example 2 and Example 1 is as follows: In the preprocessing step S1, the edge passivation etching process is omitted, and the front gradient size textured surface is directly prepared after chemical cleaning.

[0043] The remaining preparation process is the same as in Example 1.

[0044] Product effectiveness test The back-contact solar cells prepared in Examples 1-3 and Comparative Examples 1-2 were subjected to performance tests, mainly including optical performance testing, electrical performance and bifaciality testing, and reliability and aging performance testing.

[0045] (1) The methods for testing optical performance are as follows: Front and back reflectance measurement: Measurements were performed using a UV-Vis-NIR spectrophotometer equipped with an integrating sphere. During testing, the battery sample was placed in the test optical path, and a standard light source (wavelength range 300-1100nm) was incident perpendicularly on both the front and back of the battery. The integrating sphere was used to collect the reflected light signal at all angles, and the spectrometer recorded the spectral reflectance data. The weighted average reflectance across the entire wavelength range was then calculated.

[0046] Average transmittance across the entire wavelength range: Measurements were performed using the same UV-Vis-NIR spectrophotometer in transmission mode. A standard light source was incident perpendicularly from the front of the battery, and an integrating sphere was used on the back of the battery to collect all transmitted light (including direct and scattered light). The spectral transmittance data was measured, and its average value in the 300-1100 nm range was calculated.

[0047] (2) The methods for testing electrical properties and duplexity are as follows: Front-side photoelectric conversion efficiency testing: under standard test conditions (AM 1.5G spectrum, 1000 W / m²). 2 Measurements were performed using an AAA-grade solar simulator and a matching IV testing system at an irradiance of 25°C (cell temperature). During testing, it was ensured that the light irradiated only uniformly onto the front of the cell, while the back of the cell was completely shaded. The current-voltage characteristic curve of the cell was measured to obtain the short-circuit current, open-circuit voltage, and fill factor, and the front photoelectric conversion efficiency was calculated.

[0048] Backside photoelectric conversion efficiency testing: Maintain the same standard test conditions and equipment. Flip the battery so that light shines evenly only on the back side, while ensuring the front side is completely shaded. Measure the current-voltage characteristic curve under backside illumination and calculate the backside photoelectric conversion efficiency.

[0049] Bifaciality calculation: Based on the measured front and back photoelectric conversion efficiencies, the bifaciality of the battery is calculated using the formula (back efficiency / front efficiency) × 100%.

[0050] (3) The methods for reliability and aging performance testing are as follows: Damp heat aging test and reliability assessment: Battery samples after initial performance testing were placed in a programmable damp heat aging test chamber. The chamber temperature was set to 85℃ and the relative humidity to 85% RH, and a constant temperature and humidity treatment was performed for 1000 consecutive hours. After aging, the samples were removed and evaluated according to the following methods: Interface morphology observation: The cross-section of the battery is observed using a scanning electron microscope, with a focus on the interface between the functional film layer and the silicon substrate, as well as between the film layers, to confirm whether there are defects such as peeling, cracking or bulging.

[0051] Adhesion test: The adhesion of the anti-corrosion layer or key functional film layer on the battery surface is quantitatively tested according to the tape peeling method specified in standard ASTM D3359, and the peel strength value is recorded.

[0052] Performance degradation assessment: Compare the photoelectric conversion efficiency of the front and back sides of the battery samples before and after damp heat aging treatment, recalculate the bifaciality, and assess the degree of degradation.

[0053] The test results are shown in Table 1.

[0054] Table 1 As shown in Table 1, the back-contact solar cell prepared in the embodiments of the present invention has a front reflectivity ≤2.9%, a back reflectivity ≤3.8%, an average transmittance of ≥93.3% across the entire wavelength band, a front efficiency ≥26.8%, a back efficiency ≥24.7%, and a bifaciality ≥92.2%. After damp heat aging test, the film layer has no defects such as peeling, cracking, or bulging, the adhesion of the anti-corrosion layer is still greater than or equal to 5.2 N / cm, and the bifaciality attenuation is less than 1.1%, which can ensure the long-term operational reliability of the BC module in complex outdoor environments.

[0055] Comparative Example 1 simplifies the gradient-size textured surface preparation process of Example 1, which was divided into three stages, into two stages. This results in the textured surface structure changing from a gradient composite structure of "large pyramid at the bottom + small pyramid at the top" to a pyramid structure with a more uniform size distribution, a less robust bottom structure, and an unnatural transition. This significantly reduces the light scattering ability of the battery and the compatibility with subsequent film layers. Although the interface morphology and adhesion are less affected after aging, the final bifaciality and long-term stability and reliability deteriorate significantly.

[0056] Comparative Example 2 omitted the plasma edge chamfering process, which leads to stress concentration and sharp edges on the silicon wafer. These sharp edges are highly susceptible to becoming crack initiation points during subsequent film deposition processes and under long-term thermal stress. This not only significantly reduces film adhesion but also makes the film prone to peeling or cracking after humid heat aging, ultimately causing severe performance degradation.

[0057] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention. Therefore, the scope of protection of this patent should be determined by the appended claims.

Claims

1. A method for fabricating a back-contact solar cell, characterized in that, Includes the following steps: S1. On the pre-treated silicon wafer, an inductively coupled plasma etching process is used to prepare a gradient-size textured surface on the front side, forming a gradient-size composite textured surface structure with a large bottom pyramid and a small top pyramid on the front side of the silicon wafer. S2. Mask layer deposition, nanoimprint patterning and plasma etching are performed sequentially on the back side of the silicon wafer to prepare the back microstructure; S3. Deposit a gradient antireflection film on the front side and a light-transmitting film on the back side, and finally perform post-processing to obtain a back contact solar cell; The steps for preparing the front gradient size velvet surface include the following three stages: In the first stage, sulfur hexafluoride and oxygen with a flow rate ratio of (3.8-4.2):1 were introduced and etched for 0.8-1.2 minutes at an RF power of 140-160W, a bias power of 25-35W, and a temperature of 50-70℃. In the second stage, sulfur hexafluoride and oxygen were introduced at a flow rate ratio of (3.3-3.7):(1.3-1.7), and etching was performed for 0.8-1.2 minutes under the same power and temperature conditions. In the third stage, sulfur hexafluoride and oxygen were introduced at a flow rate ratio of (2.8-3.2):(1.8-2.2), and etching was performed for 0.8-1.2 minutes under the same power and temperature conditions.

2. The preparation method according to claim 1, characterized in that, In step S2, the mask layer deposition process is as follows: using SiH4 and N2O as precursors, a SiO2 film layer is deposited on the back side of the silicon wafer using plasma-enhanced chemical vapor deposition.

3. The preparation method according to claim 1, characterized in that, In step S2, the nanoimprint patterning process is as follows: a nanopillar template matching the size of the front textured surface is prepared, the template is pressed onto the SiO2 film layer, cured by ultraviolet light, and a patterned mask is formed after demolding; the plasma etching process is as follows: the pattern of the patterned mask is etched into the silicon wafer by inductively coupled plasma etching to form a nanopillar array on the back side.

4. The preparation method according to claim 3, characterized in that, The nanopillar array has a period of 1.8-2.2 μm, a pillar diameter of 400-600 nm, and an etching depth of 500-700 nm. This size design matches the period of the small pyramid on the front side to achieve complementarity of the light scattering paths on the front and back sides.

5. The preparation method according to claim 1, characterized in that, In step S3, the front gradient antireflective film sequentially comprises: a bottom alumina film, a middle titanium oxide film, and a surface gradient silicon nitride film; the bottom alumina film has a thickness of 14-16 nm and a refractive index of 1.60-1.64; the middle titanium oxide film has a thickness of 7-9 nm and a refractive index of 2.30-2.40; the surface gradient silicon nitride film has a thickness of 65-75 nm and a refractive index that gradually changes from 1.75-1.85 to 1.95-2.

05.

6. The preparation method according to claim 1 or 5, characterized in that, In step S3, the back light-transmitting film comprises: a bottom silicon dioxide film and a surface graded silicon nitride film; the bottom silicon dioxide film has a thickness of 45-55 nm and a refractive index of 1.44-1.47; the surface graded silicon nitride film has a thickness of 85-95 nm and a refractive index that gradually changes from 1.48-1.52 to 1.92-1.

98.

7. The preparation method according to claim 6, characterized in that, After depositing the front gradient antireflection film and the back light-transmitting film, the method further includes testing the combined spectral response of the front and back sides of the battery, and providing feedback and fine-tuning of the film parameters of the front gradient antireflection film and the back light-transmitting film according to a preset optical performance threshold.

8. The preparation method according to claim 6, characterized in that, In step S3, the post-processing procedure is to deposit an anti-corrosion layer on the surface of the back transparent film.

9. A back-contact solar cell, characterized in that, It is prepared by the preparation method according to any one of claims 1-8.

10. A BC component, characterized in that, It includes at least one back-contact solar cell as described in claim 9.

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