Nitride epitaxial structure, method for preparing same, and micro-led device

Abstract

The application discloses a nitride epitaxial structure, a preparation method thereof and a Micro-LED device. The nitride epitaxial structure comprises a substrate, a first semiconductor material layer, a nitride light-emitting layer and a second semiconductor material layer, and the nitride light-emitting layer comprises a quantum well layer with a high In component; the first semiconductor material layer comprises a composite nanostructure layer, and the composite nanostructure layer comprises a plurality of composite nanostructures with different sizes; the composite nanostructure comprises a Si nano-pillar body and an Al metal microstructure, and the surfaces of the Si nano-pillar body and the Al metal microstructure are nitrided to form SiN and AlN. The application introduces a composite nanostructure layer and tensile stress, greatly improves In incorporation capacity, and utilizes direct mutual relaxation of composite nanostructures with different sizes to release stress and improve the epitaxial quality of the nitride quantum well layer, so that a nitride quantum well structure with low stress and a high In component is finally obtained, and the preparation requirement of a full-nitride multi-color device is met.

Description

Technical Field

[0001] This invention relates to the field of nitride semiconductor device technology, and more particularly to a nitride epitaxial structure, its preparation method, and a Micro-LED device. Background Technology

[0002] Micro-LED is composed of an array of micron-sized semiconductor light-emitting units. The development of Micro-LED is considered to be one of the fastest-growing display technologies in the world. Due to its advantages such as small size, high resolution, low power consumption, and high reliability, it is widely used in various fields such as visible light communication applications, large flat panel displays, virtual reality and wearable displays, television and lighting, optogenetics and light sources for neural interfaces.

[0003] It is widely known in the industry that nitride semiconductors are used to manufacture blue and green Micro-LEDs, while phosphide semiconductors are currently used for red Micro-LEDs. However, combining different semiconductor materials increases the production difficulty and manufacturing cost of RGB full-color Micro-LEDs. Compared to nitrides, phosphides have a phase diffusion coefficient that is an order of magnitude higher and a surface recombination rate that is two orders of magnitude higher. The high surface recombination rate and large carrier diffusion length of phosphides exacerbate surface recombination in the device. As the size shrinks, the efficiency of phosphide Micro-LED chips will decrease more significantly. In addition, phosphides have poor temperature characteristics and their performance degrades severely at high temperatures. Therefore, the fabrication of Micro-LEDs based on all-nitride materials holds promise for realizing full-color displays.

[0004] However, due to the scarcity of GaN single-crystal materials in nature and the extreme difficulty in growing bulk single-crystal GaN, GaN material growth mainly employs heteroepitaxial methods. Si substrates have become a focus of industry attention due to their low cost, large size, and conductivity. However, the large lattice mismatch and thermal stress mismatch between the Si substrate and the epitaxial layer generate enormous stress, leading to cracks and even splitting in the epitaxial layer. Compared to Si substrates, sapphire (Al2O3) epitaxial growth technology is more mature and has become the commonly used substrate material in the industry.

[0005] Nitride red LED units require high-In content materials as quantum well layers to achieve red light emission. Therefore, high-In content quantum well layers will increase the lattice mismatch between them and quantum barrier layers, leading to the generation of interface defects and increased stress within the quantum well layer. Defects lead to increased nonradiative recombination, while stress severely affects In incorporation into the quantum well layer. At the same time, stress will also cause a piezoelectric field that exacerbates the quantum confinement Stark effect (QCSE), affecting the radiative recombination efficiency of charge carriers. Therefore, using existing technologies to directly fabricate nitride red LED units faces the problems of low efficiency and wide spectral width.

[0006] In summary, achieving low-stress, high-In-content nitride quantum well structures on heterogeneous substrates such as sapphire is key to fabricating high-performance red Micro-LED units and is of great significance for accelerating the industrial application of Micro-LEDs. Summary of the Invention

[0007] To address the shortcomings of existing technologies, the present invention aims to provide a nitride epitaxial structure, its preparation method, and a Micro-LED device.

[0008] To achieve the aforementioned objectives, the technical solution adopted by this invention includes:

[0009] In a first aspect, the present invention provides a nitride epitaxial structure comprising a substrate, a first semiconductor material layer, a nitride light-emitting layer and a second semiconductor material layer sequentially stacked along a specified direction, wherein the nitride light-emitting layer includes a nitride quantum well layer and the In component of the nitride quantum well layer accounts for more than 30% of the total number of atoms.

[0010] The first semiconductor material layer includes multiple sublayers, and each of the multiple sublayers contains a composite nanostructure layer, wherein the composite nanostructure layer includes multiple composite nanostructures with different sizes and independently spaced distribution.

[0011] Along the specified direction, the composite nanostructure comprises sequentially connected Si nanopillars and Al metal microstructures, wherein the surface of the Si nanopillars is nitrided to form a SiN layer, and the surface of the Al metal microstructure is nitrided to form an AlN layer.

[0012] Secondly, the present invention also provides a method for preparing a nitride epitaxial structure, comprising:

[0013] A first semiconductor material layer is epitaxially grown on the substrate surface;

[0014] A nitride light-emitting layer is epitaxially grown on the surface of the first semiconductor material layer;

[0015] A second semiconductor material layer is epitaxially grown on the surface of the nitride light-emitting layer;

[0016] The process of growing the first semiconductor material layer includes forming a composite nanostructure layer:

[0017] Repeating step ad multiple times forms Al metal microstructures and Si nanopillars:

[0018] a. Perform Al thermal surface treatment at a temperature of 500-1000℃;

[0019] b. Perform the first annealing treatment at a temperature of 500-1000℃;

[0020] c. Perform Si hot surface treatment at a temperature of 500-1000℃;

[0021] d. Perform a second annealing treatment at a temperature of 500-1000℃;

[0022] And, step e is performed to nitrid the surfaces of the Al metal microstructure and the Si nanopillars:

[0023] e. Perform N-type thermal surface treatment at a temperature of 900-1100℃.

[0024] Based on the above technical solution, compared with the prior art, the beneficial effects of the present invention include at least the following:

[0025] This invention introduces a composite nanostructure layer between the substrate and the nitride light-emitting layer. By utilizing the thermal adaptation and lattice mismatch between Si and nitride materials to introduce tensile stress in the epitaxial layer, the incorporation capability of In in the nitride quantum well layer is greatly improved. At the same time, the direct mutual relaxation of composite nanostructures of different sizes can effectively release stress, reduce the stress distribution of the epitaxial layer at the substrate interface, and improve the epitaxial quality of the nitride quantum well layer. Finally, a low-stress, high-In-content nitride quantum well structure is obtained, which meets the fabrication requirements of all-nitride multi-color Micro-LEDs and has great significance for their industrial application.

[0026] The above description is merely an overview of the technical solution of the present invention. In order to enable those skilled in the art to better understand the technical means of this application and to implement it in accordance with the contents of the specification, the preferred embodiments of the present invention are described below in conjunction with detailed drawings. Attached Figure Description

[0027] Figure 1 This is a cross-sectional schematic diagram of a nitride epitaxial structure provided in a typical embodiment of the present invention;

[0028] Figure 2 This is a schematic diagram of the distribution state of the composite nanostructure provided in another typical embodiment of the present invention;

[0029] Figure 3 This is a cross-sectional schematic diagram of the nitride epitaxial structure provided in another typical embodiment of the present invention.

[0030] Explanation of reference numerals in the attached figures:

[0031] 1. Substrate; 2. First semiconductor material layer; 3. Nitride light-emitting layer; 4. Second semiconductor material layer;

[0032] 21. Nitride roughening layer; 22. Undoped nitride layer; 23. Doped nitride layer; 24. Nitride barrier layer; 25. Nitride buffer layer; 26. Nitride capping layer;

[0033] 20. Composite nanostructure layer; 201. AlN islands; 202. Si nanopillars; 203. Al metal microstructure;

[0034] 31. Nitride quantum well layer; 32. Nitride quantum barrier layer. Detailed Implementation

[0035] In view of the shortcomings of the prior art, the inventors of this invention, through long-term research and extensive practice, have proposed the technical solution of this invention. The following will further explain and illustrate this technical solution, its implementation process, and its principles.

[0036] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and therefore the scope of protection of the invention is not limited to the specific embodiments disclosed below.

[0037] Moreover, relational terms such as “first” and “second” are used merely to distinguish one component or method step from another that has the same name, and do not necessarily require or imply any such actual relationship or order between these components or method steps.

[0038] The embodiments of the present invention propose a Micro-LED epitaxial wafer containing red light emitting units and its preparation method, which overcomes the problem of difficult growth of high In composition nitride quantum well layers in the prior art. The purpose is to improve the crystal quality of the nitride quantum well layer, reduce the probability of nonradiative recombination caused by defects, thereby improving the quantum efficiency of the epitaxial wafer, reducing the emission spectrum width, and improving the emission color purity and stability of the epitaxial wafer.

[0039] For the purposes mentioned above, see [link to relevant documentation]. Figure 1 and Figure 3As shown, this embodiment of the invention first provides a nitride epitaxial structure, including a substrate 1, a first semiconductor material layer 2, a nitride light-emitting layer 3, and a second semiconductor material layer 4 sequentially stacked along a specified direction. The first semiconductor material layer 2 and the second semiconductor material layer 4 have opposite conductivity characteristics, and the nitride light-emitting layer 3 includes a nitride quantum well layer 31, wherein the In component atomic ratio of the nitride quantum well layer 31 is greater than 30%. The first semiconductor material layer 2 includes multiple sublayers, and each of the multiple sublayers contains a composite nanostructure layer 20. The composite nanostructure layer 20 includes multiple composite nanostructures with different sizes and independently spaced distribution. Along the specified direction, the composite nanostructure includes Si nanopillars 202 and Al metal microstructures 203 sequentially connected. The surface of the Si nanopillars 202 is nitrided to form a SiN layer, and the surface of the Al metal microstructures 203 is nitrided to form an AlN layer.

[0040] Regarding the specific structure of each sublayer in the first semiconductor layer, the embodiments of the present invention provide two different methods. One method is to place the composite nanostructure layer 20 near the substrate 1, and the other method is to place the composite nanostructure layer 20 relatively close to the nitride light-emitting layer 3, with a nitride capping layer 26 between it and the nitride light-emitting layer 3.

[0041] Regarding the first method described above, in some embodiments, along the specified direction, the first semiconductor material layer 2 sequentially includes: the composite nanostructure layer 20, and a nitride roughening layer 21, an undoped nitride layer 22, and a doped nitride layer 23. The composite nanostructure also includes a plurality of AlN islands 201. One end of the Si nanopillar 202 is connected to the AlN island 201, and the other end is connected to the Al metal microstructure 203.

[0042] In some embodiments, the AlN island structure includes a first island and a second island, the volume ratio of the first island to the second island is (1.2-2):1, and the second island is distributed between any two adjacent first islands.

[0043] Regarding specific dimensions, in some implementations, the diameter of the first island is 500-3000 nm.

[0044] As a typical example, such as Figure 1As shown, the red light unit of the Micro-LED epitaxial wafer prepared by the first layering method described above includes a substrate 1, a composite nanostructure layer 20, a nitride roughening layer 21, an undoped nitride layer 22, an n-type doped nitride layer 23, a nitride light-emitting layer 3, and a p-type nitride layer (as the second semiconductor material layer 4) in a specified direction. The composite nanostructure layer 20 includes: composite nanostructures with different spatial sizes distributed at intervals, specifically including AlN islands 201 as the substrate microstructure, Si nanopillars 202 in the middle, and Al metal microstructures 203 at the top.

[0045] Regarding the second method described above, in some other embodiments, along the specified direction, the first semiconductor material layer 2 sequentially includes: a doped nitride layer 23, a nitride barrier layer 24, a nitride buffer layer 25, the composite nanostructure layer 20, and a nitride capping layer 26. One end of the Si nanopillar 202 is connected to the nitride buffer layer 25, and the other end is connected to the Al metal microstructure 203. The nitride buffer layer 25 is doped with Si. Along the specified direction, the Si doping concentration in the nitride buffer layer 25 is (5 × 10⁻⁶) / 2. 17 -1×10 18 cm -3 Linearly decreases to (0-1×10) 17 cm -3 The Si doping concentration in the nitride capping layer 26 ranges from (0-1×10⁻⁶) to (1×10⁻⁶)⁻¹. 17 cm -3 Linearly increasing to (2×10) 17 -8×10 17 cm -3 ).

[0046] In some more specific embodiments, the Al metal microstructure 203 includes a first metal microstructure and a second metal microstructure, the volume ratio of the first metal microstructure and the second metal microstructure being (1.2-2):1, and the second metal microstructure being distributed between any two adjacent first metal microstructures.

[0047] Regarding the specific dimensions, in some more specific embodiments, the diameter of the first metal microstructure is 100-500 nm; and / or, the height of the Si nanopillars 202 is 10-100 nm.

[0048] See details Figure 3 As shown, in the second method, since the composite nanostructure layer 20 is closer to the nitride light-emitting layer 3, an uneven structure can be formed in the nitride capping layer 26 and the nitride light-emitting layer 3. This structure has higher photoelectric conversion performance and light extraction efficiency compared to the flat film structure in the first method.

[0049] As a typical example, such as Figure 3 As shown, the red light unit of the Micro-LED epitaxial wafer prepared using the second layering method described above includes a substrate 1, an n-type doped nitride layer 23, an n-type nitride blocking layer 24, an n-type nitride buffer layer 25, a composite nanostructure layer 20, an n-type nitride capping layer 26, a nitride light-emitting layer 3, and a p-type nitride layer (as the second semiconductor material layer 4) in a specified direction. The composite nanostructure layer 20 includes: spatially spaced composite nanostructures with different occupancy. Specifically, the composite nanostructure includes Si nanopillars 202 at the bottom and Al metal microstructures 203 at the top. The difference between this layering structure and the first method is that the AlN islands 201 are omitted, and instead, a gradient decreasing Si doping concentration trend is formed in the n-type nitride buffer layer 25.

[0050] The foregoing description introduces the technical concept provided by this invention from a structural perspective. To obtain the aforementioned nitride epitaxial structure, this invention also proposes a method for preparing the nitride epitaxial structure, which includes the following main steps:

[0051] A first semiconductor material layer 2 is epitaxially grown on the surface of substrate 1;

[0052] A nitride light-emitting layer 3 is epitaxially grown on the surface of the first semiconductor material layer 2;

[0053] A second semiconductor material layer 4 is epitaxially grown on the surface of the nitride light-emitting layer 3.

[0054] The process of growing the first semiconductor material layer 2 in the first major step includes forming a composite nanostructure layer 20:

[0055] Step ad is repeated multiple times to form Al metal microstructures 203 and Si nanopillars 202, and step e is performed to nitrid the surfaces of the Al metal microstructures 203 and Si nanopillars 202:

[0056] a. Perform Al thermal surface treatment at a temperature of 500-1000℃;

[0057] b. Perform the first annealing treatment at a temperature of 500-1000℃;

[0058] c. Perform Si hot surface treatment at a temperature of 500-1000℃;

[0059] d. Perform a second annealing treatment at a temperature of 500-1000℃;

[0060] e. Perform N-type thermal surface treatment at a temperature of 900-1100℃.

[0061] Corresponding to the first type of stacking method of the first semiconductor material layer 2 shown above, in some embodiments, the composite nanostructure layer 20 is disposed adjacent to the substrate 1, and the formation process of the composite nanostructure layer 20 further includes:

[0062] Before step ad, step fh is executed multiple times, followed by step i, to form AlN islands 201:

[0063] f. Perform N-type heat treatment on the surface for 5-30 seconds at a temperature of 500-1000℃;

[0064] g. Perform Al hot surface treatment at a temperature of 500-1000℃ for 10-60 seconds;

[0065] h. Perform a third annealing treatment at a temperature of 500-1000℃ for 20-50 seconds;

[0066] i. Perform N-type heat treatment on the surface at a temperature of 500-1000℃ for 20-90 seconds;

[0067] The Si nanopillars 202 are formed on the top of the AlN islands 201. The execution order of steps a and b is to first cycle steps ab for 10-120 rounds, and then cycle steps cd for 100-1000 rounds. The Al hot surface treatment time in step a is 5-20s, the first annealing time in step b is 10-30s, the Si hot surface treatment time in step c is 10-100s, and the second annealing time in step d is 10-60s.

[0068] In the above steps, the thermal surface treatment of a certain element refers to the process of introducing a precursor (or source) of the corresponding element into a reaction chamber containing the structure to be treated under heating conditions to carry out a surface thermal reaction. Injection of N thermal surface treatment and Al thermal surface treatment are widely used in semiconductor technology. The specific parameters and conditions can be referred to in various existing methods for thermal surface treatment of the corresponding element on substrate 1 or nitride surface.

[0069] In this first layering method, a composite nanostructure is introduced on the growth substrate in the process of composite nanostructure layer 20. On the one hand, by introducing Si nanopillars on the growth substrate, the incorporation of In atoms on the growth surface of nitride quantum well layer 31 under tensile stress becomes relatively easy. Thus, tensile stress can be introduced in the epitaxial layer by utilizing the thermal adaptation and lattice mismatch between Si and nitride materials. The thermal tensile stress of Si nanopillars and the tensile stress of lattice mismatch greatly improve the incorporation of In in nitride quantum well layer 31. On the other hand, the stress can be effectively released through the direct mutual relaxation of the composite nanostructure, reducing the stress distribution of the epitaxial layer at the substrate 1 interface. At the same time, the composite nanostructure strengthens the lateral epitaxy of the undoped nitride epitaxial layer and improves the crystal quality of the epitaxial layer. This reduces nonradiative recombination in nitride light-emitting layer 3, reduces leakage channels, and thus improves the brightness, leakage current, and ESD antistatic discharge performance of the epitaxial wafer.

[0070] As a typical example, the preparation method for forming the first type of stacking specifically includes the following process steps:

[0071] S1: Provide substrate 1 for use as support for epitaxial layer growth;

[0072] S2: Growing a composite nanostructure layer 20 on substrate 1, including the following steps:

[0073] S21: Growth of substrate microstructure, including 2-6 repetitions of steps S211-S213 followed by step S214:

[0074] S211: Perform N-type heat treatment on the surface for 5-30 seconds at a temperature of 500-1000℃;

[0075] In this step, N-thermal surface treatment is beneficial for the formation of nucleation centers on the surface of substrate 1, increasing the adhesion between the atoms on the surface of substrate 1 and substrate 1. Conventional processes also involve N-surface thermal treatment of substrate 1 (called N-treatment); however, it is different from the one-time N-thermal surface treatment in conventional processes. In conventional processes, N-thermal surface treatment has a crucial impact on the nucleation layer. Insufficient N-surface thermal treatment will lead to uneven distribution of nucleation centers on the surface of substrate 1, making it difficult to obtain high-quality nitride materials. Therefore, conventional N-thermal treatment requires sufficient processing time.

[0076] Unlike traditional N-thermal surface treatment, this process incorporates periodic N-thermal surface treatment. A single N-thermal surface treatment of substrate 1 during the cycle is insufficient. During the cycle, the N-thermal treatment on the surface of substrate 1 gradually accumulates, resulting in different potential energy on the surface of substrate 1 in each cycle. In the initial stage of the cycle, low-density nucleation centers can be formed on the surface of substrate 1 after treatment. Atoms will first form low-density nucleation centers in specific regions. As the cycle progresses, the N-thermal treatment on the surface of substrate 1 is strengthened to varying degrees during the cycle. Atoms on the surface of substrate 1 will form new nucleation centers in regions outside the nucleation center regions that have been formed in the previous cycle. Thus, the nucleation center positions on the surface of substrate 1 are different during the cycle, resulting in a periodic interval distribution.

[0077] During the cycle, the Al atom capping layer formed by the N-thermal surface treatment in step S211 forms an AlN nucleation pattern structure with Al atoms as nucleation centers. During the periodic cycle, after the N-thermal surface treatment in step S211, new AlN islands 201 are formed in the region between the multiple AlN islands 201 formed in the previous cycle, resulting in a distribution of multiple AlN islands 201 spaced apart on the surface of substrate 1. Furthermore, during the cycle, the Al atom capping layer covers the AlN islands 201 formed in the previous cycle. Finally, the Al atom capping layer, under the action of N heat treatment, increases the size of the pattern structure of the previous cycle, and finally forms multiple AlN islands 201 of different sizes spaced apart on the surface of substrate 1. Because there is a large lattice mismatch between Si and substrate 1, Si nanopillars are introduced at different positions in the thickness direction using the AlN islands 201 of different heights to avoid defects caused by large stress and improve the crystal quality of the epitaxial wafer. In the thickness direction, the stress relaxation effect between the composite nanopillar structures formed by AlN islands 201 of different heights can be used to reduce stress.

[0078] S212: Perform Al hot surface treatment at a temperature of 500-1000℃ for 10-60s to form an Al coating layer.

[0079] S213: Anneal at 500-1000℃ for 20-50 seconds;

[0080] Based on step S211, the annealing process in step S213 forms nucleation centers with Al atom distribution on the surface of substrate 1. After the N-thermal surface treatment in step S211, multiple AlN islands 201 are formed. During the periodic cycle, after the N-thermal surface treatment in step S211, multiple AlN islands 201 are formed in the region between the multiple AlN islands 201 formed in the previous cycle. Finally, multiple AlN islands 201 of different sizes are formed and spaced apart on the surface of substrate 1.

[0081] S214; subjected to N-heat surface treatment at 500-1000℃ for 20-90s;

[0082] After completing step S21, proceed to step S22: grow the nanopillar structure, which includes periodically repeating alternating steps S221 and S222 a total of 10-120 times.

[0083] S221: Perform Al hot surface treatment at a temperature of 500-1000℃ for 5-20 seconds;

[0084] S222: Annealing at 500-1000℃ for 10-30 seconds;

[0085] During the periodic cycle of steps S221 and S222, a non-equilibrium deposition state exists where deposition and desorption coexist. Step S221 causes Al atoms to be deposited on the surface of substrate 1 and AlN island 201. After annealing in step S222, Al atoms migrate and reach an equilibrium distribution. Because AlN island 201 has a relatively stable low-energy state in the direction parallel to the surface of substrate 1, Al atoms on the sidewalls of AlN island 201 are desorbed and removed during annealing due to their relatively high energy state. In this way, an Al metal microstructure 203 can be formed on the top of AlN island 201.

[0086] S23: Growth of the top microstructure, including a periodically repeated alternating step of 100-1000 times:

[0087] S231: Perform Si hot surface treatment at a temperature of 500-1000℃ for 10-100s;

[0088] S232: Interrupt the Si hot surface treatment for 10-60 seconds and perform annealing;

[0089] S24: Perform N-heat surface treatment at a temperature of 900-1100℃ for 20-60 seconds;

[0090] The Al metal microstructure 203 is formed by the periodic alternation of S231 and S232, with the top and bottom of the Si nanopillar structure having a height of 20-100 nm. The nanostructure material atoms to be prepared are dissolved in the micro-nano metal liquid structure and then precipitated and axially grown to form the nanostructure. That is, by introducing the Si atoms required for the Si nanopillars into the surface of the metal microspheres, the Si atoms are dissolved and precipitated in the metal microspheres and continue to grow to form Si nanopillars. The Al metal microstructure 203 is formed by the N-thermal surface treatment in step S24 to form a microstructure with an AlN layer on the surface, and the Si nanopillar structure has a SiN layer on its surface.

[0091] Furthermore, after the Si thermal surface treatment in step S23, Si atoms are also formed on the sidewalls of AlN islands 201 and on the surface region of substrate 1 between adjacent AlN islands 201. In the N thermal surface treatment in step S24, a SiN layer is formed. Since it is difficult for SiN dielectric film to nucleate on the surface, the AlN microstructure is the nucleation center of the nitride buffer layer 25, and AlN nucleation centers are spatially distributed at high and low levels.

[0092] As a more preferred approach, by controlling the growth time and cycle number, Si deposition will not occur in the exposed area when the AlN pattern completely covers the surface of substrate 1, and SiN dielectric film will not form, thus avoiding affecting the quantity of the composite nanostructure. Specifically, as follows... Figure 2 As shown.

[0093] S3: A nitrided nucleation layer with a thickness of 10-100 nm is grown at a temperature of 500-900℃;

[0094] S4: A nitride roughening layer 21 with a thickness of 100-500 nm is grown at a temperature of 1000-1100℃;

[0095] S5: An undoped nitride layer 22 with a thickness of 1000-5000 nm is grown at a temperature of 1050-1250℃;

[0096] S6: Growing n-type nitride layers with a thickness of 1000-5000 nm at temperatures of 1050-1250℃, with a doping concentration of 1×10⁻⁶. 18 -5×10 19 cm -3 ;

[0097] S7: The nitride quantum well layer 31 and nitride quantum barrier layer 32, grown in cyclical alternation steps S71-S72 at temperatures of 650-950℃, serve as the light-emitting layer, including:

[0098] S71: A nitride quantum well layer 31 with a thickness of 0.5-5 nm is grown at a temperature of 650-850℃. Most of the stress in the light-emitting layer comes from the bottom layer. For example, using a Si substrate 1 can more easily realize long-wavelength epitaxial wafers compared to a sapphire substrate 1. Changes in the stress of the bottom layer have a great impact on the light-emitting layer. Therefore, even if the composite nanostructure layer 20 is formed in a location relatively far from the light-emitting layer, it can still play a role in stress regulation of the light-emitting layer.

[0099] S72: Nitride quantum barrier layer 32 with a thickness of 6-25 nm is grown at a temperature of 700-950℃.

[0100] S8: Grow a p-type nitride layer with a thickness of 50-300 nm at a temperature of 850-1050℃, with a doping concentration of 1×10⁻⁶. 19 -5×10 20 cm -3 .

[0101] In steps S3-S8 above, each film layer grown is a common film layer in the field. For specific process parameters, please refer to various existing technical solutions. They will not be described in detail in this invention.

[0102] Alternatively, in some embodiments corresponding to the second type of stacking of the first semiconductor material layer 2 shown above, in some embodiments, along the specified direction, the first semiconductor material layer 2 sequentially includes: a doped nitride layer 23, a nitride barrier layer 24, a nitride buffer layer 25, the composite nanostructure layer 20, and a nitride capping layer 26. The execution order of step ad is to cycle step ad 10-50 times. The time for Al thermal surface treatment in step a is 20-120s, the time for the first annealing treatment in step b is 5-30s, the time for Si thermal surface treatment in step c is 5-40s, and the time for the second annealing treatment in step d is 10-45s.

[0103] For this second stacking method, on the one hand, the deformation relaxation stress between composite nanostructures with different occupancy sites can reduce the growth compressive stress of the nitride luminescent layer 3, improve the crystal quality of the nitride luminescent layer 3, and reduce non-radiative recombination. On the other hand, by introducing Si nanopillars 202, the incorporation of In atoms on the growth surface of the nitride quantum well layer 31 becomes relatively easier under tensile stress conditions. Thus, the thermal compatibility and lattice mismatch between Si and nitride materials can be used to introduce tensile stress in the epitaxial layer, greatly improving the nitride quantum well layer's performance. In is incorporated into the well layer 31; in addition, a nanostructure distribution is formed on the surface of the nitride light-emitting layer 3 using Al atom nucleation and aggregation centers. The quantum dot confinement effect can be used to reduce QCSE (Stark effect), improve the incorporation of In and enhance the recombination efficiency of electrons and holes. Furthermore, the reflection of light from the light-emitting layer to the substrate 1 by the Al atom nucleation and aggregation centers can be reflected to enhance the front light emission. This can also reduce non-radiative recombination in the nitride light-emitting layer 3, reduce leakage channels, and thus improve the brightness, leakage current and ESD antistatic discharge performance of the epitaxial wafer.

[0104] As a typical example, the preparation method for forming the second type of stacking includes the following steps:

[0105] S1: Provide substrate 1 for use as support for epitaxial layer growth;

[0106] S2: An n-type nitride layer with a thickness of 1-5 μm, i.e., doped nitride layer 23, is grown at a temperature of 1050-1250℃ with a Si doping concentration of 1×10⁻⁶. 1s -1×10 19 cm -3 In this step, the n-type nitride layer serves as the carrier injection layer of the nitride light-emitting layer 3. Because the doping concentration of the n-type nitride layer affects the voltage, brightness, leakage current, and electrostatic discharge (ESD) performance of the epitaxial wafer, when the doping concentration fluctuates, the voltage, brightness, leakage current, and ESD performance of the epitaxial wafer will fluctuate. Therefore, in order to maintain the consistency of the performance of the epitaxial wafer product for specific product applications, it is necessary to keep its doping concentration stable.

[0107] S3: An n-type nitride barrier layer 24 with a thickness of 10-50 nm is grown at a temperature of 1065-1265℃, with a Si doping concentration of 1×10⁻⁶. 18 -1×10 19 cm -3 The n-type nitride barrier layer 24 grows a relatively low-doped thin layer under relatively high temperature conditions. On the one hand, it prevents Si atoms from diffusing across the nitride buffer layer 25 to the n-type nitride layer and affecting its doping concentration. On the other hand, it prevents Si interstitial impurity atoms formed in the n-type nitride layer due to high doping concentration from diffusing into the n-type nitride buffer layer and affecting the distribution of nucleation aggregation centers in step S5.

[0108] S4: An n-type nitride buffer layer 25 with a thickness of 20-100 nm is grown at a temperature of 950-1050℃, with a Si doping concentration of (5×10⁻⁶). 17 -1×10 1s cm -3 Linearly decreasing to (0-1×10) 17 cm -3 The n-type nitride buffer layer 25 utilizes the Si doping concentration to form a decreasing doping gradient in the thickness direction, which is crucial for forming composite nanostructures with size differences.

[0109] S5: Growth of nanostructured layers, including step S51 forming nucleation and aggregation centers and step S52 forming nanopillar structures:

[0110] S51: Formation of nucleation and aggregation centers, including the periodic repetition of the following steps 10-50 times:

[0111] S511: Perform Al hot surface treatment at a temperature of 500-1000℃ for 20-120s to form an Al metal deposition layer.

[0112] S512: Annealing is performed at 500-1000℃ for 5-30s. Annealing causes Al atoms to migrate along the planar direction and form Al atom nucleation and aggregation centers. These nucleation and aggregation centers serve as a precursor for catalyzing the formation of Si nanopillars and transforming them into Al metal microstructure 203.

[0113] S513: Perform Si hot surface treatment at a temperature of 500-1000℃ for 5-40s. This step forms a Si deposition layer.

[0114] S514: Annealing is performed at a temperature of 500-1000℃ for 10-45s. During the annealing process, Si atoms covering the Al nucleation centers diffuse into the interior of the Al nucleation centers, and Si atoms covering the adjacent Al nucleation aggregation centers diffuse into the interior of the n-type nitride buffer layer 25. This changes the doping gradient of the n-type nitride buffer layer 25 in the thickness direction. That is, the potential energy of the surface of the n-type nitride buffer layer 25 is different during the periodic cycle of step S5. Thus, when Al is hot-treated after Si hot-treatment, some Al atoms continue to agglomerate on the original nucleation centers, while other Al atoms can form new small-sized nucleation aggregation centers in new positions.

[0115] During the periodic cycle, as the Al capping layer is deposited, the vertical and horizontal occupancy of Al nucleation and aggregation centers continuously increases, forming large Al atom nucleation and aggregation centers. That is, compared with the newly formed Al nucleation and aggregation centers in the previous cycle, the occupancy is smaller, forming small Al nucleation and aggregation centers. Through step S5, Al atom nucleation and aggregation centers with a height of 20-500nm and a width of 5-100nm are formed. The occupancy ratio of adjacent Al atom nucleation and aggregation centers (volume ratio: 1.2 < ratio < 2) is used to reduce the stress of the light-emitting layer by utilizing the multi-composite structure interface relaxation in the thickness direction caused by the height difference. If the height ratio difference is too small, the stress relaxation effect of the height difference in the thickness direction cannot be reflected. If the difference is too large, it will cause the distance between the surface of the light-emitting layer and the p-type layer to be too large, affecting the uniformity of carrier (hole) injection.

[0116] S52: Formation of nanopillar structures, including a periodically repeated alternating step of 10-100 times:

[0117] S521: Perform Si hot surface treatment at a temperature of 500-1000℃ for 10-100s;

[0118] S522: Interrupt the Si hot surface treatment, which is equivalent to performing an annealing process for 10-60 seconds;

[0119] The above-mentioned periodic alternating steps S231 and S232 form an Al metal microstructure 203 with a height of 2-10 nm for the top and bottom of the Si nanopillar structure. The specific process is as follows: the atoms of the nanostructure material to be prepared are dissolved in the micro-nano metal liquid structure and then precipitated and axially grown to form a nanopillar structure. That is, by introducing Si atoms required for Si nanopillars on the surface of metal microspheres, the Si atoms are dissolved and precipitated in the metal microspheres and continue to grow to form Si nanopillars 202.

[0120] In the above embodiments, the present invention utilizes the characteristic that silicon atoms dissolve and precipitate in micro / nano liquid metal structures and grow axially to form nanostructures, thereby growing silicon nanopillars below the metal island-shaped protrusions. The specific principle is as follows: The present invention introduces Si atoms on the surface of the metal island-shaped protrusions. The Si atoms dissolve under heat treatment, and under the continuous treatment of Si atoms, Si forms a non-equilibrium diffusion growth on the surface of the metal island-shaped protrusions. On the one hand, with the heat treatment of Si, a high concentration of Si atoms accumulates on the surface of the liquid metal structure, creating a large concentration difference between the surface and the interior of the liquid metal structure. That is, the surface has a high diffusion potential energy, causing Si atoms to continuously diffuse and precipitate crystals from the direction of high diffusion energy to low diffusion energy in the direction of the concentration difference. On the other hand, the precipitation of Si atoms from other positions on the surface requires a higher saturation, while the precipitation of solid Si nanopillars at the interface of the bottom of the liquid metal structure has the lowest diffusion energy, causing Si atoms to continuously diffuse in the direction of the concentration difference, precipitating from the bottom of the liquid metal, and finally forming silicon nanopillars at the bottom liquid-solid interface, rather than forming silicon nanopillars in other directions.

[0121] S6: An n-type nitride capping layer 26 with a thickness of 10-50 nm is grown at a temperature of 800-1000℃, with Si doping concentration ranging from 0-1×10⁻⁶. 17 cm -3 Linearly increasing to (2×10) 17 -8×10 17 cm -3 The purpose of this configuration is that the n-type nitride capping layer 26 utilizes the increasing doping gradient of Si doping concentration in the thickness direction. Firstly, it forms a diffusion gradient for Si atoms distributed on the surface of the nanopillar structure formed in step S52, reducing the absorption of light by free Si atoms as impurity atoms in the nitride emitting layer 3. Secondly, the increasing gradient trend increases the diffusion barrier of Si atoms in the thickness direction, preventing Si atoms from diffusing into the nitride emitting layer 3 to form non-radiative recombination and leakage centers, thus improving the brightness and leakage performance of the epitaxial wafer. Thirdly, the n-type nitride capping layer 26 covers the Al atom nucleation and aggregation centers to form a metal-covered light-reflecting structure, increasing the forward reflection of the optical fiber from the nitride emitting layer 3 to the substrate 1, improving the forward light emission of the epitaxial wafer, and thus increasing the brightness of the epitaxial wafer.

[0122] S7: The nitride quantum well layer 31 and nitride quantum barrier layer 32, grown in cyclical alternation steps S71-S72 at temperatures of 650-950℃, serve as the light-emitting layer, including:

[0123] S71: A nitride quantum well layer 31 with a thickness of 0.5-5 nm is grown at a temperature of 650-850℃.

[0124] S72: Nitride quantum barrier layer 32 with a thickness of 6-25 nm is grown at temperatures of 700-950℃.

[0125] S8: A p-type nitride layer with a thickness of 100-300 nm is grown at a temperature of 850-1050℃, with a typical doping concentration of 1×10⁻⁶. 19 -5×10 20 cm -3 .

[0126] It is clear that the above steps S2 / S3 / S7 / S8 correspond to the existing growth processes of various corresponding films, while steps S4 and S6 require special adjustment of the Si element doping gradient in order to achieve the corresponding functions in conjunction with the composite nanostructure layer 20.

[0127] Furthermore, it can be observed that the specific structural composition and processing conditions differ when the composite nanostructure layer 20 is placed in different positions. When it is placed on the surface of the substrate 1, multiple AlN islands 201 of different sizes need to be formed on the surface of the substrate 1 as a base. Si nanopillars 202 and Al metal microstructures 203 are formed on the top of the AlN islands 201 to achieve extended growth. This method utilizes AlN islands 201 of different sizes and activities to form a composite nanostructure with varying heights and diameters, which essentially shields the stress mismatch transmitted from the substrate 1. When the composite nanostructure layer is placed on the substrate 1, the specific structural composition and processing conditions differ. When 20 is located near the nitride light-emitting layer 3, a gradually decreasing Si doping concentration needs to be formed in the underlying film layer, namely the nitride buffer layer 25, to form a Si diffusion barrier. In this way, during the Si thermal surface treatment process, Si atoms tend to aggregate unevenly to form composite nanostructures with size differences. In contrast, undoped or uniformly doped nucleation layers tend to diffuse uniformly. During the cycle process, the surface potential energy difference of Si thermal treatment is not obvious, making it difficult to form highly differentiated composite nanostructures. Furthermore, an increasing Si doping concentration needs to be formed in the nitride capping layer 26.

[0128] As a typical application of the above-mentioned technical solutions, a third aspect of the present invention also provides a Micro-LED device, which includes a plurality of light-emitting units, wherein the light-emitting units include red light-emitting units, and the red light-emitting units have a nitride epitaxial structure provided or prepared in any of the above embodiments.

[0129] The technical solution of the present invention will be further described in detail below through several embodiments and in conjunction with the accompanying drawings. However, the selected embodiments are only for illustrating the present invention and do not limit the scope of the present invention.

[0130] Example 1

[0131] This embodiment illustrates a fabrication process for a red-light Micro-LED epitaxial wafer, as detailed below:

[0132] S1: Provides a 4-inch sapphire substrate for use as a support for epitaxial layer growth;

[0133] S2: Growing a composite nanostructure layer on the substrate, including the following steps:

[0134] S21: Grow AlN island structures, including performing step S214 once after four periodically repeating alternating steps S211-S213.

[0135] S211: Under conditions of 750℃ and 150 torr, N-heat surface treatment is performed by introducing NH3 at a flow rate of 75 slm for 17 s.

[0136] S212: Under conditions of 750℃ and 400 torr, an Al thermal surface treatment is performed for 35s by introducing a TMAl source with a flow rate of 450 sccm. This step forms an Al coating layer.

[0137] S213: Stop the TMA source and perform annealing for 35 seconds at a temperature of 750℃ and a pressure of 400 torr.

[0138] S214; Under conditions of temperature 750℃ and pressure 400 torr, N-heat surface treatment was performed by introducing 55slm of NH3 for 55s;

[0139] S22: Growth of nanopillar structures, including the periodic repetition of alternating steps S221 and S222 a total of 65 times:

[0140] S221: Under the conditions of 750℃ and 500 torr, Al thermal surface treatment was performed for 13s by introducing a TMAl source with a flow rate of 650 sccm.

[0141] S222: Annealing at 750℃ and 500 torr for 20 seconds;

[0142] S23: Growth of the top microstructure, including 550 repetitive alternating steps:

[0143] S231: At a temperature of 750℃ and 600 torr, a SiH4 source of 550 sccm is introduced to perform Si thermal surface treatment for 55 s.

[0144] S232: Interrupt the Si hot surface treatment for 35 seconds and perform annealing;

[0145] S24: Under conditions of 1000℃ and 400 torr, N-heat surface treatment is performed by introducing 105 slm of NH3 for 40 s.

[0146] S3: Under the conditions of temperature 700℃ and pressure 500 torr, a GaN nucleation layer with a thickness of 55nm is grown by introducing a TMG source with a flow rate of 55sccm and an NH3 flow rate of 55slm.

[0147] S4: Under conditions of 1050℃ and 200 torr, a 300nm thick GaN roughening layer is grown by introducing a TMG source with a flow rate of 165 sccm and NH3 with a flow rate of 50 slm.

[0148] S5: Under the conditions of temperature 1150℃ and pressure 200 torr, a TMG source with a flow rate of 245 sccm and NH3 with a flow rate of 55 slm are introduced to grow an undoped GaN layer with a thickness of 3000 nm.

[0149] S6: Under conditions of 1150℃ and 200 torr, a 3000nm thick n-type GaN nitride layer is grown by introducing a TMG source with a flow rate of 380 sccm, NH3 with a flow rate of 55 slm, and SiH4 with a flow rate of 110 sccm. The Si doping concentration is 1×10⁻⁶. 19 cm -3 ;

[0150] S7: The InGaN quantum well layer and GaN quantum barrier layer grown in the cyclical alternation steps S71-S72 (total cycle count 9 times) serve as the light-emitting layer, including:

[0151] S71: An InGaN quantum well layer with a thickness of 2.5 nm is grown by introducing a TEG source with a flow rate of 195 sccm and NH3 with a flow rate of 78 slm under the conditions of temperature 750℃ and pressure 400 torr.

[0152] S72: A GaN quantum barrier layer with a thickness of 15 nm is grown by introducing a TEG source with a flow rate of 245 sccm and NH3 with a flow rate of 78 slm under the conditions of temperature 825℃ and pressure 400 torr.

[0153] S8: Under conditions of 950℃ and 400 torr, a 170nm thick p-type nitride layer was grown by introducing a TEG source with a flow rate of 360 sccm, NH3 with a flow rate of 55 slm, and Cp2Mg with a flow rate of 720 sccm. The Mg doping concentration was 1×10⁻⁶. 20 cm -3 .

[0154] Comparative Example 1-1

[0155] This comparative example is largely the same as Example 1, with the main difference being:

[0156] Step S2 is omitted, and the growth of the nitride nucleation layer in step S3 is performed directly on the substrate.

[0157] Comparative Examples 1-2

[0158] This comparative example is largely the same as Example 1, with the main difference being:

[0159] Steps S22-S24 are omitted, and the nitride nucleation layer of step S3 is grown directly on the surface of the AlN island structure.

[0160] Comparative Examples 1-3

[0161] This comparative example is largely the same as Example 1, with the main difference being:

[0162] Step S24 was omitted, and the Al metal microstructure and Si columnar structure were not nitrided.

[0163] Comparative Examples 1-4

[0164] This comparative example is largely the same as Example 1, with the main difference being:

[0165] Step S21 is changed to: simultaneously and continuously introducing Al and N sources, keeping the temperature and time consistent with Example 1, to form a continuous and flat AlN film layer.

[0166] Comparative Examples 1-5

[0167] This comparative example is largely the same as Example 1, with the main difference being:

[0168] In step S21, a conventional Al pre-deposition process is used to form AlN islands of uniform size.

[0169] S211: Under conditions of 750℃ and 400 torr, a TMAl source with a flow rate of 450 sccm is introduced to perform Al hot surface treatment for 105s; then the TMA source is stopped and annealing is performed for 50s.

[0170] S212; Under conditions of 750℃ and 400 torr, N-heat surface treatment was performed by introducing 65slm of NH3 for 75s.

[0171] Example 2

[0172] This embodiment is largely the same as Embodiment 1, with the main difference being in step S2:

[0173] By controlling the flow rate and time process parameters in each step, the AlN islands almost completely occupy the surface of the substrate, with virtually no exposed areas. The conditions for step S2 are as follows:

[0174] S21: Grow AlN island structures, including performing step S214 once after four periodically repeating alternating steps S211-S213.

[0175] S211: Under the conditions of temperature 650℃ and pressure 75torr, N hot surface treatment is performed by introducing NH3 at a flow rate of 40slm for 17s.

[0176] S212: Under the conditions of temperature 650℃ and pressure 600Torr, Al thermal surface treatment was performed for 45s by introducing a TMAl source with a flow rate of 650sccm.

[0177] S213: Stop the TMA source and perform annealing for 25 seconds at a temperature of 750℃ and a pressure of 400 torr.

[0178] S214; Under conditions of 750℃ and 400 torr, N-heat surface treatment was performed by introducing 75slm of NH3 for 55s.

[0179] Example 3

[0180] This embodiment illustrates the fabrication process of the second type of red Micro-LED epitaxial wafer, as shown below:

[0181] S1: Provides a 4-inch sapphire substrate for use as a support for epitaxial layer growth;

[0182] S2: Under conditions of 1150℃ and 200 torr, a 3μm thick n-type GaN layer is grown by introducing a TMG source with a flow rate of 480 sccm, NH3 with a flow rate of 55 slm, and SiH4 with a flow rate of 220 sccm. The Si doping concentration is 5 × 10⁻⁶. 18 cm -3 ;

[0183] S3: Under conditions of 1165℃ and 200 torr, a 30nm thick n-type GaN barrier layer is grown by introducing a TMG source with a flow rate of 120sccm, NH3 with a flow rate of 50slm, and SiH4 with a flow rate of 80sccm. The Si doping concentration is 1×10⁻⁶. 19 cm -3 ;

[0184] S4: Under conditions of 1000℃ and 200 torr, a 60nm thick n-type GaN layer is grown by introducing a TMG source with a flow rate of 78 sccm, NH3 with a flow rate of 55 slm, and SiH4 with an initial flow rate of 45 sccm. The Si source flow rate is gradually reduced, and the Si doping concentration is increased from 8 × 10⁻⁶. 17 cm -3 Decrease linearly to 5×10 16 cm -3 ;

[0185] S5: Growth of nanostructured layers, including step S51 forming nucleation and aggregation centers and step S52 forming nanopillar structures:

[0186] S51: Formation of nucleation and aggregation centers, including the periodic repetition of the following steps 30 times:

[0187] S511: Under the conditions of temperature 750℃ and pressure 500 torr, TMAl with a flow rate of 500 sccm is introduced to perform Al hot surface treatment for 60s to form an Al metal deposition layer.

[0188] S512: Annealing at 750℃ and 500 torr for 60s;

[0189] S513: Under the conditions of temperature 750℃ and pressure 500 torr, SiH4 with a flow rate of 450 sccm is introduced to perform Si hot surface treatment for 23s;

[0190] S514: Annealing at 750℃ and 500 torr for 30 seconds;

[0191] S52: Formation of nanopillar structures, involving 55 repetitive alternating steps:

[0192] S521: Under the conditions of temperature 750℃ and pressure 500 torr, SiH4 with a flow rate of 500 sccm is introduced to perform Si hot surface treatment for 55s;

[0193] S522: Interrupt Si hot surface treatment for 35 seconds;

[0194] S6: Under conditions of 900℃ and 200 torr, a 30nm thick n-type GaN capping layer is grown by introducing a TEG source with a flow rate of 105 sccm, an NH3 source with a flow rate of 50 slm, and a SiH4 source with an initial flow rate of 30 sccm. The Si source flux is gradually increased, and the Si doping concentration is increased from 5 × 10⁻⁶ to 10⁻⁶. 16 cm -3 linearly increasing to 5×10 17 cm -3 ;

[0195] S7: The nitride quantum well layer and nitride quantum barrier layer grown in the cyclical alternation steps S71-S72 (total cycle count 9 times) serve as the light-emitting layer, including:

[0196] S71: An InGaN quantum well layer with a thickness of 2.5 nm is grown by introducing a TEG source with a flow rate of 195 sccm and NH3 with a flow rate of 78 slm under the conditions of temperature 750℃ and pressure 400 torr.

[0197] S72: A GaN quantum barrier layer with a thickness of 15 nm is grown by introducing a TEG source with a flow rate of 245 sccm and NH3 with a flow rate of 78 slm under the conditions of temperature 825℃ and pressure 400 torr.

[0198] S8: A 170 nm thick p-type GaN layer was grown under conditions of 950 °C and 400 torr, with a TEG source at a flow rate of 360 sccm, NH3 at a flow rate of 55 slm, and Cp2Mg at a flow rate of 720 sccm. The Mg doping concentration was 1 × 10⁻⁶. 20 cm -3 .

[0199] Comparative Example 3-1

[0200] This comparative example is largely the same as Example 3, the main difference being that the Si doping concentration remains constant at 4.25 × 10⁻⁶. 17 cm -3 .

[0201] Comparative Example 3-2

[0202] This comparative example is largely the same as Example 3, with the main difference being:

[0203] S4: Under conditions of 1000℃ and 200 torr, a 60nm thick n-type GaN layer is grown by introducing a TMG source with a flow rate of 78 sccm, NH3 with a flow rate of 55 slm, and SiH4 with an initial flow rate of 18 sccm. The Si source flow rate is gradually reduced, and the Si doping concentration is increased from 3 × 10⁻⁶. 17 cm -3 Decrease linearly to 5×10 16 cm -3 .

[0204] In this comparative example, the initial doping concentration of Si is relatively low.

[0205] Comparative Example 3-3

[0206] This comparative example is largely the same as Example 3, with the main difference being:

[0207] S4: Under conditions of 1000℃ and 200 torr, a 60nm thick n-type GaN layer is grown by introducing a TMG source with a flow rate of 78 sccm, NH3 with a flow rate of 55 slm, and SiH4 with an initial flow rate of 390 sccm. The Si source flow rate is gradually reduced, and the Si doping concentration is increased from 5 × 10⁻⁶. 18 cm -3 Decrease linearly to 5×10 16 cm -3 .

[0208] In this comparative example, the initial doping concentration of Si is relatively high.

[0209] Comparative Examples 3-4

[0210] This comparative example is largely the same as Example 3, the main difference being that sub-steps S513 and S514 are not performed in step S51:

[0211] S51: Formation of nucleation and aggregation centers, including the periodic repetition of the following steps 30 times:

[0212] S511: Under the conditions of temperature 750℃ and pressure 500 torr, TMAl with a flow rate of 500 sccm is introduced to perform Al hot surface treatment for 60s to form an Al metal deposition layer.

[0213] S512: Annealing at 750℃ and 500 torr for 60s.

[0214] In this comparative example, no Si thermal surface treatment or corresponding annealing treatment was performed during the cycle.

[0215] Performance Characterization

[0216] The red nitride epitaxial wafers obtained through the above embodiments and comparative examples were used to test the wavelength uniformity (std / nm) and full width at half maximum (HW / nm) of the epitaxial wafers prepared by the above embodiments and comparative examples using photoluminescence (PL). Then, Micro-LEDs were fabricated using the same preparation process, and they were tested using an LED optoelectronic performance tester, including luminous intensity (Lop / mW) under a 2mA current injection condition, ESD yield and leakage current yield under reverse voltage of 2000V and 7V, and peak luminous efficiency (PQE / %) in the current range of 1-5mA. The results are shown in the table below.

[0217] HW / nm Lop / mW / 1mA HW / nm ESD / % IR / % EQE / % Example 1 0.72 14.2 49.2 99.8 100 12.1 Comparative Example 1-1 1.65 12.1 55.3 97.5 96.7 10.3 Comparative Examples 1-2 2.68 10.9 61.2 96.8 96.8 7.4 Comparative Examples 1-3 1.64 11.6 58.2 95.2 95.7 8.6 Comparative Examples 1-4 2.36 10.1 60.8 94.7 94.2 6.5 Comparative Examples 1-5 1.92 12.4 57.6 95.7 96.4 9.3 Example 2 0.61 15.3 50.1 100 99.1 12.9 Example 3 0.87 14.6 51.5 99.1 98.8 11.8 Comparative Example 3-1 1.81 12.9 55.4 97.1 98.8 9.7 Comparative Example 3-2 1.33 11.3 57.3 95.1 96.8 9.5 Comparative Example 3-3 1.21 10.8 57.7 93.1 93.8 8.9 Comparative Examples 3-4 1.58 11.1 58.1 96.1 95.8 9.8

[0218] As can be clearly seen from the table above, Comparative Examples 1-1 to 1-5 all showed a significant performance decrease compared to Example 1. This indicates that forming a complete composite nanostructure, especially one containing a nanocolumnar structure with a high-low differential distribution, is the key to obtaining excellent device performance. Furthermore, the nitride layer on the surface of the nanocolumnar structure also significantly helps to improve device performance. In addition, Comparative Examples 3-1 to 3-4 also showed a significant performance decrease compared to Example 3, indicating that in the second embodiment, using an appropriate Si concentration gradient is an important prerequisite for forming nanocolumnar structures with a high-low differential distribution.

[0219] It should be understood that the above embodiments are merely illustrative of the technical concept and features of the present invention, and are intended to enable those skilled in the art to understand the content of the present invention and implement it accordingly. They should not be construed as limiting the scope of protection of the present invention. All equivalent changes or modifications made in accordance with the spirit and essence of the present invention should be covered within the scope of protection of the present invention.

Claims

1. A nitride epitaxial structure, comprising a substrate, a first semiconductor material layer, a nitride light-emitting layer and a second semiconductor material layer sequentially stacked along a specified direction, wherein the nitride light-emitting layer includes a nitride quantum well layer, and the In component of the nitride quantum well layer accounts for more than 30% of the total number of atoms. Its features are, The first semiconductor material layer includes multiple sublayers, and each of the multiple sublayers contains a composite nanostructure layer, wherein the composite nanostructure layer includes multiple composite nanostructures with different sizes and independently spaced distribution. Along the specified direction, the composite nanostructure comprises sequentially connected Si nanopillars and Al metal microstructures, wherein the surface of the Si nanopillars is nitrided to form a SiN layer, and the surface of the Al metal microstructure is nitrided to form an AlN layer.

2. The nitride epitaxial structure according to claim 1, characterized in that, Along the specified direction, the first semiconductor material layer sequentially includes: the composite nanostructure layer, and a nitride roughening layer, an undoped nitride layer, and a doped nitride layer. The doped nitride layer has the opposite conductivity characteristics to the second semiconductor material layer. The composite nanostructure also includes multiple AlN islands. One end of the Si nanopillar is connected to the AlN island, and the other end is connected to the Al metal microstructure.

3. The nitride epitaxial structure according to claim 2, characterized in that, The AlN island structure includes a first island and a second island, with a volume ratio of (1.2-2):1 between the first island and the second island. The second island is distributed between any two adjacent first islands.

4. The nitride epitaxial structure according to claim 2, characterized in that, The diameter of the first island is 500-3000 nm.

5. The nitride epitaxial structure according to claim 1, characterized in that, Along the specified direction, the first semiconductor material layer sequentially includes: a nitride roughening layer, an undoped nitride layer, a doped nitride layer, a nitride barrier layer, a nitride buffer layer, the composite nanostructure layer, and a nitride capping layer. The doped nitride layer has the opposite conductivity characteristics to the second semiconductor material layer. One end of the Si nanopillar is connected to the nitride buffer layer, and the other end is connected to the Al metal microstructure. Both the nitride buffer layer and the nitride capping layer are doped with Si; along the specified direction, the Si doping concentration in the nitride buffer layer increases from (5 × 10⁻⁶) to (5 × 10⁻⁶)⁻¹. 17 -1×10 18 cm -3 Linearly decreases to (0-1×10) 17 cm -3 The Si doping concentration in the nitride capping layer is (0-1×10⁻⁶) 17 cm -3 Linearly increasing to (2×10) 17 -8×10 17 cm -3 ).

6. The nitride epitaxial structure according to claim 5, characterized in that, The Al metal microstructure includes a first metal microstructure and a second metal microstructure, with a volume ratio of (1.2-2):

1. The second metal microstructure is distributed between any two adjacent first metal microstructures.

7. The nitride epitaxial structure according to claim 6, characterized in that, The diameter of the first metal microstructure is 100-500 nm; and / or the height of the Si nanopillars is 10-100 nm.

8. The method for preparing the nitride epitaxial structure according to any one of claims 1-7, characterized in that, include: A first semiconductor material layer is epitaxially grown on the substrate surface; A nitride light-emitting layer is epitaxially grown on the surface of the first semiconductor material layer; A second semiconductor material layer is epitaxially grown on the surface of the nitride light-emitting layer; The process of growing the first semiconductor material layer includes forming a composite nanostructure layer: Step ad is repeated multiple times to form Al metal microstructures and Si nanopillars, and step e is performed to nitrid the surfaces of the Al metal microstructures and Si nanopillars: a. Perform Al thermal surface treatment at a temperature of 500-1000℃; b. Perform the first annealing treatment at a temperature of 500-1000℃; c. Perform Si hot surface treatment at a temperature of 500-1000℃; d. Perform a second annealing treatment at a temperature of 500-1000℃; e. Perform N-type thermal surface treatment at a temperature of 900-1100℃.

9. The preparation method according to claim 8, characterized in that, The composite nanostructure layer is disposed adjacent to the substrate, and the formation process of the composite nanostructure layer further includes: Before step ad, step fh is executed multiple times, followed by step i, to form AlN islands: f. Perform N-type heat treatment on the surface for 5-30 seconds at a temperature of 500-1000℃; g. Perform Al hot surface treatment at a temperature of 500-1000℃ for 10-60 seconds; h. Perform a third annealing treatment at a temperature of 500-1000℃ for 20-50 seconds; i. Perform N-type heat treatment on the surface at a temperature of 500-1000℃ for 20-90 seconds; The Si nanopillars are formed on the top of the AlN islands, and the execution order of steps a and b is to first cycle steps a and b for 10-120 rounds, and then cycle steps c and d for 100-1000 rounds. The Al hot surface treatment time in step a is 5-20s, the first annealing time in step b is 10-30s, the Si hot surface treatment time in step c is 10-100s, and the second annealing time in step d is 10-60s. Alternatively, along the specified direction, the first semiconductor material layer sequentially includes: a doped nitride layer, a nitride barrier layer, a nitride buffer layer, the composite nanostructure layer, and a nitride capping layer. The execution order of steps a-d is to cycle through steps a-d for 10-50 rounds. In step a, the Al thermal surface treatment time is 20-120s, in step b, the first annealing treatment time is 5-30s, in step c, the Si thermal surface treatment time is 5-40s, and in step d, the second annealing treatment time is 10-45s.

10. A Micro-LED device, characterized in that, It includes multiple light-emitting units, wherein the light-emitting units include red light-emitting units, and the red light-emitting units have the nitride epitaxial structure as described in any one of claims 1-7.

Images