Display device

Abstract

An embodiment discloses a display device, comprising: a substrate defining a plurality of pixel regions spaced apart from each other and a plurality of transmissive regions disposed between the plurality of pixel regions; a scan line extending on the substrate along a first direction; and a plurality of data lines extending on the substrate along a second direction intersecting the first direction, wherein each of the plurality of pixel regions includes a plurality of sub-pixels, each of the plurality of sub-pixels including: a first primary sub-pixel and a first redundant sub-pixel that output a first light; a second primary sub-pixel and a second redundant sub-pixel that output a second light; and a third primary sub-pixel and a third redundant sub-pixel that output a third light, wherein the first primary sub-pixel, the first redundant sub-pixel, the second primary sub-pixel, the second redundant sub-pixel, the third primary sub-pixel, and the third redundant sub-pixel are sequentially disposed in the first direction or the second direction.

Description

[0001] Cross-references to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2024-0202671, filed on December 31, 2024, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] The implementation relates to a transparent display device using light-emitting diodes (LEDs). Background Technology

[0004] Display devices used in computer monitors, televisions (TVs), mobile phones, etc., include: self-emissive organic light-emitting display (OLED) devices; and liquid crystal display (LCD) devices that require a separate light source.

[0005] The applications of display devices are becoming increasingly diverse, including not only computer monitors and TVs, but also personal portable devices, and research is underway on display devices with larger display areas and reduced size and weight.

[0006] Furthermore, display devices, including those using light-emitting diodes (LEDs), are currently attracting attention as next-generation display devices. Because LEDs are formed from inorganic rather than organic materials, they are highly reliable, resulting in a longer lifespan than liquid crystal displays or organic light-emitting displays. In addition, LEDs not only have fast illumination speeds but also excellent luminous efficiency, superior stability due to their excellent shock resistance, and the ability to display high-brightness images. Summary of the Invention

[0007] The implementation aims to provide a display device in which subpixels of the same color are arranged at constant intervals.

[0008] The implementation aims to provide a transparent display device with high transmittance.

[0009] The implementation aims to provide a display device in which opaque pixel areas and multiple lines overlap to maximize the area of ​​the transmissive region.

[0010] The purpose of this invention is not limited to the above-described purposes, and other purposes not mentioned will be clearly understood by those skilled in the art from the following description.

[0011] A display device according to an embodiment includes: a substrate defining a plurality of pixel regions spaced apart from each other and a plurality of transmissive regions disposed between the plurality of pixel regions; a scan line extending on the substrate along a first direction; and a plurality of data lines extending on the substrate along a second direction intersecting the first direction, wherein each of the plurality of pixel regions includes a plurality of sub-pixels, each of the plurality of sub-pixels including: a first main sub-pixel and a first redundant sub-pixel that outputs a first light; a second main sub-pixel and a second redundant sub-pixel that outputs a second light; and a third main sub-pixel and a third redundant sub-pixel that outputs a third light, wherein the first main sub-pixel, the first redundant sub-pixel, the second main sub-pixel, the second redundant sub-pixel, the third main sub-pixel, and the third redundant sub-pixel are sequentially disposed in the first direction or the second direction. Attached Figure Description

[0012] The above and other objects, features and advantages of the present invention will become more apparent to those skilled in the art from the detailed description of exemplary embodiments of the invention with reference to the accompanying drawings, in which:

[0013] Figure 1 This is a schematic configuration diagram of a display device according to one embodiment of the present invention;

[0014] Figure 2A This is a partial cross-sectional view of a display device according to an embodiment of the present invention;

[0015] Figure 2B This is a perspective view of a tiling display device according to an embodiment of the present invention;

[0016] Figure 3 This is a schematic enlarged plan view of the display area of ​​a display device according to an embodiment of the present invention;

[0017] Figure 4 It is a view showing the state in which sub-pixels of the same color are set not adjacent to each other in the pixel area;

[0018] Figure 5 It is a view showing the state in which subpixels of the same color are set adjacent to each other in the pixel area;

[0019] Figure 6 This is a view showing an active layer in a pixel region according to an embodiment of the present invention;

[0020] Figure 7 This is a view showing scan lines, driving transistors, a first transistor, and a second transistor in a pixel region according to an embodiment of the present invention;

[0021] Figure 8 This is a view showing a low-potential power line in a pixel area according to an embodiment of the present invention;

[0022] Figure 9 This is a view showing data lines in a pixel area according to an embodiment of the present invention;

[0023] Figure 10 This is a view showing a high-potential power line in a pixel area according to an embodiment of the present invention;

[0024] Figure 11 This is a view showing a light-emitting element, a first connecting electrode, and a second connecting electrode according to an embodiment of the present invention;

[0025] Figure 12 This is a cross-sectional view of a sub-pixel of a display device according to an embodiment of the present invention;

[0026] Figure 13 This is a pixel circuit diagram of a display device according to an embodiment of the present invention;

[0027] Figure 14 This is a pixel circuit diagram of a display device according to another embodiment of the present invention;

[0028] Figure 15 This is an enlarged plan view of the display area of ​​a display device according to another embodiment of the present invention;

[0029] Figure 16 This is a pixel circuit diagram of a display device according to another embodiment of the present invention;

[0030] Figure 17 This is an enlarged plan view of the display area of ​​a display device according to another embodiment of the present invention. Detailed Implementation

[0031] The advantages and features of the present invention, as well as its implementation methods, will become clear from the following detailed description of the embodiments in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments described below, but can be implemented in various different forms. These embodiments are provided merely to fully disclose the invention and to adequately convey its scope to those skilled in the art.

[0032] The shapes, dimensions, ratios, angles, quantities, etc., disclosed in the accompanying drawings used to describe embodiments of the invention are merely examples, and therefore the invention is not limited to the items shown in the figures. Throughout the specification, the same reference numerals denote the same components. Furthermore, in describing the invention, detailed descriptions of related known technologies are omitted where it is determined that such detailed descriptions would unnecessarily obscure the spirit of the invention. When terms such as “provided,” “comprising,” “having,” “including,” etc., are used in this specification, additional parts may be added unless “only” is used. Components referred to in the singular may also be referred to in the plural unless otherwise expressly indicated.

[0033] When interpreting components, a component is interpreted as including an error margin, even if there is no separate explicit description of such an error margin.

[0034] In describing positional relationships, such as when the positional relationship between two parts is described as "on top of," "above," "below," "beside," etc., one or more other parts may be located between the two parts, unless "immediately adjacent" or "directly" is used.

[0035] The situation in which an element or layer is described as being on another element or layer includes the situation in which the element or layer is directly located on another element or layer, and the situation in which yet another element or layer is inserted between the element or layer and another element or layer.

[0036] Although terms like "first," "second," etc., are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from another. Therefore, the "first component" mentioned below can also be the "second component" within the technical spirit of this invention.

[0037] Throughout the specification, similar reference numerals denote similar components.

[0038] The dimensions and thicknesses of each component shown in the accompanying drawings are for ease of description and are not necessarily limited to the dimensions and thicknesses of the components shown in this specification.

[0039] Features of various embodiments of the present invention can be combined with each other in part or in whole, and various technical links and operations are possible. Embodiments can be implemented independently of each other or together in a related relationship.

[0040] The invention will now be described with reference to the accompanying drawings.

[0041] Figure 1 This is a schematic configuration diagram of a display device according to one embodiment of the present invention. For ease of description, Figure 1 Only the display panel PN, gate driver GD, data driver DD, and timing controller TC among the various components of the display device 100 are shown.

[0042] Reference Figure 1 The display device 100 includes: a display panel PN comprising a plurality of sub-pixels SP; a gate driver GD and a data driver DD providing various signals to the display panel PN; and a timing controller TC controlling the gate driver GD and the data driver DD.

[0043] The gate driver GD supplies multiple scan signals to multiple scan lines SL based on multiple gate control signals provided by the timing controller TC. Figure 1 In this diagram, a gate driver GD is shown as being disposed at a distance from one side of the display panel PN, but the number and arrangement of gate drivers GD are not limited thereto.

[0044] The data driver DD supplies data voltage to multiple data lines DL based on multiple data control signals and image data provided by the timing controller TC. The data driver DD can use a reference gamma voltage to convert image data into data voltage and supply the converted data voltage to the multiple data lines DL.

[0045] The timing controller TC arranges the externally input image data and provides the image data to the data driver DD. The timing controller TC can use externally input synchronization signals (e.g., dot clock signals, data enable signals, and horizontal / vertical synchronization signals) to generate gate control signals and data control signals. Furthermore, the timing controller TC can control the gate driver GD and the data driver DD by providing the generated gate control signals and data control signals to the gate driver GD and the data driver DD, respectively.

[0046] The display panel PN is a structure used to display images to a user and includes multiple sub-pixels SP. In the display panel PN, multiple scan lines SL and multiple data lines DL intersect each other, and multiple sub-pixels SP can be formed at the intersections of the scan lines SL and the data lines DL.

[0047] The display area AA and the non-display area NA can be defined in the display panel PN.

[0048] The display area AA is the area in the display device 100 where an image is displayed. It is composed of multiple pixels PX (see...). Figure 2B Multiple sub-pixels SP and pixel circuits for driving the multiple sub-pixels SP can be disposed in the display area AA. The multiple sub-pixels SP are the smallest unit constituting the display area AA, and n sub-pixels SP can form one pixel PX. The multiple light-emitting elements 120 (see...) are used to drive the multiple light-emitting elements 120 (see...) Figure 3Thin-film transistors and the like can be disposed in each of the multiple sub-pixels SP. Depending on the type of display panel PN, the multiple light-emitting elements 120 can be defined differently. For example, when the display panel PN is an inorganic light-emitting display panel, the light-emitting elements 120 can be light-emitting diodes (LEDs) or micro-LEDs.

[0049] Multiple signal lines transmitting various signals to multiple sub-pixels SP are arranged in the display area AA. For example, the multiple signal lines may include multiple data lines DL providing data voltage to each of the multiple sub-pixels SP, multiple scan lines SL providing scan signals to each of the multiple sub-pixels SP, etc. The multiple scan lines SL may extend in one direction in the display area AA and may be connected to the multiple sub-pixels SP, and the multiple data lines DL may extend in the display area AA in a direction different from this one direction and may be connected to the multiple sub-pixels SP. In addition, low-potential power lines, high-potential power lines, etc. may be further provided in the display area AA, but the present invention is not limited thereto.

[0050] The non-display area NA is the area where no image is displayed and can be defined as the area extending from the display area AA. Within the non-display area NA, connection lines and pad electrodes for transmitting signals to the sub-pixels SP of the display area AA, as well as driver integrated circuit ICs such as gate driver ICs and data driver ICs, can be provided.

[0051] Meanwhile, the non-display area NA may be located on the rear surface of the display panel PN, that is, on the surface without sub-pixels SP, or may be omitted, and is not limited to what is shown in the attached figure.

[0052] Meanwhile, drivers such as gate driver GD, data driver DD, and timing controller TC can be connected to the display panel PN in various ways. For example, the gate driver GD can be installed in the non-display area NA using the gate in panel (GIP) method, or it can be installed between multiple sub-pixels SP in the display area AA using the gate in active area (GIA) method.

[0053] For example, the data driver DD and the timing controller TC can be formed on separate flexible films and printed circuit boards, and the display panel PN, the data driver DD, and the timing controller TC can be electrically connected by bonding the flexible film and the printed circuit board to pad electrodes formed in the non-display area NA of the display panel PN.

[0054] As another example, when the gate driver GD is mounted within the display area AA using the GIA method, and a side line SRL is formed connecting the signal lines on the front surface of the display panel PN to the pad electrodes on the rear surface of the display panel PN (see... Figure 2ABy bonding the flexible film and printed circuit board to the rear surface of the display panel PN, the non-display area NA on the front surface of the display panel PN can be minimized. Therefore, when the gate driver GD, data driver DD, and timing controller TC are connected to the display panel PN as described above, a virtually bezel-less design can be achieved. A more detailed description will refer to... Figure 2A and 2B .

[0055] Figure 2A This is a partial cross-sectional view of a display device according to an embodiment of the present invention. Figure 2B This is a perspective view of a tiled display device according to an embodiment of the present invention.

[0056] Multiple pad electrodes for transmitting various signals to multiple sub-pixels SP are disposed in the non-display area NA of the display panel PN. For example, a first pad electrode PAD1 for transmitting signals to multiple sub-pixels SP is disposed in the non-display area NA on the front surface of the display panel PN, and a second pad electrode PAD2 electrically connected to driving components such as flexible films and printed circuit boards is disposed in the non-display area NA on the rear surface of the display panel PN.

[0057] In this case, although not shown in the figure, various signal lines (e.g., scan lines SL, data lines DL, etc.) connected to multiple sub-pixels SP can extend from the display area AA to the non-display area NA and can be electrically connected to the first pad electrode PAD1.

[0058] Furthermore, the side line SRL is disposed along the side surface of the display panel PN. The side line SRL can electrically connect the first pad electrode PAD1 on the front surface of the display panel PN to the second pad electrode PAD2 on the rear surface of the display panel PN. Therefore, signals can be transmitted from the driving components on the rear surface of the display panel PN to multiple sub-pixels SP through the second pad electrode PAD2, the side line SRL, and the first pad electrode PAD1. Therefore, by placing the driving components on the rear surface of the display panel PN and forming a signal transmission path between the front and rear surfaces of the display panel PN, the area of ​​the non-display area NA on the front surface of the display panel PN can be minimized.

[0059] In addition, refer to Figure 2B A large-screen tiled display device TD can be achieved by connecting multiple display devices 100. In this case, when the tiled display device TD uses devices with... Figure 2A When the display device 100 with minimized borders is implemented as shown, the seam area between the display devices 100 where no image is displayed can be minimized, thereby improving display quality.

[0060] For example, a pixel PX may include multiple subpixels SP, and the spacing D1 between the outermost pixel PX of one display device 100 and the outermost pixel PX of another adjacent display device 100 may be implemented in the same way as the spacing D1 between pixels PX in one display device 100. Therefore, since the spacing of pixels PX between display devices 100 is configured to be constant, the seam area can be minimized.

[0061] However, Figure 2A and 2B As is exemplary, the display device 100 according to one embodiment of the present invention may be a general display device in which a border exists, but is not limited thereto.

[0062] Figure 3 This is a schematic enlarged plan view of the display area of ​​a display device according to an embodiment of the present invention.

[0063] Reference Figure 3 A pixel region UPA, in which pixels are formed, and a transmissive region TA surrounding the pixel region UPA are formed in the display area AA. Since the light-emitting element 120, driven by the pixel circuit, is formed in the pixels of the display area AA, the multiple pixel regions UPA can be substantially opaque areas, and the multiple transmissive regions TA can be substantially transparent areas. In this case, the pixel region UPA can also be defined as a light-emitting area, because it is the area that displays the light emitted from the light-emitting element 120. Furthermore, since the pixel region UPA is the area in which pixel circuitry is formed, it can also be defined as a circuitry area.

[0064] Multiple pixel areas UPA are areas where light-emitting elements 120 are provided and images are displayed. Multiple pixel areas UPA can be configured to be spaced apart from each other while having multiple transmissive areas TA between them. For example, multiple pixel areas UPA can be configured to form multiple rows and columns.

[0065] A pixel area UPA may include multiple sub-pixels SP. These multiple sub-pixels SP may include primary sub-pixels MSP and redundant sub-pixels SSP. According to an implementation, three primary sub-pixels MSP and three redundant sub-pixels SSP may be provided, but the number of each sub-pixel is not limited to this.

[0066] The primary sub-pixel (MSP) may include a first primary sub-pixel (MSP1) that outputs the first light, a second primary sub-pixel (MSP2) that outputs the second light, and a third primary sub-pixel (MSP3) that outputs the third light. The redundant sub-pixel (SSP) may include a first redundant sub-pixel (SSP1) that outputs the first light, a second redundant sub-pixel (SSP2) that outputs the second light, and a third redundant sub-pixel (SSP3) that outputs the third light.

[0067] The first primary sub-pixel MSP1 and the first redundant sub-pixel SSP1 can output first light within the same wavelength range, the second primary sub-pixel MSP2 and the second redundant sub-pixel SSP2 can output second light within the same wavelength range, and the third primary sub-pixel MSP3 and the third redundant sub-pixel SS3 can output third light within the same wavelength range.

[0068] The first light can be light R in the red wavelength range, the second light can be light G in the green wavelength range, and the third light can be light B in the blue wavelength range. However, the implementation is not limited to this. For example, the first light can be light in the blue wavelength range, the second light can be light in the red wavelength range, and the third light can be light in the green wavelength range.

[0069] The driving transistors DT in multiple main sub-pixels (MSPs) and redundant sub-pixels (SSPs) can be arranged in a column in the second direction (Y-axis direction). Multiple main sub-pixels (MSPs) and redundant sub-pixels (SSPs) can be arranged in a column while overlapping with areas where data lines DL, low-potential power lines VSS, and high-potential power lines VDD are located.

[0070] According to the implementation method, the first primary sub-pixel MSP1, the first redundant sub-pixel SSP1, the second primary sub-pixel MSP2, the second redundant sub-pixel SSP2, the third primary sub-pixel MSP3, and the third redundant sub-pixel SS3 can be sequentially arranged in a first direction (X-axis direction) or a second direction (Y-axis direction), for example, arranged in a column. Sequential arrangement can mean arranging the sub-pixels in the order listed above.

[0071] The spacing between the first primary sub-pixel MSP1 and the first redundant sub-pixel SSP1 can be the same as the spacing between the second primary sub-pixel MSP2 and the second redundant sub-pixel SSP2. This configuration offers the advantage that the primary sub-pixels MSP and redundant sub-pixels SSP emitting the same color of light are arranged adjacent to each other at a constant spacing, thus ensuring a uniform color distribution.

[0072] Multiple micro-light-emitting elements (LEDs) can be epitaxially grown on a wafer and then transferred to a panel. Therefore, some LEDs may contain defective pixels that do not emit light or emit light abnormally due to various defects. Therefore, redundant sub-pixels (SSPs) can be configured to prepare for defective pixels after transfer to the panel. Thus, when a defect is found in the main sub-pixel (MSP) during process inspection, the redundant SSP can be configured to be driven. Therefore, any one or both of the main sub-pixel (MSP) and redundant SSPs can be used in the panel.

[0073] For example, when either the primary subpixel or the redundant subpixel is defective, and therefore only the other operates, the following problem exists: the spacing between subpixels is not constant, resulting in uneven color.

[0074] Reference Figure 4 When the primary sub-pixels (MSPs) are arranged together on one side and the redundant sub-pixels (SSPs) are arranged together on the other side, the third redundant sub-pixel (SSP3) can be designed to be driven when the third primary sub-pixel (MSP3) is determined to be defective. However, in this case, the interval L2 between the second primary sub-pixel (MSP2) and the third redundant sub-pixel (SSP3) becomes too large compared to the interval L1 between the first primary sub-pixel (MSP1) and the second primary sub-pixel (MSP2). Therefore, problems of image quality and recognizability degradation may occur.

[0075] On the other hand, refer to Figure 5 When the primary sub-pixel MSP and the redundant sub-pixel SSP are alternately set, it can be seen that even when the third primary sub-pixel MSP3 is defective, the interval L2 between the second primary sub-pixel MSP2 and the third redundant sub-pixel SSP3 can become relatively short, thus enhancing color uniformity.

[0076] Refer again Figure 3 The pixel region UPA may overlap with lines extending in the column direction among multiple lines (e.g., data lines DL and / or reference lines RL). By forming the pixel region UPA in an area with multiple opaque lines, the area of ​​the transmissive region TA can be ensured throughout the entire display area AA. Specifically, the pixel region UPA having multiple sub-pixels SP can be an area with low transmittance and is substantially opaque due to the construction of the pixel circuitry and light-emitting element 120 disposed in the multiple sub-pixels SP.

[0077] According to the implementation, multiple sub-pixels SP of the pixel region UPA can be configured to overlap with opaque lines extending along the column direction, such as data lines DL, low-potential power lines VSS, and high-potential power lines VDD. Therefore, by configuring the multiple sub-pixels SP of the pixel region UPA such that the multiple sub-pixels SP overlap with multiple lines, the area of ​​the opaque area in the entire display area AA can be reduced and the area of ​​the transmissive area TA can be maximized.

[0078] According to one implementation, the reference line RL can be fabricated using the active layer of the second transistor T2 to create a transparent line. Therefore, the reference line RL can be configured such that at least a portion of it does not overlap with the sub-pixel SP. Because the reference line RL does not overlap with the sub-pixel SP, the opaque pixel area UPA can be further reduced.

[0079] Each of the multiple sub-pixels SP may include pixel circuitry connected to a data line DL, a reference line RL, a low-potential power line VSS, and a high-potential power line VDD. Pixel circuitry may include multiple transistors.

[0080] According to the implementation, among the transistors constituting the pixel circuit, the first transistor T1 connected to the data line DL can be shared by the main sub-pixel MSP and the redundant sub-pixel SSP. For example, the first main sub-pixel MSP1 and the first redundant sub-pixel SSP1 can share the 1-1 transistor T11. Therefore, when the 1-1 transistor T11 is turned on in response to the scan signal, the data voltage can be simultaneously applied to the gate of the first main sub-pixel MSP1 and the gate of the first redundant sub-pixel SSP1.

[0081] The second primary sub-pixel MSP2 and the second redundant sub-pixel SSP2 can share 1-2 transistors T12. The third primary sub-pixel MSP3 and the third redundant sub-pixel SSP3 can share 1-3 transistors T13.

[0082] With this configuration, the size of the sub-pixel SP can be reduced because each main sub-pixel and redundant sub-pixel share the first transistor T1. Therefore, the area of ​​the transmission region TA can be increased by reducing the area of ​​the pixel region UPA.

[0083] The scan line SL may include a first scan line SL1 extending in the same second direction (Y-axis direction) as the multiple data lines DL, a second scan line SL2 extending in a first direction (X-axis direction) intersecting the second direction, and a third scan line (or sub-scan line) SL3 branching from or extending from the second scan line SL2 and set parallel to the second scan line SL2.

[0084] The first direction can be a horizontal line, and the second direction can be a vertical line, but they are not limited to these. For example, the first direction can be a vertical line, while the second direction can be a horizontal line.

[0085] The active layer of the first transistor T1 can extend in the second direction (Y-axis direction) and overlap with the second scan line SL2 and the third scan line SL3 to have a dual-gate structure. Therefore, leakage current blocking performance can be improved.

[0086] Multiple transmissive regions TA are areas within the display area AA, excluding areas with multiple lines and multiple pixel areas UPA, and the multiple transmissive regions TA have relatively high transmittance. Light is transmitted through the transmissive regions TA, and the background located at the rear surface of the display device 100 can be seen from the front surface of the display device 100. The multiple transmissive regions TA can be configured to be spaced apart from each other while having multiple lines and multiple pixel areas UPA. The multiple transmissive regions TA can be configured to surround multiple pixel areas UPA. Therefore, the display device 100 according to one embodiment of the present invention can be implemented as a transparent display device 100 by including multiple transmissive regions TA.

[0087] Figure 6This is a view showing an active layer in a pixel region according to an embodiment of the present invention. Figure 7 This is a view showing scan lines, driving transistors, a first transistor, and a second transistor in a pixel region according to an embodiment of the present invention.

[0088] Reference Figure 6 As described above, the pixel region UPA may include three main sub-pixels and three redundant sub-pixels. Multiple first active layers ACT11, ACT12, and ACT13 of the first transistor may extend in the second direction (Y-axis direction) and may be spaced apart from each other in the first direction (X-axis direction). Multiple driving active layers DACT11, DACT12, DACT21, DACT22, DACT31, and DACT32 of the driving transistor may be connected to the second active layers ACT21, ACT22, ACT23, ACT24, ACT25, and ACT26 of the second transistor. Furthermore, the second active layers ACT21, ACT22, ACT23, ACT24, ACT25, and ACT26 of the second transistor may be connected to each other. Therefore, the signal output from the driving transistor DT can be applied to the reference line RL through the second transistor T2. The light blocking layer LS (see...) Figure 12 It can be set below the driving active layer of the driving transistor DT.

[0089] Reference Figure 7 The driving transistor DT includes a 1-1 driving transistor DT11 for the first main sub-pixel MSP1, a 1-2 driving transistor DT12 for the first redundant sub-pixel SSP1, a 2-1 driving transistor DT21 for the second main sub-pixel MSP2, a 2-2 driving transistor DT22 for the second redundant sub-pixel SSP2, a 3-1 driving transistor DT31 for the third main sub-pixel MSP3, and a 3-2 driving transistor DT32 for the third redundant sub-pixel SSP3. Each driving transistor may include a driving active layer DACT and a gate DGE (see...). Figure 12 ), drive drain DDE and drive source DSE. Multiple capacitors Cst can be set to overlap with the drive transistor DT respectively.

[0090] The first transistor T1 may include a 1-1 transistor T11 connected to a 1-1 driving transistor DT11 and a 1-2 driving transistor DT12, a 1-2 transistor T12 connected to a 2-1 driving transistor DT21 and a 2-2 driving transistor DT22, and a 1-3 transistor T13 connected to a 3-1 driving transistor DT31 and a 3-2 driving transistor DT32.

[0091] According to the implementation, the 1-1 driving transistor DT11 of the first main sub-pixel MSP1 and the 1-2 driving transistor DT12 of the first redundant sub-pixel SSP1 can share the first transistor T1. The 1-1 driving gate DGE11 of the 1-1 driving transistor DT11 and the 1-2 driving gate DGE12 of the 1-2 driving transistor DT12 can be connected to each other. Therefore, the data voltage applied from the 1-1 transistor T11 can be jointly applied to the 1-1 driving gate DGE11 of the 1-1 driving transistor DT11 and the 1-2 driving gate DGE12 of the 1-2 driving transistor DT12, as shown by arrow DPL.

[0092] The 2-1 drive gate DGE21 of the 2-1 drive transistor DT21 and the 2-2 drive gate DGE22 of the 2-2 drive transistor DT22 can be connected to each other. Therefore, the data voltage applied from the 1-2 transistor T12 can be jointly applied to the 2-1 drive gate DGE21 of the 2-1 drive transistor DT21 and the 2-2 drive gate DGE22 of the 2-2 drive transistor DT22.

[0093] The 3-1 driving gate DGE31 of the 3-1 driving transistor DT31 and the 3-2 driving gate DGE32 of the 3-2 driving transistor DT32 can be connected to each other. Therefore, the data voltage applied from the 1-3 transistor T13 can be jointly applied to the 3-1 driving gate DGE31 of the 3-1 driving transistor DT31 and the 3-2 driving gate DGE32 of the 3-2 driving transistor DT32.

[0094] With this configuration, since two driving transistors are connected to a first transistor T1, the number of transistors can be reduced, thereby reducing the area of ​​the pixel region UPA. Therefore, the area of ​​the transmissive region TA can be increased.

[0095] The scan line SL may include a second scan line SL2 and a third scan line SL3 branching from multiple pixel regions UPA. Therefore, the first active layer ACT1 of the first transistor T1 may extend in the second direction and overlap with each of the second scan line SL and the third scan line SL3 to form a dual-gate structure. The third scan line SL3 may also be referred to as an auxiliary scan line. The third scan line SL3 may be shorter than the second scan line SL2.

[0096] Each second transistor T2 may include a second active layer ACT2, a second gate GE2, a second drain DE2, and a second source SE2, and may be configured to be adjacent to the driving transistor DT. A scan line SL may include a first scan line SL1 extending in a second direction (Y-axis direction) and overlapping with the second active layer ACT2 of the second transistor to form the second gate GE2.

[0097] The second transistor T2 may include a 2-1 transistor T21 connected to the 1-1 driving transistor DT11, a 2-2 transistor T22 connected to the 1-2 driving transistor DT12, a 2-3 transistor T23 connected to the 2-1 driving transistor DT21, a 2-4 transistor T24 connected to the 2-2 driving transistor DT22, a 2-5 transistor T25 connected to the 3-1 driving transistor DT31, and a 2-6 transistor T26 connected to the 3-2 driving transistor DT32.

[0098] Figure 8 This is a view showing a low-potential power line in a pixel area according to an embodiment of the present invention. Figure 9 This is a view showing data lines in a pixel area according to an embodiment of the present invention. Figure 10 This is a view showing a high-potential power line in a pixel area according to an embodiment of the present invention.

[0099] Reference Figures 8 to 10 The low-potential power line VSS can be placed on the driving transistor DT and the capacitor Cst. The data line DL can be placed on the low-potential power line VSS. The high-potential power line VDD can be placed on the data line DL. An insulating layer can be placed between the low-potential power line VSS, the data line DL, and the high-potential power line VDD to electrically insulate each layer.

[0100] The low-potential power line VSS, data line DL, and high-potential power line VDD can be configured to overlap with the sub-pixel SP. The low-potential power line VSS can be positioned between the storage capacitor Cst, the driving transistor DT, and multiple data lines DL, and overlaps with the area where multiple data lines DL are located. The low-potential power line VSS can overlap with multiple data lines DL, the driving transistor DT, and the storage capacitor Cst. The high-potential power line VDD can overlap with multiple data lines DL, the driving transistor DT, the storage capacitor Cst, and the low-potential power line VSS. The high-potential power line VDD can be positioned between the light-emitting element 120 and the data lines DL, and overlaps with the area where multiple data lines DL are located. Therefore, the area of ​​the transmissive region TA can be increased by minimizing the area of ​​the pixel region UPA.

[0101] Figure 11 This is an enlarged plan view of the display area of ​​a display device according to an embodiment of the present invention. Figure 12 This is a cross-sectional view of a sub-pixel of a display device according to an embodiment of the present invention.

[0102] Reference Figure 11 and 12Each of the multiple sub-pixels SP includes pixel circuitry and one or more light-emitting elements 120. The pixel circuitry may include multiple transistors T1, T2, and DT, as well as a storage capacitor Cst, and supplies drive current to the light-emitting elements 120. For example, the pixel circuitry may include a first transistor T1, a second transistor T2, a drive transistor DT, and a storage capacitor Cst. Furthermore, the multiple sub-pixels SP disposed in a pixel region UPA can be connected to scan lines SL, multiple data lines DL, a reference line RL, a high-potential power line VDD, and a low-potential power line VSS, and can receive various signals.

[0103] The substrate 110 is a structure for supporting various components included in the display device 100, and may be made of an insulating material. For example, the substrate 110 may be made of glass, resin, etc. In addition, the substrate 110 may include polymers or plastics, or may be made of a flexible material.

[0104] A light-blocking layer LS is disposed on each of a plurality of sub-pixels SP on the substrate 110. The light-blocking layer LS blocks light incident from the bottom of the substrate 110 onto the driving active layer DACT of the driving transistor DT. Since the light-blocking layer LS blocks light incident on the driving active layer DACT of the driving transistor DT, leakage current can be minimized.

[0105] A buffer layer 111 is disposed on the substrate 110 and the light-blocking layer LS. The buffer layer 111 reduces the penetration of moisture or impurities through the substrate 110. The buffer layer 111 may be composed of a single layer or multiple layers of, for example, silicon oxide (SiOx) and / or silicon nitride (SiNx), but is not limited thereto. However, depending on the type of substrate 110 or the type of transistor, the buffer layer 111 may be omitted, but is not limited thereto.

[0106] The driving transistor DT and the second transistor T2 are disposed in each of the plurality of sub-pixels SP on the buffer layer 111.

[0107] The driving transistor DT, the first transistor T1, and the second transistor T2 for each of the multiple sub-pixels SP can be either a P-type thin-film transistor or an N-type thin-film transistor. For example, in a P-type thin-film transistor, current can flow from the source to the drain as holes move from the source to the drain. In an N-type thin-film transistor, current can flow from the drain to the source as electrons move from the source to the drain. In the following description, it is assumed that the driving transistor DT, the first transistor T1, and the second transistor T2 are P-type thin-film transistors that allow current to flow from the source to the drain, but the invention is not limited thereto.

[0108] First, a driving transistor DT is disposed in each of the plurality of sub-pixels SP on the buffer layer 111. The driving transistor DT can be disposed between multiple data lines DL and the substrate 110 and electrically connected to the first transistor T1. The driving transistor DT is a transistor used to control the driving current supplied to the light-emitting element 120. The driving transistors DT of the plurality of sub-pixels can be disposed in a column in the column direction.

[0109] The driving transistor DT includes the driving active layer DACT, the driving gate DGE, the driving source DSE, and the driving drain DDE.

[0110] The driving active layer DACT is disposed on the buffer layer 111. The driving active layer DACT may be made of semiconductor materials such as oxide semiconductor, amorphous silicon or polycrystalline silicon, but is not limited thereto.

[0111] A gate insulating layer 112 is disposed on the driving active layer DACT. The gate insulating layer 112 is an insulating layer used to electrically insulate the driving active layer DACT and the driving gate DGE, and may be composed of a single layer or multiple layers of silicon oxide (SiOx) and / or silicon nitride (SiNx), but is not limited thereto.

[0112] The driving gate DGE is disposed on the gate insulating layer 112. The driving gate DGE may be composed of a single layer or multiple layers of conductive materials such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr) or their alloys, but is not limited thereto.

[0113] A first interlayer insulating layer 113a is disposed on the driving gate DGE. A contact hole is formed in the first interlayer insulating layer 113a for connecting the driving source DSE to the driving active layer DACT. The first interlayer insulating layer 113a is an insulating layer for protecting the structure located below it, and may be composed of a single layer or multiple layers of silicon oxide (SiOx) and / or silicon nitride (SiNx), but is not limited thereto.

[0114] The driving source DSE is disposed on the first interlayer insulating layer 113a. The driving source DSE is electrically connected to the driving active layer DACT through a contact hole formed in the first interlayer insulating layer 113a. In addition, the driving source DSE can be electrically connected to the second transistor T2. The driving source DSE can be composed of a single layer or multiple layers of conductive materials such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or alloys thereof, but is not limited thereto.

[0115] The second interlayer insulating layer 113b is disposed on the driving source electrode DSE. The second interlayer insulating layer 113b is an insulating layer for protecting the structure located below the second interlayer insulating layer 113b, and may be composed of a single layer or multiple layers of silicon oxide (SiOx) and / or silicon nitride (SiNx), but is not limited thereto.

[0116] The first passivation layer 114a is disposed on the second interlayer insulating layer 113b. The first passivation layer 114a is an insulating layer for protecting the structure located below the first passivation layer 114a, and may be composed of a single layer or multiple layers of silicon oxide (SiOx) and / or silicon nitride (SiNx), but is not limited thereto.

[0117] The driving drain DDE is disposed on the first passivation layer 114a. The driving drain DDE is electrically connected to the driving active layer DACT through contact holes formed in the first passivation layer 114a, the first interlayer insulating layer 113a, and the second interlayer insulating layer 113b. Furthermore, the driving drain DDE can be electrically connected to the low-potential power line VSS through contact holes formed in the first passivation layer 114a. The driving drain DDE can be composed of a single layer or multiple layers of conductive materials such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or alloys thereof, but is not limited thereto.

[0118] Next, a first transistor T1 is disposed in each of the plurality of sub-pixels SP on the buffer layer 111. The first transistor T1 is for transmitting the data voltage Data (see...) Figure 13 The transistor that transmits data to the gate of the driving transistor DT is called a switching transistor. In this case, multiple first transistors T1 in multiple sub-pixels SP in a pixel region UPA are configured to overlap with the scan line SL and can be arranged in a row in the row direction.

[0119] Specifically, the scan line SL can extend along the row direction on the gate insulating layer 112 and can span multiple pixel regions UPA.

[0120] The first transistor T1 includes a first active layer ACT1, a first gate GE1, a first source SE1, and a first drain DE1.

[0121] The first active layer ACT1 is disposed on the buffer layer 111. The first active layer ACT1 may be made of a semiconductor material such as oxide semiconductor, amorphous silicon or polycrystalline silicon, but is not limited thereto.

[0122] A first gate GE1 is disposed on the gate insulating layer 112. The first gate GE1 can be electrically connected to the scan line SL. For example, the first gate GE1 can be integrally formed with the scan line SL. The first gate GE1 can be made of a single layer or multiple layers of conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr) or alloys thereof, but is not limited thereto.

[0123] The first drain DE1 is disposed between the first interlayer insulating layer 113a and the second interlayer insulating layer 113b. The first drain DE1 is electrically connected to the first active layer ACT1 through contact holes formed in the first interlayer insulating layer 113a and the gate insulating layer 112. Furthermore, the first drain DE1 can be electrically connected to the second gate GE2 of the second transistor T2 through contact holes in the first interlayer insulating layer 113a. The first drain DE1 may be composed of a single layer or multiple layers of conductive materials such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or alloys thereof, but is not limited thereto.

[0124] The first source electrode SE1 is disposed on the first passivation layer 114a. The first source electrode SE1 is electrically connected to the first active layer ACT1 through the first passivation layer 114a, the second interlayer insulating layer 113b, and contact holes in the first interlayer insulating layer 113a. Furthermore, the first source electrode SE1 can be electrically connected to the data line DL. For example, the first source electrode SE1 can be integrally formed with the data line DL. The first source electrode SE1 can be composed of a single layer or multiple layers of conductive materials such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or alloys thereof, but is not limited thereto.

[0125] Next, a second transistor T2 is disposed on the buffer layer 111 in each of the plurality of sub-pixels SP. The second transistor T2 may be disposed between the plurality of data lines DL and the substrate 110 and electrically connected to the driving transistor DT. The second transistor T2 is a transistor used to compensate for the threshold voltage of the driving transistor DT and may be referred to as a sensing transistor. The second transistors T2 of the plurality of sub-pixels SP may be disposed in a column along the column direction of the protrusion of the scan line SL. For example, the second transistors T2 of the plurality of sub-pixels SP on one side of the scan line SL may be configured to correspond to the column direction of the protrusion of the scan line SL, and the second transistors T2 of the plurality of sub-pixels SP on the other side of the scan line SL may be configured to correspond to the protrusion of the scan line SL. Therefore, the plurality of second transistors T2 disposed in a pixel region UPA may be disposed in a column in the column direction.

[0126] The second transistor T2 includes a second active layer ACT2, a second gate GE2, a second source SE2, and a second drain DE2.

[0127] The second active layer ACT2 is disposed between the buffer layer 111 and the gate insulating layer 112. The second active layer ACT2 may be made of a semiconductor material such as oxide semiconductor, amorphous silicon or polycrystalline silicon, but is not limited thereto.

[0128] In this scenario, the second active layers ACT2 of multiple adjacent sub-pixels SP can be connected to each other. For example, the second active layers ACT2 of the first, second, and third sub-pixels disposed on one side of the scan line SL can extend in the column direction and be connected to each other, and can be connected together to the second drain DE2 disposed in the first sub-pixel. Furthermore, the second active layers ACT2 of the first, second, and third sub-pixels disposed on the other side of the scan line SL can also extend in the column direction and be connected to each other, and can be connected together to the second drain DE2 disposed in the first sub-pixel. That is, since the connection portion of the channel region of the second active layer ACT2 connecting multiple sub-pixels SP to the reference line RL is made of a transparent material of the second active layer ACT2 rather than an opaque conductive material, the transmittance at the outermost edge of the pixel region UPA can be enhanced. Furthermore, since the connection portion of the channel region of the second active layer ACT2 connecting multiple sub-pixels SP to the reference line RL is made of the material of the second active layer ACT2, contact holes can be eliminated, and the structure of the pixel region UPA can be simplified. A sub-pixel can be a concept that includes a primary sub-pixel and redundant sub-pixels.

[0129] The second gate GE2 is disposed between the gate insulating layer 112 and the first interlayer insulating layer 113a. The second gate GE2 can be electrically connected to the scan line SL. For example, the second gate GE2 can be integrally formed with and electrically connected to the protrusion of the scan line SL. The second gate GE2 can be made of a single layer or multiple layers of conductive materials such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or alloys thereof, but is not limited thereto.

[0130] The second source electrode SE2 is disposed between the first interlayer insulating layer 113a and the second interlayer insulating layer 113b. The second source electrode SE2 is electrically connected to the second active layer ACT2 through contact holes in the first interlayer insulating layer 113a and the gate insulating layer 112. Furthermore, the second source electrode SE2 may be integrally formed with and electrically connected to the drive source electrode DSE. The second source electrode SE2 may be composed of a single layer or multiple layers of conductive materials such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or alloys thereof, but is not limited thereto.

[0131] The second drain DE2 is disposed between the first passivation layer 114a and the second passivation layer 114b. The second drain DE2 is electrically connected to the second active layer ACT2 through contact holes formed in the first passivation layer 114a, the second interlayer insulating layer 113b, the first interlayer insulating layer 113a, and the gate insulating layer 112. The second drain DE2 may be integrally formed with and electrically connected to the reference line RL. The second drain DE2 may be composed of a single layer or multiple layers of conductive materials such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or alloys thereof, but is not limited thereto.

[0132] Next, a storage capacitor Cst is disposed on the gate insulating layer 112. The storage capacitor Cst can be disposed between multiple data lines DL and the driving transistor DT. The storage capacitor Cst can store the potential difference between the driving gate DGE and the driving source DSE of the driving transistor DT while the light-emitting element 120 emits light, and can allow a constant driving current to be supplied to the light-emitting element 120. The storage capacitor Cst may include a first capacitor electrode C1 electrically connected to the driving gate DGE and a second capacitor electrode C2 electrically connected to the driving source DSE, thus maintaining a constant voltage between the driving gate DGE and the driving source DSE.

[0133] Specifically, a first capacitor electrode C1 is disposed on the gate insulating layer 112. The first capacitor electrode C1 may be integrally formed with the driving gate DGE. A second capacitor electrode C2 is disposed on the first interlayer insulating layer 113a. The first capacitor electrode C1 and the second capacitor electrode C2 may be configured to overlap each other while having the first interlayer insulating layer 113a between them. In this case, the second capacitor electrode C2 may be integrally formed with the driving source DSE. The first capacitor electrode C1 and the second capacitor electrode C2 may be composed of a single layer or multiple layers of conductive materials such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or alloys thereof, but are not limited thereto.

[0134] Next, an auxiliary electrode AE ​​is disposed on the first passivation layer 114a. The auxiliary electrode AE ​​is an electrode used to electrically connect the driving source DSE and the first reflecting electrode RE1. The driving source DSE and the first reflecting electrode RE1 can be electrically connected to each other through the auxiliary electrode AE. The auxiliary electrode AE ​​can be composed of a single layer or multiple layers of conductive materials such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or alloys thereof, but is not limited thereto.

[0135] A low-potential power line (VSS) is disposed on the second interlayer insulating layer 113b. The VSS can be disposed along the column direction and can overlap with multiple pixel regions (UPAs). The VSS can be electrically connected to the drive drain (DDE). The VSS can be composed of a single layer or multiple layers of conductive materials such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or alloys thereof, but is not limited thereto.

[0136] A reference line RL is disposed on the first passivation layer 114a. The reference line RL may be disposed along the column direction and may overlap with multiple pixel regions UPA. The reference line RL may be disposed adjacent to the protruding portion of the scan line SL and may be electrically connected to multiple second transistors T2 disposed on the protruding portion of the scan line SL. The reference line RL may be composed of a single layer or multiple layers of conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or alloys thereof, but is not limited thereto.

[0137] Multiple data lines DL are disposed on the first passivation layer 114a. The multiple data lines DL can extend in the column direction and overlap with multiple pixel regions UPA. The multiple data lines DL can be disposed on the driving transistor DT and the storage capacitor Cst, and overlap with the driving transistor DT and the storage capacitor Cst.

[0138] Next, a second passivation layer 114b is disposed on the driving transistor DT, the first transistor T1, the second transistor T2, the storage capacitor Cst, the reference line RL, and the data line DL. The second passivation layer 114b is an insulating layer used to protect the structure located below the second passivation layer 114b, and may be composed of a single layer or multiple layers of silicon oxide (SiOx) and / or silicon nitride (SiNx), but is not limited thereto.

[0139] A first planarization layer 115a is disposed on a second passivation layer 114b. The first planarization layer 115a can planarize the upper portion of the substrate 110 on which a plurality of transistors and storage capacitors Cst are disposed. The first planarization layer 115a may be composed of a single layer or multiple layers, and may be made of, for example, photoresist or acrylic-based organic materials, but is not limited thereto.

[0140] Meanwhile, although not shown in the figure, an additional passivation layer may be provided on the first planarization layer 115a. For example, a passivation layer composed of a single layer or multiple layers of silicon oxide (SiOx) and / or silicon nitride (SiNx) may be formed on the first planarization layer 115a to protect the structure located below the passivation layer.

[0141] Next, a plurality of first reflective electrodes RE1 are disposed on the first planarization layer 115a. The plurality of first reflective electrodes RE1 can be disposed in a plurality of sub-pixels SP, and can simultaneously reflect light emitted from the light-emitting element 120 to the outside of the display device 100 while electrically connecting the driving transistor DT and the light-emitting element 120. The plurality of first reflective electrodes RE1 can be disposed adjacent to the driving source electrode DSE in a plurality of sub-pixels SP. The plurality of first reflective electrodes RE1 can be made of an opaque conductive material with high reflectivity, such as titanium (Ti), gold (Au), silver (Ag), copper (Cu), or alloys thereof, but are not limited thereto.

[0142] The second reflective electrode RE2 and the high-potential power line VDD are disposed on the first planarization layer 115a. The second reflective electrode RE2 and the high-potential power line VDD are integrally formed and can reflect light emitted from the light-emitting element 120 to the outside of the display device 100 while providing a high-potential power supply voltage to the light-emitting element 120. The second reflective electrodes RE2 of multiple sub-pixels SP can be connected to each other and integrally formed. The second reflective electrode RE2 and the high-potential power line VDD can extend in the column direction and can be configured to overlap with the light-emitting element 120. The second reflective electrode RE2 and the high-potential power line VDD can be configured to overlap with multiple data lines DL, reference lines RL, and low-potential power lines VSS. The second reflective electrode RE2 and the high-potential power line VDD can be made of an opaque conductive material with high reflectivity, such as titanium (Ti), gold (Au), silver (Ag), copper (Cu), or alloys thereof, but are not limited thereto.

[0143] The third passivation layer 114c is disposed on the plurality of first reflective electrodes RE1 and second reflective electrodes RE2. The third passivation layer 114c is an insulating layer for protecting the structure located below the third passivation layer 114c, and may be composed of a single layer or multiple layers of silicon oxide (SiOx) and / or silicon nitride (SiNx), but is not limited thereto.

[0144] An adhesive layer AD is disposed on the third passivation layer 114c. The adhesive layer AD can be formed on the entire surface of the substrate 110 and can fix the light-emitting element 120 disposed on the adhesive layer AD. The adhesive layer AD can be made of a photocurable adhesive material that can be cured by light. For example, the adhesive layer AD can be selected from adhesive polymers, epoxy resins, UV resins, polyimide-based materials, acrylate-based materials, urethane-based materials, and polydimethylsiloxane (PDMS), but is not limited thereto.

[0145] Multiple light-emitting elements 120 are respectively disposed in multiple sub-pixels SP on the adhesive layer AD. The light-emitting elements 120 may be disposed on multiple data lines DL and electrically connected to driving transistors DT. The light-emitting elements 120 are elements that emit light through current, and may include red light-emitting elements 120 emitting red light, green light-emitting elements 120 emitting green light, and blue light-emitting elements 120 emitting blue light, and combinations thereof can achieve various colors of light, including white. For example, the light-emitting elements 120 may be light-emitting diodes (LEDs) or micro-LEDs, but are not limited thereto.

[0146] A red light-emitting element 120 may be disposed in a first sub-pixel, a green light-emitting element 120 may be disposed in a second sub-pixel, and a blue light-emitting element 120 may be disposed in a third sub-pixel. Multiple light-emitting elements 120 disposed in a pixel region UPA may be disposed in a column in the column direction. Furthermore, the multiple light-emitting elements 120 may be configured to overlap with the second reflective electrodes RE2 in multiple sub-pixels SP, respectively.

[0147] Each of the plurality of light-emitting elements 120 includes a first semiconductor layer 121, a light-emitting layer 122, a second semiconductor layer 123, a first electrode 124, a second electrode 125, and an encapsulation film 126.

[0148] A first semiconductor layer 121 is disposed on the adhesive layer AD, and a second semiconductor layer 123 may be disposed on the first semiconductor layer 121. The first semiconductor layer 121 and the second semiconductor layer 123 may be layers formed by doping specific materials with n-type and p-type impurities. For example, each of the first semiconductor layer 121 and the second semiconductor layer 123 may be a layer in which materials such as gallium nitride (GaN), indium aluminum phosphide (InAlP), and gallium arsenide (GaAs) are doped with n-type or p-type impurities. Furthermore, the p-type impurity may be magnesium, zinc (Zn), beryllium (Be), etc., and the n-type impurity may be silicon (Si), germanium, tin (Sn), etc., but is not limited thereto.

[0149] A light-emitting layer 122 is disposed between a first semiconductor layer 121 and a second semiconductor layer 123. The light-emitting layer 122 can emit light by receiving holes and electrons from the first semiconductor layer 121 and the second semiconductor layer 123. The light-emitting layer 122 can be formed in a single-layer or multiple quantum well (MQW) structure and is made of, for example, indium gallium nitride (InGaN), gallium nitride (GaN), etc., but is not limited thereto.

[0150] A first electrode 124 is disposed on the first semiconductor layer 121. The first electrode 124 is used to electrically connect the driving transistor DT and the first semiconductor layer 121. In this case, the first semiconductor layer 121 may be a semiconductor layer doped with n-type impurities, and the first electrode 124 may be a cathode. The first electrode 124 may be disposed on the upper surface of the first semiconductor layer 121 exposed from the light-emitting layer 122 and the second semiconductor layer 123. The first electrode 124 may be made of a conductive material, such as a transparent conductive material like indium tin oxide (ITO), indium zinc oxide (IZO), or an opaque conductive material like titanium (Ti), gold (Au), silver (Ag), copper (Cu), or alloys thereof, but is not limited thereto.

[0151] The second electrode 125 is disposed on the second semiconductor layer 123. The second electrode 125 may be disposed on the upper surface of the second semiconductor layer 123. The second electrode 125 is an electrode used for electrically connecting the high-potential power line VDD and the second semiconductor layer 123. In this case, the second semiconductor layer 123 may be a semiconductor layer doped with p-type impurities, and the second electrode 125 may be an anode. The second electrode 125 may be made of a conductive material, such as a transparent conductive material like indium tin oxide (ITO), indium zinc oxide (IZO), or an opaque conductive material like titanium (Ti), gold (Au), silver (Ag), copper (Cu), or alloys thereof, but is not limited thereto.

[0152] Next, an encapsulation film 126 is formed around the first semiconductor layer 121, the light-emitting layer 122, the second semiconductor layer 123, the first electrode 124, and the second electrode 125. The encapsulation film 126 may be made of an insulating material and may protect the first semiconductor layer 121, the light-emitting layer 122, and the second semiconductor layer 123. Furthermore, since contact holes exposing the first electrode 124 and the second electrode 125 are formed in the encapsulation film 126, the first connecting electrode CE1 and the second connecting electrode CE2 may be electrically connected to the first electrode 124 and the second electrode 125.

[0153] Simultaneously, a portion of the side surface of the first semiconductor layer 121 can be exposed from the encapsulation film 126. The light-emitting element 120 fabricated on the wafer can be separated from the wafer and transferred to the display panel PN. However, during the process of separating the light-emitting element 120 from the wafer, a portion of the encapsulation film 126 can be torn off. For example, since the portion of the encapsulation film 126 adjacent to the lower edge of the first semiconductor layer 121 of the light-emitting element 120 can be torn off during the separation process of the light-emitting element 120 and the wafer, a portion of the lower side surface of the first semiconductor layer 121 can be exposed to the outside. Even when the lower part of the light-emitting element 120 is exposed from the encapsulation film 126, short-circuit defects can be reduced because the first connection electrode CE1 and the second connection electrode CE2 are formed after the formation of the second planarization layer 115b and the third planarization layer 115c covering the side surface of the first semiconductor layer 121.

[0154] Next, the second planarization layer 115b and the third planarization layer 115c are disposed on the adhesive layer AD and the light-emitting element 120.

[0155] The second planarization layer 115b may overlap with portions of the side surfaces of the plurality of light-emitting elements 120 to fix and protect the plurality of light-emitting elements 120. The torn portions of the encapsulation film 126 protecting the side surfaces of the first semiconductor layer 121 of the light-emitting elements 120 may be covered by the second planarization layer 115b. Therefore, contact and short-circuit defects between the connection electrodes and the first semiconductor layer 121 can be prevented in the future.

[0156] A third planarization layer 115c is formed to cover the second planarization layer 115b and the upper portion of the light-emitting element 120. Contact holes may be formed in the third planarization layer 115c, through which the first electrode 124 and the second electrode 125 of the light-emitting element 120 are exposed. Since the first electrode 124 and the second electrode 125 of the light-emitting element 120 are exposed from the third planarization layer 115c, but the third planarization layer 115c is partially disposed in the region between the first electrode 124 and the second electrode 125, short-circuit defects can be reduced. The second planarization layer 115b and the third planarization layer 115c may be composed of a single layer or multiple layers, and may be made of, for example, photoresist or acrylic-based organic materials, but are not limited thereto.

[0157] The first connecting electrode CE1 and the second connecting electrode CE2 are disposed on the third planarization layer 115c.

[0158] The first connection electrode CE1 is an electrode that electrically connects the first electrode 124 of the light-emitting element 120 to the driving transistor DT. The first connection electrode CE1 can be electrically connected to the first reflective electrode RE1 through contact holes formed in the third planarization layer 115c, the second planarization layer 115b, and the third passivation layer 114c, while simultaneously being electrically connected to the first electrode 124 exposed from the third planarization layer 115c. Therefore, the first electrode 124 and the driving source DSE can be electrically connected through the first connection electrode CE1, the first reflective electrode RE1, and the auxiliary electrode AE.

[0159] The second connecting electrode CE2 is an electrode that electrically connects the second electrode 125 of the light-emitting element 120 and the high-potential power line VDD. The second connecting electrode CE2 can be electrically connected to the second reflective electrode RE2 and the high-potential power line VDD simultaneously with the second electrode 125 exposed from the third planarization layer 115c, and through contact holes formed in the third planarization layer 115c, the second planarization layer 115b, and the third passivation layer 114c. Therefore, the second electrode 125 and the high-potential power line VDD can be electrically connected via the second connecting electrode CE2.

[0160] The first connecting electrode CE1 and the second connecting electrode CE2 may be made of transparent conductive materials such as indium tin oxide (ITO) or indium zinc oxide (IZO), but are not limited to these.

[0161] Meanwhile, in the accompanying drawings, although the driving source DSE of the driving transistor DT and the first electrode 124 of the light-emitting element 120 are shown to be electrically connected, the driving drain DDE of the driving transistor DT and the second electrode 125 of the light-emitting element 120 may also be electrically connected depending on the type of driving transistor DT and the design of the pixel circuit, but the present invention is not limited thereto.

[0162] Next, in the pixel region UPA, a dam BB is disposed on the third planarization layer 115c, the first connecting electrode CE1, and the second connecting electrode CE2. The dam BB can be disposed at a certain interval from the light-emitting element 120. The dam BB can be disposed at the boundary between multiple sub-pixels SP and can cover portions of the first connecting electrode CE1 and the second connecting electrode CE2. The dam BB can be spaced apart from the transmissive region TA. The dam BB can be made of an opaque material (e.g., black resin) to reduce color mixing between multiple sub-pixels SP, but is not limited thereto.

[0163] A protective layer 116 is disposed on the first connecting electrode CE1, the second connecting electrode CE2, and the embankment BB. The protective layer 116 is a layer used to protect the structure located below it. The protective layer 116 may be composed of a single layer or multiple layers, and may be made of, but is not limited to, benzocyclobutene, transparent epoxy resin, photoresist, acrylic organic materials, or inorganic materials such as silicon oxide (SiOx) or silicon nitride (SiNx).

[0164] Simultaneously, multiple sub-pixels SP can be configured to overlap with multiple lines to ensure the area of ​​the transmissive region TA. In this case, drive current fluctuations may occur in each of the multiple sub-pixels SP due to some lines. For example, the drive transistor DT and storage capacitor Cst of each of the multiple sub-pixels SP can be connected to the data line DL by overlapping with the data line DL. In this case, the voltage of the drive gate DGE may fluctuate due to the data line DL, which applies different voltages for each frame. The drive current flowing to the light-emitting element 120 may fluctuate simultaneously with the voltage fluctuation of the drive gate DGE, and brightness variations may occur due to crosstalk, thus degrading the display quality.

[0165] Therefore, in a display device 100 according to an embodiment of the present invention, considering the dielectric constant of the insulating layer disposed between the storage capacitor Cst and the driving transistor DT and the data line DL, the voltage fluctuation of the driving gate DGE caused by the data line DL can be reduced by adjusting the thickness of the insulating layer. For example, an inorganic insulating film disposed on the substrate 110 with a thickness of several thousand angstroms (Å) can be formed, i.e., an insulating layer such as a buffer layer 111, a gate insulating layer 112, a first interlayer insulating layer 113a, and a second passivation layer 114b. However, since the first passivation layer 114a and the second interlayer insulating layer 113b, which are insulating layers disposed between the data line DL and the storage capacitor Cst, are formed with a thickness of at least several micrometers (μm) different from other insulating layers, the voltage fluctuation of the driving transistor DT caused by the data line DL can be minimized. Therefore, the thickness of the insulating layer between the data line DL and the storage capacitor Cst can be thicker than each of the thicknesses of the buffer layer 111, the gate insulating layer 112, the first interlayer insulating layer 113a, and the second passivation layer 114b.

[0166] Figure 13 This is a pixel circuit diagram of a display device according to an embodiment of the present invention.

[0167] Reference Figure 13 The pixel circuits of the main sub-pixel MSP and the pixel circuits of the redundant sub-pixel SSP can share the first transistor T1.

[0168] The pixel circuit of the master sub-pixel (MSP) includes a light-emitting element 120, a driving transistor DT for driving the light-emitting element 120, a first transistor T1, a second transistor T2, and a capacitor Cst. Transistors DT, T1, and T2 may be implemented as p-type transistors, but are not limited thereto.

[0169] The pixel circuit is connected to a constant voltage node that is subjected to a DC voltage (or a constant voltage), such as the data line DL that is subjected to the data voltage Data, the scan line that is subjected to the gate signal Scan, the VDD node that is subjected to the pixel drive voltage (EVDD), and the VSS node that is subjected to the pixel base voltage (EVSS). The constant voltage node is connected to the power lines provided on the display panel PN, and the power lines can be connected to all sub-pixels together.

[0170] The driving transistor DT includes a first electrode connected to a first node n1, a gate connected to a second node n2, and a second electrode connected to a VSS node. The light-emitting element 120 includes an anode connected to a VDD node and a cathode connected to the first node n1. The light-emitting element 120 may be a microLED, but is not limited thereto. A capacitor Cst is connected between the first node n1 and the second node n2 to charge the gate-source voltage of the driving transistor DT.

[0171] A first transistor T1 is connected between the data line DL, to which the data voltage Data is applied, and the second node n2, and is turned on in response to the gate turn-on voltage of the gate signal Scan. When the first transistor T1 is turned on, the data voltage is applied to the second node n2. The first transistor T1 includes a first electrode connected to the data line DL, a second electrode connected to the second node n2, and a gate connected to the scan line SL to which the gate signal Scan is applied. The first transistor T1 can be implemented as a dual-gate structure, wherein the two transistors are connected in series to reduce leakage current.

[0172] In this scenario, since the driving transistor DT of the redundant sub-pixel SSP is also connected to the second node n2, the data voltage can be simultaneously applied to the gate of the driving transistor DT of the main sub-pixel MSP and the gate of the driving transistor DT of the redundant sub-pixel SSP. According to the embodiment, since the main sub-pixel MSP and the redundant sub-pixel SSP share the first transistor T1, the light transmittance can be increased by reducing the number of transistors.

[0173] The second transistor T2 is connected between the sensing line RL1, to which the reference voltage Ref is applied, and the first node n1, and is turned on in response to the gate turn-on voltage of the gate signal Scan. When the second transistor T2 is turned on, the first node n1 is electrically connected to the sensing line RL1. The second transistor T2 includes a first electrode connected to the first node n1, a second electrode connected to the sensing line RL1, and a gate connected to the scan line SL to which the gate signal Scan is applied.

[0174] Sensing line RL1 can be connected to the sensing channel of data driver DD. The analog-to-digital converter (ADC) of the sensing channel can be connected to the compensation circuit of timing controller TC. The external compensation circuit includes: an ADC connected to the sensing line; and compensation circuitry that modulates pixel data using a compensation value selected based on digital data input from the ADC. The current or voltage sensed by sensing line RL1 is converted into digital data by the ADC and input to the compensation circuitry of timing controller TC. By sensing the electrical characteristics (e.g., threshold voltage and mobility) of the driving transistor DT, which serves as the driving element of light-emitting element 120, in each sub-pixel via sensing line RL1 and modulating the pixel data (digital data) of the input image using the deviation (or change) of the electrical characteristics of the driving transistor DT, the external compensation circuitry can compensate for the deviation (or change) of the electrical characteristics of the driving transistor DT in each pixel in real time.

[0175] Figure 14 This is a pixel circuit diagram of a display device according to another embodiment of the present invention. Figure 15 This is an enlarged plan view of the display area of ​​a display device according to another embodiment of the present invention.

[0176] Reference Figure 14 The pixel circuits of the main sub-pixel MSP and the redundant sub-pixel SSP can each have a first transistor T1. Therefore, the first transistor T1 of the main sub-pixel MSP and the first transistor T1 of the redundant sub-pixel SSP can be turned on simultaneously in response to the gate signal Scan. The first transistor T1 of the main sub-pixel MSP can apply a data voltage to the gate of the driving transistor DT of the main sub-pixel MSP, and the first transistor T1 of the redundant sub-pixel SSP can apply a data voltage to the gate of the driving transistor DT of the redundant sub-pixel SSP.

[0177] Reference Figure 15 The implementation method is similar to that described above. Figure 3 In one implementation, multiple sub-pixels are arranged in the second direction, but the difference is that the main sub-pixel MSP and the redundant sub-pixel SSP are not alternately arranged.

[0178] The scan line may include a first scan line SL1 extending in a first direction and a second scan line SL2 branching from the first scan line SL1. The second scan line SL2 may have a shorter length than the first scan line SL1 in the first direction.

[0179] The primary sub-pixel (MSP) can be set on one side of the first scan line SL1. The primary sub-pixel (MSP) can be set between the first scan line SL1 and the second scan line SL2. The primary sub-pixels (MSPs) can be set in the order of the first primary sub-pixel (MSP1), the second primary sub-pixel (MSP2), and the third primary sub-pixel (MSP3).

[0180] The redundant sub-pixel SSP can be set on the other side of the first scan line SL1. The redundant sub-pixel SSP can be set in the order of the first redundant sub-pixel SSP1, the second redundant sub-pixel SSP2, and the third redundant sub-pixel SSP3.

[0181] The first transistor T1, configured to overlap with the second scan line SL2, can apply data voltage to the first main sub-pixel MSP1, the second main sub-pixel MSP2, and the third main sub-pixel MSP3. The bold arrows indicate the direction of data voltage application or current flow.

[0182] The first transistor T1, which is configured to overlap with the first scan line SL1, can apply data voltage to the first redundant sub-pixel SSP1, the second redundant sub-pixel SSP2, and the third redundant sub-pixel SSP3. The bold arrows indicate the direction of data signal transmission or current flow.

[0183] Figure 16 This is a pixel circuit diagram of a display device according to another embodiment of the present invention. Figure 17 This is an enlarged plan view of the display area of ​​a display device according to another embodiment of the present invention.

[0184] Reference Figure 16 Because the pixel circuits of the main sub-pixel and the pixel circuits of the redundant sub-pixel are not only set to face each other, but also... Figure 14 The circuit structure is the same as that in the previous example, so its detailed description will be omitted.

[0185] Reference Figure 17 The principal sub-pixels and redundant sub-pixels can be set symmetrically to each other based on the scan line. For example, based on the scan line SL, the principal sub-pixels can be set as first principal sub-pixel MSP1, second principal sub-pixel MSP2, and third principal sub-pixel MSP3 in the direction away from the scan line SL, and the redundant sub-pixels can be set as first redundant sub-pixel SSP1, second redundant sub-pixel SSP2, and third redundant sub-pixel SSP3 in the direction away from the scan line SL.

[0186] Multiple first transistors T1 can be disposed between the primary sub-pixel MSP and the redundant sub-pixel SSP. Among the multiple first transistors T1, some can apply data signals to the primary sub-pixel MSP, and some can apply data signals to the redundant sub-pixel SSP. In this structure, since the primary sub-pixel MSP1 and the first redundant sub-pixel SSP1, which emit light of the same color, are disposed relatively close to each other, while the third primary sub-pixel MSP3 and the third redundant sub-pixel SSP3, which emit light of the same color, are disposed relatively far apart, the spacing between the sub-pixels is uneven. Therefore, image quality and recognizability may be degraded.

[0187] One implementation provides a display device in which image quality is improved by setting sub-pixels of the same color at constant intervals.

[0188] The implementation can maximize the area of ​​the transmissive zone in the display device by configuring the opaque components among the components of the display device to overlap.

[0189] The effects of the present invention are not limited to those illustrated above; various other effects are included in the present invention.

[0190] Although embodiments of the invention have been described in more detail with reference to the accompanying drawings, the invention is not limited to these embodiments, but can be modified in various ways without departing from the spirit of the invention.

[0191] Therefore, the embodiments disclosed herein are not intended to limit the technical spirit of the invention, but rather to describe it, and the scope of the technical spirit of the invention is not limited by these embodiments. Thus, it should be understood that the above embodiments are exemplary and not restrictive in all respects.

Claims

1. A display device, comprising: A substrate, wherein a plurality of pixel regions spaced apart from each other and a plurality of transmissive regions disposed between the plurality of pixel regions are defined therein; A scan line extending along a first direction on the substrate; as well as Multiple data lines extend on the substrate along a second direction intersecting the first direction. Each of the plurality of pixel regions comprises a plurality of sub-pixels. Each of the plurality of sub-pixels includes: a first principal sub-pixel and a first redundant sub-pixel for outputting a first light; a second principal sub-pixel and a second redundant sub-pixel for outputting a second light; and a third principal sub-pixel and a third redundant sub-pixel for outputting a third light. The first principal sub-pixel, the first redundant sub-pixel, the second principal sub-pixel, the second redundant sub-pixel, the third principal sub-pixel, and the third redundant sub-pixel are sequentially arranged in the first direction or the second direction.

2. The display device according to claim 1, wherein the first light is light within the red wavelength range. The second light is light within the green wavelength range. The third light is light within the blue wavelength range.

3. The display device according to claim 1, wherein the interval between the first primary sub-pixel and the first redundant sub-pixel is the same as the interval between the second primary sub-pixel and the second redundant sub-pixel.

4. The display device according to claim 1, wherein the first primary sub-pixel and the first redundant sub-pixel share a first transistor connected to the data line. The second primary sub-pixel and the second redundant sub-pixel share a first transistor connected to the data line. The third primary sub-pixel and the third redundant sub-pixel share a first transistor connected to the data line.

5. The display device according to claim 4, further comprising a sub-scan line extending from the scan line and parallel to the scan line in the first direction. The first active layer of the first transistor extends in the second direction and overlaps with the scan line and the sub-scan line.

6. The display device according to claim 4, wherein each of the plurality of sub-pixels further comprises: A driving transistor is disposed between the plurality of data lines and the substrate and is electrically connected to the first transistor; The second transistor is disposed between the plurality of data lines and the substrate and is electrically connected to the driving transistor; A storage capacitor is disposed between the plurality of data lines and the driving transistor and is electrically connected to the gate of the driving transistor; as well as A light-emitting element is disposed on the plurality of data lines and electrically connected to the driving transistor.

7. The display device according to claim 6, wherein the driving transistors of the plurality of sub-pixels are arranged in a column in the second direction.

8. The display device according to claim 6, wherein the second transistors of the plurality of sub-pixels are arranged in a column in the second direction.

9. The display device according to claim 6, wherein the plurality of data lines are disposed on the driving transistor and the storage capacitor, and overlap with the driving transistor and the storage capacitor.

10. The display device according to claim 6, further comprising a low-potential power line disposed between the storage capacitor, the driving transistor, and the plurality of data lines. The low-potential power line overlaps with the area where the multiple data lines are located.

11. The display device of claim 10, wherein the low-potential power line overlaps with the driving transistor and the storage capacitor.

12. The display device according to claim 10, further comprising a high-potential power line disposed between the light-emitting element and the data line. The high-potential power line overlaps with the area where the multiple data lines are located.

13. The display device according to claim 6, wherein the driving active layer of the driving transistor is connected to the second active layer of the second transistor.

14. The display device of claim 6, wherein the second active layer of the second transistor of the first main sub-pixel, the second active layer of the second transistor of the second main sub-pixel, and the second active layer of the second transistor of the third main sub-pixel are connected to each other.

15. The display device of claim 10, wherein the gate of the first primary sub-pixel and the gate of the first redundant sub-pixel are connected to each other.

16. The display device according to claim 1, wherein the primary sub-pixels and redundant sub-pixels that output light of the same color are arranged adjacent to each other at a constant interval.

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