Deep learning based dtco cross-layer performance matching method and related products

Abstract

This application discloses a deep learning-based DTCO cross-layer performance matching method and related products, applicable to the semiconductor technology field. The method includes: obtaining target electrical performance indicators of the target bottom-layer bulk silicon device; performing a logarithmic transformation on the off-state leakage current in the target electrical performance indicators, then normalizing the target electrical performance indicators to obtain target feature data; inputting the target feature data into a target matching model to obtain target process parameters corresponding to the target top-layer low-temperature SOI device; the target matching model is a four-layer fully connected feedforward neural network with inverse mapping capability from electrical performance to process parameters. Thus, by introducing a four-layer fully connected feedforward neural network, accurate inverse mapping from electrical performance to process parameters is achieved, effectively shortening the design cycle and improving design efficiency while ensuring device electrical compatibility.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a deep learning-based DTCO cross-layer performance matching method and related products. Background Technology

[0002] With the continuous development of three-dimensional sequential integration technology, the heterogeneous stacking of bottom bulk silicon devices and top low-temperature silicon-on-insulator (SOI) devices has become the mainstream architecture for high-density integrated chips. Precise matching of the electrical performance of the two types of devices is the key to ensuring the stability and performance of the overall circuit.

[0003] Current mainstream matching methods rely on a combination of technology computer-aided design (TCAD) simulation and manual debugging. This involves repeatedly adjusting process parameters based on design experience and conducting multiple simulations to compare performance errors, resulting in drawbacks such as numerous iterations, long simulation cycles, and low R&D efficiency. Furthermore, this matching method struggles to achieve high-dimensional optimization of multiple parameters, is prone to getting trapped in local optima, cannot simultaneously achieve precise matching of multiple electrical indicators, and is difficult to form a Design-Technology Co-Optimization (DTCO) closed loop. Consequently, it fails to improve design efficiency while ensuring device electrical compatibility.

[0004] Therefore, how to improve design efficiency while ensuring the electrical compatibility of devices is a problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0005] To address the aforementioned issues, this application provides a deep learning-based DTCO cross-layer performance matching method and related products. By introducing a four-layer fully connected feedforward neural network, it achieves accurate inverse mapping from electrical performance to process parameters, effectively shortening the design cycle and improving design efficiency while ensuring the electrical compatibility of the device.

[0006] In a first aspect, embodiments of this application provide a deep learning-based DTCO cross-layer performance matching method, applied to the matching of bottom-layer bulk silicon devices and top-layer low-temperature SOI devices in three-dimensional sequential integration, including: Obtain the target electrical performance parameters of the target underlying bulk silicon device; the target electrical performance parameters include saturation drive current, off-state leakage current, saturation threshold voltage, subthreshold swing, maximum transconductance in the range of 0 to 1.2V, maximum gate capacitance, and average integral capacitance in the range of 0 to 1.2V. Logarithmically transform the leakage current in the off state and normalize the target electrical performance index to obtain target characteristic data; The target feature data is input into the target matching model to obtain the target process parameters corresponding to the target top-layer low-temperature SOI device; the target process parameters include silicon film thickness, equivalent oxide layer thickness, gate work function, and gate width; the target matching model is a four-layer fully connected feedforward neural network with the ability to reverse map electrical performance to process parameters.

[0007] Optionally, the method further includes: The target process parameters are input into the target TCAD model, and the corresponding simulated electrical performance indicators are obtained; Determine the absolute relative error between the simulated electrical performance index and the target electrical performance index; Combining the first preset stopping condition, the target process parameters are iteratively optimized based on the absolute and relative errors to form a closed-loop DTCO optimization.

[0008] Optionally, the method further includes: Based on the target process parameters, a first integrated circuit simulation program (SPICE) model corresponding to the target top-level low-temperature SOI device is extracted; Determine the second SPICE model corresponding to the target underlying bulk silicon device; A test circuit for a complementary metal-oxide-semiconductor (CMOS) inverter was built based on the first SPICE model and the second SPICE model. The simulation was performed based on the CMOS inverter test circuit, and the target simulation results were obtained.

[0009] Optionally, the target matching model is trained using the following method: Construct a simulation dataset; the simulation dataset includes training process parameters and corresponding training electrical performance indicators; The simulation dataset is preprocessed to obtain feature data for training. Construct an initial matching model consisting of a four-layer fully connected feedforward neural network; Combining the second preset stopping condition and the training feature data, the mean squared error is used as the loss function, and the initial matching model is trained using the Adaptive Moment Estimation (Adam) optimizer to obtain the target matching model.

[0010] Optionally, the construction of the simulation dataset includes: An initial TCAD model was constructed based on experimental data corresponding to the experimental top-level low-temperature SOI device. The simulated electrical characteristics of the experimental top-level low-temperature SOI device were determined based on the initial TCAD model. Based on the first threshold, the initial TCAD model is calibrated according to the actual electrical characteristics and the simulated electrical characteristics to obtain a calibrated TCAD model; Determine the process parameters for training based on the preset value range; The training process parameters are input into the calibration TCAD model to obtain the training electrical performance indicators; A simulation dataset is constructed based on the training process parameters and the training electrical performance indicators.

[0011] Optionally, the four-layer fully connected feedforward neural network includes a first hidden layer, a second hidden layer, a third hidden layer, and an output layer; The first hidden layer contains 64 nodes, the second hidden layer contains 128 nodes, the third hidden layer contains 64 nodes, and the output layer contains 4 nodes.

[0012] Optionally, the method further includes: Based on the simulation dataset, the training power consumption performance index is input into the target matching model to obtain the corresponding predicted process parameters; Determine the coefficient of determination between the predicted process parameters and the corresponding training process parameters; The determination coefficient is compared with the preset qualified judgment threshold, and the inverse mapping capability of the target matching model is determined based on the comparison result.

[0013] Secondly, embodiments of this application provide a deep learning-based DTCO cross-layer performance matching device, which is applied to the matching of bottom-layer bulk silicon devices and top-layer low-temperature SOI devices in three-dimensional sequential integration, including: The acquisition module is used to acquire the target electrical performance indicators of the target underlying bulk silicon device; the target electrical performance indicators include saturation drive current, off-state leakage current, saturation threshold voltage, subthreshold swing, maximum transconductance in the range of 0 to 1.2V, maximum gate capacitance, and average integral capacitance in the range of 0 to 1.2V. The preprocessing module is used to perform logarithmic transformation on the leakage current in the off state and normalize the target electrical performance index to obtain target feature data. The prediction module is used to input the target feature data into the target matching model and obtain the target process parameters corresponding to the target top-layer low-temperature SOI device; the target process parameters include silicon film thickness, equivalent oxide layer thickness, gate work function and gate width; the target matching model is a four-layer fully connected feedforward neural network with the ability to inversely map electrical performance to process parameters.

[0014] Thirdly, embodiments of this application provide a deep learning-based DTCO cross-layer performance matching device, comprising: Memory, used to store computer programs; A processor, used to implement the steps of the deep learning-based DTCO cross-layer performance matching method as described above when executing the computer program.

[0015] Fourthly, embodiments of this application provide a readable storage medium storing a computer program, which, when executed by a processor, implements the steps of the deep learning-based DTCO cross-layer performance matching method described above.

[0016] As can be seen from the above technical solutions, compared with the prior art, this application has the following advantages: This application provides a deep learning-based DTCO cross-layer performance matching method, applicable to matching bottom-layer bulk silicon devices and top-layer low-temperature SOI devices in three-dimensional sequential integration. First, the target electrical performance indicators of the target bottom-layer bulk silicon device are obtained. These indicators include saturation drive current, off-state leakage current, saturation threshold voltage, subthreshold swing, maximum transconductance in the 0-1.2V range, maximum gate capacitance, and average integral capacitance in the 0-1.2V range. Then, the off-state leakage current is logarithmically transformed, and the target electrical performance indicators are normalized to obtain target feature data. Finally, the target feature data is input into the target matching model to obtain the target process parameters corresponding to the target top-layer low-temperature SOI device. These process parameters include silicon film thickness, equivalent oxide thickness, gate work function, and gate width. The target matching model is a four-layer fully connected feedforward neural network with inverse mapping capability from electrical performance to process parameters. Thus, by introducing a four-layer fully connected feedforward neural network, accurate inverse mapping from electrical performance to process parameters is achieved, effectively shortening the design cycle and improving design efficiency while ensuring device electrical compatibility. Attached Figure Description

[0017] Figure 1 A flowchart illustrating a deep learning-based DTCO cross-layer performance matching method is provided for embodiments of this application. Figure 2 A schematic diagram showing a comparison of electrical characteristic curves of a device provided in an embodiment of this application; Figure 3 A schematic diagram of a target simulation result provided in an embodiment of this application; Figure 4 A schematic diagram illustrating a training method for a target matching model provided in an embodiment of this application; Figure 5 A schematic diagram of a four-layer fully connected feedforward neural network provided in an embodiment of this application; Figure 6 This is a schematic diagram illustrating the change in loss of a model during training and validation under different training cycles, as provided in an embodiment of this application. Figure 7 A schematic diagram of a determination coefficient provided for an embodiment of this application; Figure 8 This is a schematic diagram of a deep learning-based DTCO cross-layer performance matching device provided in an embodiment of this application. Detailed Implementation

[0018] As mentioned earlier, existing matching methods cannot improve design efficiency while ensuring device electrical compatibility. Specifically, current mainstream matching methods rely on TCAD simulation combined with manual debugging. This involves repeatedly adjusting process parameters based on design experience and comparing performance errors through multiple simulations, resulting in numerous iterations, long simulation cycles, and low development efficiency. Furthermore, this matching method struggles to achieve high-dimensional optimization of multiple parameters, is prone to getting trapped in local optima, cannot simultaneously achieve precise matching of multiple electrical indicators, and is difficult to form a DTCO closed loop. Consequently, it fails to improve design efficiency while ensuring device electrical compatibility.

[0019] To address the aforementioned issues, this application provides a deep learning-based DTCO cross-layer performance matching method. This method can be applied to matching the bottom-layer bulk silicon device and the top-layer low-temperature SOI device in three-dimensional sequential integration. The method includes: first, obtaining the target electrical performance indicators of the target bottom-layer bulk silicon device. These indicators include saturation drive current, off-state leakage current, saturation threshold voltage, subthreshold swing, maximum transconductance in the 0-1.2V range, maximum gate capacitance, and average integral capacitance in the 0-1.2V range. Then, a logarithmic transformation is performed on the off-state leakage current, and the target electrical performance indicators are normalized to obtain target feature data. Finally, the target feature data is input into the target matching model to obtain the target process parameters corresponding to the target top-layer low-temperature SOI device. These process parameters include silicon film thickness, equivalent oxide layer thickness, gate work function, and gate width. The target matching model is a four-layer fully connected feedforward neural network with the ability to inversely map electrical performance to process parameters.

[0020] Thus, by introducing a four-layer fully connected feedforward neural network, the precise inverse mapping from electrical performance to process parameters is completed, effectively shortening the design cycle and improving design efficiency while ensuring the electrical compatibility of the device.

[0021] It should be noted that the deep learning-based DTCO cross-layer performance matching method and related products provided in this application can be applied to the field of semiconductor technology. The above are merely examples and do not limit the application areas of the deep learning-based DTCO cross-layer performance matching method and related products provided in this application.

[0022] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0023] Figure 1 A flowchart illustrating a deep learning-based DTCO cross-layer performance matching method provided in this application embodiment. (Combined with...) Figure 1 As shown in the embodiments of this application, a deep learning-based DTCO cross-layer performance matching method may include: S101: Obtain the target electrical performance indicators of the target underlying bulk silicon device; the target electrical performance indicators include saturation drive current, off-state leakage current, saturation threshold voltage, subthreshold swing, maximum transconductance in the range of 0 to 1.2V, maximum gate capacitance, and average integral capacitance in the range of 0 to 1.2V.

[0024] In practical applications, three-dimensional sequential integration requires fabricating the bottom-layer bulk silicon device first, followed by the top-layer low-temperature SOI device. The first obtained bottom-layer bulk silicon device can be called the target bottom-layer bulk silicon device, and its corresponding top-layer low-temperature SOI device can be called the target top-layer low-temperature SOI device. To achieve electrical performance matching between the target top-layer low-temperature SOI device and the target bottom-layer bulk silicon device, it is first necessary to obtain the target electrical performance indicators of the target bottom-layer bulk silicon device, and then perform inverse mapping of process parameters through an introduced target matching model. Specifically, the target electrical performance indicators of the target bottom-layer bulk silicon device include the saturation drive current Is. dsat Leakage current I in the off state doff Saturation threshold voltage V tsat Subthreshold swing SS sat Maximum transconductance G in the range of 0 to 1.2V mmax Maximum gate capacitance C ggmax and the average integrating capacitance C in the range of 0 to 1.2V.integ Seven key indicators. Furthermore, the target electrical performance indicators can be obtained through simulation calculations using the target TCAD model or through actual measurements. The target TCAD model is calibrated to ensure that the error of the above seven key indicators is less than 5%.

[0025] S102: Perform logarithmic transformation on the leakage current in the off state and normalize the target electrical performance index to obtain target characteristic data.

[0026] In practical applications, the simulated values ​​of leakage current in the off-state range widely, typically from 1.16 × 10⁻⁶. -13 A to 1.90×10 -10 A. The numerical dynamic range shows significant differences. Therefore, it is necessary to first perform a logarithmic transformation on the off-state leakage current in the obtained target electrical performance indicators to narrow its numerical distribution range. Then, based on the compressed numerical range after transformation, and combined with the simulated value ranges of the other target electrical performance indicators, a unified minimum-maximum (Min-Max) normalization process is completed for all indicators, finally obtaining the target characteristic data corresponding to each target electrical performance indicator. In addition, the simulated value range of the saturation drive current is usually 2.41 × 10⁻⁶. -5 A-1.55×10 -4 A. The simulated range of the saturation threshold voltage is typically 0.25V-0.51V, the simulated range of the subthreshold swing is typically 65.83mV / dec-138.52mV / dec, and the simulated range of the maximum transconductance in the 0 to 1.2V range is typically 5.53×10⁻⁶. -5 S-2.75×10 -4 The simulated value for the maximum gate capacitance, S, is typically in the range of 4.61 × 10⁻⁶. -16 F-1.13×10 -15 The simulated value for the average integrating capacitance, F, in the range of 0 to 1.2V, is typically 2.82 × 10⁻⁶. -16 F-8.05×10 -16 F.

[0027] S103: Input the target feature data into the target matching model and obtain the target process parameters corresponding to the target top-level low-temperature SOI device; the target process parameters include silicon film thickness, equivalent oxide layer thickness, gate work function and gate width; the target matching model is a four-layer fully connected feedforward neural network with the ability to reverse map electrical performance to process parameters.

[0028] In practical applications, this application introduces a target matching model. This model employs a four-layer fully connected feedforward neural network structure, capable of accurately determining the corresponding target process parameters based on the given electrical performance indicators of the target top-layer low-temperature SOI device. In other words, it possesses the inverse mapping capability of deriving corresponding process parameters from device electrical performance indicators. Since the core requirement of cross-layer performance matching in this application is to ensure that the electrical performance indicators of the target top-layer low-temperature SOI device are consistent with those of the target bottom-layer bulk silicon device, the processed target feature data of the target bottom-layer bulk silicon device can be used as model input, imported into the trained target matching model, and then the model accurately derives and outputs the target process parameters adapted to the target top-layer low-temperature SOI device within milliseconds. Specifically, the target process parameters include the silicon film thickness T. si Equivalent oxide layer thickness T ox Gate work function WF and gate width W g Four core process parameters.

[0029] Furthermore, since there are different ways to form a closed-loop DTCO optimization, this application embodiment can describe one possible formation method.

[0030] In one instance, the method further includes: The target process parameters are input into the target TCAD model, and the corresponding simulated electrical performance indicators are obtained; Determine the absolute relative error between the simulated electrical performance index and the target electrical performance index; Combining the first preset stopping condition, the target process parameters are iteratively optimized based on the absolute and relative errors to form a closed-loop DTCO optimization.

[0031] In practical applications, the predicted target process parameters can be input into the target TCAD model to extract the corresponding simulated electrical performance indicators. It's understandable that the simulated electrical performance indicators also include seven key indicators: saturation drive current, turn-off leakage current, saturation threshold voltage, subthreshold swing, maximum transconductance in the 0-1.2V range, maximum gate capacitance, and average integral capacitance in the 0-1.2V range. However, there may be some numerical differences between these seven key indicators and those corresponding to the target electrical performance indicators. Furthermore, the absolute relative error (ARE) is calculated by comparing the simulated and target electrical performance indicators. The corresponding expression is as follows: ; In the formula These are the electrical characteristic parameters of an N-type metal-oxide-semiconductor (NMOS) device, i.e., the simulated electrical performance indicators corresponding to the target top-layer low-temperature SOI device. These are the electrical characteristic parameters of a P-type metal-oxide-semiconductor (PMOS) device, i.e., the target electrical performance indicators corresponding to the target underlying bulk silicon device. It is understood that the target underlying bulk silicon device in the embodiments of this application can be a 55-nanometer bulk silicon PMOS. Figure 2 This is a schematic diagram comparing the electrical characteristic curves of a device provided in an embodiment of this application. (Combined with...) Figure 2 As shown, taking one possible scenario as an example, the red line corresponds to the target bottom-layer bulk silicon device, and the blue line corresponds to the target top-layer low-temperature SOI device, with an absolute value of |V. gs |, the absolute value of the drain-source current is |I ds |, the absolute value of the total gate capacitance is |C gg | Figure 2 The two dashed lines in 'a' are drawn using logarithmic coordinates, which allows us to obtain the saturation drive current, turn-off leakage current, saturation threshold voltage, subthreshold swing, maximum transconductance in the 0 to 1.2V range, maximum gate capacitance, and average integral capacitance in the 0 to 1.2V range, which are respectively 3.01 × 10⁻⁶. -5 A, 1.12×10 -12 A, 0.4044V, 71.03mV / dec, 6.15×10 -5 S, 4.98×10 -16 F and 3.59×10 -16 F; The simulated electrical performance parameters corresponding to the saturation drive current, turn-off leakage current, saturation threshold voltage, subthreshold swing, maximum transconductance in the 0 to 1.2V range, maximum gate capacitance, and average integral capacitance in the 0 to 1.2V range are 3.03 × 10⁻⁶. -5 A, 1.24 × 10 -12 A. 0.4044V, 70.91mV / dec, 6.09×10 -5 S, 5.09×10 -16 F and 3.68×10 -16F. Combining the expressions corresponding to ARE above, the AREs for each indicator are 0.66%, 10.71%, 0, 0.17%, 0.98%, 2.21%, and 2.51%, respectively. Among them, the AREs of most key indicators are less than 3%, with the absolute relative error of the saturation threshold voltage being 0. The absolute relative error of the turn-off leakage current is 10.71%, which is still within an acceptable range due to its exponential sensitivity. If the verification results meet the first preset stopping condition (e.g., ARE < 10% for all indicators), the final process parameters are output; if not, the verification sample (this set of data) is added to the training set, triggering incremental learning of the target matching model and iteratively optimizing the target process parameters, thereby forming a closed-loop DTCO optimization. It can be understood that the saturation drive current, turn-off leakage current, saturation threshold voltage, subthreshold swing, and maximum transconductance in the range of 0 to 1.2V can be obtained through the drain-source current-gate-source voltage curve ( Figure 2 a) is determined. Specifically, I dsat Take V gs I at =1.2V ds I doff Take V gs I at =0V ds V tsat Take I ds V when =100 nA gs SS sat Take V gs =V tsat The slope extracted at -0.15V, G mmax This is the maximum value obtained after differentiating the linearly scaled drain-source current versus gate-source voltage curve. V gs I is the gate-source voltage. ds This is the drain-source current. The maximum gate capacitance and the average integrated capacitance over the range of 0 to 1.2V can be obtained from the total gate capacitance-gate-source voltage curve (…). Figure 2 b) is determined. Specifically, C ggmax Take V gs C at 1.2V gg C integ Take the total gate capacitance-gate source voltage curve at V gs =Integrate over the range of 0V to 1.2V and then divide by the value of the voltage range. C gg This represents the total gate capacitance.

[0032] Furthermore, since simulation verification methods are not entirely the same, this application embodiment can describe one possible simulation verification method.

[0033] In one instance, the method further includes: Based on the target process parameters, a first SPICE model corresponding to the target top-level low-temperature SOI device is extracted; Determine the second SPICE model corresponding to the target underlying bulk silicon device; A CMOS inverter test circuit was built based on the first SPICE model and the second SPICE model. The simulation was performed based on the CMOS inverter test circuit, and the target simulation results were obtained.

[0034] In practical applications, the predicted target process parameters can also be verified at the circuit level. Specifically, firstly, based on the predicted target process parameters, the Berkeley Short-channel Insulated Gate Field-effect Transistor Model-Independent Multi-Gate (BSIM-IMG) is used to extract the first SPICE model corresponding to the target top-layer low-temperature SOI device. Then, based on the process parameters corresponding to the target bottom-layer bulk silicon device, the Berkeley Short-channel Insulated Gate Field-effect Transistor Model 4 (BSIM4) is used to determine the second SPICE model corresponding to the target bottom-layer bulk silicon device. The process parameters corresponding to the target bottom-layer bulk silicon device can be obtained through experimental measurement. Furthermore, a CMOS inverter test circuit is built using the obtained first and second SPICE models, and circuit-level simulation verification is performed to obtain the target simulation results. Figure 3 This is a schematic diagram illustrating a target simulation result provided in an embodiment of this application. (In conjunction with...) Figure 3 As shown, taking one possible scenario as an example, the input voltage is V. in (and Figure 3 (corresponding to the red line in the image), the output voltage is V. out (and Figure 3 (Corresponding to the blue line in the image), the target simulation result obtained when the input voltage increases shows the inverter switching threshold voltage V. m The voltage is 0.5988V, close to the ideal value of 0.6V; the high-level noise margin is NM. H 0.5428V, low-level noise margin NM L The voltage is 0.5372V, both of which are sufficiently large and symmetrical (e.g., Figure 3 (As shown in a). Over time, the low-level to high-level transmission delay t... plh =0.5783µs, high-level to low-level transmission delay tphl =0.5744µs, rise / fall delay is well matched (e.g. Figure 3 (as shown in b in the text).

[0035] Figure 4 This is a schematic diagram illustrating a training method for a target matching model provided in an embodiment of this application. (Combined with...) Figure 4 As shown in the embodiments of this application, a method for training a target matching model may include: S401: Construct a simulation dataset; the simulation dataset includes training process parameters and training electrical performance indicators corresponding to the training process parameters.

[0036] In practical applications, a simulation dataset is first constructed. This dataset contains numerous sample pairs, each containing corresponding training process parameters and training electrical performance indicators. Understandably, the training process parameters also need to include four core process parameters: silicon film thickness, equivalent oxide thickness, gate work function, and gate width. Similarly, the training electrical performance indicators need to include seven key indicators: saturation drive current, turn-off leakage current, saturation threshold voltage, subthreshold swing, maximum transconductance in the 0-1.2V range, maximum gate capacitance, and average integral capacitance in the 0-1.2V range. However, these may differ slightly in value from the seven key indicators corresponding to the target electrical performance indicators.

[0037] Furthermore, since there are different ways to construct simulation datasets, this application embodiment can describe one possible construction method.

[0038] In one instance, constructing the simulation dataset includes: An initial TCAD model was constructed based on experimental data corresponding to the experimental top-level low-temperature SOI device. The simulated electrical characteristics of the experimental top-level low-temperature SOI device were determined based on the initial TCAD model. Based on the first threshold, the initial TCAD model is calibrated according to the actual electrical characteristics and the simulated electrical characteristics to obtain a calibrated TCAD model; Determine the process parameters for training based on the preset value range; The training process parameters are input into the calibration TCAD model to obtain the training electrical performance indicators; A simulation dataset is constructed based on the training process parameters and the training electrical performance indicators.

[0039] In practical applications, the first step is to establish an initial TCAD model of the experimental top-layer low-temperature SOI device based on experimental data (including the four core process parameters mentioned above), and determine the simulated electrical characteristics (driving current, threshold voltage, subthreshold swing, and other key indicators) of the experimental top-layer low-temperature SOI device. Understandably, due to model errors, the simulated electrical characteristics will differ from the actual electrical characteristics obtained from the measured measurements of the experimental top-layer low-temperature SOI device. Therefore, the initial TCAD model can be calibrated based on the actual and simulated electrical characteristics, using a first threshold (e.g., key indicator error below 5%), to obtain a calibrated TCAD model. It is understood that the calibrated TCAD model is also calibrated to ensure that the key indicator error is below 5%, and can be considered the same TCAD model as the target TCAD model. Then, random sampling is performed on the four core process parameters—silicon film thickness, equivalent oxide layer thickness, gate work function, and gate width—within their respective preset value ranges, generating 2000 sets of parameter combinations, thus obtaining 2000 sets of training process parameters. The silicon film thickness ranges from 6nm to 8nm, the equivalent oxide layer thickness ranges from 1.5nm to 3.5nm, the gate work function ranges from 4.4eV to 4.6eV, and the gate width ranges from 150nm to 350nm. Then, based on the calibrated TCAD model, TCAD simulations are run for each set of parameters to extract seven key indicators: saturation drive current, turn-off leakage current, saturation threshold voltage, subthreshold swing, maximum transconductance in the 0-1.2V range, maximum gate capacitance, and average integral capacitance in the 0-1.2V range. These are the training power performance indicators corresponding to the training process parameters. Finally, the training power performance indicators are combined with the corresponding training process parameters to obtain a simulation dataset containing 2000 sample pairs.

[0040] S402: Preprocess the simulation dataset to obtain training feature data.

[0041] In practical applications, the simulated values ​​of leakage current in the off-state range widely, typically from 1.16 × 10⁻⁶. -13 A to 1.90×10 -10A. The numerical dynamic ranges show significant differences. Therefore, it is necessary to first perform a logarithmic transformation on the off-state leakage current in the obtained simulation dataset to narrow its numerical distribution range. Then, based on the compressed numerical range after transformation, and combined with the simulation value ranges of other key indicators and core process parameters, a unified Min-Max normalization process is completed for the entire dataset, ultimately obtaining the training feature data corresponding to the simulation dataset. Furthermore, the simulation value ranges of each key indicator and core process parameter remain consistent with the above. Further, the training feature data can be divided into training, validation, and test sets at a ratio of 70%, 15%, and 15%, respectively.

[0042] S403: Construct an initial matching model containing a four-layer fully connected feedforward neural network.

[0043] Furthermore, the four-layer fully connected feedforward neural network includes a first hidden layer, a second hidden layer, a third hidden layer, and an output layer; The first hidden layer contains 64 nodes, the second hidden layer contains 128 nodes, the third hidden layer contains 64 nodes, and the output layer contains 4 nodes.

[0044] Figure 5 This is a schematic diagram of a four-layer fully connected feedforward neural network provided in an embodiment of this application. (Combined with...) Figure 5 As shown in the embodiment of this application, an initial matching model comprising a four-layer fully connected feedforward neural network is constructed. This four-layer fully connected feedforward neural network consists of three hidden layers and one output layer. The hidden layers are, in order, a first hidden layer, a second hidden layer, and a third hidden layer. The first hidden layer has 64 nodes, the second hidden layer has 128 nodes, and the third hidden layer has 64 nodes. All three hidden layers use a Rectified Linear Unit (ReLU) as the activation function. The output layer has four nodes, corresponding to T... si T ox WF and W g Four core process parameters were selected, using a linear activation function. Additionally, the input layer comprises seven nodes, each corresponding to I... dsat I doff V tsat SS sat G mmax C ggmax And C integ Seven key performance indicators. It should be noted that because the simulated values ​​of the off-state leakage current vary considerably, the actual input to the input layer is I, obtained by performing a logarithmic transformation of the off-state leakage current to base 10. doff (log) 10The values ​​are then normalized. For the other key indicators, their corresponding normalized values ​​are directly input. The output layer outputs the normalized values ​​corresponding to the four core process parameters, so inverse normalization is required to obtain the predicted values ​​of the process parameters.

[0045] S404: Combining the second preset stopping condition and the training feature data, using the mean squared error as the loss function, the Adam optimizer is used to train the initial matching model and obtain the target matching model.

[0046] In practical applications, Mean Squared Error (MSE) can be used as the loss function, combined with training feature data from the training set, and the Adam optimizer can be used to train the initial matching model with an initial learning rate of 0.001. Training stops when a second preset stopping condition is met, and the target matching model is obtained. The second preset stopping condition can employ an early stopping mechanism (stopping training when the validation set loss does not decrease for 50 consecutive iterations) to prevent overfitting. Figure 6 This diagram illustrates the change in model loss during training and validation under different training cycles, as provided in an embodiment of this application. Figure 6 As shown, the red line represents the validation set loss, and the blue line represents the training set loss. Both the training set loss and the validation set loss change with the iteration cycle, eventually stabilizing at approximately 1×10⁻⁶. -5 .

[0047] Furthermore, since there are different ways to verify whether a model meets the standards, this application embodiment can describe one possible verification method.

[0048] In one instance, the method further includes: Based on the simulation dataset, the training power consumption performance index is input into the target matching model to obtain the corresponding predicted process parameters; Determine the coefficient of determination between the predicted process parameters and the corresponding training process parameters; The determination coefficient is compared with the preset qualified judgment threshold, and the inverse mapping capability of the target matching model is determined based on the comparison result.

[0049] In practical applications, the coefficient of determination R can also be used. 2 As the primary evaluation metric, model performance is evaluated within the test set. Figure 7 This is a schematic diagram of a determination coefficient provided for an embodiment of this application. (In conjunction with...) Figure 7 As shown, the simulation dataset can be further combined with the training power performance indicators to input into the target matching model, and the corresponding predicted process parameters (predicted T) can be obtained. si Predicting Tox Predicting WF and predicting W g The electrical performance indicators for training applications themselves have corresponding process parameters for training (training T). si Training T ox Training WF and training W g Therefore, the coefficient of determination R between the predicted process parameters and their corresponding training process parameters can be determined. 2 Finally, a preset pass / fail threshold is introduced, and the determination coefficient R corresponding to each core process parameter is set. 2 The model is compared with a preset pass / fail threshold, and the inverse mapping capability of the target matching model is determined based on the comparison result to see if it meets the usage requirements. For example, the preset pass / fail threshold could be 0.95, meaning that when the coefficient of determination R... 2 If the value is greater than 0.95, the inverse mapping capability of the target matching model is considered to meet the standard. Further analysis is needed. Figure 7 As shown, predict T si With training T si The coefficient of determination R between them 2 =0.9547 (e.g.) Figure 7 (as shown in a), predict T ox With training T ox The coefficient of determination R between them 2 =0.9992 (e.g.) Figure 7 (As shown in b) The coefficient of determination R between the predicted WF and the training WF 2 =0.9981 (e.g.) Figure 7 (as shown in c), predict W g With training W g The coefficient of determination R between them 2 =0.9997 (e.g.) Figure 7 (As shown in d). The coefficients of determination R corresponding to the four core process parameters. 2 All values ​​are above 0.95, therefore it can be determined that the inverse mapping capability of the current target matching model meets the standard.

[0050] In summary, this application provides a deep learning-based DTCO cross-layer performance matching method, applicable to the matching of bottom-layer bulk silicon devices and top-layer low-temperature SOI devices in three-dimensional sequential integration. First, the target electrical performance indicators of the target bottom-layer bulk silicon device are obtained. These indicators include saturation drive current, off-state leakage current, saturation threshold voltage, subthreshold swing, maximum transconductance in the 0-1.2V range, maximum gate capacitance, and average integral capacitance in the 0-1.2V range. Then, the off-state leakage current is logarithmically transformed, and the target electrical performance indicators are normalized to obtain target feature data. Finally, the target feature data is input into the target matching model to obtain the target process parameters corresponding to the target top-layer low-temperature SOI device. These process parameters include silicon film thickness, equivalent oxide thickness, gate work function, and gate width. The target matching model is a four-layer fully connected feedforward neural network with the capability of inverse mapping from electrical performance to process parameters. Thus, by introducing a four-layer fully connected feedforward neural network, accurate inverse mapping from electrical performance to process parameters is achieved, effectively shortening the design cycle and improving design efficiency while ensuring device electrical compatibility.

[0051] Figure 8 This is a schematic diagram of a deep learning-based DTCO cross-layer performance matching device provided in an embodiment of this application. (Combined with...) Figure 8 As shown in the embodiment of this application, a deep learning-based DTCO cross-layer performance matching device 800 can be applied to the matching of the bottom bulk silicon device and the top low-temperature SOI device in three-dimensional sequential integration. The device includes: The acquisition module 801 is used to acquire the target electrical performance indicators of the target underlying bulk silicon device; the target electrical performance indicators include saturation drive current, off-state leakage current, saturation threshold voltage, subthreshold swing, maximum transconductance in the range of 0 to 1.2V, maximum gate capacitance, and average integral capacitance in the range of 0 to 1.2V. The preprocessing module 802 is used to perform logarithmic transformation on the leakage current in the off state and normalize the target electrical performance index to obtain target feature data. The prediction module 803 is used to input the target feature data into the target matching model and obtain the target process parameters corresponding to the target top-layer low-temperature SOI device; the target process parameters include silicon film thickness, equivalent oxide layer thickness, gate work function and gate width; the target matching model is a four-layer fully connected feedforward neural network with the ability to reverse map electrical performance to process parameters.

[0052] As one implementation method, regarding how to achieve closed-loop DTCO optimization, the aforementioned deep learning-based DTCO cross-layer performance matching device 800 further includes: an optimization module; this optimization module is used for: The target process parameters are input into the target TCAD model, and the corresponding simulated electrical performance indicators are obtained; Determine the absolute relative error between the simulated electrical performance index and the target electrical performance index; Combining the first preset stopping condition, the target process parameters are iteratively optimized based on the absolute and relative errors to form a closed-loop DTCO optimization.

[0053] As one implementation method, regarding how to achieve simulation verification, the aforementioned deep learning-based DTCO cross-layer performance matching device 800 further includes: a simulation verification module; this simulation verification module is used for: Based on the target process parameters, a first SPICE model corresponding to the target top-level low-temperature SOI device is extracted; Determine the second SPICE model corresponding to the target underlying bulk silicon device; A CMOS inverter test circuit was built based on the first SPICE model and the second SPICE model. The simulation was performed based on the CMOS inverter test circuit, and the target simulation results were obtained.

[0054] As one implementation method, the aforementioned deep learning-based DTCO cross-layer performance matching device 800 further includes a training module for training and obtaining the target matching model; the training module specifically includes a first construction module, a preprocessing submodule, a second construction module, and a training submodule. The first construction module is used to construct a simulation dataset; the simulation dataset includes training process parameters and training electrical performance indicators corresponding to the training process parameters; The preprocessing submodule is used to preprocess the simulation dataset and obtain feature data for training. The second building block is used to build an initial matching model containing a four-layer fully connected feedforward neural network; The training submodule is used to combine the second preset stopping condition and the training feature data, use the mean squared error as the loss function, and use the Adam optimizer to train the initial matching model to obtain the target matching model.

[0055] Furthermore, the four-layer fully connected feedforward neural network includes a first hidden layer, a second hidden layer, a third hidden layer, and an output layer; The first hidden layer contains 64 nodes, the second hidden layer contains 128 nodes, the third hidden layer contains 64 nodes, and the output layer contains 4 nodes.

[0056] As one implementation method, the first construction module described above is specifically used for constructing the simulation dataset: An initial TCAD model was constructed based on experimental data corresponding to the experimental top-level low-temperature SOI device. The simulated electrical characteristics of the experimental top-level low-temperature SOI device were determined based on the initial TCAD model. Based on the first threshold, the initial TCAD model is calibrated according to the actual electrical characteristics and the simulated electrical characteristics to obtain a calibrated TCAD model; Determine the process parameters for training based on the preset value range; The training process parameters are input into the calibration TCAD model to obtain the training electrical performance indicators; A simulation dataset is constructed based on the training process parameters and the training electrical performance indicators.

[0057] As one implementation method, regarding how to verify whether the model meets the standards, the aforementioned deep learning-based DTCO cross-layer performance matching device 800 further includes: a capability verification module; this capability verification module is used for: Based on the simulation dataset, the training power consumption performance index is input into the target matching model to obtain the corresponding predicted process parameters; Determine the coefficient of determination between the predicted process parameters and the corresponding training process parameters; The determination coefficient is compared with the preset qualified judgment threshold, and the inverse mapping capability of the target matching model is determined based on the comparison result.

[0058] In summary, this application first obtains the target electrical performance indicators of the target bottom-layer bulk silicon device. These indicators include saturation drive current, off-state leakage current, saturation threshold voltage, subthreshold swing, maximum transconductance in the 0-1.2V range, maximum gate capacitance, and average integral capacitance in the 0-1.2V range. Then, the off-state leakage current is logarithmically transformed, and the target electrical performance indicators are normalized to obtain target feature data. Finally, the target feature data is input into a target matching model to obtain the target process parameters corresponding to the target top-layer low-temperature SOI device. These process parameters include silicon film thickness, equivalent oxide layer thickness, gate work function, and gate width. The target matching model is a four-layer fully connected feedforward neural network with the capability of inverse mapping from electrical performance to process parameters. Thus, by introducing a four-layer fully connected feedforward neural network, accurate inverse mapping from electrical performance to process parameters is achieved, effectively shortening the design cycle and improving design efficiency while ensuring device electrical compatibility.

[0059] In addition, this application also provides a deep learning-based DTCO cross-layer performance matching device, comprising: a memory for storing a computer program; and a processor for executing the computer program to implement the steps of the deep learning-based DTCO cross-layer performance matching method described above.

[0060] In addition, this application also provides a readable storage medium storing a computer program, which, when executed by a processor, implements the steps of the deep learning-based DTCO cross-layer performance matching method as described above.

[0061] The above description of the disclosed embodiments enables those skilled in the art to make or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A deep learning-based method for cross-layer performance matching in DTCO, characterized in that, The method is applied to the matching of the bottom bulk silicon device and the top low-temperature SOI device in three-dimensional sequential integration, and the method includes: Obtain the target electrical performance parameters of the target underlying bulk silicon device; the target electrical performance parameters include saturation drive current, off-state leakage current, saturation threshold voltage, subthreshold swing, maximum transconductance in the range of 0 to 1.2V, maximum gate capacitance, and average integral capacitance in the range of 0 to 1.2V. Logarithmically transform the leakage current in the off state and normalize the target electrical performance index to obtain target characteristic data; The target feature data is input into the target matching model to obtain the target process parameters corresponding to the target top-layer low-temperature SOI device; the target process parameters include silicon film thickness, equivalent oxide layer thickness, gate work function, and gate width; the target matching model is a four-layer fully connected feedforward neural network with the ability to reverse map electrical performance to process parameters.

2. The method according to claim 1, characterized in that, The method further includes: The target process parameters are input into the target TCAD model, and the corresponding simulated electrical performance indicators are obtained; Determine the absolute relative error between the simulated electrical performance index and the target electrical performance index; Combining the first preset stopping condition, the target process parameters are iteratively optimized based on the absolute and relative errors to form a closed-loop DTCO optimization.

3. The method according to claim 1, characterized in that, The method further includes: Based on the target process parameters, a first SPICE model corresponding to the target top-level low-temperature SOI device is extracted; Determine the second SPICE model corresponding to the target underlying bulk silicon device; A CMOS inverter test circuit was built based on the first SPICE model and the second SPICE model. The simulation was performed based on the CMOS inverter test circuit, and the target simulation results were obtained.

4. The method according to claim 1, characterized in that, The target matching model is trained using the following method: Construct a simulation dataset; the simulation dataset includes training process parameters and corresponding training electrical performance indicators; The simulation dataset is preprocessed to obtain feature data for training. Construct an initial matching model consisting of a four-layer fully connected feedforward neural network; Combining the second preset stopping condition and the training feature data, the mean squared error is used as the loss function, and the Adam optimizer is used to train the initial matching model to obtain the target matching model.

5. The method according to claim 4, characterized in that, The construction of the simulation dataset includes: An initial TCAD model was constructed based on experimental data corresponding to the experimental top-level low-temperature SOI device. The simulated electrical characteristics of the experimental top-level low-temperature SOI device were determined based on the initial TCAD model. Based on the first threshold, the initial TCAD model is calibrated according to the actual electrical characteristics and the simulated electrical characteristics to obtain a calibrated TCAD model; Determine the process parameters for training based on the preset value range; The training process parameters are input into the calibration TCAD model to obtain the training electrical performance indicators; A simulation dataset is constructed based on the training process parameters and the training electrical performance indicators.

6. The method according to claim 4, characterized in that, The four-layer fully connected feedforward neural network includes a first hidden layer, a second hidden layer, a third hidden layer, and an output layer; The first hidden layer contains 64 nodes, the second hidden layer contains 128 nodes, the third hidden layer contains 64 nodes, and the output layer contains 4 nodes.

7. The method according to claim 4, characterized in that, The method further includes: Based on the simulation dataset, the training power consumption performance index is input into the target matching model to obtain the corresponding predicted process parameters; Determine the coefficient of determination between the predicted process parameters and the corresponding training process parameters; The determination coefficient is compared with the preset qualified judgment threshold, and the inverse mapping capability of the target matching model is determined based on the comparison result.

8. A deep learning-based DTCO cross-layer performance matching device, characterized in that, The device is used for matching the bottom bulk silicon device and the top low-temperature SOI device in three-dimensional sequential integration, including: The acquisition module is used to acquire the target electrical performance indicators of the target underlying bulk silicon device; the target electrical performance indicators include saturation drive current, off-state leakage current, saturation threshold voltage, subthreshold swing, maximum transconductance in the range of 0 to 1.2V, maximum gate capacitance, and average integral capacitance in the range of 0 to 1.2V. The preprocessing module is used to perform logarithmic transformation on the leakage current in the off state and normalize the target electrical performance index to obtain target feature data. The prediction module is used to input the target feature data into the target matching model and obtain the target process parameters corresponding to the target top-layer low-temperature SOI device; the target process parameters include silicon film thickness, equivalent oxide layer thickness, gate work function and gate width; the target matching model is a four-layer fully connected feedforward neural network with the ability to inversely map electrical performance to process parameters.

9. A deep learning-based DTCO cross-layer performance matching device, characterized in that, include: Memory, used to store computer programs; A processor, configured to implement the steps of the deep learning-based DTCO cross-layer performance matching method as described in any one of claims 1 to 7 when executing the computer program.

10. A readable storage medium, characterized in that, The readable storage medium stores a computer program that, when executed by a processor, implements the steps of the deep learning-based DTCO cross-layer performance matching method as described in any one of claims 1 to 7.

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