Input-output scaling calibration method and system

Abstract

This invention discloses an input-output scaling calibration method and system. In the ECO layout stage, the method constructs an independent validation set offline and uses an optimization algorithm to solve for the input scaling factor 'a' and the output compensation factor 'b'. In online application, for long interconnects whose line length exceeds the training distribution, a two-step calibration is performed: the line length is divided by 'a', and the input is the machine learning model; the predicted value is multiplied by 'b', and the output is the model. This invention achieves a calibration mechanism that enables one-time offline optimization and efficient online invocation through the collaborative work of a sample generation module, an offline optimization module, an online calibration module, and an ECO decision module. This significantly improves the prediction accuracy for long interconnects outside the distribution, avoids buffer insertion omissions due to latency underestimation, thereby reducing the number of ECO iterations and improving timing convergence efficiency.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design technology, and in particular to an input / output scaling calibration method and system. Background Technology

[0002] In the Engineering Change Order (ECO) placement phase of integrated circuit design, to accelerate the iteration process, the industry widely adopts machine learning-based delay prediction models to replace traditional static timing analysis (STA), thereby quickly assessing the impact of placement adjustments on timing. These models are typically trained on historical placement data and can learn the mapping relationship between features such as line length, logic gate type, and load capacitance and delay. They have high prediction accuracy and computational efficiency in typical placement scenarios and are therefore integrated into the ECO workflow of mainstream EDA tools.

[0003] Existing models primarily rely on training data from regular layout iterations, with line length distributions concentrated within specific intervals, allowing for good model fitting of samples within this range. However, during ECO layout, design adjustments or constraint changes may lead to interconnect structures with line lengths significantly exceeding the training sample distribution range—i.e., out-of-distribution (OOD) data. Existing models have limited extrapolation prediction capabilities when handling such long interconnects, often systematically underestimating actual latency. This bias directly causes ECO layout tools to misjudge path margins during timing evaluation, potentially skipping necessary buffer insertions or logic refactoring operations. Ultimately, timing violations are exposed in subsequent detailed routing or STA verification stages, forcing design backtracking and increasing iteration counts and design cycles. Furthermore, while using precise STA can avoid these problems, its high computational cost and reliance on detailed physical information make it difficult to frequently invoke in incremental ECO scenarios. Therefore, improving the robustness of machine learning predictions for OOD long interconnects while maintaining prediction efficiency has become a pressing technical challenge in current ECO timing optimization.

[0004] Therefore, in response to the problems mentioned above, this invention proposes an input / output scaling calibration method and system. Summary of the Invention

[0005] To overcome the problems of systematic underestimation of out-of-distribution (OOD) long interconnects in ECO layout by machine learning delayed prediction models, which easily leads to timing violations and lacks an efficient calibration mechanism, this invention proposes an input-output scaling calibration method and system. By constructing an independent validation set offline and optimizing fixed scaling parameters, the method performs feature scaling on the model input of long interconnects and compensates for the output. Without changing the original model structure and without retraining, it improves the model's prediction accuracy for OOD data, thereby ensuring the timing convergence efficiency of ECO layout.

[0006] The technical solution of the present invention is: an input / output scaling calibration method, comprising the following steps: S1. Obtain a validation slice independent of the training dataset of the machine learning latency prediction model, and construct an out-of-distribution (OOD) sample set on the validation slice by removing the buffer. The out-of-distribution sample set contains long interconnect samples whose line length exceeds the distribution range of the training data and their corresponding true latency labels. S2, Construct an objective function based on the OOD sample set. This objective function is the mean absolute percentage error, and its expression is: ; Where E is the OOD sample set, For the prediction function of the machine learning model, The feature vector is scaled after input. For the true delay label, the condition for determining whether the line length exceeds the distribution range of the training data is that the line length L is greater than the percentage of the line length distribution in the training samples that is close to 1. The objective function is used to measure the error between the predicted delay after scaling compensation and the actual delay. An optimization algorithm is used to optimize the objective function offline and solve for a set of fixed parameters, including an input scaling factor a and an output compensation factor b, where a is used to scale the input of the long interconnect line length feature and b is used to perform global compensation on the model output. S3 freezes the a and b obtained from the optimization solution and keeps them unchanged in all online ECO layout tasks; S4. During the online ECO layout process, for the current interconnected line length feature L, it is determined whether it exceeds the training data distribution range. If it does, the line length L is divided by a and then input into the machine learning delay prediction model to obtain the original prediction value. Then, the original prediction value is multiplied by b to obtain the calibrated delay prediction value. S5, based on the calibrated delay prediction value, determines whether the current interconnect needs to be buffered or timed optimized.

[0007] This invention proposes an input / output scaling calibration system, comprising: The sample generation module is used to construct an OOD sample set on a validation slice independent of the training dataset by removing the buffer, and to obtain the true delay labels corresponding to the long interconnects in the sample set. The offline optimization module, connected to the sample generation module, is used to construct an objective function based on the OOD sample set and to solve for fixed parameters a and b offline using an optimization algorithm. These parameters include an input scaling factor a and an output compensation factor b. The online calibration module, connected to the offline optimization module, is used to receive the line length feature L of the current interconnection during the ECO layout process and determine whether L exceeds the distribution range of the training data. If it does, L is divided by a and then input into the machine learning delay prediction model to obtain the original prediction value. The original prediction value is then multiplied by b to output the calibrated delay value. If it does not exceed the range, the original prediction value of the machine learning model is directly output. The ECO decision module, connected to the online calibration module, receives the calibrated delay value or the original predicted value, and determines whether the current interconnect needs to be buffered or timed optimized based on the delay value.

[0008] The beneficial effects of this invention are: 1. This invention solves for fixed parameters a and b offline in one go, without the need for retraining or parameter tuning based on the design, and can realize input scaling and output compensation for long interconnects in OOD. Compared with the existing technology that requires retraining or adjusting the model for each new design, it greatly reduces computational overhead and manpower costs, while ensuring the reproducibility of industrial applications.

[0009] 2. This invention employs a joint optimization technique of input scaling and output compensation to directly correct the systematic bias of the model when extrapolating in the feature space. Compared with the existing method of only performing linear regression calibration on the output, it can more fundamentally solve the prediction distortion problem caused by the offset of input feature distribution, thereby significantly improving the prediction accuracy of OOD long interconnects and avoiding the omission of buffer insertion due to prediction underestimation.

[0010] 3. This invention only adds division and multiplication operations during the online ECO layout process. It has a simple structure and minimal computational overhead, and can significantly improve prediction accuracy with almost no increase in runtime overhead. It is also easy to integrate into existing ECO loops.

[0011] 4. By improving the prediction accuracy of OOD long interconnects, this invention enables the ECO layout tool to more accurately identify paths that need optimization and insert buffers or perform logic refactoring in a timely manner. Compared with the situation in the prior art where timing violations occur repeatedly due to prediction deviations, this invention significantly reduces the number of ECO iterations, improves timing convergence efficiency, and enhances the overall robustness of the design process. Attached Figure Description

[0012] Figure 1 The diagram shown illustrates the workflow of this invention. Figure 2 The diagram shown is a schematic representation of the system framework of this invention. Detailed Implementation

[0013] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are some embodiments of the present invention, but not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0014] Please see Figure 1 This invention provides an embodiment of an input / output scaling calibration method, comprising: The implementation of this invention requires a pre-trained machine learning latency prediction model. This model is used to quickly estimate interconnect latency during ECO layout iterations. This model is typically built based on a regression algorithm, and its input features include, but are not limited to, reconstructed line length, logic gate type, drive strength, load capacitance, and input transition time; the output is a latency value (e.g., rise / fall latency). The model training data comes from historical layout designs, and its line length distribution is mainly concentrated in a specific range. For example, in 28nm process technology, typical line lengths are between 10μm and 200μm, with 95% of the sample line lengths being less than 150μm. However, this model tends to underestimate long interconnects (i.e., out-of-distribution data, OOD) whose line lengths exceed this distribution range.

[0015] The implementation of this invention does not depend on specific EDA tools or process nodes. However, for ease of description, the following embodiments will take the ECO layout scenario under the 28nm process node as an example and assume that the machine learning model used is a random forest model. This solution is also applicable to other process nodes and other types of machine learning models.

[0016] This invention provides an embodiment: In the ECO layout process, the training of the machine learning model is based on a complete set of layout designs. To avoid data leakage and ensure the generalization ability of calibration parameters, this invention selects a verification tape-out that is completely independent of the training set and the test set, that is, a 28nm process test chip design that does not participate in model training, and implements the sample set construction on this tape-out.

[0017] Specifically, on the verification tape-out, an initial layout is performed using EDA tools to obtain detailed physical information for all interconnects. Then, through script control, some buffers are intentionally removed from the layout, turning previously buffered long interconnects into bufferless long interconnects, thus generating samples with line lengths exceeding the normal distribution range. This operation simulates the extreme long interconnect scenarios that may occur in ECO layouts. After removing the buffers, the Static Timing Analysis (STA) tool is rerun to extract the true delay labels y_i (including rise / fall delays) of these long interconnects. Simultaneously, the feature vector xi of each sample is recorded, including the reconstructed line length L_i (in μm), logic gate type, and drive strength. All samples constitute the OOD sample set E, denoted as E = {(x_i, y_i) | i=1,…,N}, where N is the number of samples (e.g., N=5000). To ensure the representativeness of the sample set, the line length distribution should cover the range above the upper limit of the training distribution up to the extreme long interconnects (e.g., line lengths exceeding 500 μm).

[0018] For the OOD sample set E, this invention constructs the Mean Absolute Percentage Error (MAPE) as the objective function to minimize the relative error between the predicted delay and the actual delay after scaling compensation. In this embodiment, taking the simulated annealing algorithm as an example, the MAPE objective function is minimized offline using the simulated annealing algorithm, solving for fixed scalars a and b, where a is used for input scaling and b is used for output compensation. The specific optimization formula is as follows: ; Where x_{i,a,clamped} is the same as the original feature vector x_{i,OOD}, except that the line length component is divided by a before being input into the machine learning model; y_i is the true delay label, and after optimization, a and b remain unchanged. In online ECO layout, the calibration delay for arbitrarily long interconnects is calculated as follows: Where L is the original reconstruction line length. This scheme requires only one offline optimization and is applicable to all designs.

[0019] This invention employs simulated annealing to solve the aforementioned optimization problem. Simulated annealing is a global optimization algorithm that effectively avoids getting trapped in local optima and is suitable for handling such nonlinear objective functions. The algorithm parameters are set as follows: initial temperature T0 = 100, cooling rate α = 0.95, Markov chain length Lk = 200 at each temperature, and termination temperature Tend = 1e-3. The search ranges for parameters a and b are set to [0.5, 2.0] and [0.5, 2.0], respectively. The algorithm iterates until the temperature drops to the termination temperature, outputting the optimal solution (a, b). In one experiment, the optimized parameters were a = 0.82 and b = 1.36. This indicates that for long OOD interconnects, the line length feature needs to be compressed to 0.82 times its original value before inputting into the model, and the model output amplified by 1.36 times to match the actual latency.

[0020] After optimizing and obtaining values ​​a and b, they are fixed and stored in a configuration file for use in all subsequent ECO layout tasks, eliminating the need for re-optimization for different designs. During online ECO layout, for the interconnect currently being evaluated, its reconstructed line length L is first extracted. Whether L exceeds the training data distribution range is determined, typically using a threshold, specifically the 99.9 percentile of the line length in the training samples, denoted as L1. If L ≤ L1, the original model prediction is used directly. If L > L1, then perform the calibration procedure: A1. Divide the original line length L by a to get the scaled line length L' = L / a.

[0021] A2, construct the calibrated feature vector x', replace the line length component in the original feature vector with L', and keep the other features unchanged.

[0022] A3, input x' into the machine learning model to obtain the original predicted value. '.

[0023] A4, Calculate the calibrated delay value .

[0024] The ECO placement tool determines whether a path meets timing constraints based on the calibrated latency value. If the expected latency of a path exceeds 80% of the clock cycle, a buffer may need to be inserted or logic refactored to optimize timing. Because the calibrated latency is closer to the actual STA value, the tool can more accurately identify long interconnects that need optimization, avoiding the omission of buffer insertions due to underestimated predictions, thereby improving timing convergence efficiency.

[0025] This invention provides Embodiment 1: In this example, three different designs (Design 1, 2, and 3) were selected as test objects under a 28nm process, and each design underwent multiple rounds of ECO layout iterations. The timing results before and after applying the calibration method of this invention were compared. Evaluation metrics included the MAPE predicted by the model before and after calibration (relative to the true STA), the final number of timing violation paths after ECO iterations, and the average number of ECO iterations. The experimental results are shown in Table 1.

[0026] Table 1 Design Comparison Results

[0027] As shown in Table 1, after calibration, MAPE decreased by an average of about 60%, the number of timing violations decreased by more than 80%, and the number of ECO iterations was halved, which greatly improved the timing convergence efficiency.

[0028] Comparative Example 1 provided by the present invention: This example uses the exact same ECO layout process and machine learning model as Example 1, but without any calibration of the long interconnects in the OOD, directly outputting the model's raw predictions for timing decisions. Experiments were run on the same three designs, and the results are shown in Table 1 as the "before calibration" data. It is evident that without calibration, the model has a large prediction error for long interconnects, resulting in many timing violations not being detected in time, a significant increase in the number of ECO iterations, and a prolonged design convergence period.

[0029] Comparative Example 2 is provided in this invention: This example uses a precise STA (Simultaneous Targeting) algorithm instead of a machine learning model for ECO timing evaluation. Specifically, a complete STA is run in each ECO layout iteration to obtain all path delays. While this approach avoids prediction errors, it incurs significant computational overhead. For example, in Design 3, a single STA run takes approximately 3 hours, while a machine learning model prediction takes only a few seconds. Using STA for ECO requires 7 iterations to complete one convergence, totaling over 21 hours; whereas using the calibrated machine learning model of this invention, the total time is less than 30 minutes. From the above comparison, it can be seen that this invention maintains both accuracy and the efficiency of machine learning, balancing accuracy and speed.

[0030] Comparative Example 3 is provided in this invention: This example only performs linear regression calibration on the model output (i.e., only optimizes b while keeping a=1), without scaling the input features. Optimizing b on the same dataset yields b=1.52. As shown in Table 2, after applying this to the three designs, the calibrated MAPE values ​​are 14.2%, 11.8%, and 16.7%, respectively, which are still higher than the results of the joint optimization in this invention (8.7%, 7.2%, and 9.3%). This indicates that output compensation alone cannot adequately correct the model extrapolation error caused by the shift in the input feature distribution; joint optimization of input scaling and output compensation is necessary.

[0031] Table 2. Calibration Comparison Results

[0032] Please see Figure 2 Based on the above method, the present invention also provides an input / output scaling calibration system for the ECO layout stage, the system comprising: The sample generation module is responsible for constructing an OOD sample set on an independent validation tape. After receiving a design netlist and layout information that was not used in model training, the module automatically performs the following operations: First, it identifies the locations of buffers in the initial layout; second, it randomly or based on a line length threshold removes some buffers (simulating long interconnects); third, it uses the STA tool to obtain the true latency labels after removal; fourth, it collects the feature vectors and labels of all long interconnect samples to form the OOD sample set E. The sample set output by the module contains feature data (including line lengths) and true latency values, stored in a standard format for use by the offline optimization module.

[0033] The offline optimization module connects to the sample generation module, reads the OOD sample set E, and solves for the optimal parameters a and b based on a preset objective function (MAPE) and an optimization algorithm (simulated annealing). For a given set of (a, b), this module iterates through each sample in the sample set E, constructs scaled features, then calls a machine learning model (which needs to be pre-loaded) to calculate predicted values, compares them with the true labels, calculates weighted or unweighted MAPE, and then implements the simulated annealing algorithm, including initial solution generation, neighborhood search, acceptance criteria, and annealing scheduling. After the algorithm converges, it outputs the optimal (a, b), and finally writes the optimized a and b into a configuration file for subsequent use by the online calibration module.

[0034] This module also supports user-defined optimization parameters (such as temperature range, search boundary, and weighting strategy) to adapt to different process or model requirements.

[0035] The online calibration module is integrated into the ECO layout tool. After receiving the feature vector of the current interconnect, this module extracts the line length L and uses a threshold judgment unit to read the preset training data line length distribution threshold L1 in the configuration file to determine whether L exceeds the threshold. If it does not exceed the threshold, it directly jumps to the original model prediction; if it does exceed the threshold, it triggers the calibration process. When the calibration process is triggered, the line length L is divided by a through the input scaling unit to construct a new feature vector x'. Then, x' is input into the machine learning model through the model call interface to obtain the original prediction value. The calibration delay is obtained by multiplying the original predicted value by b through the output compensation unit. Finally, the calibration delay is returned to the ECO decision module through the data output unit.

[0036] The ECO decision module receives the latency value output by the online calibration module and, combined with information from the timing constraint library, evaluates whether the current interconnect meets timing requirements. If the latency exceeds the allowable range, corresponding optimization operations are triggered. The module interacts with the layout engine to update the layout and enter the next iteration. By using more accurate latency values, the ECO decision module can make more reasonable optimization choices, reduce unnecessary iterations, and thus improve convergence efficiency.

[0037] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention in any other way. Any person skilled in the art may make changes or modifications to the above-disclosed technical content to create equivalent embodiments that can be applied to other fields. However, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the protection scope of the present invention.

Claims

1. An input / output scaling calibration method, characterized in that, It includes the following steps: S1, obtain a validation slice independent of the training dataset, and generate an out-of-distribution (OOD) sample set containing long interconnects on the validation slice by removing the buffer. The out-of-distribution sample set contains multiple long interconnect samples and their corresponding true delay labels. S2, Based on the OOD sample set, construct an objective function to measure the error between the predicted delay after scaling compensation and the actual delay; S3. The above objective function is optimized offline using an optimization algorithm to solve for a set of fixed parameters, including the input scaling factor a and the output compensation factor b. S4. During the online ECO layout process, for the line length feature L of the current interconnection, it is determined whether it exceeds the distribution range of the training data. If it does, the line length feature is divided by the input scaling factor a and then input into the pre-trained machine learning delay prediction model to obtain the original prediction value. Then, the original prediction value is multiplied by the output compensation factor b to obtain the calibrated delay prediction value. The condition for determining whether it exceeds the distribution range of the training data is that the line length L is greater than the percentage of the line length distribution in the training samples that is close to 1.

2. The input / output scaling calibration method according to claim 1, characterized in that: The verification tape-out is an independent process node tape-out that has not participated in the training or testing of the machine learning model. The operation of removing the buffer is used to construct long interconnect samples with line lengths exceeding the distribution range of training samples.

3. The input / output scaling calibration method according to claim 1, characterized in that, The objective function is the mean absolute percentage error, and its expression is: Where E is the OOD sample set, For the prediction function of the machine learning model, The feature vector is scaled after input. This is the actual delayed label.

4. The input / output scaling calibration method according to claim 1, characterized in that: The input scaling factor a is used to compress the line length features of long interconnects to adapt them to the training distribution of the model; the output compensation factor b is used to globally scale the model output to match the absolute value of the true latency.

5. The input / output scaling calibration method according to claim 1, characterized in that, The condition for determining whether the training data distribution range is exceeded also includes: extracting at least one preset target feature from the feature vector of the current interconnection, and determining whether the feature value of the target feature is greater than the preset high quantile threshold of the target feature distribution in the training samples. The target feature is a physical quantity that is concentrated in the training samples but causes out-of-distribution situations in the actual ECO layout.

6. The input / output scaling calibration method according to claim 1, characterized in that: The input scaling factor a and the output compensation factor b are frozen after offline optimization and remain unchanged in all online ECO layout tasks, without the need for re-optimization for different designs.

7. The input / output scaling calibration method according to claim 1, characterized in that: The pre-trained machine learning delay prediction model is a regression-based time series prediction model, whose input features include at least line length, logic gate type, drive strength, and load capacitance.

8. The input / output scaling calibration method according to claim 1, characterized in that, The online ECO layout process includes: during the layout iteration, applying calibrated delay prediction values ​​to paths identified as long interconnects to determine whether a buffer needs to be inserted or path reconstruction needs to be performed.

9. An input / output scaling calibration system, comprising an input / output scaling calibration method according to any one of claims 1-8, characterized in that, include: The sample generation module is used to construct an OOD sample set on an independent verification tape by removing buffers and obtain the corresponding real delay labels. The offline optimization module is used to construct an objective function based on the OOD sample set and to solve for fixed parameters a and b using an optimization algorithm. The objective function is the mean absolute percentage error. The online calibration module is used to receive the line length feature L of the current interconnect during the ECO layout process, determine whether it exceeds the training distribution, and if it does, divide the line length L by the parameter a and input it into the machine learning delay prediction model to obtain the original prediction value. Then, multiply the prediction value by the parameter b and output the calibrated delay value. The ECO decision module is used to determine whether the current interconnect needs buffer insertion or timing optimization based on the calibrated delay value.

10. An input / output scaling calibration system according to claim 9, characterized in that: The online calibration module also includes a threshold judgment unit, which is used to determine whether the current line length L is greater than the preset distribution threshold. If not, the original prediction value of the machine learning model is directly output; if so, the input-output scaling calibration process is executed.

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