A fast read system and method for NAND Flash memory
By generating and delaying the read enable signal in the SoC chip to trigger the reading and sampling of data from the NAND Flash memory, the problem of low read efficiency under asynchronous interface is solved, achieving fast read and high throughput.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- 奕行智能科技(广州)有限公司
- Filing Date
- 2026-04-01
- Publication Date
- 2026-07-03
AI Technical Summary
NAND Flash memory has slow read and write speeds and low read efficiency under asynchronous interface timing, making synchronous data transmission impossible.
The clock signal output from the clock source of the SoC chip is processed by the read enable signal generation module to generate a read enable signal, which triggers data reading in the NAND Flash memory. After being delayed by the programmable delay unit, the sampling clock is output to the read data capture unit for data sampling.
It enables fast reading of NAND Flash memory, improves data throughput and read speed, and achieves near-synchronous interface operation, making full use of hardware resources.
Smart Images
Figure CN122337280A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of NAND Flash technology, and in particular to a fast read system and method for NAND Flash memory. Background Technology
[0002] NAND Flash memory uses asynchronous interface timing, resulting in slow read and write speeds. Specifically, this memory lacks a unified clock signal to synchronize data transmission; read and write operations are triggered by level changes in control signals such as RD (read signal) and WE (write signal). During a read operation, a low level on the RD signal controls data output, and only one byte can be read per low-level cycle. For each byte read, the RD signal sends only one pulse, then stops, waiting for the next instruction. This method results in low read efficiency. Summary of the Invention
[0003] To address at least some of the problems mentioned above in the prior art, the present invention provides a fast read method for NAND Flash memory, comprising the following steps: The clock signal output from the clock source of the SoC chip is processed by the read enable signal generation module to generate a read enable signal, which is then output to the NAND Flash memory and the programmable delay unit of the SoC chip. The NAND Flash memory triggers a data read operation on the falling edge of the read enable signal, outputting data byte by byte to the data bus; and In a SoC chip, a programmable delay unit delays the read enable signal and outputs a sampling clock to the read data capture unit. The read data capture unit samples the data on the data bus on the rising edge of the sampling clock.
[0004] Furthermore, in the SoC chip, the direct memory access engine controls the clock source to output a clock signal. The clock signal is processed by the read enable signal generation module to generate a read enable signal, which is then output to the NAND Flash memory via the output clock pin. At the same time, the output clock pin outputs the read enable signal to the output clock pin, and then transmits it to the programmable delay unit.
[0005] Furthermore, it also includes: The CPU in the SoC chip sends a read data command to the direct memory access engine and sets the size of the data block to be read.
[0006] Furthermore, the software driver in the CPU sets the size of the data blocks read from the NAND Flash memory in the direct memory access engine.
[0007] The present invention also provides a fast read system for NAND Flash memory, comprising: NAND Flash memory, which is connected to the SoC chip; SoC chips, including: The direct memory access engine is connected to the clock source and the read data capture unit; The clock source is connected to the read enable signal generation module; The read enable signal generation module is connected to the clock pin; The clock pin is connected to the NAND Flash memory and the programmable delay unit; A programmable delay unit, which is connected to the read data capture unit; A read data capture unit is configured to sample data transferred from the NAND Flash memory.
[0008] Furthermore, the SoC chip also includes an input data pin, which is connected to the read data capture unit and connected to the NAND Flash memory via a data bus.
[0009] Furthermore, the clock pin includes an output clock pin and an input clock pin connected together, wherein the output clock pin is connected to the NAND Flash memory and the read enable signal generation module, and the input clock pin is connected to the programmable delay unit.
[0010] Furthermore, the SoC chip also includes a CPU, which is configured to control the operation of the direct memory access engine.
[0011] Furthermore, the direct memory access engine controls the clock source to generate a clock signal, and the read enable signal generation module processes the clock signal to generate a read enable signal and transmits it to the output clock pin; The output clock pin transmits the read enable signal to the NAND Flash memory and the input clock pin; The NAND Flash memory triggers a data read operation on the falling edge of the read enable signal, outputting data byte by byte to the data bus; The read enable signal is transmitted from the input clock pin to the programmable delay unit, and after being delayed by the programmable delay unit, it is output as a sampling clock to the read data capture unit. The data on the data bus is sampled by the read data capture unit on the rising edge of the sampling clock.
[0012] The present invention has at least the following beneficial effects: The fast read method for NAND Flash memory of the present invention utilizes the clock inside the SoC chip to generate a read enable signal, which can realize the continuous sending of read enable signals to the NAND Flash memory. Compared with the traditional non-continuous single-byte read, it improves the data throughput of the interface and the data read speed, and can achieve near-synchronous operation on the asynchronous interface of NAND Flash memory.
[0013] This invention loops the clock output from the SoC chip back to the programmable delay unit of the SoC chip. After being delayed by the programmable delay unit, it is output as a sampling clock to the read data capture unit. By driving the sampling through the internal clock of the SoC chip, the waiting time is reduced and hardware resources are fully utilized. Attached Figure Description
[0014] To further illustrate the above and other advantages and features of the various embodiments of the present invention, a more specific description of the embodiments of the invention will be presented with reference to the accompanying drawings. It is to be understood that these drawings depict only typical embodiments of the invention and are therefore not intended to limit its scope. In the drawings, identical or corresponding parts will be indicated by identical or similar reference numerals for clarity.
[0015] Figure 1 A schematic diagram of a fast read system for NAND Flash memory according to an embodiment of the present invention is shown.
[0016] Figure 2 A timing diagram for writing and reading data is shown according to an embodiment of the present invention.
[0017] Figure 3 A timing diagram for reading data according to an embodiment of the present invention is shown. Detailed Implementation
[0018] It should be noted that the components in the accompanying drawings may be shown exaggerated for illustrative purposes and may not be to scale.
[0019] In this invention, the various embodiments are merely intended to illustrate the solutions of the invention and should not be construed as limiting.
[0020] In this invention, unless otherwise specified, the quantifiers “a” and “one” do not exclude scenarios involving multiple elements.
[0021] It should also be noted that, in the embodiments of the present invention, only a portion of the parts or components may be shown for clarity and simplicity. However, those skilled in the art will understand that, under the teachings of the present invention, the required parts or components can be added as needed for specific scenarios.
[0022] It should also be noted that within the scope of this invention, the terms "same", "equal", and "equal to" do not mean that the two values are absolutely equal, but allow for a certain reasonable error. In other words, the terms also cover "substantially the same", "substantially equal", and "substantially equal to".
[0023] It should also be noted that in the description of this invention, the terms "center," "longitudinal," "lateral," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the invention and for simplifying the description, and do not explicitly or implicitly suggest that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.
[0024] Furthermore, the embodiments of the present invention describe the process steps in a specific order. However, this is only for the convenience of distinguishing each step, and is not a limitation on the order of each step. In different embodiments of the present invention, the order of each step can be adjusted according to the process.
[0025] Figure 1 A schematic diagram of a fast read system for NAND Flash memory according to an embodiment of the present invention is shown.
[0026] like Figure 1 As shown, a fast NAND Flash memory read system includes a SoC chip 100 and a NAND Flash memory 200, which are connected by a PCB board 300.
[0027] The SoC chip 100 includes a direct memory access (DMA) engine 101, a clock source 102, a read data capture unit 103, a clock pin 104, a programmable delay unit 105, an input data pin 106, and a read enable signal generation module 107.
[0028] The direct memory access engine 101 is connected to the clock source 102 and the read data capture unit 103. The direct memory access engine 101 controls the clock source 102 to generate a clock signal with adjustable frequency and duty cycle. The direct memory access engine 101 controls the read data capture unit 103 to start.
[0029] The read enable signal generation module 107 is connected to the clock source 102 and is used to convert the clock signal output by the clock source 102 into a read enable signal that meets the asynchronous timing requirements of NAND Flash.
[0030] Clock pin 104 includes an output clock pin 1041 and an input clock pin 1042 connected together. Output clock pin 1041 is connected to read enable signal generation module 107 and NAND Flash memory 200, and is used to output a read enable signal to NAND Flash memory 200.
[0031] The programmable delay unit 105 is connected to the read data capture unit 103 and the input clock pin 1042.
[0032] The programmable delay unit 105 is used to adjust the sampling point of the read data capture unit 103, and the value of the programmable delay unit 105 can be adjusted as needed.
[0033] The input clock pin 1042 loops the read enable signal output from the output clock pin 1041 back to the programmable delay unit 105 within the SoC chip 100. Since the programmable delay unit 105 is connected to the read data capture unit 103, the read enable signal output from the input clock pin 1042 is delayed by the programmable delay unit 105 and used as the sampling clock for the read data capture unit 103.
[0034] Input data pin 106 connects to read data capture unit 103 and NAND Flash memory 200. Input data pin 106 is connected to NAND Flash memory 200 via data bus.
[0035] The SoC chip 100 also includes a CPU (not shown) for controlling the operation of the direct memory access engine 101. A software driver in the CPU sets the size of data blocks read from the NAND Flash memory within the direct memory access engine 101.
[0036] A method for fast reading of NAND Flash memory includes the following steps: Step 1: The CPU sends a read data instruction to the Direct Memory Access Engine 101 and sets the size of the data block to be read. The software driver in the CPU sets the size of the data block to be read from the NAND Flash memory in the Direct Memory Access Engine 101.
[0037] Step 2: The direct memory access engine 101 controls the clock source 102 to output a clock signal, which is processed by the read enable signal generation module 107 to output a read enable signal. The read enable signal is output from the clock pin 104 to the NAND Flash memory 200 and the programmable delay unit 105.
[0038] The read enable signal output by the read enable signal generation module 107 is output to the NAND Flash memory 200 and the input clock pin 1042 through the output clock pin 1041, and then output to the programmable delay unit 105 through the input clock pin 1042.
[0039] Step 3: The NAND Flash memory 200 triggers a data read operation on the falling edge of the read enable signal, and outputs the data byte by byte to the data bus.
[0040] Step 4: The programmable delay unit 105 outputs a sampling clock to the read data capture unit 103, and the read data capture unit 103 samples the data on the data bus on the rising edge of the sampling clock.
[0041] The read enable signal is delayed by the programmable delay unit 105 and then output as a sampling clock to the read data capture unit 103.
[0042] Figure 2 A timing diagram for writing and reading data is shown according to an embodiment of the present invention.
[0043] like Figure 2 As shown, the first line contains the Command Latch Enable (CLE) signal. The CLE signal changes from low to high and then back to low. When the CLE signal is high, the content transmitted on the I / O bus is interpreted as a command by the NAND Flash memory; when the CLE signal is low, the content on the I / O bus is interpreted as an address (ALE signal high) or data (ALE signal low) depending on the state of the ALE signal.
[0044] The second line is the chip select signal (CE signal). CLE changes from high to low and then back to high. The chip select signal is active low. When the CE signal is low, the corresponding NAND Flash memory is activated, responding to other control signals (CLE / ALE / RE / WE) and bus data.
[0045] The third line is the write enable signal (WE signal), which is active low. When WE changes from high to low, the NAND Flash memory is ready to receive commands / addresses / data from the bus; when WE changes from low to high, the NAND Flash memory latches the commands / addresses / data.
[0046] The sixth line contains the I / O bus data. When latched on the rising edge of WE, the commands and address values transmitted sequentially on the I / O bus are: 00, addr1 col, addr2 col, addr1 row, addr2 row, addr3 row, 30. 00 is the first byte command for page programming, indicating "Address to be sent next, ready to start programming." Addr1 col and addr2 col are column addresses, and addr1 row, addr2 row, addr3 row are row addresses. 30 is the second byte command for page programming, indicating "Address sent, start programming operation."
[0047] The fourth line is the Address Latch Enable (ALE) signal. The ALE signal is active high, indicating that an address is being transmitted on the I / O bus. When a command is transmitted on the I / O bus, the ALE signal goes low; when an address is transmitted on the I / O bus, the ALE signal goes high.
[0048] The fifth line contains the read enable signal (RE signal). The RE signal is active low. When reading data begins, the RE signal changes from high to low. When RE changes from high to low, the NAND Flash memory begins sending data to the bus. When RE changes from low to high, the NAND Flash memory ends the current data output.
[0049] During the data reading process, the I / O bus transmits data byte by byte: data0, data1, data2, ..., dataN.
[0050] Figure 3 A timing diagram for reading data according to an embodiment of the present invention is shown.
[0051] like Figure 3 As shown, the first row is the chip select signal (CE signal). During the data reading process, the CE signal is at a low level, and it becomes high level after the data reading is completed.
[0052] The second line is the Address Latch Enable (ALE) signal. The ALE signal is active high, indicating that an address is being transmitted on the I / O bus. When a command is transmitted on the I / O bus, the ALE signal goes low; when an address is transmitted, the ALE signal goes high. During data reading, the ALE signal is initially high as the NAND Flash memory receives the read address. After the address is received, the ALE signal goes low.
[0053] The third line is the read enable signal (RE signal). The RE signal is active low. When reading data begins, the RE signal changes from high to low. When RE changes from high to low, the NAND Flash memory begins sending data to the bus; when RE changes from low to high, the NAND Flash memory ends the current data output. Trp represents the duration of RE being active low, and Th represents the duration of RE being active high. Tceh represents the hold time of RE relative to CE, the time from when RE goes high until CE goes high.
[0054] The fourth line represents the data transmitted via the bus.
[0055] While some embodiments of the present invention have been described in this application, those skilled in the art will understand that these embodiments are merely illustrative. Numerous variations, alternatives, and improvements will arise in those skilled in the art under the teachings of this invention without departing from its scope. The appended claims are intended to define the scope of the invention and thereby cover methods and structures within the scope of the claims themselves and their equivalents.
Claims
1. A method for fast read of a NAND Flash memory, characterized in that, Includes the following steps: The clock signal output from the clock source of the SoC chip is processed by the read enable signal generation module to generate a read enable signal, which is then output to the NAND Flash memory and the programmable delay unit of the SoC chip. The NAND Flash memory triggers a data read operation on the falling edge of the read enable signal, outputting data byte by byte to the data bus; as well as In a SoC chip, a programmable delay unit delays the read enable signal and outputs a sampling clock to the read data capture unit. The read data capture unit samples the data on the data bus on the rising edge of the sampling clock.
2. The NAND Flash memory quick read method of claim 1, wherein, In the SoC chip, the direct memory access engine controls the clock source to output a clock signal. The clock signal is processed by the read enable signal generation module to generate a read enable signal, which is then output to the NAND Flash memory via the output clock pin. At the same time, the output clock pin outputs the read enable signal to the output clock pin, and then transmits it to the programmable delay unit.
3. The method of claim 1, wherein, Also includes: The CPU in the SoC chip sends a read data command to the direct memory access engine and sets the size of the data block to be read.
4. The NAND Flash memory quick read method of claim 3, wherein, The software driver in the CPU sets the size of the data blocks read from the NAND Flash memory in the direct memory access engine.
5. A NAND Flash memory fast read system, characterized in that, include: NAND Flash memory, which is connected to the SoC chip; SoC chips, including: The direct memory access engine is connected to the clock source and the read data capture unit; The clock source is connected to the read enable signal generation module; The read enable signal generation module is connected to the clock pin; The clock pin is connected to the NAND Flash memory and the programmable delay unit; A programmable delay unit, which is connected to the read data capture unit; A read data capture unit is configured to sample data transferred from the NAND Flash memory.
6. The NAND Flash memory quick read system of claim 5, wherein, The SoC chip also includes an input data pin, which is connected to the read data capture unit and connected to the NAND Flash memory via a data bus.
7. The NAND Flash memory quick read system of claim 5, wherein, The clock pin includes an output clock pin and an input clock pin connected together, wherein the output clock pin is connected to the NAND Flash memory and the read enable signal generation module, and the input clock pin is connected to the programmable delay unit.
8. The NAND Flash memory quick read system of claim 5, wherein, The SoC chip also includes a CPU, which is configured to control the operation of the direct memory access engine.
9. The NAND Flash memory quick read system of claim 7, wherein, The direct memory access engine controls the clock source to generate a clock signal, and the read enable signal generation module processes the clock signal to generate a read enable signal and transmits it to the output clock pin. The output clock pin transmits the read enable signal to the NAND Flash memory and the input clock pin; The NAND Flash memory triggers a data read operation on the falling edge of the read enable signal, outputting data byte by byte to the data bus; The read enable signal is transmitted from the input clock pin to the programmable delay unit, and after being delayed by the programmable delay unit, it is output as a sampling clock to the read data capture unit. The data on the data bus is sampled by the read data capture unit on the rising edge of the sampling clock.