Pad structure in PCB and optimization method of pad impedance in PCB

Abstract

The application provides a pad structure in a PCB and a method for optimizing the impedance of a pad in a PCB, and relates to the technical field of circuit board design. The pad structure comprises: a target pad formed on the PCB; a first transmission line electrically connected to the target pad, the line width of the first transmission line being smaller than the width of the target pad; a second transmission line electrically connected to the first transmission line, the line width of the second transmission line being smaller than the width of the target pad; and a third transmission line electrically connected to the second transmission line, the line width of the third transmission line being larger than the line width of the second transmission line. By setting the line widths of the first transmission line and the second transmission line to be smaller than the width of the target pad, a high-impedance thin line section is formed, and by utilizing the high characteristic impedance characteristic of the high-impedance thin line section, the capacitive low impedance of the wide pad itself can be effectively offset, so that the overall impedance of the pad area is improved without increasing the cost and process difficulty.

Description

Technical Field

[0001] This application relates to the field of circuit board design technology, and in particular to a pad structure in a PCB and a method for optimizing the pad impedance in a PCB. Background Technology

[0002] With the rapid development of information technology, the demand for data processing volume and transmission rate is growing exponentially. High-speed serial computer expansion bus standards such as Peripheral Component Interconnect Express (PCIe) 5.0 or PCIe 6.0 have been widely used. In such high-speed interface applications, signal integrity has become a key factor determining system performance. Printed Circuit Boards (PCBs), as the carriers of electrical connections between electronic components, have pads that are crucial for achieving inter-board interconnection. Wide pads (such as gold finger pads, Ball Grid Array (BGA) pads, and connector pads) are typically much larger than the linewidth of conventional signal transmission lines due to the need to withstand greater mechanical stress or meet specific packaging requirements. However, in high-speed signal transmission, the parasitic capacitance formed between wide pads and the reference layer leads to a significant decrease in the characteristic impedance of this area, causing signal reflection and attenuation, severely affecting signal integrity. Taking gold finger pads as an example, as a key component for inter-board interconnection, they are used to insert daughter boards (such as memory modules, graphics cards, etc.) into the motherboard connector to achieve electrical conduction. With the continuous increase in signal speed, the gold finger structure, due to its physical size limitations, has become a difficult area for impedance control, posing a severe challenge to existing PCB design processes. Similarly, BGA pads and connector pads, due to their large size, also face the same impedance mismatch problem in high-frequency signal transmission.

[0003] In related technologies, the following technical solutions are commonly used to optimize the impedance of pads in PCBs: (1) Adjusting the size of the anti-pad of the reference layer below the pad. Specifically, by removing part of the copper foil on the power or ground layer below the pad, the distance between the signal and the reference layer is increased in order to improve the impedance value. However, this solution is limited by wiring density and space constraints. (2) Using low dielectric constant materials to make PCB substrates. Specifically, by selecting materials with lower dielectric constants, the parasitic capacitance between the signal line and the reference layer is reduced, thereby improving impedance matching. However, low dielectric materials are expensive and complex to implement. (3) Designing transmission lines with segmented gradient linewidths. That is, on the transmission lines connected to the pads, a line shape design that gradually widens from narrow is adopted to smoothly transition impedance changes. However, segmented gradient linewidths rely on high-precision processes and may introduce additional impedance discontinuity problems.

[0004] Therefore, there is an urgent need for a solution that can effectively optimize the impedance of the pad area without increasing costs and process difficulty. Summary of the Invention

[0005] This application provides a method for optimizing the pad structure and impedance of a PCB, which improves the problems of high cost, difficult process, or limited impedance improvement when optimizing the impedance of PCB pads using related technologies.

[0006] In a first aspect, this application provides a pad structure in a PCB, including:

[0007] The target pad is formed on this PCB;

[0008] The first transmission line is electrically connected to the target pad, and the line width of the first transmission line is smaller than the width of the target pad.

[0009] The second transmission line is electrically connected to the first transmission line, and the width of the second transmission line is smaller than the width of the target pad.

[0010] The third transmission line is electrically connected to the second transmission line, and the line width of the third transmission line is greater than that of the second transmission line.

[0011] In one possible implementation, the linewidth of the second transmission line is the same as that of the first transmission line.

[0012] In one possible implementation, the line width of the first transmission line is the minimum line width allowed by PCB design rules.

[0013] In one possible implementation, the linewidth of the third transmission line is configured to give the third transmission line a target characteristic impedance, which is the same as the characteristic impedance of the signal transmission line in the non-pad area of ​​the PCB.

[0014] In one possible implementation, the side of the first transmission line is aligned with the corresponding side of the target pad.

[0015] In one possible implementation, the first angle between the second transmission line segment and the first transmission line segment is 30° to 60°, and the second angle between the second transmission line segment and the third transmission line segment is 30° to 60°.

[0016] In one possible implementation, both the first included angle and the second included angle are 45°.

[0017] In one possible implementation, the pad structure in the PCB further includes an anti-pad structure disposed on a PCB reference layer below the target pad.

[0018] In a second aspect, this application provides a circuit board, including a substrate and at least one pad structure in a PCB as described in any of the first aspects.

[0019] Thirdly, this application provides a method for optimizing the pad impedance in a PCB, used to optimize the pad structure in the PCB as described in any of the first aspects, wherein the method for optimizing the pad impedance in the PCB includes:

[0020] Identify the target pads on the PCB;

[0021] Lay out the first transmission line on the PCB and make the first transmission line electrically connected to the target pad. The line width of the first transmission line is smaller than the width of the target pad.

[0022] Lay a second transmission line on the PCB and electrically connect the second transmission line to the first transmission line. The width of the second transmission line is smaller than the width of the target pad.

[0023] A third transmission line is laid on the PCB and electrically connected to the second transmission line. The line width of the third transmission line is greater than that of the second transmission line.

[0024] Fourthly, this application provides an apparatus for optimizing the impedance of pads in a PCB, comprising:

[0025] The determination module is used to determine the target pads on the PCB;

[0026] The processing module is used to lay a first transmission line on the PCB and electrically connect the first transmission line to the target pad, wherein the line width of the first transmission line is smaller than the width of the target pad; lay a second transmission line on the PCB and electrically connect the second transmission line to the first transmission line, wherein the line width of the second transmission line is smaller than the width of the target pad; and lay a third transmission line on the PCB and electrically connect the third transmission line to the second transmission line, wherein the line width of the third transmission line is greater than the line width of the second transmission line.

[0027] Fifthly, this application provides an electronic device, including: a processor, and a memory communicatively connected to the processor;

[0028] Memory is used to store instructions executed by the computer;

[0029] A processor is used to execute computer-executable instructions stored in memory to implement a method for optimizing pad impedance in a PCB, which is a third aspect.

[0030] In a sixth aspect, this application provides a computer-readable storage medium storing computer-executable instructions, which, when executed, are used to implement the method for optimizing pad impedance in a PCB according to the third aspect.

[0031] In a seventh aspect, this application provides a computer program product, including a computer program that, when executed, implements the method for optimizing pad impedance in a PCB according to the third aspect.

[0032] This application provides a method for optimizing the pad structure and impedance of a PCB. The PCB pad structure includes: a target pad formed on the PCB; a first transmission line electrically connected to the target pad, the line width of which is smaller than the width of the target pad; a second transmission line electrically connected to the first transmission line, the line width of which is smaller than the width of the target pad; and a third transmission line electrically connected to the second transmission line, the line width of which is greater than the line width of the second transmission line. By setting the line widths of the first and second transmission lines to be smaller than the width of the target pad, this application forms high-impedance thin segments, effectively compensating for the impedance reduction caused by parasitic capacitance between the wide pad and the reference layer, significantly improving the overall characteristic impedance of the pad area, bringing it close to the target impedance value, thereby improving signal integrity and helping to reduce reflection and attenuation in high-speed signal transmission. Simultaneously, since it does not involve the selection of special materials such as low dielectric constant materials, it does not increase material costs; and by adopting a conventional straight-line design, it is fully compatible with existing PCB processing technology, reducing the implementation difficulty and impedance discontinuity risk caused by the high-precision process requirements of gradient line structures. Furthermore, by setting the line width of the third transmission line to be greater than that of the second transmission line, the signal is ensured to transition smoothly from the pad area to the regular transmission area, which helps to achieve overall impedance matching. This effectively optimizes the impedance of the pad area without increasing cost or process difficulty, and can be widely used in various wide pad scenarios such as gold finger pads, BGA pads, and connector pads. Attached Figure Description

[0033] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0034] Figure 1 This is a schematic diagram of the gold finger pad structure in a PCB without impedance optimization in related technologies.

[0035] Figure 2 This is a schematic diagram of the gold finger pad structure after impedance optimization using an adjusted anti-pad size scheme in related technologies.

[0036] Figure 3 A schematic diagram of a pad structure in a PCB provided for an exemplary embodiment of this application;

[0037] Figure 4 Another schematic diagram of the pad structure in a PCB provided as an exemplary embodiment of this application;

[0038] Figure 5 A schematic diagram comparing impedance values ​​corresponding to different impedance optimization schemes is provided for an exemplary embodiment of this application;

[0039] Figure 6 A flowchart illustrating a method for optimizing pad impedance in a PCB, provided as an exemplary embodiment of this application;

[0040] Figure 7 Another flowchart illustrating a method for optimizing pad impedance in a PCB is provided for an exemplary embodiment of this application.

[0041] Figure 8 A schematic diagram of a device for optimizing pad impedance in a PCB provided as an exemplary embodiment of this application;

[0042] Figure 9 A schematic diagram of the structure of an electronic device provided as an exemplary embodiment of this application.

[0043] In the diagram, 30—pad structure in PCB; 31—target pad; 32—first transmission line; 33—second transmission line; 34—third transmission line; 35—anti-pad structure; 80—pad impedance optimization device in PCB; 81—determining module; 82—processing module; 90—electronic device; 91—processor; 92—memory; 93—communication interface.

[0044] The accompanying drawings have illustrated specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to specific embodiments. Detailed Implementation

[0045] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0046] The terms “first,” “second,” etc., used in the specification and claims of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented, for example, in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, products, or apparatus.

[0047] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties. Furthermore, the collection, use and processing of the relevant data must comply with relevant laws, regulations and standards, and corresponding operation entry points are provided for users to choose to authorize or refuse.

[0048] In related technologies, when optimizing the impedance of PCB pads by adjusting the size of anti-pads, the impedance improvement is limited even when the anti-pad is expanded to a larger size due to the inherently large size of wide pads (such as gold finger pads), making it difficult to achieve the target impedance value. Furthermore, with increasing PCB routing density, other signal lines often need to be routed below the pads, failing to provide a complete reference plane and further exacerbating impedance mismatch. While using low-dielectric-constant materials to optimize PCB pad impedance can improve impedance matching by reducing parasitic capacitance, the high cost of these materials significantly increases PCB raw material costs, hindering cost control and limiting their widespread application in mass production. When using transmission lines with segmented, gradually tapered linewidths to optimize PCB pad impedance, the tapered linewidth is difficult to manufacture precisely in conventional PCB manufacturing processes, and linewidth accuracy is easily affected by process capabilities, relying on high-precision processes. Simultaneously, the segmented design increases routing and simulation complexity; improper transition design may introduce new impedance abrupt changes, further restricting high-frequency performance.

[0049] For example, we will use the gold finger pad as an example. Figure 1 This is a schematic diagram of a gold finger pad structure on a PCB that has not undergone impedance optimization in related technologies. For example... Figure 1 As shown, the transmission line of the gold finger pad consists of three segments, all with the standard line width used in conventional designs (e.g., 7mil, corresponding to an 85Ω characteristic impedance), and no anti-pad structure is set. Figure 2This is a schematic diagram of the gold finger pad structure after impedance optimization using an adjusted anti-pad size scheme in related technologies. Figure 2 As shown, the transmission line of this gold finger pad is also a three-segment design, and the line width remains a standard line width (e.g., 7mil). However, an anti-pad structure is added to the reference layer below the gold finger pad. However, because the gold finger pad itself is quite wide, even with the addition of the anti-pad, the impedance improvement is still limited, making it difficult to effectively solve the problem of low impedance.

[0050] To address the aforementioned issues, this application provides an optimized solution for pad structures in PCBs. By introducing a cascaded structure of "thin-line compensation + wide-line restoration" in wide pad regions with high impedance requirements, the high characteristic impedance of the thin-line segments offsets the inherent low capacitive impedance of the wide pads, thereby achieving an overall impedance improvement in the pad region without increasing cost or manufacturing complexity. Specifically, based on the principle of impedance compensation, two thin transmission lines (i.e., the first and second transmission lines) with a line width smaller than the pad width are sequentially electrically connected after the wide pad (such as gold finger pads, BGA pads, connector pads, etc.) to form a high-impedance compensation segment. This segment compensates for the impedance reduction caused by parasitic capacitance between the wide pad and the reference layer. Subsequently, a wide transmission line (i.e., the third transmission line) with a line width greater than the second transmission line is electrically connected, restoring it to the same target characteristic impedance as conventional signal transmission lines on the PCB. This ensures a smooth transition of the signal from the pad region to the conventional transmission region, effectively optimizing the pad region impedance without increasing cost or manufacturing complexity. This solution can be widely applied to various wide pad scenarios.

[0051] The technical solution of this application and how the technical solution of this application solves the above-mentioned technical problems are described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of this application will now be described with reference to the accompanying drawings.

[0052] Figure 3 This is a schematic diagram of a pad structure in a PCB provided for an exemplary embodiment of this application. Figure 3 As shown, the pad structure 30 in this PCB includes:

[0053] Target pad 31 is formed on this PCB;

[0054] The first transmission line 32 is electrically connected to the target pad 31, and the line width of the first transmission line 32 is smaller than the width of the target pad 31.

[0055] The second transmission line 33 is electrically connected to the first transmission line 32, and the line width of the second transmission line 33 is smaller than the width of the target pad 31.

[0056] The third transmission line 34 is electrically connected to the second transmission line 33, and the line width of the third transmission line 34 is greater than that of the second transmission line 33.

[0057] Here, target pad 31 refers to a pad on the PCB whose characteristic impedance is low due to its large geometric size. For example, combined with... Figure 1 and Figure 2 The target pad can be a gold finger pad, which is a metal contact structure located on the edge of the PCB for inserting connectors to achieve inter-board interconnection. Its width is usually much larger than the line width of a conventional signal transmission line (e.g., Figure 1 and Figure 2 (The 7mil standard linewidth is shown in the figure). It is understood that the target pad is not limited to gold finger pads, but may also include other types of wide pads such as ball grid array (BGA) pads and connector pads. Any pad that requires impedance control due to its large size can be used as the target pad of this application.

[0058] For example, such as Figure 3 As shown, the first transmission line 32 is directly electrically connected to the target pad 31, such as a gold finger pad, and its line width is set to be smaller than the width of the target pad 31, for example, 3 mil. Since the characteristic impedance of the transmission line is inversely proportional to its line width, the thinner the line width, the higher the characteristic impedance. Therefore, the first transmission line 32 can form a high impedance region to offset the low capacitive impedance generated by the target pad 31 due to its large width.

[0059] Correspondingly, the second transmission line 33 is electrically connected to the first transmission line 32, and its line width is also set to be smaller than the width of the target pad 31, such as 3mil or 4mil. By connecting the two thin lines in series, a sufficiently long high impedance compensation area can be formed, which can more effectively improve the overall characteristic impedance of the pad area.

[0060] Furthermore, by electrically connecting a wider transmission line after the thin-line compensation section, the transmission line is restored to its normal impedance level, achieving a smooth transition from the pad compensation area to the normal transmission area. (Still referencing...) Figure 3 The third transmission line 34 is electrically connected to the second transmission line 33, and its line width is set to be greater than that of the second transmission line 33, for example, 7 mil.

[0061] The PCB pad structure provided in this application, by setting the line widths of the first and second transmission lines to be smaller than the width of the target pad, forms high-impedance thin line segments. This effectively compensates for the impedance reduction caused by parasitic capacitance between the wide pad and the reference layer, significantly improving the overall characteristic impedance of the pad area and bringing it close to the target impedance value. This improves signal integrity and helps reduce reflection and attenuation in high-speed signal transmission. Simultaneously, since it does not involve the selection of special materials such as low-dielectric-constant materials, it avoids increasing material costs. Furthermore, the conventional straight-line design is fully compatible with existing PCB manufacturing processes, reducing the implementation difficulty and impedance discontinuity risk associated with the high-precision process requirements of gradient line structures. In addition, by setting the line width of the third transmission line to be greater than that of the second transmission line, a smooth transition of the signal from the pad area to the conventional transmission area is ensured, facilitating overall impedance matching. This effectively optimizes the pad area impedance without increasing cost or process complexity, and can be widely applied to various wide pad scenarios such as gold finger pads, BGA pads, and connector pads.

[0062] In some embodiments, the linewidth of the second transmission line is the same as that of the first transmission line.

[0063] For example, see reference Figure 3 The first transmission line 32 and the second transmission line 33 both use the same thin line width, for example, 3 mil, thus forming thin line compensation segments of equal width.

[0064] In this embodiment, by setting the line width of the second transmission line to be the same as that of the first transmission line, a thin line compensation structure with equal width is formed. This equal width design simplifies the wiring complexity and makes it easy to implement quickly in PCB design tools. In addition, the thin line with equal width can form a uniform high impedance compensation area, which helps to reduce the additional impedance fluctuations introduced by the line width change, making the compensation effect more stable and controllable.

[0065] In some embodiments, the line width of the first transmission line is the minimum line width allowed by PCB design rules.

[0066] For example, combined Figure 3 As shown, the first transmission line 32 adopts the minimum line width that can be reliably achieved under current process conditions, such as 3mil, which is a relatively extreme processing size.

[0067] It should be noted that the minimum trace width allowed by the above PCB design rules refers to the minimum conductor width that can guarantee a high production yield, determined based on the specific PCB manufacturing process capabilities. This value varies depending on the process capabilities of different PCB manufacturers. For example, for standard processes of conventional flame-retardant copper-clad laminate (Flame Retardant Type 4, abbreviated as FR-4) boards, the minimum trace width may be 3mil or 4mil; for more advanced precision processes, the minimum trace width may reach 2mil or less. In the embodiments of this application, the specific value should be determined according to the design rules of the actual PCB manufacturing process. The example of 3mil is only for illustrative purposes, and the specific value of the minimum trace width allowed by the PCB design rules is not limited here.

[0068] Accordingly, taking the gold finger pad as an example, such as Figure 3 As shown, the first transmission line 32 is directly electrically connected to the target pad 31, such as the gold finger pad, and its line width is set to 3mil, which is the minimum line width allowed by the current conventional PCB process design rules; the second transmission line 33 also uses a 3mil line width, forming a thin line compensation segment of equal width with the first transmission line 32; the third transmission line 34 uses a conventional line width of 7mil, restoring to the standard impedance level.

[0069] In this embodiment, by setting the linewidth of the first transmission line to the minimum linewidth allowed by PCB design rules, and utilizing the characteristic that the minimum linewidth corresponds to the highest characteristic impedance, the low impedance caused by parasitic capacitance of the target pad can be maximized, thereby achieving the best impedance improvement effect. Secondly, using the minimum linewidth allowed by the design rules means full compatibility with existing PCB process capabilities without exceeding process limits or increasing equipment precision, thus pursuing the best compensation effect without increasing process difficulty and manufacturing costs. In addition, the minimum linewidth value is a known parameter in the design rules, which designers can directly use, further simplifying the design process while ensuring the reliability and repeatability of the design.

[0070] In some embodiments, the linewidth of the third transmission line is configured to have a target characteristic impedance, which is the same as the characteristic impedance of the signal transmission line in the non-pad area of ​​the PCB.

[0071] Here, target characteristic impedance refers to the standard impedance value set in the PCB design to achieve signal integrity, such as 50Ω or 85Ω commonly used for single-ended signals, or 85Ω or 100Ω commonly used for differential signals; signal transmission lines in non-pad areas refer to ordinary signal traces on the PCB that have not undergone special impedance optimization, i.e., normal transmission lines used in conventional designs. For example, combining... Figure 3The target pad 31 shown is, for example, a gold finger pad. The third transmission line 34 uses a standard line width, such as 7 mil, as in conventional designs. Under typical PCB stack-up and material parameters, the characteristic impedance corresponding to a 7 mil line width is approximately 85Ω. This is consistent with the 85Ω target impedance required by the PCIe interface standard and is also the same as the characteristic impedance of conventional signal transmission lines in other non-pad areas of the PCB. Through this design, the third transmission line 34 becomes a bridge connecting the compensation area and the conventional transmission area, achieving a smooth impedance transition.

[0072] It should be noted that the specific linewidth value of the third transmission line 34 is not fixed, but depends on various factors such as the PCB's layer stack-up structure, dielectric material, and reference layer distance. For example, for different layer stack-up designs, the linewidth required to achieve the target impedance of 85Ω may be 6mil, 7mil, or 8mil. Therefore, the core of this embodiment is to ensure that the characteristic impedance of the third transmission line 34 is consistent with the characteristic impedance of conventional signal lines on the PCB, rather than being limited to a specific linewidth value. Those skilled in the art can determine the actual linewidth required to achieve the target characteristic impedance based on specific PCB design parameters, using impedance calculation tools or design rules provided by the manufacturer.

[0073] For example, refer to Figure 3 In the impedance optimization design of the gold finger pads, the first transmission line 32 and the second transmission line 33 use a minimum line width of 3mil to form a high impedance compensation section, while the third transmission line 34 uses a line width of 7mil. This line width value is a normal line width that can achieve the target impedance of 85Ω, calculated based on the PCB stack-up, and is completely consistent with the line width and impedance of other conventional PCIe signal traces on the PCB. Therefore, the signal in the gold finger area, after fine-line compensation, can be smoothly connected to the back-end conventional signal network through the third transmission line 34, ensuring the impedance continuity of the entire transmission path.

[0074] In another application scenario, if the target pad 31 is a BGA pad and the target characteristic impedance of a conventional signal line on the PCB is 100Ω (such as some Ethernet interface standards), then the line width of the third transmission line 34 should be set to a line width value that can achieve 100Ω impedance under the PCB stack-up, consistent with other 100Ω signal traces outside the BGA area.

[0075] In this embodiment, by setting the linewidth of the third transmission line to have the same target characteristic impedance as the signal transmission line in the non-pad area of ​​the PCB, it ensures that the signal output from the pad compensation area can smoothly transition to the regular transmission area with a standard impedance. This reduces new signal reflections introduced by impedance abrupt changes, helping to ensure overall signal integrity. Furthermore, this design eliminates the need for an additional impedance matching network, simplifying PCB design and improving design efficiency. Additionally, based on the principle of "achieving the target characteristic impedance," the linewidth can be flexibly adjusted according to different PCB stack-ups and impedance standards (such as 50Ω, 85Ω, 100Ω, etc.), exhibiting good versatility.

[0076] In some embodiments, the side of the first transmission line is aligned with the corresponding side of the target pad.

[0077] Here, "side" refers to the two boundary lines of the transmission line and the pad along the signal transmission direction; "corresponding side" means that the left side of the transmission line corresponds to the left side of the pad, and the right side of the transmission line corresponds to the right side of the pad, forming a one-to-one alignment relationship.

[0078] For example, combined Figure 3 The pad structure 30 in the PCB shown has a first transmission line 32 that is directly electrically connected to a target pad 31, such as a gold finger pad. At the connection point, the left side of the first transmission line 32 is aligned with the left side of the target pad 31, and they are completely flush. The right side of the first transmission line 32 is also aligned with the right side of the target pad 31, and they are completely flush. This design ensures that there are no protruding or recessed "jagged" structures in the transition area from the target pad 31 to the first transmission line 32, forming a smooth boundary transition.

[0079] Taking specific numerical values ​​as an example, we will still refer to Figure 3 The gold finger pads have a relatively wide size (e.g., 12mil-20mil, depending on the gold finger design specifications), while the first transmission line 32 uses a thinner line width (e.g., 3mil). In an misaligned design, if the first transmission line 32 is connected to the left or right, it will cause a "step" or "gap" on one side. These geometric abrupt changes will introduce additional parasitic capacitance or inductance, exacerbating impedance discontinuities. However, the embodiments of this application align the two sides respectively, so that the connection always maintains a smooth boundary regardless of the width of the pads or the thinness of the transmission line, thereby minimizing structural abrupt changes.

[0080] In another implementation, if the target pad 31 is a BGA pad (usually circular or square), the above "side alignment" can be understood as the center line of the transmission line being aligned with the center line of the pad, and the two sides of the transmission line being symmetrically distributed relative to the center of the pad, which can also achieve a smooth boundary transition.

[0081] In this embodiment, by aligning the side of the first transmission line with the corresponding side of the target pad, a smooth boundary transition can be formed at the connection point. This reduces geometric abrupt changes such as "steps" or "gap" caused by off-center connections, helps reduce unnecessary impedance discontinuities, and effectively reduces the risk of signal reflection. Furthermore, this design conforms to PCB routing specifications, is easy to implement, and does not increase design complexity, improving signal integrity while ensuring engineering feasibility.

[0082] In some embodiments, the first included angle between the second transmission line segment and the first transmission line segment is 30° to 60°, and the second included angle between the second transmission line segment and the third transmission line segment is 30° to 60°.

[0083] In some embodiments, both the first included angle and the second included angle are 45°.

[0084] For example, the first angle between the second transmission line segment and the first transmission line segment is set to 45°, and the second angle between the second transmission line segment and the third transmission line segment is also set to 45°. Figure 3 Taking the pad structure 30 in the PCB shown as an example, the first transmission line 32 extends horizontally from the target pad 31, such as a gold finger pad. The second transmission line 33 is electrically connected to the first transmission line 32 at a 45° angle. The third transmission line 34 is also electrically connected to the second transmission line 33 horizontally, thus forming a "horizontal-45°-horizontal" trace path. With this design, the signal can change direction at a relatively gentle angle during transmission, reducing the severe reflections caused by right-angle bends.

[0085] It should be noted that the aforementioned 30° to 60° range is an optimal angle range verified through experiments or optimized through simulation. When the included angle is less than 30°, the routing transition is too gentle. Although signal reflection is small, it will occupy too much routing space, which is not conducive to high-density routing. When the included angle is greater than 60° (especially close to 90°), signal reflection increases significantly, affecting signal integrity. The 30° to 60° range (especially 45°) achieves a good balance between signal integrity and space utilization efficiency.

[0086] In practice, the setting of the first and second included angles should take into account the grid system of the PCB design tool and the limitations of the manufacturing process. For example, in commonly used PCB design software, 45° angle routing is the easiest to implement and the most commonly used non-right-angle turn because it aligns well with the design grid and is compatible with the process capabilities of most manufacturers.

[0087] In another implementation, if a 45° angle cannot be used due to space constraints, it can be flexibly adjusted within the range of 30° to 60°. For example, in a compact BGA fan-out area, a smaller angle of 30° or 35° can be used for routing; in areas with more space, an angle of 55° or 60° can be used.

[0088] It should be noted that the two included angles in the embodiments of this application can be the same or different. For example, the first included angle between the second transmission line 33 and the first transmission line 32 is 45°, and the second included angle between the second transmission line 33 and the third transmission line 34 is 50°. Both are within the range of 30° to 60°, and the technical effect of this application can be achieved in the same way. In practical applications, designers can flexibly configure the angles according to the specific wiring space and layout requirements.

[0089] In this embodiment, by controlling the angles between the second and first transmission lines and between the second and third transmission lines within the range of 30° to 60°, the transmission quality of high-speed signals is effectively improved, which helps to reduce impedance discontinuities caused by abrupt changes in direction. Furthermore, the 30° to 60° range (especially 45°) achieves a good balance between signal integrity and routing space utilization efficiency, ensuring the smoothness of the traces while avoiding excessive routing space occupied by excessively small angles. In addition, this angle range has good compatibility with the grid systems of mainstream PCB design tools, making design implementation easier and conforming to conventional PCB manufacturing process capabilities without increasing process difficulty.

[0090] Based on the above embodiments, in some embodiments, the pad structure in the PCB further includes: an anti-pad structure disposed on the PCB reference layer below the target pad.

[0091] Specifically, in this embodiment, a portion of the copper foil is removed from the reference layer (such as a power layer or ground layer) below the target pad to form an anti-pad structure, thereby increasing the spacing between the signal and the reference layer, further reducing parasitic capacitance, and helping to improve the impedance of the pad area, thus forming a synergistic optimization effect with the aforementioned fine-line compensation structure.

[0092] For example, Figure 4 Another schematic diagram of the pad structure in a PCB provided for an exemplary embodiment of this application. (See diagram below.) Figure 4 As shown, the pad structure in this PCB is Figure 3Based on the three-segment transmission line design shown, an anti-pad structure is further set on the PCB reference layer below the target pad 31. The figure shows the target pad 31 (e.g., a gold finger pad), the first transmission line 32, the second transmission line 33, the third transmission line 34, and the anti-pad structure 35. The first transmission line 32 is electrically connected to the target pad 31, and its width is smaller than the width of the target pad 31, for example, using the minimum allowable width of 3mil according to PCB design rules. The second transmission line 33 is electrically connected to the first transmission line 32, and its width is also smaller than the width of the target pad 31, for example, the same width as the first transmission line 32, also 3mil. The third transmission line 34 is electrically connected to the second transmission line 33, and its width is greater than the width of the second transmission line 33, for example, set to a width that gives the third transmission line 34 the target characteristic impedance, such as 7mil, corresponding to a target impedance of 85Ω.

[0093] and Figure 3 The structures shown are different, Figure 4 An anti-pad structure 35 is provided on the PCB reference layer (e.g., the power layer or ground layer adjacent to the signal layer) below the target pad 31. The anti-pad structure 35 is formed by removing copper foil from the reference layer in the area corresponding to the target pad 31, thereby increasing the dielectric thickness in the vertical direction between the target pad 31 and the reference layer. This is equivalent to increasing the spacing between the signal and the reference layer, thereby reducing parasitic capacitance.

[0094] It should be noted that the shape and size of the anti-pad structure 35 can be designed according to actual needs. In one implementation, the shape of the anti-pad structure 35 can match the shape of the target pad 31, for example, it can be rectangular, and its size is slightly larger than the size of the target pad 31, such as a gold finger pad, to ensure that the area below the pad structure is completely hollowed out. In another implementation, the size of the anti-pad structure 35 can be optimized according to the target impedance increase, and the optimal window size can be determined through simulation.

[0095] Accordingly, with Figure 2 The anti-pad structure shown in the related technology is used as a comparison. Figure 2 The same diagram shows an anti-pad structure below the pads, but its transmission lines still use a standard line width (e.g., 7mil) and no thin-line compensation segments are provided. Figure 4 The embodiment of this application shown combines the anti-pad structure with the three-segment fine-line compensation structure to achieve a dual optimization effect: on the one hand, the impedance is improved by the fine-line compensation of the first and second transmission lines, and on the other hand, the parasitic capacitance is further reduced by the anti-pad structure. The two work together to achieve a better impedance improvement effect than a single optimization scheme.

[0096] For example, Figure 5This is a schematic diagram comparing impedance values ​​corresponding to different impedance optimization schemes, provided as an exemplary embodiment of this application. For example... Figure 5 As shown, the scheme using only the anti-pad structure (i.e. Figure 2 The corresponding solution can increase the impedance of the target pad, such as the gold finger area, from 57.5291Ω (unoptimized, i.e., m1) to 75.5008Ω (i.e., m2); while this application uses a solution combining fine-line compensation and an anti-pad structure (such as...). Figure 4 As shown, the impedance can be further increased to 78.1329Ω (i.e., m3), which demonstrates the synergistic effect of combining the anti-pad structure with the fine-line compensation structure.

[0097] It should be noted that, in practice, the anti-pad structure can be set up after the three-segment transmission line layout is completed, or it can be done simultaneously as part of the overall design. Designers can complete the drawing and setting of the anti-pad structure during the impedance optimization process, according to the workflow of the PCB design tool.

[0098] In this embodiment, by setting an anti-pad structure on the PCB reference layer below the target pad, the spacing between the signal and the reference layer is increased, effectively reducing parasitic capacitance and thus helping to improve the impedance of the pad area. Furthermore, the anti-pad structure is a standard PCB design process, requiring no special equipment or materials, and does not increase additional cost or process difficulty, demonstrating good engineering feasibility. In addition, the window shape and size of the anti-pad structure can be flexibly adjusted according to actual needs. Designers can determine the optimal window parameters through simulation optimization to adapt to the requirements of different pad types, different stack-up structures, and different impedance targets, thereby achieving refined impedance matching design.

[0099] This application also provides a circuit board, including a substrate and at least one pad structure in a PCB as described in any of the above embodiments.

[0100] The circuit board provided in this application integrates the aforementioned pad structure. The pad area of ​​the circuit board adopts a three-segment fine-line compensation design, which effectively improves the characteristic impedance of wide pads, significantly improves the quality of high-speed signal transmission, and reduces signal reflection and attenuation. Secondly, the pad structure does not involve special materials and is realized entirely using conventional PCB substrates and standard processes, so its manufacturing cost is controllable and suitable for mass production. In addition, the circuit board can be widely used in various wide pad scenarios such as gold fingers, BGA, and connectors, and has good versatility and industrial practical value.

[0101] The above embodiments describe the pad structure in a PCB after impedance optimization. The following specific embodiments will illustrate how to optimize the pad impedance in a PCB.

[0102] Figure 6This is a flowchart illustrating a method for optimizing pad impedance in a PCB, provided as an exemplary embodiment of this application. The method for optimizing pad impedance in a PCB provided in this embodiment is used to optimize the pad structure in a PCB as described in any of the above embodiments. Figure 6 As shown, the method for optimizing the pad impedance in this PCB includes the following steps:

[0103] S601. Identify the target pads on the PCB.

[0104] For example, in one implementation, a pre-designed automated pad impedance optimization program can be packaged as a plugin and installed in the corresponding path of the PCB design tool. Further, a new menu item (e.g., "Pad Impedance Optimization") is added to the PCB design tool's menu bar to launch the automated program. Correspondingly, the user submits an optimization command for the pad impedance in the PCB through the client. The server responds to the optimization command by clicking the menu item, launching the automated program, and automatically identifying and determining the target pads to be optimized in the current PCB design file based on the program's preset algorithm logic. This preset logic may include filtering based on pad size thresholds, net type, or user-preset marked areas.

[0105] In another implementation, a pre-designed automated pad impedance optimization tool can be deployed independently on a server. Correspondingly, the user submits optimization commands for pad impedance in the PCB to the server via a client; the server responds to the command, runs the automated pad impedance optimization tool, and automatically parses the PCB design file based on the tool's preset rule engine to determine the target pads that meet the optimization criteria.

[0106] It should be noted that the target pads mentioned above can be pads within a specific area specified by the user, or all pads on all layers in the current PCB design file. There are no specific limitations on the number or selection range of target pads. Accordingly, the aforementioned automated program or tool can automatically determine the set of target pads to be optimized based on preset filtering conditions (such as pad size, net, layer, etc.).

[0107] S602. Lay out the first transmission line on the PCB and make the first transmission line electrically connected to the target pad. The line width of the first transmission line is smaller than the width of the target pad.

[0108] For example, see reference Figure 3The first transmission line is directly electrically connected to the target pad, such as the gold finger pad, and its line width is set to be smaller than the width of the gold finger pad, for example, 3 mil. Since the characteristic impedance of the transmission line is inversely proportional to its line width, the thinner the line width, the higher the characteristic impedance. Therefore, the first transmission line can form a high impedance region to offset the low capacitive impedance caused by the large width of the target pad.

[0109] S603. Lay out a second transmission line on the PCB and make the second transmission line electrically connected to the first transmission line. The line width of the second transmission line is smaller than the width of the target pad.

[0110] For example, such as Figure 3 As shown, the second transmission line is electrically connected to the first transmission line, and its line width is also set to be smaller than the width of the gold finger pad, such as 3mil or 4mil. By connecting the two thin lines in series, a sufficiently long high impedance compensation area can be formed, which can more effectively improve the overall characteristic impedance of the pad area.

[0111] S604. Lay out a third transmission line on the PCB and make the third transmission line electrically connected to the second transmission line. The line width of the third transmission line is greater than the line width of the second transmission line.

[0112] In this step, a wider transmission line is electrically connected after the thin-line compensation section to restore the transmission line to its normal impedance level, achieving a smooth transition from the pad compensation area to the normal transmission area. For example, such as... Figure 3 As shown, the third transmission line is electrically connected to the second transmission line, and its line width is set to be greater than that of the second transmission line, for example, 7mil.

[0113] Figure 7 This document provides another flowchart illustrating a method for optimizing pad impedance in a PCB, as an exemplary embodiment of this application. Figure 7 As shown, the method for optimizing the pad impedance in this PCB includes the following steps:

[0114] S701. Identify the target pads on the PCB.

[0115] S702. Lay out the first transmission line on the PCB and make the first transmission line electrically connected to the target pad. The line width of the first transmission line is smaller than the width of the target pad, and the side of the first transmission line is aligned with the corresponding side of the target pad.

[0116] The line width of the first transmission line is the minimum line width allowed by PCB design rules, such as 3mil.

[0117] S703. Lay out a second transmission line on the PCB and make the second transmission line electrically connected to the first transmission line. The line width of the second transmission line is smaller than the width of the target pad, and the included angle between the second transmission line and the first transmission line is 30° to 60°.

[0118] Preferably, the angle between the second transmission line segment and the first transmission line segment is 45°.

[0119] S704. Lay out a third transmission line on the PCB and make the third transmission line electrically connected to the second transmission line. The line width of the third transmission line is greater than the line width of the second transmission line, and the included angle between the second and third transmission lines is 30° to 60°.

[0120] Specifically, the linewidth of the third transmission line is configured to have a target characteristic impedance, which is the same as the characteristic impedance of the signal transmission lines in the non-pad area of ​​the PCB. For example, the third transmission line may have a 7mil linewidth.

[0121] Preferably, the angle between the second transmission line segment and the third transmission line segment is 45°.

[0122] S705. Deploy anti-pad structures on the PCB and position the anti-pad structures on the PCB reference layer below the target pads.

[0123] In summary, this application has at least the following advantages:

[0124] By setting the linewidths of the first and second transmission lines to be smaller than the width of the target pad, high-impedance thin segments are formed, effectively compensating for the impedance reduction caused by parasitic capacitance between the wide pad and the reference layer. This significantly improves the overall characteristic impedance of the pad area, bringing it close to the target impedance value, thereby improving signal integrity and helping to reduce reflection and attenuation in high-speed signal transmission. Simultaneously, since it does not involve the selection of special materials such as low-dielectric-constant materials, there is no increase in material costs; and the use of a conventional straight-line design ensures full compatibility with existing PCB manufacturing processes, reducing the implementation difficulty and impedance discontinuity risks associated with the high-precision process requirements of gradient line structures. Furthermore, by setting the linewidth of the third transmission line to be greater than that of the second transmission line, a smooth transition of the signal from the pad area to the conventional transmission area is ensured, contributing to overall impedance matching. This effectively optimizes the pad area impedance without increasing cost or process complexity, and can be widely applied to various wide-pad scenarios such as gold finger pads, BGA pads, and connector pads.

[0125] Figure 8 A schematic diagram of a device for optimizing pad impedance in a PCB provided as an exemplary embodiment of this application. Figure 8As shown, the pad impedance optimization device 80 in this PCB includes a determination module 81 and a processing module 82, wherein:

[0126] Module 81 is used to determine the target pads on the PCB.

[0127] Processing module 82 is used to lay a first transmission line on the PCB and electrically connect the first transmission line to the target pad, wherein the line width of the first transmission line is smaller than the width of the target pad; lay a second transmission line on the PCB and electrically connect the second transmission line to the first transmission line, wherein the line width of the second transmission line is smaller than the width of the target pad; and lay a third transmission line on the PCB and electrically connect the third transmission line to the second transmission line, wherein the line width of the third transmission line is greater than the line width of the second transmission line.

[0128] The PCB pad impedance optimization device provided in this application embodiment can execute the technical solution shown in the above-described PCB pad impedance optimization method embodiment. Its implementation principle and beneficial effects are similar, and will not be repeated here.

[0129] It should be noted that the division of the various modules in the above device is merely a logical functional division. In actual implementation, they can be fully or partially integrated into a single physical entity, or they can be physically separated. Furthermore, these modules can be implemented entirely in software via processing element calls; they can be fully implemented in hardware; or some modules can be implemented by processing element calls to software, while others are implemented in hardware. For example, a processing module can be a separate processing element, or it can be integrated into a chip within the device. Alternatively, it can be stored as program code in the device's memory, and its functions can be called and executed by a processing element. The implementation of other modules is similar. Moreover, these modules can be fully or partially integrated together, or they can be implemented independently. The processing element here can be an integrated circuit with signal processing capabilities. During implementation, each step of the above method or each of the above modules can be completed through integrated logic circuits in the hardware of the processor element or through software instructions.

[0130] For example, these modules can be one or more integrated circuits configured to implement the above methods, such as one or more Application Specific Integrated Circuits (ASICs), one or more Digital Signal Processors (DSPs), or one or more Field Programmable Gate Arrays (FPGAs). As another example, when a module is implemented using processing element scheduler code, the processing element can be a general-purpose processor, such as a Central Processing Unit (CPU) or other processor capable of calling program code. Furthermore, these modules can be integrated together as a System-On-a-Chip (SOC).

[0131] In the above embodiments, implementation can be achieved, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented in software, it can be implemented, in whole or in part, as a computer program product. A computer program product includes one or more computer instructions. When the computer instructions are loaded and executed on a computer, all or part of the flow or function according to the embodiments of this application is generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, Digital Subscriber Line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available media can be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., Digital Video Discs, DVDs), or semiconductor media (e.g., solid-state disks (SSDs)).

[0132] Figure 9 A schematic diagram of the structure of an electronic device provided as an exemplary embodiment of this application. For example... Figure 9 As shown, the electronic device 90 in this embodiment includes:

[0133] At least one processor 91; and a memory 92 communicatively connected to the at least one processor;

[0134] The memory 92 stores instructions that can be executed by at least one processor 91 to cause the electronic device to perform the method as described in any of the above embodiments.

[0135] Alternatively, the memory 92 can be either standalone or integrated with the processor 91.

[0136] The memory 92 may include high-speed random access memory (RAM) and may also include non-volatile memory, such as at least one disk storage device.

[0137] The processor 91 may be a central processing unit (CPU), an application-specific integrated circuit (ASIC), or one or more integrated circuits configured to implement the embodiments of this application. Specifically, when implementing the method for optimizing pad impedance in a PCB as described in the foregoing method embodiments, the electronic device may be, for example, a server or other electronic device with processing capabilities.

[0138] Optionally, the electronic device may also include a communication interface 93. In specific implementations, if the communication interface 93, memory 92, and processor 91 are implemented independently, they can be interconnected via a bus to complete communication. The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be categorized as address buses, data buses, control buses, etc., but this does not imply that there is only one bus or one type of bus.

[0139] Optionally, in a specific implementation, if the communication interface 93, memory 92, and processor 91 are integrated on a single chip, then the communication interface 93, memory 92, and processor 91 can communicate through an internal interface.

[0140] The implementation principle and technical effects of the electronic device provided in this embodiment can be found in the foregoing embodiments, and will not be repeated here.

[0141] This application also provides a computer-readable storage medium storing computer-executable instructions. When the computer-executable instructions are executed, they are used to implement the method steps as described in the above method embodiments. The specific implementation methods and technical effects are similar and will not be repeated here.

[0142] The aforementioned computer-readable storage media can be implemented from any type of volatile or non-volatile storage device or a combination thereof, such as Static Random Access Memory (SRAM), Electrically Erasable Programmable Read Only Memory (EEPROM), Erasable Programmable Read Only Memory (EPROM), Programmable Read Only Memory (PROM), Read Only Memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk. The readable storage medium can be any available medium accessible to a general-purpose or special-purpose computer.

[0143] An exemplary readable storage medium is coupled to a processor, enabling the processor to read information from and write information to the readable storage medium. Of course, the readable storage medium can also be a component of the processor. The processor and the readable storage medium can reside in an application-specific integrated circuit (ASIC). Alternatively, the processor and the readable storage medium can exist as discrete components in a pad impedance optimization device on a PCB.

[0144] This application also provides a computer program product, including a computer program, which, when executed, implements the method steps as described in the above method embodiments. The specific implementation and technical effects are similar and will not be repeated here.

[0145] Those skilled in the art will understand that all or part of the steps of the above-described method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When executed, the program performs the steps of the above-described method embodiments; and the aforementioned storage medium includes various media capable of storing program code, such as ROM, RAM, magnetic disks, or optical disks.

[0146] Finally, it should be noted that other embodiments of the invention will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This invention is intended to cover any variations, uses, or adaptations of the invention that follow the general principles of the invention and include common knowledge or customary techniques in the art not disclosed herein, and is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of the invention is limited only by the appended claims.

Claims

1. A pad structure in a PCB, characterized in that, include: The target pad is formed on the PCB; The first transmission line is electrically connected to the target pad, and the line width of the first transmission line is smaller than the width of the target pad; The second transmission line is electrically connected to the first transmission line, and the line width of the second transmission line is smaller than the width of the target pad. The third transmission line is electrically connected to the second transmission line, and the line width of the third transmission line is greater than that of the second transmission line.

2. The pad structure in the PCB according to claim 1, characterized in that, The line width of the second transmission line is the same as that of the first transmission line.

3. The pad structure in the PCB according to claim 1 or 2, characterized in that, The line width of the first transmission line is the minimum line width allowed by PCB design rules.

4. The pad structure in the PCB according to claim 1 or 2, characterized in that, The linewidth of the third transmission line is configured to give the third transmission line a target characteristic impedance, which is the same as the characteristic impedance of the signal transmission line in the non-pad area of ​​the PCB.

5. The pad structure in the PCB according to claim 1 or 2, characterized in that, The side of the first transmission line is aligned with the corresponding side of the target pad.

6. The pad structure in the PCB according to claim 1 or 2, characterized in that, The first included angle between the second transmission line segment and the first transmission line segment is 30° to 60°, and the second included angle between the second transmission line segment and the third transmission line segment is 30° to... .

7. The pad structure in the PCB according to claim 6, characterized in that, Both the first included angle and the second included angle are 45°.

8. The pad structure in the PCB according to claim 1 or 2, characterized in that, Also includes: An anti-pad structure is set on the PCB reference layer below the target pad.

9. A circuit board, characterized in that, It includes a substrate and at least one pad structure in a PCB as described in any one of claims 1 to 8.

10. A method for optimizing pad impedance in a PCB, characterized in that, The method for optimizing the pad structure in a PCB as described in any one of claims 1 to 8, wherein the method for optimizing the pad impedance in the PCB includes: Identify the target pads on the PCB; A first transmission line is laid on the PCB and electrically connected to the target pad. The line width of the first transmission line is smaller than the width of the target pad. A second transmission line is laid on the PCB and electrically connected to the first transmission line. The line width of the second transmission line is smaller than the width of the target pad. A third transmission line is laid on the PCB and electrically connected to the second transmission line. The line width of the third transmission line is greater than that of the second transmission line.

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