Real-time task scheduling method and system based on industrial internet of things, and medium

Abstract

The application discloses a real-time task scheduling method and system based on an industrial Internet of Things, and a medium, the method comprising: taking a heterogeneous two-level bitmap structure as a unique carrier of task priority and readiness state, incorporating corresponding heterogeneous two-level bitmap search fixed overhead, and completing provable real-time admission control of a newly-built task through a response time iteration criterion; a ready task that passes the provable real-time admission control completes heterogeneous two-level bitmap search within a limited clock cycle; when the heterogeneous two-level bitmap search identifies mutual exclusion lock competition and priority inversion risk, a deterministic bitmap migration protocol is executed through a processor atomic instruction, the readiness queue is physically migrated at the moment when priority inheritance takes effect through the deterministic bitmap migration protocol, the problem of inheritance taking effect but scheduling lagging is eliminated, and the response certainty of a control task in a resource competition scene is ensured.

Description

Technical Field

[0001] This invention relates to the field of industrial Internet of Things (IoT) technology, and specifically to a real-time task scheduling method, system, and medium based on industrial IoT. Background Technology

[0002] In industrial IoT scenarios, edge gateway devices need to handle multiple heterogeneous task loads simultaneously, such as time-sensitive network control commands, industrial bus data acquisition, and edge AI inference; the task scheduling latency of the real-time operating system directly determines the stability and security of the control system.

[0003] Currently, the industrial IoT real-time operating system scheduler mainly suffers from the following problems: 1. Industrial IoT edge devices need to handle heterogeneous workloads such as control tasks, data acquisition tasks, and protocol parsing tasks; when the number of tasks increases, the bitmap scheduler of the existing real-time operating system relies on linked list or array traversal for selecting multiple tasks of the same priority, and the worst-case scheduling delay is unpredictable.

[0004] 2. Existing real-time operating system response time analysis does not include bitmap search overhead as an independent term in the calculation model, which fails to meet the functional safety certification requirements of the Industrial Internet of Things.

[0005] 3. In industrial IoT scenarios, protocol parsing tasks frequently access shared tag models, and low-priority protocol tasks holding locks cause high-priority control tasks to be blocked, affecting the real-time performance of the control system.

[0006] 4. Industrial IoT edge devices need to synchronize with time-sensitive networks, but existing real-time operating system schedulers lack a deterministic synchronization mechanism with network time, and cannot guarantee that the scheduling time of control tasks is aligned with the time-sensitive network time window. Summary of the Invention

[0007] The present invention proposes a real-time task scheduling method, system, and medium based on the Industrial Internet of Things to solve the problems mentioned in the background.

[0008] To achieve the above objectives, the present invention adopts the following technical solution: The real-time task scheduling method based on the Industrial Internet of Things of the present invention includes the following steps: S1. Define priority rules and ready state marking rules, and build a heterogeneous two-level bitmap structure; S2. Based on the heterogeneous bilevel bitmap structure as the sole carrier of task priority and readiness status, the corresponding heterogeneous bilevel bitmap search fixed overhead is incorporated, and verifiable real-time admission control of new tasks is completed through response time iterative criteria. S3, a ready task that can verify the passage of real-time access control, completes the heterogeneous two-level bitmap search within a limited clock cycle; S4. When the heterogeneous two-level bitmap search identifies mutex lock contention and priority inversion risks, the deterministic bitmap migration protocol is executed through processor atomic instructions. S5. After the deterministic bitmap migration protocol completes the update of the ready state, the task context switch is completed based on the locked highest priority task information. S6. After the task context switch is completed, CPU control is transferred to the highest priority task.

[0009] Preferably, step S1 includes the following steps: Define a heterogeneous two-level bitmap structure including a priority bitmap and a task bitmap array, and generate a heterogeneous two-level bitmap standard carrier adapted to the target processor. Based on the heterogeneous two-level bitmap structure, the highest priority location is completed within one processor clock cycle using the processor's hardware instructions, generating hardware instruction mapping rules for bitmap operations. The overhead of fixed bitmap search is quantified based on hardware instruction mapping rules.

[0010] Preferably, step S2 includes the following steps: A scheduling timing constraint model is built based on the fixed bitmap search overhead as the core invariant. Based on the scheduling timing constraint model, input all parameters of the newly created industrial IoT heterogeneous task, and set the initial iteration value and convergence threshold. Based on the set full parameters and initial iteration values, multiple rounds of iterative calculations are performed. After each round of iteration, the absolute value of the difference between two adjacent iteration results is checked to see if it is not greater than the convergence threshold. If it is satisfied, the iteration is determined to be converged. After the iteration is converged, the upper bound of the calculated task response time is checked to see if it is not greater than the task relative deadline. If it is satisfied, the task admission is determined to be successful. Otherwise, the task creation request is rejected, and a task admission determination result is generated. Based on the task admission determination results and combined with the heterogeneous two-level bitmap structure, a unique priority number and bitmap slot are assigned to the admitted tasks, generating a one-to-one binding relationship table of task-priority-bitmap slot. At the same time, the upper bound parameter of the response time of the pre-verified tasks is fixed, forming a set of legal tasks that have passed admission.

[0011] Preferably, step S3 includes the following steps: At the standard scheduling trigger node that exits from an interrupt or returns from a system call, bitmap state synchronization is performed based on the binding relationship table: all admitted ready tasks are atomically set in the corresponding slots of the bitmap to generate a valid two-level bitmap after the ready state is synchronized. Based on the effective two-level bitmap and combined with the hardware instruction mapping rules, the first-level priority search is performed: the priority bitmap is scanned at the hardware level, and the highest priority position is located within one processor clock cycle to obtain the highest priority number. Based on the highest priority number, the corresponding highest priority task is indexed, and the second-level task search is performed again using hardware instructions: the ready task identifier is located within no more than 4 processor clock cycles, and the target ready task number is obtained. Based on the highest priority number and the target ready task number, a unique highest priority ready task is locked, and a context switch request signal triggered by scheduling is generated synchronously; at the same time, a full detection of mutex lock contention and priority inversion risks is completed, and the risk detection results are output.

[0012] Preferably, step S4 includes the following steps: Based on the risk detection results, the execution scenario is determined as follows: If it is confirmed that there is a scenario where a high-priority task is waiting for a mutex lock held by a low-priority task, the priority inheritance mechanism is immediately triggered. The effective priority of the low-priority task is calculated based on the highest priority. Transitive priority inheritance is also supported to ensure that the priority increase is completely transmitted along the lock waiting chain. Finally, the original priority and the target effective priority of the task to be migrated are generated. Based on the original priority of the task to be migrated and the effective priority of the target, perform the original priority bitmap update: atomically clear the ready bits of low-priority tasks in the task bitmap array corresponding to the original priority; after clearing, check whether there are still other ready tasks under the original priority. If not, synchronously and atomically clear the priority bits corresponding to the task to be migrated in the priority bitmap, and generate the original priority bitmap update result. Based on the update result of the original priority bitmap, perform an atomic update of the new priority bitmap: atomically place the ready bit of the task to be migrated into the task bitmap array corresponding to the promoted effective priority; synchronously atomically set the priority existence bit corresponding to the target effective priority in the priority bitmap, and generate a two-level bitmap after the migration is completed; Based on the completed bi-level bitmap, a full state consistency check is performed. After the check passes, the information of the highest priority ready task is corrected and output. At the same time, the upper bound of the task blocking time after priority inversion suppression is generated.

[0013] Preferably, step S5 includes the following steps: Based on the highest priority task information, perform a context switching trigger verification: compare the priority of the currently running task with the final locked highest priority. If the current task has a lower priority, then formally trigger the context switching process and generate a context switching trigger signal. Based on the context switching trigger signal, perform current task context saving: In accordance with the architecture specifications of the target processor platform, fully save all context information of the currently running task, such as general-purpose registers, floating-point registers, stack pointers, program counters, etc., store them in the private stack space corresponding to the task, and generate a confirmation result that the current task context saving is complete. Based on the confirmation result of the current task context, perform target task context restoration: read and fully restore the register context, stack pointer and program counter of the highest priority ready task from the private stack space of the highest priority ready task, complete the full reconstruction of the task execution environment, and generate the execution environment of the highest priority task. Based on the highest priority task's execution environment, the execution status is updated synchronously: the corresponding task's execution status marker in the bilevel bitmap is updated synchronously, a consistent bilevel bitmap after task execution status synchronization is generated, and CPU execution permissions are pre-allocated at the same time.

[0014] Preferably, step S6 includes the following steps: Based on the highest priority task's runtime environment and the pre-allocation of CPU runtime permissions, the final control transfer is performed: the CPU control is completely transferred to the highest priority ready task that has completed runtime environment reconstruction, the task is formally executed according to preset logic, and a start signal for the formal execution of the task is generated. Based on the upper bound parameter of the task response time, perform TSN time synchronization coordination: link with the gPTP time synchronization mechanism to obtain the gPTP global timestamp in real time; when it is detected that the upper bound of the current task's scheduling delay is close to the boundary of the gPTP synchronization period, the scheduler is triggered to actively relinquish CPU control and wait for the next gPTP synchronization time window to generate the time-synchronized scheduling control result. When a task is completed, blocked, or suspended, a closed-loop update of the bitmap state is performed: according to the defined bitmap operation specifications, the ready or blocked state of the corresponding task in the bilevel bitmap is atomically updated, and the updated bilevel bitmap is generated. Based on the full-process scheduling execution data, bitmap state change records, and actual task response time data, a full archive is executed to generate operational data with controllable scheduling cycle jitter.

[0015] Preferably, the scheduling timing constraint model is as follows:

[0016] in, For the task In the Upper bound of response time after the next iteration For the task Worst execution time For the task The upper bound of the maximum blocking time due to priority inversion For all tasks above Priority task set, This is the task identifier for high-priority tasks. High priority task The task cycle, High priority task Worst execution time In response time Internal, high-priority tasks For the task The maximum number of disturbances generated, For context switching overhead time, Interruption response time is consumed. This represents the cost of bitmap search.

[0017] A real-time task scheduling system based on the Industrial Internet of Things includes: The heterogeneous bilevel bitmap maintenance module is used to define priority rules and ready state marking rules, and to build a heterogeneous bilevel bitmap structure. The verifiable real-time admission control module is used to incorporate the heterogeneous bi-level bitmap structure as the sole carrier of task priority and readiness status, incorporate the fixed overhead of searching the corresponding heterogeneous bi-level bitmap, and complete the verifiable real-time admission control of new tasks through response time iterative criteria. The deterministic search module is used to verify the pass of real-time access control for ready tasks, and completes the heterogeneous two-level bitmap search within a limited clock cycle. The deterministic bitmap migration protocol module is used to complete the execution of the deterministic bitmap migration protocol through processor atomic instructions when the heterogeneous two-level bitmap search identifies mutex lock contention and priority flip risks. The context switching module is used to perform task context switching based on the locked highest priority task information after the deterministic bitmap migration protocol has completed the update of the ready state. After the task context switching is completed, CPU control is transferred to the highest priority task.

[0018] In another aspect, the present invention also discloses a computer-readable storage medium storing a computer program, which, when executed by a processor, causes the processor to perform the steps of the method described above.

[0019] As can be seen from the above technical solution, the present invention provides a real-time task scheduling method based on the Industrial Internet of Things. Compared with the prior art, the present invention has the following advantages: 1. This invention reduces the scheduling algorithm complexity to strict determinism through a heterogeneous two-level bitmap architecture, with bitmap search overhead not exceeding 8 processor instruction cycles, thus meeting the deterministic scheduling requirements in industrial IoT scenarios.

[0020] 2. By incorporating the bitmap search overhead as a fixed value into the upper bound calculation model of scheduling delay, this invention enables the worst-case upper bound of scheduling delay to be verified during the system design phase, thus meeting the functional safety certification requirements of the Industrial Internet of Things.

[0021] 3. This invention uses a deterministic bitmap migration protocol to complete the physical migration of the ready queue the instant priority inheritance takes effect, eliminating the problem of scheduling lag despite inheritance taking effect, and ensuring the deterministic response of control tasks in resource contention scenarios.

[0022] 4. The upper limit of the scheduling delay of this invention can be synchronized with the time of the time-sensitive network, ensuring that the scheduling time of the control task is aligned with the network time window in the industrial Ethernet time-sensitive network. Attached Figure Description

[0023] Figure 1 This is a flowchart illustrating the real-time task scheduling method based on the Industrial Internet of Things (IIoT) of the present invention.

[0024] Figure 2 This is a logical architecture diagram of the real-time task scheduling method based on the Industrial Internet of Things of the present invention.

[0025] Figure 3 This is a system block diagram of the real-time task scheduling system based on the Industrial Internet of Things of the present invention. Detailed Implementation

[0026] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are some embodiments of the present invention, but not all embodiments.

[0027] like Figure 1 As shown, the real-time task scheduling method based on the Industrial Internet of Things in this embodiment includes the following steps: S1. Define priority rules and ready state marking rules, and build a heterogeneous two-level bitmap structure; S2. Based on the heterogeneous bilevel bitmap structure as the sole carrier of task priority and readiness status, the corresponding heterogeneous bilevel bitmap search fixed overhead is incorporated, and verifiable real-time admission control of new tasks is completed through response time iterative criteria. S3, a ready task that can verify the passage of real-time access control, completes the heterogeneous two-level bitmap search within a limited clock cycle; S4. When the heterogeneous two-level bitmap search identifies mutex lock contention and priority inversion risks, the deterministic bitmap migration protocol is executed through processor atomic instructions. S5. After the deterministic bitmap migration protocol completes the update of the ready state, the task context switch is completed based on the locked highest priority task information. S6. After the task context switch is completed, CPU control is transferred to the highest priority task.

[0028] This embodiment is applied to the multi-unit coordinated control system of a 3×50MW back-pressure heating unit in a thermal power plant; the system hardware platform adopts a domestically produced ARM Cortex-M55 processor and runs the time-sensitive heterogeneous bitmap real-time task scheduling system described in this invention.

[0029] Furthermore, S1 includes the following steps: Define a heterogeneous two-level bitmap structure including a priority bitmap and a task bitmap array, and generate a heterogeneous two-level bitmap standard carrier adapted to the target processor. The heterogeneous bilevel bitmap structure is as follows: / / Priority bitmap: 4 64-bit unsigned integers, supporting 256 priorities typedef struct { uint64_t word[4]; / / word[0]: priority 0-63, word[1]: priority 64-127, ... Bitmap_P_t; / / Task bitmap array: Each priority level corresponds to 4 64-bit unsigned integers typedef struct { uint64_t task_bits

[256] [4]; / / Supports 256 tasks per priority level Bitmap_T_t; Based on the heterogeneous two-level bitmap structure, the highest priority location is completed within one processor clock cycle using the processor's hardware instructions, generating hardware instruction mapping rules for bitmap operations. The overhead of fixed bitmap search is quantified based on hardware instruction mapping rules.

[0030] The code for implementing priority search using the CLZ instruction is as follows: / / ARM Cortex-M55 Platform Implementation static inline uint8_t find_highest_priority(Bitmap_P_t *bmp) { for (int i = 0; i<4; i++) { if (bmp->word[i] != 0) { / / CLZ instruction: Calculate the number of leading zeros uint8_t lz = __CLZ(bmp->word[i]); return (i * 64) + (63 - lz); } } return 255; / / No ready tasks }; Furthermore, S2 includes the following steps: A scheduling timing constraint model is built based on the fixed bitmap search overhead as the core invariant. Based on the scheduling timing constraint model, input all parameters of the newly created industrial IoT heterogeneous task, and set the initial iteration value and convergence threshold. Based on the set full parameters and initial iteration values, multiple rounds of iterative calculations are performed. After each round of iteration, the absolute value of the difference between two adjacent iteration results is checked to see if it is not greater than the convergence threshold. If it is satisfied, the iteration is determined to be converged. After the iteration is converged, the upper bound of the calculated task response time is checked to see if it is not greater than the task relative deadline. If it is satisfied, the task admission is determined to be successful. Otherwise, the task creation request is rejected, and a task admission determination result is generated. Based on the task admission determination results and combined with the heterogeneous two-level bitmap structure, a unique priority number and bitmap slot are assigned to the admitted tasks, generating a one-to-one binding relationship table of task-priority-bitmap slot. At the same time, the upper bound parameter of the response time of the pre-verified tasks is fixed, forming a set of legal tasks that have passed admission.

[0031] Furthermore, S3 includes the following steps: At the standard scheduling trigger node that exits from an interrupt or returns from a system call, bitmap state synchronization is performed based on the binding relationship table: all admitted ready tasks are atomically set in the corresponding slots of the bitmap to generate a valid two-level bitmap after the ready state is synchronized. Based on the effective two-level bitmap and combined with the hardware instruction mapping rules, the first-level priority search is performed: the priority bitmap is scanned at the hardware level, and the highest priority position is located within one processor clock cycle to obtain the highest priority number. Based on the highest priority number, the corresponding highest priority task is indexed, and the second-level task search is performed again using hardware instructions: the ready task identifier is located within no more than 4 processor clock cycles, and the target ready task number is obtained. Based on the highest priority number and the target ready task number, a unique highest priority ready task is locked, and a context switch request signal triggered by scheduling is generated synchronously; at the same time, a full detection of mutex lock contention and priority inversion risks is completed, and the risk detection results are output.

[0032] like Figure 2 As shown, step S4 includes the following steps: Based on the risk detection results, the execution scenario is determined as follows: If it is confirmed that there is a scenario where a high-priority task is waiting for a mutex lock held by a low-priority task, the priority inheritance mechanism is immediately triggered. The effective priority of the low-priority task is calculated based on the highest priority. Transitive priority inheritance is also supported to ensure that the priority increase is completely transmitted along the lock waiting chain. Finally, the original priority and the target effective priority of the task to be migrated are generated. Based on the original priority of the task to be migrated and the effective priority of the target, perform the original priority bitmap update: atomically clear the ready bits of low-priority tasks in the task bitmap array corresponding to the original priority; after clearing, check whether there are still other ready tasks under the original priority. If not, synchronously and atomically clear the priority bits corresponding to the task to be migrated in the priority bitmap, and generate the original priority bitmap update result. Based on the update result of the original priority bitmap, perform an atomic update of the new priority bitmap: atomically place the ready bit of the task to be migrated into the task bitmap array corresponding to the promoted effective priority; synchronously atomically set the priority existence bit corresponding to the target effective priority in the priority bitmap, and generate a two-level bitmap after the migration is completed; Based on the completed bi-level bitmap, a full state consistency check is performed. After the check passes, the information of the highest priority ready task is corrected and output. At the same time, the upper bound of the task blocking time after priority inversion suppression is generated.

[0033] Example of atomic migration code: Deterministic Bitmap Migration Protocol void dbmp_migrate(uint8_t tid, uint8_t p_old, uint8_t p_new) { uint32_t primask = __get_PRIMASK(); __disable_irq(); / / Disables interrupts to ensure atomicity / / Clear the original priority bitmap Bitmap_T.task_bits[p_old][tid / 64]&= ~(1ULL<<(tid % 64)); / / Check if the original priority is empty bool p_old_empty = true; for (int i = 0; i<4; i++) { if (Bitmap_T.task_bits[p_old][i]!= 0) { p_old_empty = false; break } } / / Update priority bit if (p_old_empty) { Bitmap_P.word[p_old / 64]&= ~(1ULL<<(p_old % 64)); } / / Set the new priority bitmap Bitmap_T.task_bits[p_new][tid / 64]|= (1ULL<<(tid % 64)); Bitmap_P.word[p_new / 64] |= (1ULL<<(p_new % 64)); __set_PRIMASK(primask); / / Restore interrupted state }; The actual performance data measured on the intelligent heating unit's field controller GD32F450@200MHz is shown in the table below:

[0034] The following table compares the technology with existing technologies:

[0035] In summary, the verification results after 30 days of continuous operation of Unit 3 in a certain thermal power plant are as follows: Control cycle stability: Main steam temperature control cycle fluctuation <5μs, less than the required 50μs; Task deadline fulfillment rate: 100%; Priority flip suppression effect: Maximum blocking time reduced from 120μs to 35μs; System availability: 99.99%, with only planned downtime for maintenance; Test environment: ambient temperature 25±5℃, relative humidity 45%—75%, power supply voltage 24V DC±5%.

[0036] Furthermore, S5 includes the following steps: Based on the highest priority task information, perform a context switching trigger verification: compare the priority of the currently running task with the final locked highest priority. If the current task has a lower priority, then formally trigger the context switching process and generate a context switching trigger signal. Based on the context switching trigger signal, perform current task context saving: In accordance with the architecture specifications of the target processor platform, fully save all context information of the currently running task, such as general-purpose registers, floating-point registers, stack pointers, program counters, etc., store them in the private stack space corresponding to the task, and generate a confirmation result that the current task context saving is complete. Based on the confirmation result of the current task context, perform target task context restoration: read and fully restore the register context, stack pointer and program counter of the highest priority ready task from the private stack space of the highest priority ready task, complete the full reconstruction of the task execution environment, and generate the execution environment of the highest priority task. Based on the highest priority task's execution environment, the execution status is updated synchronously: the corresponding task's execution status marker in the bilevel bitmap is updated synchronously, a consistent bilevel bitmap after task execution status synchronization is generated, and CPU execution permissions are pre-allocated at the same time.

[0037] Furthermore, S6 includes the following steps: Based on the highest priority task's runtime environment and the pre-allocation of CPU runtime permissions, the final control transfer is performed: the CPU control is completely transferred to the highest priority ready task that has completed runtime environment reconstruction, the task is formally executed according to preset logic, and a start signal for the formal execution of the task is generated. Based on the upper bound parameter of the task response time, perform TSN time synchronization coordination: link with the gPTP time synchronization mechanism to obtain the gPTP global timestamp in real time; when it is detected that the upper bound of the current task's scheduling delay is close to the boundary of the gPTP synchronization period, the scheduler is triggered to actively relinquish CPU control and wait for the next gPTP synchronization time window to generate the time-synchronized scheduling control result. When a task is completed, blocked, or suspended, a closed-loop update of the bitmap state is performed: according to the defined bitmap operation specifications, the ready or blocked state of the corresponding task in the bilevel bitmap is atomically updated, and the updated bilevel bitmap is generated. Based on the full-process scheduling execution data, bitmap state change records, and actual task response time data, a full archive is executed to generate operational data with controllable scheduling cycle jitter.

[0038] Furthermore, the scheduling timing constraint model is as follows:

[0039] in, For the task In the Upper bound of response time after the next iteration For the task Worst execution time For the task The upper bound of the maximum blocking time due to priority inversion For all tasks above Priority task set, This is the task identifier for high-priority tasks. High priority task The task cycle, High priority task Worst execution time For high-priority tasks within the response time Rn(k) For the task The maximum number of disturbances generated, For context switching overhead time, Interruption response time is consumed. This represents the cost of bitmap search.

[0040] like Figure 3 As shown, a real-time task scheduling system based on the Industrial Internet of Things includes: The heterogeneous bilevel bitmap maintenance module is used to define priority rules and ready state marking rules, and to build a heterogeneous bilevel bitmap structure. The verifiable real-time admission control module is used to incorporate the heterogeneous bi-level bitmap structure as the sole carrier of task priority and readiness status, incorporate the fixed overhead of searching the corresponding heterogeneous bi-level bitmap, and complete the verifiable real-time admission control of new tasks through response time iterative criteria. The deterministic search module is used to verify the pass of real-time access control for ready tasks, and completes the heterogeneous two-level bitmap search within a limited clock cycle. The deterministic bitmap migration protocol module is used to complete the execution of the deterministic bitmap migration protocol through processor atomic instructions when the heterogeneous two-level bitmap search identifies mutex lock contention and priority flip risks. The context switching module is used to perform task context switching based on the locked highest priority task information after the deterministic bitmap migration protocol has completed the update of the ready state. After the task context switching is completed, CPU control is transferred to the highest priority task.

[0041] In another aspect, the present invention also discloses a computer-readable storage medium storing a computer program, which, when executed by a processor, causes the processor to perform the steps of the method described above.

[0042] In the above embodiments, implementation can be achieved, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented in software, it can be implemented, in whole or in part, as a computer program product. A computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the flow or function according to the embodiments of this application is generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid-state disk), etc.

[0043] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes the element.

[0044] The various embodiments in this specification are described in a related manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the system embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions of the method embodiments.

[0045] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A real-time task scheduling method based on the Industrial Internet of Things, characterized in that, Includes the following steps: S1. Define priority rules and ready state marking rules, and build a heterogeneous two-level bitmap structure; S2. Based on the heterogeneous bilevel bitmap structure as the sole carrier of task priority and readiness status, the corresponding heterogeneous bilevel bitmap search fixed overhead is incorporated, and verifiable real-time admission control of new tasks is completed through response time iterative criteria. S3, a ready task that can verify the passage of real-time access control, completes the heterogeneous two-level bitmap search within a limited clock cycle; S4. When the heterogeneous two-level bitmap search identifies mutex lock contention and priority inversion risks, the deterministic bitmap migration protocol is executed through processor atomic instructions. S5. After the deterministic bitmap migration protocol completes the update of the ready state, the task context switch is completed based on the locked highest priority task information. S6. After the task context switch is completed, CPU control is transferred to the highest priority task.

2. The real-time task scheduling method based on the Industrial Internet of Things according to claim 1, characterized in that: S1 includes the following steps: Define a heterogeneous two-level bitmap structure including a priority bitmap and a task bitmap array, and generate a heterogeneous two-level bitmap standard carrier adapted to the target processor. Based on the heterogeneous two-level bitmap structure, the highest priority location is completed within one processor clock cycle using the processor's hardware instructions, generating hardware instruction mapping rules for bitmap operations. The overhead of fixed bitmap search is quantified based on hardware instruction mapping rules.

3. The real-time task scheduling method based on the Industrial Internet of Things according to claim 2, characterized in that: S2 includes the following steps: A scheduling timing constraint model is built based on the fixed bitmap search overhead as the core immutable variable. Based on the scheduling timing constraint model, input all parameters of the newly created industrial IoT heterogeneous task, and set the initial iteration value and convergence threshold. Based on the set full parameters and initial iteration values, multiple rounds of iterative calculations are performed. After each round of iteration, the absolute value of the difference between two adjacent iteration results is checked to see if it is not greater than the convergence threshold. If it is satisfied, the iteration is determined to be converged. After the iteration is converged, the upper bound of the calculated task response time is checked to see if it is not greater than the task relative deadline. If it is satisfied, the task admission is determined to be successful. Otherwise, the task creation request is rejected, and a task admission determination result is generated. Based on the task admission determination results and combined with the heterogeneous two-level bitmap structure, a unique priority number and bitmap slot are assigned to the admitted tasks, generating a one-to-one binding relationship table of task-priority-bitmap slot. At the same time, the upper bound parameter of the response time of the pre-verified tasks is fixed, forming a set of legal tasks that have passed admission.

4. The real-time task scheduling method based on the Industrial Internet of Things according to claim 3, characterized in that: S3 includes the following steps: At the standard scheduling trigger node that exits from an interrupt or returns from a system call, bitmap state synchronization is performed based on the binding relationship table: all admitted ready tasks are atomically set in the corresponding slots of the bitmap to generate a valid two-level bitmap after the ready state is synchronized. Based on the effective two-level bitmap and combined with the hardware instruction mapping rules, the first-level priority search is performed: the priority bitmap is scanned at the hardware level, and the highest priority position is located within one processor clock cycle to obtain the highest priority number. Based on the highest priority number, the corresponding highest priority task is indexed, and the second-level task search is performed again using hardware instructions: the ready task identifier is located within no more than 4 processor clock cycles, and the target ready task number is obtained. Based on the highest priority number and the target ready task number, a unique highest priority ready task is locked, and a context switch request signal triggered by scheduling is generated synchronously; at the same time, a full detection of mutex lock contention and priority inversion risks is completed, and the risk detection results are output.

5. The real-time task scheduling method based on the Industrial Internet of Things according to claim 4, characterized in that: S4 includes the following steps: Based on the risk detection results, the execution scenario is determined as follows: If it is confirmed that there is a scenario where a high-priority task is waiting for a mutex lock held by a low-priority task, the priority inheritance mechanism is immediately triggered. The effective priority of the low-priority task is calculated based on the highest priority. Transitive priority inheritance is also supported to ensure that the priority increase is completely transmitted along the lock waiting chain. Finally, the original priority and the target effective priority of the task to be migrated are generated. Based on the original priority of the task to be migrated and the effective priority of the target, perform the original priority bitmap update: atomically clear the ready bits of low-priority tasks in the task bitmap array corresponding to the original priority; after clearing, check whether there are still other ready tasks under the original priority. If not, synchronously and atomically clear the priority bits corresponding to the task to be migrated in the priority bitmap, and generate the original priority bitmap update result. Based on the update result of the original priority bitmap, perform an atomic update of the new priority bitmap: atomically place the ready bit of the task to be migrated into the task bitmap array corresponding to the promoted effective priority; synchronously atomically set the priority existence bit corresponding to the target effective priority in the priority bitmap, and generate a two-level bitmap after the migration is completed; Based on the completed bi-level bitmap, a full state consistency check is performed. After the check passes, the information of the highest priority ready task is corrected and output. At the same time, the upper bound of the task blocking time after priority inversion suppression is generated.

6. The real-time task scheduling method based on the Industrial Internet of Things according to claim 5, characterized in that: S5 includes the following steps: Based on the highest priority task information, perform a context switching trigger verification: compare the priority of the currently running task with the final locked highest priority. If the current task has a lower priority, then formally trigger the context switching process and generate a context switching trigger signal. Based on the context switching trigger signal, perform current task context saving: In accordance with the architecture specifications of the target processor platform, fully save all context information of the currently running task, such as general-purpose registers, floating-point registers, stack pointers, program counters, etc., store them in the private stack space corresponding to the task, and generate a confirmation result that the current task context saving is complete. Based on the confirmation result of the current task context, perform target task context restoration: read and fully restore the register context, stack pointer and program counter of the highest priority ready task from the private stack space of the highest priority ready task, complete the full reconstruction of the task execution environment, and generate the execution environment of the highest priority task. Based on the highest priority task's execution environment, the execution status is updated synchronously: the corresponding task's execution status marker in the bilevel bitmap is updated synchronously, a consistent bilevel bitmap after task execution status synchronization is generated, and CPU execution permissions are pre-allocated at the same time.

7. The real-time task scheduling method based on the Industrial Internet of Things according to claim 6, characterized in that: S6 includes the following steps: Based on the highest priority task's runtime environment and the pre-allocation of CPU runtime permissions, the final control transfer is performed: the CPU control is completely transferred to the highest priority ready task that has completed runtime environment reconstruction, the task is formally executed according to preset logic, and a start signal for the formal execution of the task is generated. Based on the upper bound parameter of the task response time, perform TSN time synchronization coordination: link with the gPTP time synchronization mechanism to obtain the gPTP global timestamp in real time; when it is detected that the upper bound of the current task's scheduling delay is close to the boundary of the gPTP synchronization period, the scheduler is triggered to actively relinquish CPU control and wait for the next gPTP synchronization time window to generate the time-synchronized scheduling control result. When a task is completed, blocked, or suspended, a closed-loop update of the bitmap state is performed: according to the defined bitmap operation specifications, the ready or blocked state of the corresponding task in the bilevel bitmap is atomically updated, and the updated bilevel bitmap is generated. Based on the full-process scheduling execution data, bitmap state change records, and actual task response time data, a full archive is executed to generate operational data with controllable scheduling cycle jitter.

8. The real-time task scheduling method based on the Industrial Internet of Things according to claim 7, characterized in that: The scheduling timing constraint model is as follows: in, For the task In the Upper bound of response time after the next iteration For the task Worst execution time For the task The upper bound of the maximum blocking time due to priority inversion For all tasks above Priority task set, This is the task identifier for high-priority tasks. High priority task The task cycle, High priority task Worst execution time In response time Internal, high-priority tasks For the task The maximum number of disturbances generated, For context switching overhead time, Interruption response time is consumed. This represents the cost of bitmap search.

9. A real-time task scheduling system based on the Industrial Internet of Things (IIoT), employing the real-time task scheduling method based on the Industrial Internet of Things as described in any one of claims 1-8, characterized in that, include: The heterogeneous bilevel bitmap maintenance module is used to define priority rules and ready state marking rules, and to build a heterogeneous bilevel bitmap structure. The verifiable real-time admission control module is used to incorporate the heterogeneous bi-level bitmap structure as the sole carrier of task priority and readiness status, incorporate the fixed overhead of searching the corresponding heterogeneous bi-level bitmap, and complete the verifiable real-time admission control of new tasks through response time iterative criteria. The deterministic search module is used to verify the pass of real-time access control for ready tasks, and completes the heterogeneous two-level bitmap search within a limited clock cycle. The deterministic bitmap migration protocol module is used to complete the execution of the deterministic bitmap migration protocol through processor atomic instructions when the heterogeneous two-level bitmap search identifies mutex lock contention and priority flip risks. The context switching module is used to perform task context switching based on the locked highest priority task information after the deterministic bitmap migration protocol has completed the update of the ready state. After the task context switch is complete, CPU control is transferred to the highest priority task.

10. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by a processor, it causes the processor to perform the steps of the method as described in any one of claims 1 to 8.

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