Circuit for testing power semiconductors and control method, test method

Abstract

This application relates to the field of semiconductor manufacturing technology, proposing a circuit and control method for testing power semiconductors, as well as a testing method. The circuit for testing power semiconductors includes at least three sets of inverters and a three-phase power coupling unit with at least three sets of ports. The DC terminals of the at least three sets of inverters are interconnected to form a common DC bus. Each set of ports of the three-phase power coupling unit is connected to the AC terminal of the corresponding inverter. At least two of the at least three sets of inverters contain the power semiconductor device under test. The inverter includes a DC capacitor unit, an AC filter unit, and a three-phase bridge circuit. The AC filter unit is an L-type filter, an LC-type filter, an LCL-type filter, or an LC combination filter. The topology of the three-phase bridge circuit is a two-level topology, a three-level topology, a multi-level topology, an H-bridge topology, or an H-bridge combination. This method enables active power testing of power semiconductor devices, improves testing accuracy and reliability, and enhances the flexibility of power semiconductor device testing methods.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing technology, and in particular to a circuit and control method for testing power semiconductors, and a testing method. Background Technology

[0002] In the field of power semiconductor manufacturing, in order to ensure the reliability of power semiconductor devices, it is usually required to conduct aging tests on the devices to obtain the actual application conditions of the devices, so as to simulate the operating state of the devices in real working scenarios and verify their long-term stability.

[0003] Currently, most power semiconductor device tests in the industry employ reactive power testing. This method covers a limited range of operating conditions and cannot encompass the complex and varied operating conditions of power semiconductors in real-world applications. Furthermore, the reactive power testing conditions differ significantly from the actual application conditions of the devices, making it difficult to reflect the device's performance and aging trends under real-world operating conditions, and thus failing to meet the requirements for high-precision and high-reliability testing. Therefore, there is an urgent need to propose a novel technical solution to address at least one of the technical problems in this field. Summary of the Invention

[0004] This application addresses the technical problems existing in the prior art by providing a circuit and control method for testing power semiconductors, as well as a testing method, to realize active power testing of power semiconductor devices, improve the testing accuracy and reliability of device operating condition results, and enhance the flexibility of power semiconductor device testing methods.

[0005] The aforementioned power semiconductors include IGBTs, MOSFETs, silicon carbide MOSFETs, thyristors (SCRs), GaN HEMTs, diodes, etc.

[0006] In a first aspect, embodiments of this application provide a circuit for testing power semiconductors, including at least three sets of inverters and a three-phase power coupling unit having at least three sets of ports;

[0007] The DC terminals of the at least three sets of inverters are interconnected to form a common DC bus.

[0008] Each group of ports of the three-phase power coupling unit is connected to the AC terminal of the corresponding inverter.

[0009] At least one of the at least three sets of inverters contains the power semiconductor device under test;

[0010] The inverter includes a DC capacitor unit, an AC filter unit, and a three-phase bridge circuit; the AC filter unit is an L-type filter, an LC-type filter, an LCL-type filter, or an LC combination filter; the topology of the three-phase bridge circuit is a two-level topology, a three-level topology, a multi-level topology, an H-bridge topology, or an H-bridge combination.

[0011] Secondly, embodiments of this application provide a control method for testing power semiconductors. This method is applied to the circuit for testing power semiconductors provided in the first aspect, and includes the following steps:

[0012] Select at least one inverter containing the power semiconductor device under test from at least three groups of inverters as the inverter under test;

[0013] When the inverter under test outputs positive power, the negative power output value of the remaining inverters in at least three groups of inverters is adjusted based on the common DC bus power, and power matching is achieved by relying on the three-phase power coupling unit, so that the inverter outputting positive power reaches the set test stress.

[0014] When the inverter under test outputs negative power, the positive power output of the remaining inverters is adjusted based on the common DC bus, and power matching is achieved by relying on the three-phase power coupling unit, so that the inverter that outputs negative power reaches the set test stress.

[0015] Alternatively, at least two inverters containing the power semiconductor device under test can be selected from at least three groups of inverters as Inverter under Test 1 and Inverter under Test 2.

[0016] When the first inverter under test outputs positive power, the second inverter under test outputs negative power. Based on the common DC bus power, the power output value of the remaining inverters in at least three sets of inverters is adjusted, and power matching is achieved by relying on the three-phase power coupling unit, so that the first inverter outputting positive power and the second inverter outputting negative power reach the set test stress.

[0017] When the inverter under test 1 outputs negative power, the inverter under test 2 outputs positive power. Based on the common DC bus power, the power output value of the remaining inverters in at least three sets of inverters is adjusted, and power matching is achieved by relying on the three-phase power coupling unit, so that the inverter 1 that outputs negative power and the inverter 2 that outputs positive power reach the set test stress.

[0018] Thirdly, embodiments of this application provide a testing method for power semiconductors. This method is applied to the circuit for testing power semiconductors provided in the first aspect and the control method for testing power semiconductors provided in the second aspect. The method includes the following steps:

[0019] Set test stress parameters, verify the on / off state of the DC circuit breaker and AC circuit breaker in the circuit, confirm that the voltage of the inverter DC capacitor unit is within a stable range, and that the coil wiring method of the three-phase power coupling unit is compatible with the test requirements.

[0020] An inverter containing the power semiconductor device under test is selected as the inverter under test. When the inverter under test outputs positive or negative power, the negative or positive power output of the other inverters is adjusted based on the common DC bus power. Power matching is achieved by relying on the three-phase power coupling unit so that the inverter under test reaches the set test stress.

[0021] This application provides a circuit and control method for testing power semiconductors, as well as a testing method. The circuit for testing power semiconductors includes at least three sets of inverters and a three-phase power coupling unit with at least three sets of ports. The DC terminals of the at least three sets of inverters are interconnected to form a common DC bus. Each set of ports of the three-phase power coupling unit is connected to the AC terminal of the corresponding inverter. At least two of the at least three sets of inverters contain the power semiconductor device under test. The inverters include a DC capacitor unit, an AC filter unit, and a three-phase bridge circuit. The AC filter unit is an L-type filter, an LC-type filter, an LCL-type filter, or an LC combined filter. The topology of the three-phase bridge circuit is a two-level topology, a three-level topology, a multi-level topology, an H-bridge topology, or an H-bridge combination. This technical solution can realize active power testing of power semiconductor devices, improve the testing accuracy and reliability of device operating condition results, and increase the flexibility of power semiconductor device testing methods. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of the structure of a circuit for testing power semiconductors according to an embodiment of this application;

[0023] Figure 2 This is a schematic flowchart of a control method for testing power semiconductors according to an embodiment of this application;

[0024] Figure 3 This is a schematic flowchart of a testing method for power semiconductors according to an embodiment of this application;

[0025] Figure 4 This is a schematic diagram of the structure of an electronic device according to an embodiment of this application;

[0026] Figure 5 This is a schematic diagram of the structure of an electronic device according to an embodiment of this application;

[0027] Figure 6 This is a schematic diagram of the structure of an electronic device according to an embodiment of this application;

[0028] Figure 7 This is a schematic diagram of the structure of an electronic device according to an embodiment of this application;

[0029] Figure 8 This is a schematic diagram of the structure of an active power testing circuit according to an embodiment of this application;

[0030] Figure 9 This is a schematic diagram of another active power test circuit according to an embodiment of this application.

[0031] Figure 1 In the middle, 11. Inverter 1; 21. Inverter 2; 31. Inverter 3; 40. Three-phase power coupling unit;

[0032] Figure 4 In the middle, 401, the first and third groups of three-phase coils; 402, the second and third groups of three-phase coils; 403, the third group of three-phase coils;

[0033] Figure 5 Among them, 411, the first and third groups of three-tap single-phase transformers; 412, the second and third groups of three-tap single-phase transformers; 413, the third and third groups of three-tap single-phase transformers;

[0034] Figure 6 In the middle, 421, the first three-phase double-tapped transformer; 422, the second three-phase double-tapped transformer;

[0035] Figure 7 Among them, 421 is the first three-phase double-tap transformer; 422 is the second three-phase double-tap transformer; and 423 is the third three-phase double-tap transformer.

[0036] Figure 8 and Figure 9 In the diagram, 11. Inverter 1; 12. AC Circuit Breaker 1; 13. DC Circuit Breaker 1; 21. Inverter 2; 22. AC Circuit Breaker 2; 23. DC Circuit Breaker 3; 31. Inverter 3; 32. AC Circuit Breaker 3; 33. DC Circuit Breaker 3; 40. Three-phase power coupling unit; 110. Three-phase bridge circuit 1; 111. DC capacitor; 112. Filter unit; 210. Three-phase bridge circuit 2; 211. DC capacitor 2; 212. Filter unit 2; 310. Three-phase bridge circuit 3; 311. DC capacitor 3; 312. Filter unit 3; 51. Inverter 5; 511. DC capacitor 5; 512. Filter unit 5. Detailed Implementation

[0037] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0038] To address at least one technical problem in the related art, embodiments of this application provide a circuit and control method for testing power semiconductors, as well as a testing method.

[0039] This application provides a circuit for testing power semiconductors, comprising: at least three sets of inverters and a three-phase power coupling unit with at least three sets of ports; the DC terminals of the at least three sets of inverters are interconnected to form a common DC bus; each set of ports of the three-phase power coupling unit is connected to the AC terminal of the corresponding inverter; at least two of the at least three sets of inverters contain the power semiconductor device under test. The inverters include a DC capacitor unit, an AC filter unit, or a three-phase bridge circuit; the AC filter unit is an L-type filter, an LC-type filter, an LCL-type filter, or an LC combined filter; the topology of the three-phase bridge circuit is a two-level topology, a three-level topology, a multi-level topology, an H-bridge topology, or an H-bridge combination.

[0040] Figure 1 This is a schematic diagram of a circuit for testing power semiconductors, provided as an embodiment of this application. In an optional embodiment, such as... Figure 1 As shown, in a circuit used for testing power semiconductors, at least three sets of inverters are coupled together for testing via a three-phase power coupling unit having three or more sets of ports. Simultaneously, the DC terminals of at least three sets of inverters are connected together. At least two of the aforementioned at least three sets of inverters contain the power semiconductor device under test. Figure 1 As shown, a three-phase power coupling unit 40 with three or more ports is connected to the AC terminals of inverter one 11, inverter two 21, and inverter three 31, respectively. The DC terminals of inverter one, inverter two, and inverter three are connected together. Figure 1As shown, three inverters are connected via a three-port three-phase power coupling unit. Optionally, more than three-port three-phase power coupling units can be used to connect to even more inverters. In the above example, the circuit structure eliminates the need for an additional dedicated test inverter, reducing equipment costs and long-term reliability risks. Multiple inverters working with multi-port coupling units can address the issues of insufficient stress during time-lapse testing and the requirement for perfectly equal positive and negative power by using power complementarity. Furthermore, it supports the expansion of more inverters to meet the testing needs of power semiconductors in different batches. The common DC bus design also provides a foundation for stable power flow between multiple inverters, ensuring the successful implementation of active power testing.

[0041] Optionally, the circuit for testing power semiconductors also includes switches with circuit-breaking functions (including but not limited to circuit breakers, contactors, electronic switches, knife switches, solid-state switches, etc.), such as AC circuit breakers and / or DC circuit breakers. The AC circuit breaker is connected in series between the AC terminal of the inverter and the corresponding port of the three-phase power coupling unit, and the DC circuit breaker is connected in series between the DC terminal of the inverter and the common DC bus. The AC and DC circuit breakers are used to disconnect the fault path when the power semiconductor device under test fails, preventing the fault from spreading to other inverters or the common DC bus. Thus, through the fault isolation function of the circuit breaker, the fault circuit can be quickly disconnected when a single device under test fails, preventing the fault from spreading to other inverters or the common DC bus, protecting other normal devices under test and circuit components in the system, reducing test interruptions caused by faults, and significantly improving the operational reliability of the entire test circuit.

[0042] Optionally, in the circuit used for testing power semiconductors, the three-phase power coupling unit is a three-phase core-type transformer. The three-phase core-type transformer includes a magnetic core and three sets of three-phase coils wound on the magnetic core. Each set of three-phase coils constitutes one port of the three-phase power coupling unit and is connected to the corresponding AC terminal of the inverter. The other end is coupled to each other through the magnetic core. The three sets of three-phase coils are coupled to each other through the magnetic core, and each set of three-phase coils adopts a star connection or a delta connection. In this way, the three-phase core-type transformer achieves efficient magnetic coupling of each set of coils through the magnetic core, ensuring the stability and efficiency of power transfer between multiple inverters and meeting the requirements of active power testing for closed-loop power flow. The flexible choice of star or delta connection can adapt to different inverter voltage levels and test scenarios, while the core-type structure is relatively compact, saving circuit installation space.

[0043] Optionally, in the circuit used for testing power semiconductors, the three-phase power coupling unit is a three-phase group transformer, which includes three groups of three-tapped single-phase transformers. The taps of each group of three-tapped single-phase transformers constitute a set of ports of the three-phase power coupling unit and are connected to the corresponding AC terminals of the inverter. The non-tapped terminals of each group of three-tapped single-phase transformers are connected in a star or delta configuration. Thus, the three independent groups of three-tapped single-phase transformers are easy to maintain individually, and if one group of transformers fails, the entire unit does not need to be replaced, reducing maintenance costs. Star or delta connections can flexibly match different grid and inverter voltage requirements, ensuring the stability of power coupling between multiple inverters and providing a reliable power transfer path for the normal conduct of active power testing.

[0044] Optionally, in the circuit used for testing power semiconductors, the three-phase power coupling unit is a multi-port coupling system. The multi-port coupling system includes two, three, or more sets of three-phase double-tapped transformers. The first taps of all three-phase double-tapped transformers are interconnected to form new taps, and the second taps respectively form the ports of each set of the three-phase power coupling unit and are connected to the corresponding AC terminals of the inverters. The internal wiring of the three-phase double-tapped transformers adopts a star or delta connection. Thus, through the design of multiple sets of three-phase double-tapped transformers and interconnected taps, the number of ports of the coupling unit can be easily expanded, supporting the connection of more inverters and adapting to a larger batch of power semiconductor tests. The double-tapped structure combined with star or delta wiring ensures the balance of power transfer among multiple inverters, meets the complementary needs of positive and negative power in different test scenarios, and further improves the flexibility and power coverage of the test circuit.

[0045] It is worth noting that the power coupling unit in this embodiment uses a three-tap three-phase core transformer, but other forms of power coupling units mentioned above can also be used. Further optionally, the circuit used to test the power semiconductor can also be used for active power aging testing of the inverter.

[0046] It is understood that the embodiments of this application, through a circuit structure consisting of at least three sets of inverters, multi-port three-phase power coupling units, and a common DC bus, effectively overcome the limitations of traditional power semiconductor testing schemes. This not only avoids the increased costs and reliability risks caused by adding additional dedicated test inverters, but also solves the flexibility problems of insufficient stress for time-delay testing and the need for complete equivalence of positive and negative power for two sets of inverters. At the same time, it overcomes the defects of single reactive power testing conditions and disconnect from actual applications, providing a testing environment for power semiconductors that is close to the real operating scenario, especially for the needs of adapter aging testing and other applications that require simulating actual operating conditions.

[0047] The main method for implementing active power testing of power semiconductor devices in this application embodiment is to construct a closed-loop circuit for actual power flow. At the hardware level, the DC terminals of at least three sets of inverters are connected via a common DC bus, providing a foundation for power transfer. A three-phase power coupling unit connects the AC terminals of each set of inverters, establishing a power transfer path between the inverters, the coupling unit, and other inverters. At the control level, when one or more sets of inverters containing the device under test output positive power to simulate the device's output power in a real-world application, the remaining inverters output negative or positive power to simulate the load absorbing power. The sum of the negative power matches the sum of the positive power, allowing power to flow effectively among the multiple sets of inverters through the coupling unit. When the inverter under test outputs negative power to simulate the device's power feedback in a real-world application, the remaining inverters switch to output positive or negative power, similarly forming a reverse power flow closed loop. In this process, the power semiconductor device under test needs to actually participate in power conversion, fully simulating its active operating state in real applications, rather than the working condition without actual power conversion in traditional reactive power testing, thereby achieving true active power testing.

[0048] The embodiments of this application contribute to improving the testing accuracy of device operating condition results. On the one hand, the solution focuses on active power testing, directly simulating the core operating states of power semiconductors in actual scenarios such as motor drive and power grid conversion. This avoids the problem of traditional reactive power testing, where the test results fail to reflect the true performance of the device due to the operating conditions being out of touch with reality, thus ensuring accuracy from the testing principle. On the other hand, the AC filter unit configured in the inverter supports various types such as L-type, LC-type, LCL-type, or LC combined filters, which can effectively filter out harmonic components on the AC side, reduce the interference of current and voltage fluctuations on test parameters, and ensure the accuracy of core test data such as power, voltage, and current. At the same time, the common DC bus design ensures that the DC terminal voltage of all inverters remains consistent, avoiding test stress deviations caused by differences in the DC voltage of each group of inverters. This ensures that multiple groups of devices under test are under unified testing conditions, improving the consistency of test results. To improve the reliability of test results, each inverter group is equipped with a switch with circuit disconnection function (including but not limited to circuit breakers, contactors, electronic switches, knife switches, solid-state switches, etc.). The AC circuit breaker is connected between the AC terminal of the inverter and the coupling unit, and the DC circuit breaker is connected between the DC terminal of the inverter and the common DC bus. When a power semiconductor device under test fails, the circuit breaker of the corresponding inverter can quickly disconnect the fault circuit, isolate the failed device from the circuit, and prevent the fault from spreading to other devices under test or the entire test circuit.

[0049] The embodiments of this application also contribute to improving the flexibility of power semiconductor device testing methods. First, the number of inverters can be flexibly expanded, not only using the basic three sets of inverters but also expanding to more sets according to the needs of the testing batch. Second, the hardware topology has high adaptability; various types of AC filter units can be selected to adapt to the current level and switching frequency of the device under test (DUT). The three-phase bridge circuit supports various power electronic topologies such as two-level, three-level, multi-level, H-bridge, and H-bridge combinations, which can match DUTs of different voltage levels, eliminating the need to design separate test circuits for devices of different specifications. Finally, the test modes can be flexibly switched, supporting individual testing of the DUT in a single inverter set, simultaneous testing of two sets of DUTs, and supplementing the power difference with other auxiliary inverters to improve test efficiency. It can also perform locked-rotor tests by disconnecting the AC circuit breakers of other inverters and active short-circuit tests to simulate the active short-circuit characteristics of a motor, covering various scenarios such as power semiconductor aging tests and fault tolerance tests, significantly improving the adaptability of the testing methods.

[0050] This application also provides a control method for testing power semiconductors, applied to circuits used for testing power semiconductors, such as... Figure 2 As shown, the control method includes the following steps:

[0051] Step 201: Select at least one inverter containing the power semiconductor device under test from at least three groups of inverters as the inverter under test. Step 202: When the inverter under test outputs positive power, adjust the negative power output value of the remaining inverters in at least three groups of inverters based on the voltage of the common DC bus, and achieve power matching by relying on the three-phase power coupling unit, so that the inverter outputting positive power reaches the set test stress.

[0052] Step 203: When the inverter under test outputs negative power, adjust the positive power output value of the remaining inverters in at least three groups of inverters based on the voltage of the common DC bus, and achieve power matching by relying on the three-phase power coupling unit, so that the inverter that outputs negative power reaches the set test stress.

[0053] Optionally, when performing a locked-rotor test on the target inverter, the AC circuit breaker connected to the other inverters is disconnected, and the locked-rotor test is performed after monitoring the DC capacitor unit voltage of the target inverter to stabilize. When performing an active short-circuit test on the target inverter, the other inverters are used as loads, and the impedance characteristics of an active short circuit in a motor are simulated based on the wiring method of the three-phase power coupling unit coils to complete the active short-circuit test. In other words, disconnecting the AC circuit breakers of the other inverters before the locked-rotor test avoids interference from the other inverters to the test process of the target inverter, and monitoring the DC capacitor unit voltage to stabilize ensures consistent initial test conditions, improving the reliability of the locked-rotor test results. The active short-circuit test uses the other inverters and the three-phase power coupling unit to simulate the real short-circuit impedance characteristics of a motor, making the test scenario closer to the short-circuit conditions in actual power semiconductor applications, filling the gap that traditional tests cannot cover special fault conditions, and further improving the comprehensiveness of the test scenarios.

[0054] Optionally, when at least three sets of inverters include a companion inverter composed of power semiconductor devices for testing, if there is a difference between the positive power output of the inverter under test and the negative power output of another inverter under test, or vice versa, the power difference is transferred through a common DC bus. Power coupling between the inverter under test and the companion inverter is ensured by a three-phase power coupling unit, with the companion inverter supplementing the positive power difference to simultaneously test both sets of inverters. Thus, by supplementing the power difference with the companion inverter, the limitation that simultaneous testing of two sets of inverters under test requires perfectly equal positive and negative power is overcome, enabling synchronous testing of both sets of inverters under test, significantly improving testing efficiency and saving testing time. The common DC bus ensures stable transmission of differential power, while the three-phase power coupling unit ensures reliable power coupling between multiple inverters, making power distribution more flexible and adaptable to scenarios where the positive and negative power output capabilities of different inverters under test are inconsistent, further improving the adaptability of the test scheme.

[0055] Optionally, the inverter is subjected to active power aging testing. During the active power aging test, the duration and stress amplitude of the tested power and power factor are adjusted according to the topology of the inverter's three-phase bridge circuit to adapt to the aging test requirements of different topology inverters. The topology types include two-level topology, three-level topology, multi-level topology, H-bridge, and H-bridge combination topology. This active power aging test is based on actual active power operating conditions and, compared to traditional reactive power aging tests, more realistically simulates the aging process of devices during long-term use, improving the effectiveness of the aging test. Adjusting the duration and stress amplitude of power and power factor according to different three-phase bridge circuit topology types can adapt to the characteristics of different topology inverters such as two-level, three-level, multi-level, H-bridge, and H-bridge combination inverters, avoiding the problem of insufficient or excessive unreasonable aging tests for some topology inverters caused by using uniform test parameters, thus improving the relevance and versatility of the aging test.

[0056] In this application's technical solution, the control method for testing power semiconductors achieves power output regulation through a common DC bus, and combines it with a three-phase power coupling unit to ensure power matching. This effectively solves the problem of insufficient stress during simultaneous testing of two sets of inverters in traditional methods, ensuring that the inverter under test can stably reach the set test stress. Dynamic adjustment of positive and negative power enables active power testing, avoiding the shortcomings of traditional reactive power testing that are disconnected from actual application conditions, allowing the test results to better reflect the true performance of the devices.

[0057] This application also provides a testing method for power semiconductors, a circuit for testing power semiconductors, and a control method for testing power semiconductors, such as... Figure 3 As shown, the testing method includes the following steps:

[0058] Step 301: Set test stress parameters, verify the on / off status of DC circuit breaker and AC circuit breaker in the circuit, confirm that the voltage of the inverter DC capacitor unit is within a stable range, and that the coil wiring method of the three-phase power coupling unit is compatible with the test requirements.

[0059] Step 302: Select the inverter containing the power semiconductor device under test as the inverter under test. When the inverter under test outputs positive power, adjust the negative power output of the other inverters based on the common DC bus voltage. Power matching is achieved by relying on the three-phase power coupling unit so that the inverter under test reaches the set test stress. When the inverter under test outputs negative power, adjust the positive power output of the other inverters.

[0060] Step 303: Monitor the power output status of the inverter under test, the operating parameters of the power semiconductor device under test, and the on / off signal of the circuit breaker. If the circuit breaker is detected to be open, terminate the current test.

[0061] Step 304: If the inverter under test continues to reach the test stress within the set time period, the operating parameters of the power semiconductor device under test are normal, and there is no circuit breaker disconnection signal, then the power semiconductor device under test is determined to have passed the test.

[0062] Optionally, step 302 above can also perform multi-inverter-under-test (DUT) round-robin testing. After completing the test of the current DUT, other inverters containing the power semiconductor devices under test are selected sequentially as new DUTs in the circuit, and steps 302 to 304 are repeated. During each switch, the power output logic of the load inverter is adjusted based on the port adaptability of the three-phase power coupling unit, without the need to re-verify the basic circuit state. Thus, multi-inverter-under-test round-robin testing adjusts the power logic based on the port adaptability of the coupling unit, without the need to repeatedly verify the basic circuit state, significantly reducing the preparation time during inverter switching and improving the testing efficiency of multiple power semiconductor devices; at the same time, it adapts to multiple inverters containing DUTs in the circuit, making full use of the architectural advantages of multiple inverters, avoiding the waste of resources in single-group testing, and enhancing the adaptability of the test scheme to batch testing requirements.

[0063] Optionally, in step 303, if a circuit breaker trip is detected, the corresponding circuit breaker can be closed after troubleshooting, the inverter DC capacitor unit voltage can be recalibrated to a stable range, and the test stress can be gradually adjusted to the set value. If the set stress can be stably reached without any abnormal parameters, the tested power semiconductor device is determined to have passed the recovery test. In other words, the recovery test mechanism after a circuit breaker trip avoids the situation where a single fault results in a device being deemed unqualified. Through the process of fault troubleshooting, voltage calibration, and gradual stress adjustment, it can verify the performance stability of the device after fault recovery, reducing the risk of misjudgment, and ensure the safety of the circuit state during the recovery process, avoiding secondary faults. This mechanism supplements the shortcomings of traditional testing that lack post-fault verification, making the test coverage more comprehensive and further ensuring the objectivity of the test results.

[0064] Further optionally, steps 301 to 304 can also be used for phased aging tests of the power semiconductor device under test. Specifically, the power duration is divided into a break-in phase, a stabilization phase, and a limit phase. Before switching between each phase, the current and voltage safety thresholds are adjusted according to the topology of the inverter's three-phase bridge circuit to ensure compatibility with the aging test requirements of different topologies.

[0065] Therefore, the phased aging test progresses step by step through the break-in, stabilization, and extreme stages, more closely resembling the aging process in actual use of power semiconductors. This avoids abnormal damage to devices caused by applying extreme stress all at once, thus improving the realism of the aging test. Simultaneously, the safety threshold is adjusted according to different topologies of the three-phase bridge circuit to adapt to the characteristic differences of two-level, three-level, multi-level, H-bridge, and H-bridge combinations. This solves the problem of traditional aging tests using uniform parameters and being incompatible with inverters of different topologies, enhancing the specificity and versatility of the aging test and ensuring the effectiveness of device aging tests under different topologies.

[0066] In this application's technical solution, the comprehensive preliminary verification in step 301 ensures compliance with initial test conditions, from test parameters, circuit breaker status, capacitor voltage to coupling unit wiring, preventing initial anomalies from affecting test results. Step 302 achieves power matching based on the common DC bus and coupling unit, ensuring effective active power testing and improving test accuracy. Step 303's real-time monitoring and fault termination mechanism promptly responds to faults such as circuit breaker disconnection, preventing fault escalation. Step 304's clear judgment criteria make test results more rigorous, comprehensively solving the problems of no initial state verification, low power control accuracy, slow fault response, and ambiguous judgment in traditional testing, significantly improving the reliability and accuracy of the test.

[0067] As an alternative embodiment, the power coupling unit with three or more sets of ports includes a three-phase core transformer, such as... Figure 4 As shown, 401, 402, and 403 are three sets of three-phase coils, which are coupled together through magnetic cores. 401, 402, and 403 can be connected in either a star or delta configuration.

[0068] Further optionally, the power coupling unit having three or more sets of ports includes a three-phase transformer, such as... Figure 5 As shown, 411, 412, and 413 are three sets of three-tap single-phase transformers. 411, 412, and 413 can be connected in either a star or delta configuration.

[0069] Further optionally, a power coupling unit with three or more ports may include a multi-port coupling system consisting of two or more sets of three-phase double-tapped transformers 421, 422, wherein one tap of each of the three-phase double-tapped transformers is connected together to form a new tap. Figure 6 As shown, the internal wiring of the three-phase double-tap transformers 421 and 422 can be either star-connected or delta-connected.

[0070] Further optionally, a power coupling unit with three or more ports may include a multi-port coupling system consisting of three sets of three-phase double-tapped transformers, or 3N sets of three-phase double-tapped transformers, or multiple sets of three-phase double-tapped transformers 421, 422, 423, wherein one tap of each of the three-phase double-tapped transformers is connected together. Figure 7 As shown, the internal wiring of three-phase double-tap transformers 421, 422, and 423 can be either star-connected or delta-connected.

[0071] It is worth noting that the above structures are merely examples, and the embodiments in this application are not intended to limit the scope. The power coupling unit described above only illustrates a form with three sets of ports. Coupling units with multiple sets of ports are extensions of this. Those skilled in the art can easily conceive of combinations of coupling units with four or more sets of ports, which will not be elaborated upon here.

[0072] In one optional embodiment of this application, reference is made to... Figure 8 The circuit structure shown includes a three-phase power coupling unit 40 with three terminals, consisting of a three-tap three-phase star or delta transformer. The three terminals of the power coupling unit are connected to three AC circuit breakers 12, 22, and 32, respectively. AC circuit breaker 12 is connected to the AC terminal of inverter 11; AC circuit breaker 22 is connected to the AC terminal of inverter 21; and AC circuit breaker 32 is connected to the AC terminal of inverter 31. The DC terminal of inverter 11 is connected to DC circuit breaker 13; the DC terminal of inverter 21 is connected to DC circuit breaker 23; and the DC terminal of inverter 31 is connected to DC circuit breaker 33. The other ends of the three DC circuit breakers are connected together to achieve a common DC bus. The circuit breakers can isolate the faulty power semiconductor device from the system when a fault occurs, preventing malfunctions in the test system and other tested devices. Inverter 11 includes a DC capacitor 111, a filter unit 112, and a three-phase bridge circuit 110 composed of the power semiconductor device under test; Inverter 21 includes a DC capacitor 211, a filter unit 212, and a three-phase bridge circuit 210 composed of the power semiconductor device under test; Inverter 31 includes a DC capacitor 311, a filter unit 312, and a three-phase bridge circuit 310 composed of the power semiconductor device under test.

[0073] The aforementioned circuit structure effectively solves the problem of fault propagation in traditional test circuits through dual fault isolation via AC and DC circuit breakers. It can quickly disconnect the fault circuit when the device under test (DUT) fails, protecting the test system and other normal DUTs. A common DC bus ensures consistent DC-side voltage across the three inverters, providing a foundation for stable power transfer between multiple inverters and meeting the core power flow requirements of active power testing. The power coupling unit, composed of a three-tapped three-phase star or delta transformer, offers flexible wiring and stable magnetic coupling, reliably connecting the three inverters for power coupling while isolating faults. Simultaneously, the DC capacitors configured in each inverter stabilize the DC-side voltage, absorbing ripple current and transient energy transfer; the filtering unit removes AC-side harmonics; and the three-phase bridge circuit directly uses the power semiconductor devices under test, ensuring the accuracy of test parameters from a hardware perspective. This enables active power testing, avoiding test deviations caused by parameter fluctuations in traditional reactive power testing.

[0074] Optionally, the test method used in the above-mentioned active power test circuit can be as follows: First, the three-phase bridge circuit 110 composed of the power semiconductor devices under test is tested, that is, test cases are applied to inverter 11. At this time, inverter 21 and inverter 31 are used as test loads of inverter 11. When inverter 11 outputs positive power, inverter 21 and inverter 31 are used as loads of inverter 11 and output negative power; when inverter 11 outputs negative power, inverter 21 and inverter 31 are used as loads of inverter 11 and output positive power. When performing a stall test on inverter 11, AC circuit breaker 22 and AC circuit breaker 32 can be selectively disconnected. When performing an active short circuit test on inverter 11, inverter 21 and inverter 31 are used as loads to simulate the characteristics of an active short circuit in a motor. Then, test cases are applied to inverter 21 and inverter 31 in sequence to test the three-phase bridge circuit 210 and the three-phase bridge circuit 310, thereby achieving the test of the corresponding power semiconductor under test.

[0075] The above testing method employs a round-robin testing logic with one set of tested inverters and two sets of loads, fully utilizing the resources of three inverters without requiring additional dedicated test loads, thus reducing equipment costs. It also solves the problem of insufficient stress for time-delay testing with traditional two sets of inverters. Specifically, the two sets of loads can provide sufficient negative and positive power to ensure the tested inverter stably reaches the set test stress, achieving active power testing close to actual operating conditions. Disconnecting the AC circuit breakers of other inverters during locked-rotor testing avoids load interference and ensures the accuracy of locked-rotor test parameters. During active short-circuit testing, other inverters are used to simulate the active short-circuit characteristics of the motor, filling the gap in traditional testing's inability to cover special fault conditions and solving the problem of single-condition testing. The round-robin testing design can also sequentially complete the testing of the tested devices in the three sets of inverters, improving test coverage and resource utilization, and avoiding the inefficiency of single-set testing.

[0076] In another alternative embodiment of this application, reference is made to... Figure 9 The circuit structure shown includes an active power test circuit comprising a three-terminal power coupling unit 40 consisting of a three-tap, three-phase core transformer. The three terminals of the power coupling unit are connected to three AC circuit breakers 12, 22, and 52, respectively. AC circuit breaker 12 is connected to the AC terminal of inverter 11. AC circuit breaker 22 is connected to the AC terminal of inverter 21; AC circuit breaker 52 is connected to the AC terminal of inverter 51. The DC terminal of inverter 11 is connected to DC circuit breaker 13. The DC terminal of inverter 21 is connected to DC circuit breaker 23; the DC terminal of inverter 51 is connected to DC circuit breaker 53. The other ends of the three DC circuit breakers are connected together to achieve a common DC bus. The circuit breakers can isolate the faulty power semiconductor device from the system when a fault occurs, preventing malfunctions in the test system and other tested devices. Inverter 11 includes a DC capacitor 111, a filter unit 112, and a three-phase bridge circuit 110 composed of the power semiconductor device under test; Inverter 21 includes a DC capacitor 211, a filter unit 212, and a three-phase bridge circuit 210 composed of the power semiconductor device under test. Inverter 51 includes a DC capacitor 511, a filter unit 512, and a three-phase bridge circuit 510 composed of the power semiconductor device under test.

[0077] This circuit structure, while retaining the advantages of AC / DC circuit breaker fault isolation and common DC bus voltage, introduces an inverter 51 composed of power semiconductor devices for testing. This inverter can adapt to the different positive and negative power output capabilities of the power semiconductor devices, overcoming the limitation of traditional two-set inverters requiring completely equal positive and negative power. The three-tapped three-phase core-type transformer has high magnetic coupling efficiency, ensuring the stability of power transfer between the three sets of inverters and providing a reliable power coupling foundation for multi-inverter collaborative testing. The inverter 51 does not occupy a test slot, focusing on supplementing power differences, optimizing test resource allocation, and creating conditions for subsequent synchronous testing of the two sets of inverters under test. Compared to... Figure 8 The circuit shown further enhances testing flexibility and adaptability, avoiding the problem of low testing efficiency caused by power mismatch.

[0078] Alternatively, the power semiconductor devices may have different capabilities in generating positive and negative power. For example, when inverter 11 generates positive power, the negative power generated by inverter 21 may be less than the positive power generated by inverter 11. In this case, inverter 51 can provide the missing negative power. This allows for simultaneous testing of both the positive power of inverter 11 and the negative power of inverter 21, improving testing efficiency and saving testing time.

[0079] The circuit structure described above directly addresses the technical problem of inconsistent positive and negative power output capabilities in power semiconductor devices. By supplementing the power difference with a companion inverter, it overcomes the rigid limitation in traditional testing that requires perfect equivalence of positive and negative power, enabling synchronous testing of two sets of inverters under test. Switching is no longer necessary after each inverter has completed its test, significantly shortening the overall testing cycle and improving batch testing efficiency. Simultaneously, the supplementary power difference ensures that both sets of inverters under test stably reach the set test stress, avoiding a decrease in test accuracy due to power mismatch. This balances testing efficiency and accuracy, resolving the traditional problem of the difficulty in achieving both simultaneously.

[0080] Optionally, the test method used in the above-mentioned active power test circuit can be as follows: First, the three-phase bridge circuit 110 composed of the power semiconductor devices under test and the three-phase bridge circuit 210 composed of the power semiconductor devices under test are tested simultaneously. A positive power test case is applied to inverter 11, and a negative power test case is applied to inverter 21. The difference between the positive and negative power is provided by inverter 51. Then, a negative power test case is applied to inverter 11, and a positive power test case is applied to inverter 21. The difference between the positive and negative power is provided by inverter 51. When the positive power applied to inverter 11 is not greater than the maximum negative power that inverter 21 can output, and when the negative power applied to inverter 11 is not greater than the maximum positive power that inverter 21 can output, inverter 51 can be left unstarted. When performing a locked-rotor test on inverter 11, AC circuit breaker 22 and AC circuit breaker 52 can be selectively disconnected. When performing an active short-circuit test on inverter 11, inverter 21 and inverter 51 act as loads to simulate the characteristics of an active short circuit in a motor.

[0081] Understandably, the above testing method supports simultaneous testing of two sets of inverters under test. Combined with the on-demand start-stop logic of the auxiliary inverter, it supplements the difference to ensure test stress meets standards when power mismatch occurs, and shuts down the auxiliary inverter to save energy when power matching occurs. Positive and negative power switching tests comprehensively verify the performance of the device under test under different power directions and power factors, covering operating conditions closer to actual power semiconductor applications, thus solving the problem of single testing conditions in traditional methods. Disconnecting the AC circuit breakers of other inverters during locked-rotor testing avoids load interference and ensures accurate test parameters. During active short-circuit testing, the auxiliary inverter, together with another inverter under test, simulates motor short-circuit characteristics, further enhancing the realism of tests under special fault conditions. Therefore, the above testing method not only solves the problems of poor flexibility and low efficiency in traditional testing, but also ensures that the test results reflect the true performance of the device through multi-scenario testing, meeting practical needs such as power semiconductor aging tests.

[0082] In the above embodiments, the power coupling unit employs a three-tap, three-phase core-type transformer. Other forms of power coupling units mentioned above can also be used. The circuit of this application can also be used for active power aging testing of inverters.

[0083] It should be noted that the descriptions of each embodiment in the above embodiments have different focuses. Parts not described in detail in a certain embodiment can be referred to in the relevant descriptions of other embodiments. Those skilled in the art should understand that the embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Moreover, this application can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code. Although preferred embodiments of this application have been described, those skilled in the art, once they understand the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this application. Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Thus, if these modifications and variations of this application fall within the scope of the claims of this application and their equivalents, this application also intends to include these modifications and variations.

Claims

1. A circuit for testing power semiconductors, characterized in that, It includes at least three sets of inverters and a three-phase power coupling unit with at least three sets of ports; The DC terminals of the at least three sets of inverters are interconnected to form a common DC bus. Each group of ports of the three-phase power coupling unit is connected to the AC terminal of the corresponding inverter. At least two of the at least three sets of inverters contain the power semiconductor device under test; The inverter includes a DC capacitor unit, an AC filter unit, and a three-phase bridge circuit; the AC filter unit is an L-type filter, an LC-type filter, an LCL-type filter, or an LC combination filter; the topology of the three-phase bridge circuit is a two-level topology, a three-level topology, a multi-level topology, an H-bridge topology, or a combination of H-bridges, etc.

2. The circuit for testing power semiconductors according to claim 1, characterized in that, It also includes switches with circuit-breaking functions, such as circuit breakers, contactors, electronic switches, knife switches, and solid-state switches; The AC circuit breaker is connected in series between the AC terminal of the inverter and the corresponding port of the three-phase power coupling unit; The AC circuit breaker is used to disconnect the fault path when the power semiconductor device under test fails.

3. The circuit for testing power semiconductors according to claim 1, characterized in that, It also includes switches with circuit-breaking functions, such as circuit breakers, contactors, electronic switches, knife switches, and solid-state switches; The DC circuit breaker is connected in series between the DC terminal of the inverter and the common DC bus. The DC circuit breaker is used to disconnect the fault path when the power semiconductor device under test fails.

4. The circuit for testing power semiconductors according to claim 1, characterized in that, The three-phase power coupling unit is a three-phase core-type transformer; The three-phase core transformer includes a magnetic core and three sets of three-phase coils wound on the magnetic core. Each set of three-phase coils constitutes a set of ports of a three-phase power coupling unit and is connected to the corresponding AC terminal of the inverter. The other end is coupled to each other through the magnetic core. The three sets of three-phase coils are coupled to each other through magnetic cores, and each set of three-phase coils adopts a star connection or a delta connection.

5. The circuit for testing power semiconductors according to claim 1, characterized in that, The three-phase power coupling unit is a three-phase group transformer. The three-phase transformer group includes three groups of three-tapped single-phase transformers. The taps of each group of three-tapped single-phase transformers form a set of ports of the three-phase power coupling unit and are connected to the AC terminals of the corresponding inverters. The non-tapped terminals of each group of three-tapped single-phase transformers are connected by a star connection or a delta connection.

6. The circuit for testing power semiconductors according to claim 1, characterized in that, The three-phase power coupling unit is a multi-port coupling system; The multi-port coupling system includes two, three, or more sets of three-phase double-tap transformers (or a combination of multiple single-phase transformers). The first taps of all three-phase double-tap transformers are interconnected, and the second taps respectively form the ports of the three-phase power coupling unit and are connected to the corresponding inverter AC terminals. The three-phase double-tap transformer uses either a star connection or a delta connection.

7. A control method for testing power semiconductors, applied to the circuit for testing power semiconductors as described in any one of claims 1-5, characterized in that, Includes the following steps: Select at least one inverter containing the power semiconductor device under test from at least three groups of inverters as the inverter under test; When the inverter under test outputs positive power, based on the common DC bus, adjust the negative power output amplitude of the remaining inverters in at least three sets of inverters, and achieve power matching by relying on the three-phase power coupling unit, so that the inverter outputting positive power reaches the set test stress. When the inverter under test outputs negative power, the positive power output of the remaining inverters is adjusted based on the common DC bus, and power matching is achieved by relying on the three-phase power coupling unit, so that the inverter that outputs negative power reaches the set test stress.

8. The control method for testing power semiconductors according to claim 6, characterized in that, When performing an active short-circuit test on the target inverter, the other inverters are used as loads, and the impedance characteristics of an active short circuit of a motor are simulated based on the wiring method of the three-phase power coupling unit coils to complete the active short-circuit test.

9. The control method for testing power semiconductors according to claim 6, characterized in that, When at least three sets of inverters include a companion inverter composed of power semiconductor devices for testing, if there is a difference between the positive power output of the inverter under test and the negative power output of another inverter under test, or a difference between the negative power output of the inverter under test and the positive power output of another inverter under test, the difference power is transferred through the DC bus, and the power coupling between the inverter under test and the companion inverter is ensured by the three-phase power coupling unit. The companion inverter supplements the positive power difference so that two sets of inverters under test can be tested simultaneously.

10. The control method for testing power semiconductors according to claim 6, characterized in that, The method further includes: performing an active power aging test on the inverter; During the active power aging test, the power duration and stress amplitude are adjusted according to the topology of the inverter's three-phase bridge circuit to adapt to the aging test requirements of different topology inverters; the topology types include two-level topology, three-level topology, multi-level topology, H-bridge topology, and H-bridge combinations.

11. A testing method for power semiconductors, applied to the testing circuit according to any one of claims 1-5 and the control method for testing power semiconductors according to any one of claims 6-9, characterized in that, Includes the following steps: Set test stress parameters, verify the on / off state of the DC circuit breaker and AC circuit breaker in the circuit, confirm that the voltage of the inverter DC capacitor unit is within a stable range, and that the coil wiring method of the three-phase power coupling unit is compatible with the test requirements. An inverter containing the semiconductor device under test is selected as the inverter under test. When the inverter under test outputs positive power, the negative power output of the other inverters is adjusted based on the common DC bus. Power matching is achieved by relying on the three-phase power coupling unit so that the inverter under test reaches the set test stress. When the inverter under test outputs negative power, the positive power output of the other inverters is adjusted. Monitor the power output status of the inverter under test, the operating parameters of the power semiconductor device under test, and the on / off signal of the circuit breaker. If the circuit breaker is detected to be open, terminate the current test. If the inverter under test continuously reaches the test stress within the set time period, the operating parameters of the power semiconductor device under test are normal, and there is no circuit breaker disconnection signal, then the power semiconductor device under test is determined to have passed the test.

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