Multi-chip interconnect signal integrity co-optimization system

Abstract

This invention relates to the field of digital signal processing technology and discloses a multi-chip interconnect signal integrity collaborative optimization system, comprising: a spatial topology map extraction module, a protocol state parsing module, a compensation decision module, an equalization compensation module, a power supply decoupling optimization module, and a clock data recovery module. The system acquires a spatial topology map characterizing the physical parasitic parameters between controlled terminals, parses bus handshake signaling to generate a protocol state vector, matches prior distortion parameters based on this vector, and then maps the equalization compensation weight matrix and applies it to the clock data recovery stage. This invention utilizes bus protocol characteristics to drive the initial weight configuration of the decision feedback equalizer, achieving proactive feedforward compensation for transient crosstalk between parallel channels, eliminating the lag dependency of the physical layer compensation mechanism on bit error feedback, and ensuring signal synchronization stability during bus transaction switching.

Description

Technical Field

[0001] This invention relates to the field of digital signal processing technology, and more specifically, to a multi-chip interconnect signal integrity collaborative optimization system. Background Technology

[0002] As solid-state storage systems evolve towards higher bandwidth and larger capacity, the interconnect architecture between the main control chip and multiple flash memory chips within the storage module becomes increasingly complex. To maintain the transmission stability of high-speed parallel buses, the industry typically adopts a circuit structure integrating an adaptive decision feedback equalization unit and a clock data recovery unit. By acquiring the voltage and time margins of the data eye diagram, the signal compensation parameters are dynamically adjusted. This feedback mechanism can maintain basic communication quality when the channel density is low and signal interference is independent. As bus throughput increases, the interconnect bus enters an ultra-high frequency concurrent state. The parasitic capacitance of interlayer vias and the mutual inductance effect between parallel traces cause transient crosstalk. In addition to optimizing the physical link layout, the compensation strategy's insufficient transient response speed for bus transaction switching restricts signal integrity. For example, Chinese invention patent application CN110598236A discloses a signal integrity testing method and system based on a simulation model and a free topology structure. It focuses on establishing a comparison between the output curves of the physical network topology structure and the simulation model, and uses offline iterative logic to improve the representation accuracy of the IBIS model.

[0003] As bus throughput increases, memory interconnect buses enter an ultra-high frequency concurrent state, and the physical spatial proximity of multi-channel parallel routing increases significantly. Transient crosstalk is caused by the parasitic capacitance of interlayer vias and the mutual inductance effect between parallel traces. However, existing bus transmission optimization schemes often isolate physical layer compensation from upper-layer bus protocol logic. Existing compensation schemes treat each channel as an isolated logical object and rely on runtime trial-and-error algorithms to converge and balance tap weights without considering the static topology relationship determined within the substrate. This optimization process, which lacks physical prior constraints and is not deeply coupled with bus handshake signaling, is prone to getting trapped in local optima when faced with the superposition of crosstalk caused by simultaneous switching of multiple channels, resulting in delayed weight adjustment or system handshake failure.

[0004] Therefore, the technical problem to be solved by this invention is to construct a collaborative optimization mechanism with physical self-consistency and protocol awareness by deeply analyzing the bus transaction flow and its corresponding static physical layout constraints. Summary of the Invention

[0005] This invention provides a multi-chip interconnect signal integrity collaborative optimization system, including a spatial topology map extraction module, a protocol state parsing module, a compensation decision module, an equalization compensation module, a power supply decoupling optimization module, and a clock data recovery module. The spatial topology map extraction module is used to obtain the spatial topology distribution map that is fixed in the non-volatile storage area. The spatial topology distribution map contains physical parasitic parameters that characterize the static geometric topology relationship of the parallel channels between the interconnection control terminal and multiple storage controlled terminals. The protocol state parsing module is used to listen to the digital bus handshake signaling, parse the opcode field of the bus transaction and the target terminal chip select status, so as to generate a protocol state vector that represents the current bus data throughput characteristics. The compensation decision module connects to the protocol state parsing module and is used to address the protocol feature image dictionary based on the protocol state vector to obtain the prior distortion parameters corresponding to the current bus concurrent read and write protocol. The equalization compensation module is connected to the spatial topology map extraction module and the compensation decision module, respectively. It uses the prior distortion parameters as dynamic indexes to call the corresponding physical parasitic parameters in the spatial topology distribution map, map and generate the compensation weight matrix of the decision feedback equalizer, and apply the compensation weight matrix to the clock data recovery module. Before the physical layer bit error feedback occurs, the initial weight configuration of the decision feedback equalizer is completed using the protocol state vector, and the sampling decision boundary of each channel is adjusted.

[0006] Preferably, the compensation decision module is used to match the predicted inter-channel energy coupling value corresponding to the current concurrent read / write transaction in the protocol feature image dictionary according to the protocol state vector; the equalization compensation module is used to, under the guidance of the prior distortion parameter, to add the predicted energy coupling value as a dynamic increment to the static loss benchmark constructed by the physical parasitic parameters, so as to generate the initial tap weight of the decision feedback equalizer for the current bus transaction switching transient. By establishing the causal relationship between the static geometric space interference relationship inside the storage controlled terminal and the dynamic signaling scheduling logic of the interconnection control terminal, the initial offset vector of the decision feedback equalizer is adjusted to compensate for the delay deviation caused by the bit error feedback calculation cycle.

[0007] Preferably, the physical parasitic parameters obtained by the spatial topology map extraction module include parallel routing length, interlayer via parasitic capacitance, and mutual inductance coefficient between adjacent channels; the spatial topology map maps the physical parasitic parameters into weight correction vectors; the equalization compensation module is used to apply static spatial constraints to the compensation weight matrix based on the weight correction vectors so that the generated compensation weights conform to the physical topology distribution of the board-level routing.

[0008] Preferably, the protocol state parsing module outputs a trigger pulse to the compensation decision module when a bus transaction switching instruction is detected in the queue to be sent; the compensation decision module, in response to the trigger pulse, suspends the heuristic optimization process of the physical layer in the initial optimization phase and introduces a compensation weight matrix generated based on the protocol feature mapping dictionary; in the continuous operation phase after the compensation value stabilizes, the compensation decision module resumes the optimization process of the physical layer to implement real-time weight fine-tuning based on bit error rate feedback.

[0009] Preferably, the power decoupling optimization module is connected to the equalization compensation module, and the system also includes a power noise monitoring module; the power noise monitoring module is used to collect the voltage fluctuation amplitude of each channel power rail; the power decoupling optimization module is used to dynamically adjust the capacitance value of the controlled capacitor array according to the voltage fluctuation amplitude, so as to suppress the synchronous switching noise generated by concurrent transactions of multiple storage controlled terminals.

[0010] Preferably, the equalization compensation module further includes a feedback fine-tuning loop, used to obtain the voltage margin and time margin of the data eye diagram after the compensation weight matrix is ​​applied, and to perform convergence iteration on the compensation weight matrix based on the voltage margin and time margin.

[0011] Preferably, the clock data recovery module includes a local phase adjustment submodule, which receives the phase offset component in the compensation weight matrix and adjusts the sampling clock phase of each channel accordingly to compensate for the inter-channel skew caused by the difference in physical wiring length at the physical level, wherein the adjustment step of the sampling clock phase is no more than 1ps.

[0012] Preferably, the protocol feature mapping dictionary is stored in non-volatile memory, and the prior distortion parameters in the protocol feature mapping dictionary are obtained by pre-calibrating the storage module under different concurrent read and write loads using offline simulation data.

[0013] Preferably, the protocol status parsing module is also used to calculate the data flip rate of each channel based on the bus transaction flow; the compensation decision module is used to obtain the data flip rate, and when the data flip rate exceeds the preset flip threshold, to increase the weight of the filter coefficient for the corresponding frequency band in the compensation weight matrix so that the transmission impedance of each channel is stabilized within the preset 50Ω range.

[0014] The embodiments of the present invention have at least the following beneficial effects: 1. In the collaborative optimization of signal integrity in multi-chip interconnects, by pre-setting the layout topology map extracted during the computer-aided design stage in the non-volatile storage area of ​​the main control unit, a mapping relationship between the physical coupling strength and compensation weights between data channels is established. When the system detects a drop in the eye diagram voltage margin of the first data channel, it can use the index of the first data channel as the addressing pointer to extract the corresponding static coupling vector from the layout topology map and perform linear scaling operations. This transforms the complex physical space geometric interference calculation into a deterministic weight addressing and data conversion process, avoiding the local optimum traps and convergence lag phenomena generated by traditional heuristic iterative algorithms when dealing with high-concurrency signals, and improving the determinism of signal compensation in multi-chip interconnect environments.

[0015] 2. By listening to and parsing the handshake signaling of the digital bus, the opcode field of the bus transaction and the chip select state of the target chip are transformed into a protocol state vector representing the current data throughput characteristics. The protocol state vector is then addressed in a preset protocol feature mapping dictionary to obtain the a priori distortion parameters corresponding to a specific bus concurrent read / write protocol. Based on this, the initial tap weights of the decision feedback equalizer are directly generated and fed forward to the local clock data recovery unit of each channel. This constructs a transmission pre-control mechanism driven by the bus protocol transaction logic, realizing the transformation from passive feedback adjustment triggered by traditional analog signal distortion to active feedforward compensation driven by the digital bus protocol state. This eliminates the lag dependence of the physical layer compensation mechanism on the underlying bit error feedback and ensures the signal synchronization stability at the moment of bus command switching.

[0016] 3. By constructing a global collaborative optimization architecture consisting of a layout topology mapping unit and a protocol state parsing unit, the static geometric space interference model determined in multi-chip interconnection is deeply coupled with the dynamic signaling scheduling logic of the upper-layer digital bus. This enables the system to instantly lock the neighboring channel affected by physical space coupling and calculate the output compensation weight matrix based on the weak voltage fluctuations of a single channel or the logical characteristics of the instruction to be issued. This cross-level technical collaboration not only reduces the system's performance requirements for high-frequency real-time sampling bandwidth, but also enhances the anti-crosstalk capability of ultra-high-density storage modules under extreme concurrency conditions through data mapping rules of the logical domain, while maintaining the board-level hardware wiring structure unchanged. This provides underlying support with logical causal self-consistency for improving the overall bandwidth utilization of the storage system. Attached Figure Description

[0017] The above and other objects, features, and advantages of exemplary embodiments of the present invention will become readily apparent from the following detailed description taken in conjunction with the accompanying drawings, in which several embodiments of the invention are illustrated by way of example and not limitation, wherein: Figure 1 This is a flowchart of the signal integrity modeling and multi-parameter collaborative optimization process of the present invention; Figure 2 This is a diagram of the multi-chip transceiver node and collaborative optimization closed-loop interaction architecture of the present invention. Detailed Implementation

[0018] The principles and spirit of the present invention will now be described with reference to several exemplary embodiments in conjunction with the accompanying drawings. It should be understood that these embodiments are provided merely to enable those skilled in the art to better understand and implement the present invention, and are not intended to limit the scope of the present invention in any way. On the contrary, these embodiments are provided to make the present invention more thorough and complete, and to fully convey the scope of the present invention to those skilled in the art.

[0019] A multi-chip interconnect signal integrity collaborative optimization system includes a spatial topology map extraction module, a protocol state parsing module, a compensation decision module, an equalization compensation module, a power supply decoupling optimization module, and a clock data recovery module. The spatial topology map extraction module is used to obtain the spatial topology distribution map that is fixed in the non-volatile storage area. The spatial topology distribution map contains physical parasitic parameters that characterize the static geometric topology relationship of the parallel channels between the interconnection control terminal and multiple storage controlled terminals. The protocol state parsing module is used to listen to the digital bus handshake signaling, parse the opcode field of the bus transaction and the target terminal chip select status, so as to generate a protocol state vector that represents the current bus data throughput characteristics. The compensation decision module connects to the protocol state parsing module and is used to address the protocol feature image dictionary based on the protocol state vector to obtain the prior distortion parameters corresponding to the current bus concurrent read and write protocol. The equalization compensation module is connected to the spatial topology map extraction module and the compensation decision module, respectively. It uses the prior distortion parameters as dynamic indexes to call the corresponding physical parasitic parameters in the spatial topology distribution map, map and generate the compensation weight matrix of the decision feedback equalizer, and apply the compensation weight matrix to the clock data recovery module. Before the physical layer bit error feedback occurs, the initial weight configuration of the decision feedback equalizer is completed using the protocol state vector, and the sampling decision boundary of each channel is adjusted.

[0020] Preferably, the compensation decision module is used to match the predicted inter-channel energy coupling value corresponding to the current concurrent read / write transaction in the protocol feature image dictionary according to the protocol state vector; the equalization compensation module is used to, under the guidance of the prior distortion parameter, to add the predicted energy coupling value as a dynamic increment to the static loss benchmark constructed by the physical parasitic parameters, so as to generate the initial tap weight of the decision feedback equalizer for the current bus transaction switching transient. By establishing the causal relationship between the static geometric space interference relationship inside the storage controlled terminal and the dynamic signaling scheduling logic of the interconnection control terminal, the initial offset vector of the decision feedback equalizer is adjusted to compensate for the delay deviation caused by the bit error feedback calculation cycle.

[0021] Preferably, the physical parasitic parameters obtained by the spatial topology map extraction module include parallel routing length, interlayer via parasitic capacitance, and mutual inductance coefficient between adjacent channels; the spatial topology map maps the physical parasitic parameters into weight correction vectors; the equalization compensation module is used to apply static spatial constraints to the compensation weight matrix based on the weight correction vectors so that the generated compensation weights conform to the physical topology distribution of the board-level routing.

[0022] Preferably, the formula for calculating the initial tap weights in the compensation weight matrix by the equilibrium compensation module is as follows: ,in, Let be the initial tap weight for the i-th data channel; This is to compensate for the gain weighting factor corresponding to the j-th protocol state determined by the decision-making module based on the prior distortion parameters; is the coupling coefficient between the i-th data channel and its neighboring channels in the physical parasitic parameters; n is the total number of associated channels affected by the current bus transaction.

[0023] Preferably, the protocol state parsing module outputs a trigger pulse to the compensation decision module when a bus transaction switching instruction is detected in the queue to be sent; the compensation decision module, in response to the trigger pulse, suspends the heuristic optimization process of the physical layer in the initial optimization phase and introduces a compensation weight matrix generated based on the protocol feature mapping dictionary; in the continuous operation phase after the compensation value stabilizes, the compensation decision module resumes the optimization process of the physical layer to implement real-time weight fine-tuning based on bit error rate feedback.

[0024] Preferably, the power decoupling optimization module is connected to the equalization compensation module, and the system also includes a power noise monitoring module; the power noise monitoring module is used to collect the voltage fluctuation amplitude of each channel power rail; the power decoupling optimization module is used to dynamically adjust the capacitance value of the controlled capacitor array according to the voltage fluctuation amplitude, so as to suppress the synchronous switching noise generated by concurrent transactions of multiple storage controlled terminals.

[0025] Preferably, the equalization compensation module further includes a feedback fine-tuning loop, used to obtain the voltage margin and time margin of the data eye diagram after the compensation weight matrix is ​​applied, and to perform convergence iteration on the compensation weight matrix based on the voltage margin and time margin.

[0026] Preferably, the clock data recovery module includes a local phase adjustment submodule, which receives the phase offset component in the compensation weight matrix and adjusts the sampling clock phase of each channel accordingly to compensate for the inter-channel skew caused by the difference in physical wiring length at the physical level, wherein the adjustment step of the sampling clock phase is no more than 1ps.

[0027] Preferably, the protocol feature mapping dictionary is stored in non-volatile memory, and the prior distortion parameters in the protocol feature mapping dictionary are obtained by pre-calibrating the storage module under different concurrent read and write loads using offline simulation data.

[0028] Preferably, the protocol status parsing module is also used to calculate the data flip rate of each channel based on the bus transaction flow; the compensation decision module is used to obtain the data flip rate, and when the data flip rate exceeds the preset flip threshold, to increase the weight of the filter coefficient for the corresponding frequency band in the compensation weight matrix so that the transmission impedance of each channel is stabilized within the preset 50Ω range.

[0029] Example 1: The current multi-chip interconnect signal integrity collaborative optimization system accesses the data flow control node of the digital bus handshake protocol; the protocol state parsing module listens to the digital bus handshake signaling, parses the opcode field of the bus transaction and the target terminal chip select status, and generates a protocol state vector characterizing the current bus data throughput characteristics. This protocol state vector is input to the compensation decision module. The compensation decision module addresses the protocol feature image dictionary pre-placed in the non-volatile storage area according to the protocol state vector, and obtains the prior distortion parameters and inter-channel energy coupling prediction values ​​corresponding to the current bus concurrent read / write protocol. The spatial topology map extraction module obtains the spatial topology including physical parasitic parameters such as parallel line length, inter-layer via parasitic capacitance, and mutual inductance coefficient between adjacent channels. The distribution map and the equalization compensation module are connected to the spatial topology map extraction module and the compensation decision module, respectively. The prior distortion parameters are used as dynamic indexes to call the corresponding physical parasitic parameters in the spatial topology distribution map. The equalization compensation module maps the physical parasitic parameters into weight correction vectors based on the spatial topology distribution map, applies static spatial constraints to the compensation process, and, guided by the prior distortion parameters, uses the energy coupling prediction value as a dynamic increment to be superimposed on the static loss benchmark constructed by the physical parasitic parameters. The above parameter mapping relationship establishes the causal relationship between the static geometric space interference relationship inside the storage controlled terminal and the dynamic signaling scheduling logic of the interconnection control terminal, and generates the initial tap weights and compensation weight matrix of the decision feedback equalizer for the current bus transaction switching transient.

[0030] The formula for calculating the initial tap weights in the compensation weight matrix by the equilibrium compensation module is as follows: ,in, Let be the initial tap weight for the i-th data channel, in millivolts. To compensate for the gain weighting factor corresponding to the j-th protocol state determined by the decision module based on the prior distortion parameters, which is a dimensionless coefficient, Let be the coupling coefficient between the i-th data channel and its neighboring channels in the physical parasitic parameters, which is a dimensionless constant. Let n be the total number of associated channels affected by the current bus transaction. When the protocol state parsing module detects a bus transaction switching command in the queue to be transmitted, it outputs a trigger pulse to the compensation decision module. In response to the trigger pulse, the compensation decision module suspends the heuristic optimization process of the physical layer during the initial optimization phase and introduces a compensation weight matrix generated based on the protocol feature mapping dictionary. The clock data recovery module includes a local phase adjustment submodule, which receives the phase offset component in the compensation weight matrix and adjusts the sampling clock phase of each channel in an adjustment step of no more than 1 ps, while simultaneously adjusting the sampling decision boundary of each channel. The equalization compensation module outputs the initial tap weight. The corresponding digital-to-analog converter (DAC) circuit is driven to output the corresponding analog bias voltage, changing the reference decision standard of the receiver's decision comparator. The local phase adjustment submodule uses a phase interpolator to receive the phase offset component, translate it into digital control code, adjust the mixed weight of multiple orthogonal clock signals, maintain the inherent period of the master clock, and generate a local sampling clock with picosecond-level bias step. This feedforward control mechanism transforms the task of suppressing multi-channel transient crosstalk into a static matrix addressing process anchored to the digital instruction stream, resolving the technical contradiction between protocol switching transients and the convergence lag of adaptive filter tap weights.

[0031] The power noise monitoring module collects the voltage fluctuation amplitude of each channel's power rail; the power decoupling optimization module dynamically adjusts the capacitance value of the controlled capacitor array based on the voltage fluctuation amplitude to suppress synchronous switching noise generated by concurrent transactions of multiple storage controlled terminals; the protocol status parsing module calculates the data toggle rate of each channel based on the bus transaction flow; the compensation decision module obtains the data toggle rate, and when the data toggle rate exceeds the preset toggle threshold, it increases the weight of the filter coefficients for the corresponding frequency band in the compensation weight matrix to keep the transmission impedance of each channel within the preset 50Ω range; during continuous operation, the compensation decision module restores the physical layer optimization process; the feedback fine-tuning loop in the system obtains the voltage margin and time margin of the data eye diagram, and performs convergent iteration on the compensation weight matrix based on the voltage margin and time margin to keep the bus handshake timing aligned under the state of multi-channel concurrent transaction switching.

[0032] Example 2: This example selects a solid-state storage test platform with an 8-channel NAND flash array. The bus communication frequency is set to 3200MT / s. An oscilloscope with a bandwidth greater than 33GHz and a sampling rate of 100GSa / s is used to capture the bus physical layer signal. Random jitter with an amplitude of 10mVrms and periodic power supply noise with a frequency of 50MHz are superimposed in the test environment to simulate channel crosstalk and power fluctuations under high-frequency concurrent conditions. The data sampling window length is controlled by the bus throughput rate and transient recovery time. The technical consideration is to balance the integrity of signal feature extraction and the processing delay of the computing unit. The corresponding decision rule requires that when the bus transmission rate is greater than 2400MT / s, the sampling window length must cover no less than 3 complete protocol transaction cycles to ensure the capture of signals. To obtain the complete envelope of inter-symbol interference while ensuring that the computational delay is lower than the phase tracking period of the clock data recovery module, the sampling window length is determined to be 12.5 ns based on this decision rule. A gradient test system for verifying the transient crosstalk suppression effect is constructed. The number of concurrent flip channels is selected as the variable characterizing the crosstalk intensity. Three operating condition gradients are set for concurrent flipping of 2 channels, 4 channels, and 8 channels. A first control group is established based on heuristic iteration of eye diagram margin, a second control group is established that only includes static topology map compensation, and an experimental group with a complete architecture of protocol state parsing module and spatial topology map extraction module is established. Under the initial benchmark of 8-channel concurrent flipping, the eye height test value of the uncompensated original signal is 45.2 mV and the eye width test value is 112.5 ps, and the eye diagram is in a highly closed state.

[0033] The protocol state parsing module listens to the bus handshake signaling and parses out the 8-channel full-concurrency write opcode. The compensation decision module outputs the gain weighting factor corresponding to the current protocol state. The spatial topology map extraction module outputs the coupling coefficients between each channel. The equilibrium compensation module is based on the formula. Calculate the initial tap weights, where Let be the initial tap weight for the i-th data channel. For gain weighting factor, The coupling coefficient is n, where n is the total number of associated channels affected by the current bus transaction; for the third data channel at the center position, the calculated initial tap weight is... The initial tap value was 32.4mV. The local phase adjustment submodule in the clock data recovery module advanced the sampling clock phase by 4.2ps based on this matrix parameter. The first control group experienced a 1.5μs tap weight convergence dead zone during the transaction switching transient. The experimental group applied an initial tap weight of 32.4mV without delay at the transaction boundary. Eye height measurement data were extracted under three gradient conditions. In the 2-channel concurrent flip state, the eye height of the first control group was 120.4mV, the second control group's eye height was 125.1mV, and the experimental group's eye height was 135.2mV. In the 4-channel concurrent flip state... Under the given conditions, the eye height of the first control group decreased to 85.6mV, the eye height of the second control group decreased to 96.3mV, and the eye height of the experimental group remained at 128.4mV. Under the condition of 8-channel concurrent extreme values, the eye height of the first control group dropped to 48.3mV, the eye height of the second control group dropped to 62.5mV, while the eye height of the experimental group remained at 105.7mV and the eye width remained at 215.3ps. The eye height gain of the experimental group was greater than the linear superposition of the gains of the first and second control groups, confirming the synergistic effect logic of protocol state parsing and static spatial topology map extraction in dynamic crosstalk suppression.

[0034] Boundary verification was conducted on the update period of the compensation weight matrix. When the update period was below the absolute lower limit of 5ns, the computation queue overflowed and packet loss occurred. When the update period was in the normal median range of 10ns to 40ns, the signal phase margin was maintained at 210.6ps to 215.3ps. When the update period exceeded the absolute upper limit of 50ns, the signal phase margin exhibited nonlinear degradation, dropping sharply from 215.3ps to 142.1ps. This degradation effect confirmed that the static topology mapping was affected by thermal drift accumulation error over a long period of time, and the working window of the update period of 10ns to 40ns was quantitatively established. Based on the linkage between the parasitic parameters of the underlying physical topology and the signaling of the higher-layer digital protocol, the experimental group eliminated the adaptive convergence delay deviation during the high-frequency transaction switching period.

[0035] Example 3: The current multi-chip interconnect signal integrity collaborative optimization system accesses the bus data flow node under the multi-layer cabling architecture. The spatial topology map extraction module obtains the parallel line length, inter-layer via parasitic capacitance, and mutual inductance coefficient between adjacent channels inside the storage controlled terminal. The above physical parasitic parameters are input to the internal weight mapping unit. For the first data channel and the second data channel that constitute an adjacent channel pair, the weight mapping unit extracts the mutual inductance coefficient and inter-layer via parasitic capacitance between them, calculates the linear weighted sum of the mutual inductance coefficient and inter-layer via parasitic capacitance, and generates the basic coupling base. The weight mapping unit extracts the parallel line length of the adjacent channel pair, calculates the product of the parallel line length and the basic coupling base, and determines the weight correction vector for the adjacent channel pair. The equalization compensation module receives the weight correction vector and applies numerical boundary constraints to the corresponding elements in the compensation weight matrix according to the weight correction vector, limiting the adjustment range of the compensation weight to the numerical range corresponding to the physical topology distribution.

[0036] The power decoupling optimization module collects the real-time voltage fluctuation amplitude of each channel's power rail and inputs it to the feedback compensator. The feedback compensator calculates the ratio of the real-time voltage fluctuation amplitude to the system's power supply reference voltage, generating a fluctuation deviation rate. The feedback compensator multiplies this fluctuation deviation rate by a preset system equivalent load capacitance constant to calculate the target capacitance compensation amount. The power decoupling optimization module calculates the difference between the current connected capacitance value of the controlled capacitor array and the target capacitance compensation amount, generating a tuning duty cycle control pulse proportional to this difference. This tuning duty cycle control pulse is then output to the switching ports of the controlled capacitor array to drive the corresponding number of redundant transistors. The capacitor branch is connected to the power rail. The protocol status parsing module calculates the data toggle rate of each channel within a unit time period. The sliding calibration unit in the compensation decision module collects the historical data toggle rate within the first 1000 bus transaction cycles during the initial power-on phase of the system. It calculates the arithmetic mean of the 1000 historical data toggle rates and adds this arithmetic mean to a dimensionless bias constant of 0.1 to determine the preset toggle threshold. When the current data toggle rate is greater than the preset toggle threshold, the compensation decision module calculates the ratio of the difference between the current data toggle rate and the preset toggle threshold. Based on the ratio of the difference, the weight of the filter coefficient corresponding to the high-frequency component in the compensation weight matrix is ​​increased.

[0037] Example 4: When the system is in the initial data solidification baseline construction phase of the interconnected printed circuit board, the test bench injects a pulse test stream covering each opcode into the bus. The detection instrument captures the time-domain waveform profile of each data channel. The multi-chip interconnect signal integrity collaborative optimization system calculates the voltage drop amplitude and phase deviation time of this waveform profile compared to the ideal eye diagram. Based on the voltage drop amplitude and phase deviation time, the prior distortion parameters are determined. The main control unit, based on the equivalent model of linear loss of the data channel, calculates the distortion parameters according to the formula. Obtain the dimensionless gain weighting factor This is established as a priori distortion parameter, where ΔV is the measured voltage drop amplitude and ΔT is the measured phase deviation time. and These represent the ideal eye height reference voltage and the ideal data symbol unit time at the current bus communication frequency, respectively. α and β are non-negative weighting coefficients characterizing the difference in amplitude loss and phase dispersion response of the line medium. Simultaneously, the test bench applies a step signal to the source channel and measures the crosstalk peak voltage of adjacent channels to obtain the predicted value of energy coupling between channels. The main control unit establishes an association matrix with the protocol opcode as the index key and the prior distortion parameter and the predicted value of energy coupling as the matching parameter, writes it into the designated address space of the non-volatile storage area, and constructs a protocol feature mapping dictionary.

[0038] The multi-chip interconnect signal integrity collaborative optimization system initiates a spatial topology map extraction module during the initial power-on initialization phase of the device. This module sends calibration probe pulses to each data channel, and an internal reflectometer receives the microwave reflection waveforms returned from each data channel port. It calculates the time difference Δt between the emission of the calibration probe pulse and the arrival of the microwave reflection waveform. This time difference Δt represents the transmission delay time and has no dimension. Based on the time difference Δt, the spatial topology map extraction module calculates the parallel path length of the corresponding data channel and extracts the amplitude step characteristics of the microwave reflection waveform. It then calculates the parasitic capacitance of interlayer vias and the mutual inductance coefficient between adjacent channels. The spatial topology map extraction module associates and binds the parallel path length, interlayer via parasitic capacitance, and mutual inductance coefficient with the corresponding channel physical identifiers, constructing a spatial topology distribution map and writing it into a buffer sequence. The multi-chip interconnect signal integrity collaborative optimization system establishes a static spatial constraint benchmark for signaling scheduling based on this spatial topology distribution map.

[0039] The above description is only a few preferred embodiments of the present invention and an explanation of the technical principles used. Those skilled in the art should understand that the scope of the invention involved in the embodiments of the present invention is not limited to the technical solutions formed by a specific combination of the above-mentioned technical features, but should also cover other technical solutions formed by any combination of the above-mentioned technical features or their equivalent features without departing from the above-mentioned inventive concept. For example, technical solutions formed by replacing the above-mentioned features with (but not limited to) technical features with similar functions disclosed in the embodiments of the present invention.

Claims

1. A multi-chip interconnect signal integrity collaborative optimization system, characterized in that, It includes a spatial topology map extraction module, a protocol state parsing module, a compensation decision module, a balance compensation module, a power supply decoupling optimization module, and a clock data recovery module. The spatial topology map extraction module is used to obtain the spatial topology distribution map that is fixed in the non-volatile storage area. The spatial topology distribution map contains physical parasitic parameters that characterize the static geometric topology relationship of the parallel channels between the interconnection control terminal and multiple storage controlled terminals. The protocol state parsing module is used to listen to the digital bus handshake signaling, parse the opcode field of the bus transaction and the target terminal chip select status, so as to generate a protocol state vector that represents the current bus data throughput characteristics. The compensation decision module connects to the protocol state parsing module and is used to address the protocol feature image dictionary based on the protocol state vector to obtain the prior distortion parameters corresponding to the current bus concurrent read and write protocol. The equalization compensation module is connected to the spatial topology map extraction module and the compensation decision module, respectively. It uses the prior distortion parameters as dynamic indexes to call the corresponding physical parasitic parameters in the spatial topology distribution map, map and generate the compensation weight matrix of the decision feedback equalizer, and apply the compensation weight matrix to the clock data recovery module. Before the physical layer bit error feedback occurs, the initial weight configuration of the decision feedback equalizer is completed using the protocol state vector, and the sampling decision boundary of each channel is adjusted.

2. The multi-chip interconnect signal integrity collaborative optimization system according to claim 1, characterized in that, The compensation decision module is used to match the predicted inter-channel energy coupling value corresponding to the current concurrent read / write transaction in the protocol feature image dictionary based on the protocol state vector; The equalization compensation module is used to dynamically add the energy coupling prediction value as an increment to the static loss benchmark constructed by physical parasitic parameters under the guidance of the prior distortion parameters, so as to generate the initial tap weight of the decision feedback equalizer for the current bus transaction switching transient. By establishing the causal relationship between the static geometric space interference relationship inside the storage controlled terminal and the dynamic signaling scheduling logic of the interconnection control terminal, the initial offset vector of the decision feedback equalizer is adjusted to compensate for the time delay deviation caused by the bit error feedback calculation cycle.

3. The multi-chip interconnect signal integrity collaborative optimization system according to claim 1, characterized in that, The physical parasitic parameters obtained by the spatial topology map extraction module include parallel line length, interlayer via parasitic capacitance, and mutual inductance coefficient between adjacent channels. Spatial topological distribution maps map physical parasitic parameters into weight correction vectors; The equalization compensation module is used to apply static spatial constraints to the compensation weight matrix based on the weight correction vector, so that the generated compensation weights conform to the physical topology distribution of the board-level routing.

4. The multi-chip interconnect signal integrity collaborative optimization system according to claim 1, characterized in that, The protocol status parsing module is used to output a trigger pulse to the compensation decision module when a bus transaction switching instruction is detected in the queue to be sent. The compensation decision module is used to respond to the trigger pulse, suspend the heuristic optimization process of the physical layer in the initial optimization phase, and introduce a compensation weight matrix generated based on the protocol feature mapping dictionary; in the continuous operation phase after the compensation value stabilizes, the compensation decision module is used to resume the optimization process of the physical layer to implement real-time weight fine-tuning based on bit error rate feedback.

5. The multi-chip interconnect signal integrity collaborative optimization system according to claim 1, characterized in that, The power decoupling optimization module is connected to the equalization compensation module, and the system also includes a power noise monitoring module; The power noise monitoring module is used to collect the voltage fluctuation amplitude of each channel power rail; The power decoupling optimization module is used to dynamically adjust the capacitance value of the controlled capacitor array according to the voltage fluctuation amplitude in order to suppress the synchronous switching noise caused by concurrent transactions of multiple storage controlled terminals.

6. The multi-chip interconnect signal integrity collaborative optimization system according to claim 1, characterized in that, The equalization compensation module also includes a feedback fine-tuning loop, which is used to obtain the voltage margin and time margin of the data eye diagram after the compensation weight matrix is ​​applied, and to perform convergence iteration on the compensation weight matrix based on the voltage margin and time margin.

7. The multi-chip interconnect signal integrity collaborative optimization system according to claim 1, characterized in that, The clock data recovery module includes a local phase adjustment submodule, which receives the phase offset component in the compensation weight matrix and adjusts the sampling clock phase of each channel accordingly to compensate for the inter-channel skew caused by the difference in physical wiring length at the physical level. The adjustment step of the sampling clock phase is no more than 1ps.

8. The multi-chip interconnect signal integrity collaborative optimization system according to claim 1, characterized in that, The protocol feature mapping dictionary is stored in non-volatile memory, and the prior distortion parameters in the protocol feature mapping dictionary are obtained by pre-calibrating the storage module under different concurrent read and write loads using offline simulation data.

9. The multi-chip interconnect signal integrity collaborative optimization system according to claim 1, characterized in that, The protocol status parsing module is also used to calculate the data flip rate of each channel based on the bus transaction flow; the compensation decision module is used to obtain the data flip rate, and when the data flip rate exceeds the preset flip threshold, it increases the weight of the filter coefficient for the corresponding frequency band in the compensation weight matrix so that the transmission impedance of each channel is stabilized within the preset 50Ω range.

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