A digital decimation filter architecture design method based on frequency band division

Abstract

The application discloses a kind of digital downsampling decimation filter architecture design methods based on frequency band division.The method first determines the target frequency band of input signal and original sampling frequency, and obtains the frequency pre-estimate of signal by the fast frequency estimation mechanism based on hysteresis comparator;Subsequently, according to the estimated frequency, the full frequency band is divided into multiple independent sub-bands, and the downsampling multiple and enable control signal are dynamically matched;Then, the signal is input into the decimation filter architecture of double-path multi-stage cascade, for the low-frequency resolution and spectrum leakage problem of wideband signal under high-speed sampling, the problem that the group delay of traditional multi-stage cascade filter is too large under high-rate decimation is broken, and high-fidelity downsampling and high-precision frequency domain analysis of wideband signal are realized.

Description

Technical Field

[0001] This invention relates to the field of digital filter design in signal processing, specifically a digital downsampling decimation filter architecture design method based on frequency band division. Background Technology

[0002] In modern digital signal processing, broadband communication, radar detection and high-precision electronic measurement, accurate frequency domain analysis of signals is the core means of obtaining signal characteristics. In order to recover broadband signals without distortion and satisfy the Nyquist sampling theorem, the system needs to use a high-speed ADC for high-frequency direct sampling. After acquiring the high-speed digital code stream, the fast Fourier transform is usually used to map the time domain sequence to the frequency domain to extract signal characteristics.

[0003] In practical engineering implementations, due to limitations in hardware memory and logic computing resources, the number of computation points in a hardware FFT module is usually fixed. High sampling rates and fixed FFT points directly result in severely low frequency resolution for low-frequency signals. When the signal under test is in the low-frequency band, it is very easy to cause the picket fence effect and spectral leakage, causing the effective low-frequency signal to be submerged in broadband background noise. The classic solution to resolve the above contradiction is downsampling. In order to prevent high-frequency noise from folding the spectrum during downsampling, a digital anti-aliasing low-pass filter must be inserted before decimation.

[0004] However, when faced with the need for broadband signal analysis, the system often requires downsampling at a high decimation rate of up to hundreds of times. If a traditional single-stage FIR filter is used to achieve high decimation, while meeting the stopband attenuation requirements, the filter order will explode exponentially, consuming a large amount of hardware multiplier resources. To address this issue, a multi-stage cascaded half-band filter approach is generally used to decompose the decimation factor. Each half-band filter can achieve a 2x decimation downsampling. However, when performing high decimation, this single architecture will expose the problem of linear accumulation of group delay, with an absolute delay time as high as hundreds of microseconds, which seriously affects the system's requirements for real-time performance and dynamic response.

[0005] Therefore, designing a suitable adaptive, multi-path decimation filtering topology architecture that balances wide bandwidth adaptability, high frequency resolution, low hardware resource consumption, and low group delay transient response is an important technical problem that urgently needs to be solved. Summary of the Invention

[0006] This invention addresses the shortcomings of existing high-rate digital decimation filtering techniques by proposing a digital downsampling decimation filtering architecture design method based on frequency band division. This method uses a hysteresis comparator for fast frequency estimation, dynamically divides the input signal into different frequency bands, and employs a dual filtering architecture of FIR universal cascaded path and CIC low-delay path for adaptive downsampling processing. This method not only effectively improves the frequency resolution of low-frequency signals and reduces the impact of spectral leakage and picket fence effect, but also greatly reduces the system group delay under high-rate decimation, showing good application prospects and commercial development value.

[0007] To achieve the above objectives, the present invention adopts the following technical solution:

[0008] S1: Before dividing the frequency band, it is necessary to determine the target frequency band range f of the input signal. min ~ f max Original sampling frequency f s And the expected downsampling factor.

[0009] S2: Through N ADC A single-frequency ADC samples a single-frequency analog signal to obtain a digital input signal. The frequency of the quantized and sampled signal is then rapidly estimated by the ADC to obtain the predicted frequency f of the target signal. est .

[0010] S3: Based on the estimated signal frequency f est The input signal is logically divided into multiple independent sub-bands. A downsampling factor D is dynamically matched to each sub-band, and the corresponding enable signal vector EN and data path selection signal S are generated in the control enable module. sel .

[0011] S4: Input the input signal into a dual-path, multi-stage cascaded decimation filter architecture, including an FIR general-purpose cascaded decimation path for processing mid-to-high frequency signals and a low-delay CIC decimation path for processing low-frequency signals.

[0012] S5: When the signal frequency falls within the low to medium downsampling factor band, the control enable signal vector EN enables the corresponding filter in the FIR universal cascaded decimation path. The sampled signal, according to the settings, will sequentially pass through an FIR low-pass filter to remove out-of-band noise, then through an FIR 4x decimation filter for initial downsampling to ensure the signal frequency meets the requirements of subsequent half-band filters. Subsequently, it will undergo progressively double-downsampling through multiple cascaded half-band filters, resulting in an output equivalent sampling rate of f. eq = f s / D downsampled signal.

[0013] S6: When the signal frequency belongs to the frequency band of high downsampling factor, the control enable signal vector EN enables the CIC low-delay decimation path and disables the corresponding filter in the FIR general cascaded decimation path. The sampled signal will pass through the CIC filter for high-factor coarse decimation according to the setting enable. After passing through the CIC compensation filter to correct the passband amplitude attenuation of the CIC filter and complete the double decimation, it will finally pass through the half-band filter for transition band sharpening and final stage double downsampling, and output a high-factor downsampled signal.

[0014] S7: The multiplexer selects the signal S based on the data path. sel The downsampled signal corresponding to the frequency band is selected for output.

[0015] In step S1, in order to satisfy the Nyquist sampling theorem and cover high-frequency signal components, the original sampling frequency f s and the maximum frequency f of the target frequency band max f should be satisfied s >2f max The sampling multiples are set to 1 (i.e., no downsampling), 4, 8, 16, 32, 64, 128, 256, and 512.

[0016] Step S2, which estimates the frequency of the input signal, specifically includes the following steps:

[0017] Step S21: First, set the upper limit threshold V for fluctuations around zero level. H With lower threshold V L To construct a digital dead zone, based on V H Set as a% of the ADC full-scale voltage amplitude, V L The threshold value is set to -a% of the ADC full-scale voltage amplitude. The threshold range needs to be adjusted appropriately according to the specific engineering situation. The value of a should be controlled between 0 and 10.

[0018] Step S22: Construct a hysteresis comparator in the pure digital domain, receive the input discrete sampling sequence x[n], and set the system status register S[n]. When x[n] ≥ V H When, let S[n]=1, when x[n]≤V L When, let S[n]=0, when V L <x[n]<V H At this time, S[n] remains unchanged from the state of the previous time step;

[0019] Step S23: Utilize the system sampling frequency f s The clock counter cnt monitors the state flip of the status register S[n]. When it detects that S[n] changes from 1 to 0, it determines that the signal has crossed zero with a falling edge, clears the counter to zero and starts accumulating.

[0020] Step S24: When S[n] is detected to change from 0 to 1, it is determined that the signal has crossed zero on the rising edge, and the accumulated value of the counter is recorded as M at this time;

[0021] Step S25: Based on the clock count M between adjacent falling and rising edges and the system sampling frequency f s Calculate the frequency prediction value f of the target signal. est The formula is:

[0022]

[0023] In step S3, the frequency band division and the setting of the downsampling factor D are achieved through logical judgment, and the estimated frequency f is... est Greater than or equal to 0.1f s And less than or equal to f max The signal is divided into the first frequency band, D is set to 1, that is, no downsampling is performed, and f is... est Greater than or equal to 0.055f s And less than 0.1f s The signal between them is divided into a second frequency band, D is set to 4, and f is... est Greater than or equal to 0.0275f s And less than 0.055f s The signal between them is divided into the third frequency band, D is set to 8, and f is... est Greater than or equal to 0.01375f s And less than 0.0275f s The signal between them is divided into the fourth frequency band, D is set to 16, and f is... est Greater than or equal to 0.006875f s And less than 0.01375f s The signal between them is divided into the fifth frequency band, D is set to 32, and f is... est Greater than or equal to 0.0034375f s And less than 0.006875f s The signal between them is divided into the sixth frequency band, D is set to 64, and f is... est Greater than or equal to 0.00171875f s And less than 0.0034375f s The signal between them is divided into the seventh frequency band, D is set to 128, and f is... est Greater than or equal to 0.000859375f s And less than 0.00171875f s The signal between them is divided into the eighth frequency band, D is set to 256, and f is... est Greater than or equal to 0.00015f sAnd less than 0.000859375f s The signals between them are divided into the ninth frequency band, and D is set to 512.

[0024] In step S4, the signal is first buffered and delayed in a first-in-first-out (FIFO) memory for alignment, and then input into a dual-path multi-stage cascaded decimation filter architecture. The corresponding filter is selected for decimation and downsampling operation according to the enable vector EN generated by the control enable module.

[0025] In step S5, if the signal enters the FIR universal cascade path, based on the N sampling of the analog signal in the system... ADC For a 6-bit ADC, the theoretical extreme value of its ideal quantization signal-to-noise ratio is calculated as SNR = 6.02 × N. ADC +1.76 (dB), the stopband attenuation target for the pre-FIR low-pass filter and all subsequent cascaded decimation filters is set to SNR+5, with a fluctuation of 2dB. The passband frequency of the pre-FIR low-pass filter in the FIR universal cascaded decimation path is set to f. max The stopband frequency is set to 1.17f. max The input sampling frequency is f s The passband ripple is set to 0.01dB, the decimation factor of the first-stage FIR decimation filter is set to 4, and the passband frequency is set to 0.1f. s The stopband frequency is set to 0.125f. s The output sampling frequency is 0.25f. s The input sampling rate of each half-band filter in a multi-stage cascade is f. s_i The transition band width is set to 0.06f. s_i The sampling multiple is 2, and the FIR general cascade sampling path can achieve a maximum sampling downsampling of 256 times.

[0026] In step S6, if the signal enters the CIC low-delay path, it will pass through a CIC filter, a CIC compensation filter, and a half-band filter. The decimation factor of the CIC filter is set to 128, the differential delay M is set to 1, and the cascade number N is [not specified]. CIC The value is set to 5, and an FIR filter is selected as the compensation filter for the CIC filter. The input sampling frequency is f. cic_com The decimation factor is set to 2, and the passband frequency is set to 0.22f. cic_com The stopband frequency is set to 0.25f. cic_com The passband ripple is set to 0.01dB, the stopband attenuation to 90dB, and the input sampling rate of the half-band filter is f. hb The transition band width is set to 0.06f. hb The low-latency CIC extraction path achieves 512x downsampling.

[0027] In step S7, after frequency estimation, based on the S generated by the control enable module... sel Select the corresponding frequency band signal output in the multiplexer. To represent the 9 states, S sel The signal requires at least 4 bits of binary width.

[0028] Compared with the prior art, the present invention has the following beneficial technical effects and significant technical progress:

[0029] By employing a frequency band division mechanism, the equivalent sampling rate dynamically scales with the frequency of the input signal, perfectly solving the problem of insufficient resolution in the low-frequency band caused by high-speed sampling and fixed-point FFT. This significantly improves the spectral resolution and essentially eliminates the low-frequency blind zone. Simultaneously, this invention separates the multi-stage half-band filter structure from the multiplier-free CIC structure, constructing a dual heterogeneous path. For mid-to-low frequency signals, a general-purpose FIR cascaded path is used to optimize hardware DSP resources; for high-rate decimation, a dedicated CIC low-delay path is provided. Based on the group delay model, at 512x decimation, this path can greatly reduce the linear accumulation of group delay under high-rate decimation, significantly reducing resource consumption while ensuring anti-aliasing performance and effectively guaranteeing the system's real-time transient response capability when processing low-frequency dynamic signals. Attached Figure Description

[0030] Figure 1 This is a system flowchart of the present invention. Detailed Implementation

[0031] The present invention will now be described in detail with reference to the accompanying drawings and embodiments. These embodiments will help those skilled in the art to further understand the present invention, but do not limit the invention in any way. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention.

[0032] Example 1

[0033] See Figure 1 The system architecture of this invention consists of a data path and a control path running in parallel. The starting point of the data path is the ADC sampling data input terminal, and the ending point is a multiplexer containing multiple frequency band tap outputs. The control path consists of a frequency estimation module and a control enable module, which are responsible for coordinating the operation of the entire filtering network.

[0034] This invention includes the following steps:

[0035] Step 1: Before inputting the signal, establish the basic parameters of the system and set the original ADC sampling frequency f. s = 200MHz, in order to satisfy the Nyquist sampling theorem, the minimum frequency f of the target frequency band is...min Set to 30kHz, maximum frequency f max Set to 30MHz, satisfying f s > 2f max The system's pre-implemented downsampling levels include: 1x (no downsampling), 4x, 8x, 16x, 32x, 64x, 128x, 256x, and 512x.

[0036] Step 2: The ADC sampled data x[n] is first bypassed and enters the frequency estimation module. The frequency estimation specifically includes the following steps:

[0037] Step 2-1: To combat Gaussian white noise, a digital hysteresis comparator is built into this module, setting a threshold that fluctuates around zero level, with an upper limit V. H Set to 5% of the ADC full-scale voltage, with a lower threshold V. L Set to -5% of the ADC full-scale voltage;

[0038] Step 2-2: Set the system status register S[n] when the input sampling sequence x[n] ≥ V H When x[n] ≤ V, the status register S[n] is locked to 1; when x[n] ≤ V L When S[n] is reset to 0, when V L <x[n]<V H At this time, S[n] remains unchanged from the state of the previous time step;

[0039] Steps 2-3: Utilize the system running in f s The counter cnt in the clock domain accurately monitors the state transition of S[n]. When it detects that S[n] changes from 1 to 0, it determines that the signal has crossed the zero point of the falling edge, the counter is cleared and starts to accumulate;

[0040] Steps 2-4: When S[n] changes from 0 to 1 and a rising edge crosses the zero point, record the counter accumulation value M at this time;

[0041] Steps 2-5: Using the frequency estimation formula, quickly calculate the predicted main frequency f of the current signal within half a waveform period. est The calculation formula is:

[0042]

[0043] Step 3: Estimate frequency f est The signal is then sent to the control enable module. This module, based on its internal comparison logic, finely divides the signal frequency band into nine sub-bands and sets the corresponding downsampling factor D. The specific mapping relationship is as follows: f... estSignals greater than or equal to 20MHz and less than or equal to 30MHz are assigned to the first frequency band, and the downsampling factor D is set to 1, meaning no downsampling is performed. est Signals greater than or equal to 11MHz and less than 20MHz are assigned to the second frequency band, D=4, and f est Signals greater than or equal to 5.5MHz and less than 11MHz are assigned to the third frequency band, with D=8. Then, the frequency is increased exponentially by 2, and f is... est Signals greater than or equal to 2.75MHz and less than 5.5MHz are assigned to the fourth frequency band, with D=16, and f... est Signals greater than or equal to 1.375MHz and less than 2.75MHz are assigned to the fifth frequency band, with D=32, and f... est Signals greater than or equal to 0.6875MHz and less than 1.375MHz are assigned to the sixth frequency band, with D=64, and f... est Signals greater than or equal to 0.34375MHz and less than 0.6875MHz are assigned to the seventh frequency band, with D=128, and f... est Signals greater than or equal to 0.171875MHz and less than 0.34375MHz are assigned to the eighth frequency band, with D=256, and f... est Signals with frequencies greater than or equal to 0.03MHz and less than 0.171875MHz are assigned to the ninth frequency band, with D=512.

[0044] Step 4: In the data path, the signal first needs to be buffered and delayed for alignment via a FIFO, and then input into a dual-path, multi-stage cascaded decimation filter architecture. Based on the enable vector EN generated by the control enable module, the corresponding filter is selected for decimation and downsampling. For the first frequency band, EN is set to 10_000000_000, enabling the pre-low-pass filter. For the second frequency band, EN is set to 11_000000_000, enabling both the pre-low-pass and FIR 4x decimation filters. For the third frequency band, EN is set to 11_100000_0 00, then enable the first half-band filter, and so on. For the fourth band, set EN to 11_110000_000; for the fifth band, set EN to 11_111000_000; for the sixth band, set EN to 11_111100_000; for the seventh band, set EN to 11_111110_000; for the eighth band, set EN to 11_111111_000; for the ninth band, set EN to 00_000000_111, enabling the three filters of the CIC path.

[0045] Step 5: If the signal enters the general FIR cascade path, it first needs to pass through an FIR low-pass filter. This filter has a passband frequency of 30MHz, a stopband frequency of 35MHz, and a stopband attenuation target strictly set to 90dB. If the signal belongs to the first frequency band, no downsampling is performed, and all subsequent decimation filters are disabled. After the FIR low-pass filter, the signal is directly output as a band 1 signal to the selector. At this point, out-of-band noise is filtered out. If the signal belongs to the second frequency band, an enabled FIR decimation filter is added to perform a four-fold decimation, reducing the sampling rate from 200MHz to 50MHz, outputting a band 2 signal. The input sampling frequency of this filter is 200MHz, and the passband cutoff frequency is 20MHz. The signal frequency is Hz, the stopband cutoff frequency is 25MHz, the passband ripple is 0.01dB, and the stopband attenuation is 90dB. If the signal belongs to the third to eighth frequency bands, in addition to enabling the FIR low-pass filter and the FIR decimation filter, it is also necessary to enable half-band filters ①, ①②, ①②③, ①②③④, ①②③④⑤, and ①②③④⑤⑥ according to the frequency band division to complete decimation downsampling of 8, 16, 32, 64, 128, and 256, and output the signals of frequency bands 3 to 8 to the selector. The input sampling frequencies of the filters are 50MHz, 25MHz, 12.5MHz, 6.25MHz, 3.125MHz, and 1.5625MHz, respectively. The passband and stopband of the half-band filter are related to f. s The 4 / 4 symmetry allows the transition band width of each half-band filter to be set to 0.06 times the input sampling frequency, i.e., 3MHz, 1.5MHz, 0.75MHz, 0.375MHz, 0.1875MHz and 0.09375MHz respectively, depending on the requirements.

[0046] Step 6: When the control enable module according to f est When the signal is determined to belong to the ninth frequency band, a 512x decimation is required. Adding a seventh-stage half-band filter above this level would cause group delay collapse. In this case, the control enable module disables all filters in the FIR universal cascade path and enables the lower CIC low-delay path. After passing through the FIFO, the signal first enters the CIC filter to complete a decimation of R=128x. The differential delay of the filter is configured as M=1, and the cascade number is N. CIC =5, and in this embodiment, the transfer function of the five-stage CIC filter is expressed as:

[0047]

[0048] After passing through the CIC filter, the sampling rate drops to 1.5625MHz. Next, the signal enters the CIC compensation filter for a 2x decimation. An FIR filter is selected as the CIC compensation filter, with a passband frequency designed at 343750Hz and a stopband at 390625Hz. The amplitude-frequency response of this module exhibits an inverse Sinc curve with an upward tilt, neutralizing the passband attenuation caused by the preceding CIC stage, restoring amplitude fluctuations to within 0.01dB, and simultaneously completing a 2x downsampling. The amplitude response of the CIC compensation filter is:

[0049]

[0050] Among them, f s1 is the output sampling rate of the preceding CIC filter, and f is the input signal frequency.

[0051] Finally, the data enters a half-band filter for a final 2x decimation, removing residual images and ultimately outputting a high-purity, low-delay band 9 signal, achieving an equivalent 512x decimation.

[0052] In this embodiment, for the multi-stage cascaded architecture of general FIR, the group delay of the linear phase FIR filter is constant at τ = (L-1) / 2 sampling periods, where L is the filter order. Since the output sampling rate of each stage decreases sequentially, the sampling period of the subsequent filter will be magnified many times in absolute time. If the system continues to use FIR cascaded at 512x decimation, the extremely low operating frequency of the final stage will cause the total group delay of the system to accumulate exponentially, triggering group delay collapse.

[0053] This invention addresses the low-delay CIC path used in high-rate decimation, fundamentally altering the delay accumulation model. The formula for calculating the group delay of the CIC filter equivalent to the input high-frequency sampling end is as follows:

[0054]

[0055] In step 6 of this embodiment, during the initial stage of 512x decimation, the CIC filter directly undertakes the 128x decimation task. The equivalent group delay introduced by this CIC filter is 317.5 input sampling periods. Under the condition of the original sampling rate of 200MHz, the absolute delay time generated by this 128x decimation action is only 1.5875μs. With the subsequent CIC compensation filter and half-band filter, the dual-path architecture completely removes residual images and corrects passband ripples while keeping the total group delay at an extremely low level, avoiding high delay, and taking into account the anti-aliasing performance and real-time transient response of the system during high-rate downsampling.

[0056] Step 7: The signals from bands 1 to 8 output by the general FIR cascade path, and the signal from band 9 generated by the CIC low-delay path, totaling nine data streams with different equivalent sampling rates, enter the selector after passing through the filter. The selector selects the signals according to the S signals sent in real time by the control enable module. sel The signal command selects a downsampled signal with a frequency matching the current input signal and sends it to the subsequent FFT module for frequency domain parameter calculation. To represent the nine states, S... sel The signal requires at least 4 bits of binary width, and the specific logical mapping is as follows: S sel =0001, select passband 1 signal, S sel =0010, Select passband 2 signal, S sel =0011, Select passband 3 signal, S sel =0100, select passband 4 signals, S sel =0101, select passband 5 signal, S sel =0110, select passband 6 signal, S sel =0111, select passband 7 signal, S sel =1000, select 8-signal passband, S sel =1001, select passband 9 signal.

[0057] This invention can perform downsampling processing on broadband digital signals at different multiples. It divides the frequency band through fast frequency estimation, selects an appropriate downsampling multiple and decimation filter path for downsampling rate operation, and solves the problem of low resolution of frequency domain information in fast Fourier transform of low frequency signals. It can reduce the impact of time delay accumulation explosion of traditional multi-stage cascaded filter groups on the real-time response of the system while achieving multi-multiple downsampling, thereby realizing high-fidelity downsampling and accurate frequency domain analysis of broadband signals.

[0058] The above description is merely a specific embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for designing a digital downsampling decimation filter architecture based on frequency band division, characterized in that, The method includes the following steps: S1: Before dividing the frequency band, it is first necessary to determine the target frequency band f of the input signal. min ~ f max Original sampling frequency f s and the expected downsampling factor; S2: Through N ADC A single-frequency ADC samples a single-frequency analog signal to obtain a digital input signal, performs rapid frequency estimation on the input signal, and obtains the frequency prediction value f of the target signal. est ; S3: Based on the estimated signal frequency f est The input signal is logically divided into multiple independent sub-bands. A downsampling factor D is dynamically matched to each sub-band, and corresponding control enable signal vector EN and data path selection signal S are generated. sel ; S4: The input signal is input to a dual-path, multi-stage cascaded decimation filter architecture, including an FIR general cascaded decimation path for processing mid-to-high frequency signals and a low-delay CIC decimation path for processing low-frequency signals. S5: When the signal frequency falls within the band of a low to medium downsampling factor, the control enable signal vector EN enables the filter corresponding to the decimation factor in the FIR universal cascaded decimation path. The sampled signal, according to the enabled setting, will sequentially pass through an FIR low-pass filter to remove out-of-band noise, then through an FIR quadruple decimation filter for initial downsampling, enabling subsequent half-band filtering. It will then undergo multi-stage cascaded half-band filters for progressively double-downsampling, resulting in an output equivalent sampling rate of f. eq = f s / D downsampled signal; S6: When the signal frequency belongs to the frequency band of high downsampling factor, the control enable signal vector EN enables the CIC low-delay decimation path and disables the corresponding filter in the FIR general cascaded decimation path. The sampled signal will pass through the CIC filter for high-factor coarse decimation according to the setting enable. After passing through the CIC compensation filter to correct the passband amplitude attenuation of the CIC filter and complete the double decimation, it will finally pass through the half-band filter for transition band sharpening and final stage double downsampling, and output a high-factor downsampled signal. S7: The multiplexer selects the signal S based on the data path. sel The downsampled signal corresponding to the frequency band is selected for output.

2. The digital downsampling decimation filter architecture design method based on frequency band division according to claim 1, characterized in that, In step S1, in order to satisfy the Nyquist sampling theorem and cover high-frequency signal components, the original sampling frequency f s and the frequency range f of the target frequency band min ~ f max f should be satisfied s >2f max The sampling multiples are 1 (i.e., no downsampling), 4, 8, 16, 32, 64, 128, 256, and 512.

3. The digital downsampling decimation filter architecture design method based on frequency band division according to claim 1, characterized in that, Step S2 specifically includes the following steps: Step S21: Set the upper threshold V for fluctuations around zero level. H With lower threshold V L To construct a digital dead zone to resist white noise; Step S22: Construct a hysteresis comparator in the pure digital domain, receive the input discrete sampling sequence x[n], and set the system status register S[n]. When x[n] ≥ V H When, let S[n]=1, when x[n]≤V L When, let S[n]=0, when V L <x[n]<V H At this time, S[n] remains unchanged from the state of the previous time step; Step S23: Utilize the system sampling frequency f s The counter cnt monitors the state flip of the status register S[n]. When it detects that S[n] changes from 1 to 0, it determines that the signal has crossed zero with a falling edge, clears the counter to zero and starts accumulating. Step S24: When S[n] is detected to change from 0 to 1, it is determined that the signal has crossed zero on the rising edge, and the accumulated value of the counter is recorded as M at this time; Step S25: Based on the clock count value M between adjacent falling and rising edges and the system sampling frequency f s Calculate the frequency prediction value f of the target signal. est The formula is:

4. The digital downsampling decimation filter architecture design method based on frequency band division according to claim 1, characterized in that, In step S3, the frequency band division and the setting of the downsampling factor D are achieved through logical judgment, and the estimated frequency f is... est Greater than or equal to 0.1f s And less than or equal to f max The signal is divided into the first frequency band, D is set to 1, that is, no downsampling is performed, and f is... est Greater than or equal to 0.055f s And less than 0.1f s The signal is divided into a second frequency band, D is set to 4, and f est Greater than or equal to 0.0275f s And less than 0.055f s The signal is divided into the third frequency band, D is set to 8, and f est Greater than or equal to 0.01375f s And less than 0.0275f s The signal is divided into the fourth frequency band, D is set to 16, and f est Greater than or equal to 0.006875f s And less than 0.01375f s The signal is divided into the fifth frequency band, D is set to 32, and f est Greater than or equal to 0.0034375f s And less than 0.006875f s The signal is divided into the sixth frequency band, D is set to 64, and f est Greater than or equal to 0.00171875f s And less than 0.0034375f s The signal is divided into the seventh frequency band, D is set to 128, and f est Greater than or equal to 0.000859375f s And less than 0.00171875f s The signal is divided into the eighth frequency band, D is set to 256, and f est Greater than or equal to 0.00015f s And less than 0.000859375f s The signal is divided into the ninth frequency band, and D is set to 512.

5. The digital downsampling decimation filter architecture design method based on frequency band division according to claim 1, characterized in that, In step S4, the signal is first buffered and delayed in a first-in-first-out (FIFO) memory for alignment, and then input into a dual-path multi-stage cascaded decimation filter architecture. The corresponding filter is selected for decimation and downsampling operation according to the EN generated by the control enable module.

6. The digital downsampling decimation filter architecture design method based on frequency band division according to claim 1, characterized in that, In step S5, based on N samples of the analog signal in the system... ADC For a 6-bit ADC, the theoretical extreme value of its ideal quantization signal-to-noise ratio is calculated as SNR = 6.02 × N. ADC +1.76 (dB), setting the stopband attenuation target for the pre-FIR low-pass filter and all subsequent cascaded decimation filters to SNR+5, with a fluctuation of 2dB, and setting the passband frequency of the pre-FIR low-pass filter in the FIR universal cascaded decimation path to f. max The stopband frequency is set to 1.17f. max The input sampling frequency is f s The first-stage FIR decimation filter has a decimation factor of 4 and a passband frequency of 0.1f. s The stopband frequency is set to 0.125f. s The output sampling frequency is 0.25f. s The input sampling rate of each half-band filter in a multi-stage cascade is f. s_i The width of the transition band is set to 0.06f. s_i The sampling multiple is 2, and the FIR general cascade sampling path can achieve a maximum sampling downsampling of 256 times.

7. The digital downsampling decimation filter architecture design method based on frequency band division according to claim 1, characterized in that, In step S6, the low-latency CIC decimation path includes a CIC filter, a CIC compensation filter, and a half-band filter. The decimation factor of the CIC filter is set to 128, the differential delay M=1, and the number of cascades N. CIC =5, an FIR filter is selected as the compensation filter for the CIC filter, and the input sampling frequency is f. cic_com The decimation factor is set to 2, and the passband frequency is set to 0.22f. cic_com The stopband frequency is set to 0.25f. cic_com The input sampling rate of the half-band filter is f hb The transition band width is set to 0.06f. hb The low-latency CIC extraction path achieves 512x downsampling.

8. The digital downsampling decimation filter architecture design method based on frequency band division according to claim 1, characterized in that, In step S7, after frequency estimation, based on the S generated by the control enable module... sel Select the corresponding frequency band signal output in the multiplexer.

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