Polycyclic network data transmission architecture, data processing node control method and storage medium

Abstract

The application discloses a multi-ring network data transmission architecture, a data processing node control method and a storage medium, relates to the field of ring network architecture control, and comprises the following steps: each data processing node is configured with a first independent communication board card, a second independent communication board card, a first processor board card, a backboard and a memory; the first independent communication board card and the second independent communication board card are connected in series to two ring networks; the first independent communication board card, the second independent communication board card, the first processor board card and the memory are all hot-pluggable; and the first independent communication board card, the second independent communication board card and the memory are in communication connection with the first processor board card. According to the application, the first independent communication board card is connected in series to the first ring network, and the second independent communication board card is connected in series to the second ring network, so that data processing can still be maintained by another independent communication board card and the ring network where the independent communication board card is located when any independent communication board card fails, and the operation reliability of the double-ring network data transmission architecture adopted by the DCS platform is improved.

Description

Technical Field

[0001] This application relates to the field of ring network architecture control technology, and in particular to a multi-ring network data transmission architecture, a data processing node control method, and a storage medium. Background Technology

[0002] The Distributed Control System (DCS) platform for nuclear power plants is used to support the operation and monitoring of safety functions. Because the DCS platform needs to process a large number of alarm and operational signals, and to meet the reliability requirements of data transmission for nuclear power plant safety monitoring, the data transmission network of existing DCS platforms typically adopts a dual-ring redundant architecture (Ethernet Ring). This means that the two rings share a data processor node and serve as backups for each other.

[0003] Because current data processor nodes need to simultaneously perform data transmission relay and data processing in a dual-ring network, a failure of a data processor node will cause simultaneous interruption of both ring networks, severely impacting the operational reliability of the DCS platform. To address this issue, some technologies employ ring network bypass devices for each data processor node. These bypass devices directly connect to both ring networks in the event of a data processor node failure, ensuring continuous data flow between the two networks.

[0004] However, the complexity of the ring network bypass device is greatly increased because it requires complex hardware such as optical switches, drive circuits, and status detection circuits, as well as additional complex control logic such as node status detection, fault determination, and bypass switching. This leads to a decrease in the operational reliability of the ring network bypass device, which in turn leads to a decrease in the operational reliability of the dual-ring network data transmission architecture adopted by the DCS platform. Summary of the Invention

[0005] In view of the above problems, this application provides a multi-ring network data transmission architecture, a data processing node control method, and a storage medium to improve the operational reliability of the dual-ring network data transmission architecture used in the DCS platform. The specific solution is as follows:

[0006] The first aspect of this application provides a multi-ring network data transmission architecture, including:

[0007] Multiple data processing nodes and at least two ring networks, the two ring networks including a first ring network and a second ring network;

[0008] The data processing node includes at least a first independent communication board, a second independent communication board, a first processor board, a backplane, and a memory. The first independent communication board is connected in series with the first ring network, and the second independent communication board is connected in series with the second ring network. The first independent communication board, the second independent communication board, the first processor board, and the memory are all hot-swappable on the backplane. The first independent communication board, the second independent communication board, and the memory are all communicatively connected to the first processor board.

[0009] In one possible implementation, the data processing node further includes:

[0010] A second processor board with the same configuration as the first processor board is hot-swappable and mounted on the backplane;

[0011] The second processor board is communicatively connected to the first independent communication board, the second independent communication board, the first processor board, and the memory.

[0012] In one possible implementation, the first processor board of the target data processing node is communicatively connected to the first independent communication board, the second independent communication board, the first processor board, and the memory of the data processing node under test. The data processing node under test is any one of the plurality of data processing nodes, and the target data processing node is any one of the plurality of data processing nodes other than the data processing node under test.

[0013] In one possible implementation, the backplane in the data processing node includes:

[0014] The base, at least four slots, a power distribution module, and an audible and visual alarm are disposed on the base;

[0015] The power distribution module is electrically connected to the slot and the audible and visual alarm, respectively.

[0016] The slot shape is adapted to the data transmission ends of the first independent communication board, the second independent communication board, the first processor board, and the second processor board.

[0017] A second aspect of this application provides a data processing node control method for a multi-ring network data transmission architecture, applied to a first processor board of a data processing node in a multi-ring network data parameter architecture as described in the first aspect and any implementation thereof. The data processing node control method includes:

[0018] Receive data transmitted from the first independent communication board and the second independent communication board, store the processing results of the data in the memory, and monitor the first health status of the first independent communication board and the second independent communication board respectively;

[0019] When the monitoring result of the first health status of the first independent communication board or the second independent communication board indicates a fault status, the first independent communication board or the second independent communication board corresponding to the fault status is switched off, and a communication fault prompt command is output.

[0020] In one possible implementation, it is also applied to a second processor board, which is the second processor board of the data processing node described in one implementation of the first aspect of this application. The data processing node control method further includes:

[0021] Monitor the second health status of the first processor board;

[0022] When the monitoring result of the second health status indicates a fault state, the first processor board is controlled to terminate operation, and the communication link between the second processor board and the memory is enabled.

[0023] The system controls the first and second independent communication boards to interrupt the main communication link with the first processor board, and controls the first and second independent communication boards to enable the secondary communication link with the second processor board, outputting a processor fault prompt command.

[0024] In one possible implementation, the method is also applied to a target data processing node, which is the target data processing node described in one implementation of the first aspect of this application. The data processing node control method further includes:

[0025] Monitor the second health status of the data processing node to be inspected;

[0026] When the monitoring result of the second health state indicates a fault state, the control is activated to terminate the operation of the data processing node under test and to enable the communication link between the target data processing node and the memory.

[0027] The system controls the first and second independent communication boards to interrupt the main communication link with the data processing node under test, and controls the first and second independent communication boards to enable the secondary communication link with the target data processing node, outputting a processor fault prompt command.

[0028] One possible implementation also includes:

[0029] Monitor the reset signal of the first processor board;

[0030] Upon receiving the reset signal, the communication link between the first processor board and the memory is enabled;

[0031] The system controls the first independent communication board and the second independent communication board to enable the main communication link with the first processor board, and controls the first independent communication board and the second independent communication board to interrupt the secondary communication link with the second processor board, and interrupts the communication link between the second processor board and the memory.

[0032] One possible implementation also includes:

[0033] Monitor the reset signal of the data processing node under test;

[0034] Upon receiving the reset signal, the communication link between the data processing node under test and the memory is activated;

[0035] The system controls the first independent communication board and the second independent communication board to enable the main communication link with the data processing node under test, and controls the first independent communication board and the second independent communication board to interrupt the secondary communication link with the target data processing node, thereby interrupting the communication link between the target data processing node and the memory.

[0036] A third aspect of this application provides a computer storage medium carrying one or more computer programs, which, when executed by a data processing node, enable the data processing node to control the data processing node in a multi-ring network data transmission architecture as described in the first aspect or any implementation thereof.

[0037] By employing the above technical solutions, the multi-ring network data transmission architecture, data processing node control method, and storage medium provided in this application, through configuring the data processing node to include at least a first independent communication board, a second independent communication board, a first processor board, and a backplane, and configuring the first independent communication board to be connected in series in the first ring network, and the second independent communication board to be connected in series in the second ring network, with both the first and second independent communication boards communicatively connected to the first processor board, enables the first and second independent communication boards to independently perform the data transmission relay function of the first ring network data. Therefore, in the event of a failure of any independent communication board, the other independent communication board can still be responsible for the data transmission relay of its respective ring network, avoiding the risk of data transmission and processing failure. Furthermore, by configuring the first, second, and first independent communication boards and the first processor board to be hot-swappable on the backplane, in the event of a failure of any independent communication board, the operation of the dual-ring network does not need to be interrupted; only the replacement of a new independent communication board is required to resolve the fault, avoiding the problem of dual-ring network interruption due to troubleshooting and improving the operational reliability of the dual-ring network. It is evident that this application improves the operational reliability of the dual-ring network data transmission architecture adopted by the DCS platform. Attached Figure Description

[0038] The above and other features, advantages, and aspects of the embodiments of this disclosure will become more apparent from the accompanying drawings and the following detailed description. Throughout the drawings, the same or similar reference numerals denote the same or similar elements. It should be understood that the drawings are schematic, and the originals and elements are not necessarily drawn to scale.

[0039] Figure 1 This application provides a schematic diagram of a dual-ring network data transmission architecture.

[0040] Figure 2 A schematic diagram of a node structure provided in this application;

[0041] Figure 3 This application provides a schematic diagram of a multi-ring network data transmission architecture.

[0042] Figure 4 This application provides a schematic diagram of the structure of a data processing node;

[0043] Figure 5 This application provides a schematic diagram of the structure of a data processing node;

[0044] Figure 6 A schematic diagram of a communication relationship provided in this application;

[0045] Figure 7 A flowchart illustrating a data processing node control method for a multi-ring network data transmission architecture provided in this application. Detailed Implementation

[0046] The embodiments of this application are described below with reference to the accompanying drawings. The terminology used in the implementation section of this application is for explaining specific embodiments only and is not intended to limit the scope of this application.

[0047] The embodiments of this application will now be described with reference to the accompanying drawings. Those skilled in the art will recognize that, with technological advancements and the emergence of new scenarios, the technical solutions provided in the embodiments of this application are equally applicable to similar technical problems.

[0048] The terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such terms are interchangeable where appropriate; this is merely a way of distinguishing objects with the same attributes in the embodiments of this application. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion, so that a process, method, system, product, or apparatus that comprises a series of elements is not necessarily limited to those elements but may include other elements not explicitly listed or inherent to those processes, methods, products, or apparatuses.

[0049] It should be noted that, in practical application scenarios, this application improves the operational reliability of the dual-ring network data transmission architecture used in the DCS platform compared to existing technologies. Specifically: Figure 1 The diagram shows a schematic of the dual-ring network data transmission architecture used in the existing DCS platform. This architecture consists of a first ring network and a second ring network, and has N nodes from node 1 to node N. The structural diagram of each node is shown below. Figure 2 As shown, the node includes a processor, network port 1, network port 2, network port 3, and network port 4. Network ports 1 and 2 are the interfaces for the node to connect to the second ring network, while network ports 3 and 4 are the interfaces for the node to connect to the first ring network. The processor is used to process and relay data input from network port 1 or network port 2, and also to process and relay data input from network port 3 or network port 4. From the above... Figure 2As shown in the schematic diagram of the node, a single processor must simultaneously handle the entire data processing and transmission relay process for both the first and second ring networks. When the processor of this node fails, the entire node will completely lose its ability to process and relay data for the dual ring networks, leading to a simultaneous interruption of the dual ring network data transmission architecture. Furthermore, to compensate for this deficiency, the existing ring network bypass device requires additional complex hardware such as optical switches, drive circuits, and status detection circuits, as well as complex control logic for node status detection, fault determination, and bypass switching, which significantly increases the complexity of the device and further reduces the operational reliability of the ring network system. This application configures the data processing node to include at least a first independent communication board, a second independent communication board, a first processor board, and a backplane. The first independent communication board is connected in series with the first ring network, and the second independent communication board is connected in series with the second ring network. Both the first and second independent communication boards are communicatively connected to the first processor board. This enables the first and second independent communication boards to independently perform the data transmission relay function of their respective ring networks without the intervention of the processor board. The first processor board performs the data processing function, thus achieving functional separation of the data processing node. In the event of a failure of either independent communication board, the other independent communication board can still be responsible for the data transmission relay of its respective ring network, and the first processor board can still complete data processing. Furthermore, if the first processor board fails, the existence of at least one fault-free independent communication board can still prevent the interruption of both ring networks. Furthermore, by configuring the first independent communication board, the second independent communication board, and the first processor board to be hot-swappable on the backplane, the operation of the dual-ring network can be restored without interrupting the operation of any independent communication board. Only the faulty independent communication board needs to be replaced to resolve the issue, avoiding dual-ring network interruption and failure due to troubleshooting, thus improving the operational reliability of the dual-ring network. Therefore, this application improves the operational reliability of the dual-ring network data transmission architecture used in the DCS platform.

[0050] The first aspect of this application provides a multi-ring network data transmission architecture, including:

[0051] Multiple data processing nodes and at least two ring networks, the two ring networks including a first ring network and a second ring network;

[0052] The data processing node includes at least a first independent communication board, a second independent communication board, a first processor board, a backplane, and a memory. The first independent communication board is connected in series with a first ring network, and the second independent communication board is connected in series with a second ring network. The first independent communication board, the second independent communication board, the first processor board, and the memory can all be hot-swapped and mounted on the backplane. The first independent communication board, the second independent communication board, and the memory are all communicatively connected to the first processor board.

[0053] It should be noted that, in practical application scenarios, the structural diagram of the multi-ring network data transmission architecture provided in the first aspect of this application is as follows: Figure 3 As shown, this multi-ring network data transmission architecture includes N data processing nodes, numbered from 1 to N. Each data processing node is a hardware device with data communication and data processing functions. The data transmission lines of the first and second ring networks are electrically connected to the corresponding first and second independent communication boards in the data processing nodes to achieve data interaction.

[0054] It should be noted that in actual application scenarios, the first and second ring networks mentioned above are backup ring networks for each other. The data transmitted can be the same or different depending on the actual needs of the scenario.

[0055] It should be noted that, in practical application scenarios, the multi-ring network data transmission architecture provided in the first aspect of this application may also include more than two ring networks, such as a three-ring network architecture or a four-ring network architecture. The specific ring network architecture level adopted can be selected based on the actual application scenario. When adopting more than two ring network architectures, it is only necessary to hot-swap independent communication boards corresponding to each ring network architecture in the data processing node. For example, when adopting a three-ring network data transmission architecture including a first ring network, a second ring network, and a third ring network, the data processing node may also include a third independent communication board. The third independent communication board is connected in series with the third ring network and is hot-swappable on the backplane. The third independent communication board is communicatively connected to the first processor board.

[0056] It should be noted that, in practical application scenarios, the structural diagram of the above data processing node can be as follows: Figure 4 As shown, the first independent communication board is connected in series with the first ring network, and the second independent communication board is connected in series with the second ring network. The first independent communication board, the second independent communication board, the first processor board, and the memory can all be hot-swapped and mounted on the backplane. The first independent communication board, the second independent communication board, and the memory are all communicatively connected to the first processor board.

[0057] It should be noted that, in practical applications, the aforementioned first and second independent communication boards can be communication boards that can independently perform data acquisition and transmission relay without the control of the first processor board. This application configures the first independent communication board to be connected in series with the first ring network and the second independent communication board to be connected in series with the second ring network, thereby distributing the data transmission relay function of the two ring networks to the corresponding independent communication boards. If any independent communication board fails, only the ring network connected to the failed independent communication board will be interrupted, while the other ring network can continue to operate, thus avoiding the risk of simultaneous interruption of all core ring networks in a multi-ring network data transmission architecture. Furthermore, by configuring the aforementioned independent communication boards, data transmission relay can be completed independently without the control of the first processing board, similarly avoiding the risk of data transmission relay failure due to controller failure.

[0058] It should be noted that in practical applications, since the data packets transmitted in a multi-ring network data transmission architecture are all edited using the corresponding Ethernet protocol, the aforementioned first and second independent communication boards can also parse and edit the data transmitted in the ring network.

[0059] In one possible implementation, the first independent communication board and the second independent communication board can also be configured with a ring network bypass device controlled by the respective independent communication board, so that in the event that both the first independent communication board and the second independent communication board are damaged, the ring network bypass device can ensure that the communication of the ring network is not interrupted.

[0060] It should be noted that, in practical applications, the aforementioned first processor board can be a device used to process ring network data sent by the first independent communication board and the second independent communication board. This application configures the first processor board to handle only data processing, while the first and second independent communication boards perform the data transmission relay function within their respective ring networks. This ensures that even if any independent communication board fails, they can still cooperate to complete the full data transmission relay and data processing functions for the faulty independent communication board, thereby improving the operational reliability of the dual-ring network data transmission architecture.

[0061] It should be noted that in practical applications, if the first processor board malfunctions, the data stored during data processing is at significant risk of loss. This can easily lead to undetected risky or potentially problematic data after troubleshooting, severely impacting the operational reliability of the dual-ring network data transmission architecture. Therefore, this application configures all memory modules to communicate with the first processor board, thereby utilizing the memory to store the data processed by the first processor board, thus improving the operational reliability of the dual-ring network data transmission architecture. Preferably, the aforementioned memory can be native non-volatile memory (NVM) to improve data storage reliability under power failure or transient failure of the first processor board.

[0062] Those skilled in the art will understand that, in practical application scenarios, the specific models of the first independent communication board, the second independent communication board, the first processor board, and the memory can be selected or developed independently based on the actual application scenario. This application does not impose too many restrictions or elaborate on the specific models of the above-mentioned devices.

[0063] It should be noted that in practical applications, since existing data processor nodes often adopt an integrated structure, if any function fails, the data processing node needs to be disassembled or replaced entirely. In this case, because the data processing node connects to two ring networks simultaneously, it can lead to an interruption of both ring networks. This application, however, configures the first independent communication board, the second independent communication board, the first processor board, and the memory to be hot-swappable on the backplane. Therefore, if any device fails, troubleshooting can be completed simply by removing the faulty device and plugging in a new one. This process does not affect the operation of other normal devices on the backplane, thus shortening troubleshooting time and avoiding the risk of interruption of both ring networks due to troubleshooting, thereby improving the operational reliability of the dual-ring network data transmission architecture.

[0064] This application configures a first independent communication board connected in series with the first ring network and a second independent communication board connected in series with the second ring network, thereby splitting the data transmission relay function of the two ring networks to the corresponding independent communication boards. If either independent communication board fails, only the ring network connected to the failed independent communication board will be interrupted, while the other ring network can continue to operate, thus avoiding the risk of simultaneous interruption of all core ring networks in a multi-ring network data transmission architecture. Furthermore, by configuring the aforementioned independent communication boards, data transmission relay can be completed independently without the control of the first processing board, similarly avoiding the risk of data transmission relay failure due to controller failure. Subsequently, by configuring the first processor board to only handle data processing functions, and having the first and second independent communication boards perform the data transmission relay function of their respective ring networks, even if either independent communication board fails, they can still cooperate to complete the complete data transmission relay and data processing functions for the failed independent communication board, improving the operational reliability of the dual-ring network data transmission architecture. Moreover, by configuring the memory to communicate with the first processor board, the data processed by the first processor board can be stored in the memory, further improving the operational reliability of the dual-ring network data transmission architecture. Finally, by configuring the first independent communication board, the second independent communication board, the first processor board, and the memory to be hot-swappable on the backplane, troubleshooting can be completed simply by removing the faulty device and plugging in a new one when any device fails. This process does not affect the operation of other normal devices on the backplane, thus shortening troubleshooting time and avoiding the risk of two-ring network interruption due to troubleshooting, thereby improving the operational reliability of the dual-ring network data transmission architecture. Therefore, this application improves the operational reliability of the dual-ring network data transmission architecture used in the DCS platform.

[0065] In one possible implementation, the aforementioned data processing node further includes:

[0066] A second processor board with the same configuration as the first processor board, the second processor board being hot-swappable and mounted on the backplane;

[0067] The second processor board is connected to the first independent communication board, the second independent communication board, the first processor board, and the memory.

[0068] It should be noted that in practical applications, when the first processor board fails, the data processing node to which it resides will be unable to perform data processing functions. Although data processing functionality can be quickly restored by promptly replacing the faulty first processor board, there is still a risk of missing critical data. Therefore, this application configures the data processing node to also include a second processor board with the same configuration as the first processor board, and configures the second processor board to communicate with the first independent communication board, the second independent communication board, and the first processor board respectively. Thus, when the first processor board fails, the second processor board takes over the data processing functions of the data processing node, thereby avoiding the risk of missing critical data and improving the operational reliability of the dual-ring network data transmission architecture. In one possible implementation, the aforementioned critical data may be fault messages, alarm messages, operating parameters, and other data processed by the nuclear power plant's safety-grade DCS platform.

[0069] It should be noted that, in practical application scenarios, the aforementioned second processor board monitors the fault status of the first processor board through a communication connection with it.

[0070] In one possible implementation, the structural diagram of the above data processing node can be as follows: Figure 5 As shown, a second processor board is configured identically to the first processor board. The second processor board is hot-swappable and mounted on the backplane. The second processor board is communicatively connected to the first independent communication board, the second independent communication board, the first processor board, and the memory.

[0071] In one possible implementation, the first processor board of the target data processing node is communicatively connected to the first independent communication board, the second independent communication board, the first processor board, and the memory of the data processing node under test. The data processing node under test is any one of a plurality of data processing nodes, and the target data processing node is any one of the plurality of data processing nodes other than the data processing node under test.

[0072] It should be noted that, in practical application scenarios, the aforementioned data processing node under inspection refers to the data processing node whose first processor board has failed. Since there are numerous data processing nodes in a DCS system, this application configures the first processor board of the target data processing node to communicate with the first independent communication board, the second independent communication board, the first processor board, and the memory of the data processing node under inspection. This allows the first processor board of the target data processing node to take over the data processing function when the first processor board of the inspected data processing node fails, thereby improving the operational reliability of the dual-ring network data transmission architecture.

[0073] Preferably, in practical application scenarios, in order to save equipment space, multiple data processing nodes are usually set up in one rack. Therefore, the target data processing node can be selected to be a node in the same rack as the data processing node under test. This reduces cabling costs while improving the cut-in rate of the target data processing node in the case of failure of the data processing node under test, thereby improving operational reliability.

[0074] In one possible implementation, the communication relationship between the target data processing node and the data processing node to be inspected is illustrated as follows: Figure 6 As shown, both the target data processing node and the data processing node under test include: a backplane, a first independent communication board, a second independent communication board, a first processor board, and a memory. The first independent communication board is connected in series in a first ring network, and the second independent communication board is connected in series in a second ring network. The first independent communication board, the second independent communication board, the first processor board, and the memory are all hot-swappable on the backplane. The first independent communication board, the second independent communication board, and the memory are all communicatively connected to the first processor board. The first processor board of the target data processing node is communicatively connected to the first independent communication board, the second independent communication board, the first processor board, and the memory of the data processing node under test.

[0075] In one possible implementation, the aforementioned data processing node to be inspected and the target data processing node can also serve as backups for each other. That is, based on the structure of the target data processing node, the first processor board of the data processing node to be inspected is communicatively connected to the first independent communication board, the second independent communication board, the first processor board, and the memory of the target data processing node.

[0076] In one possible implementation, the backplane in the data processing node includes:

[0077] The base, at least four slots, a power distribution module, and an audible and visual alarm are located on the base.

[0078] The power distribution module is electrically connected to the slot and the audible and visual alarm, respectively.

[0079] The slot shape is adapted to the data transmission ends of the first independent communication board, the second independent communication board, the first processor board, and the second processor board.

[0080] It should be noted that, in practical applications, the aforementioned audible and visual alarm device may include multiple audible and visual alarm components. The first independent communication board, the second independent communication board, the first processor board, and the second processor board are electrically connected to their respective audible and visual alarm components. When the self-test results of the first independent communication board, the second independent communication board, the first processor board, and the second processor board indicate a fault, the aforementioned audible and visual alarm components issue audible and visual alarm signals to assist maintenance personnel in quickly identifying the fault location, thereby improving troubleshooting efficiency.

[0081] The second aspect of this application provides a data processing node control method for a multi-ring network data transmission architecture, applied to the first processor board of a data processing node in a multi-ring network data parameter architecture as described in the first aspect of this application and any implementation thereof. Figure 7 The diagram shows a flowchart of the data processing node control method for this multi-ring network data transmission architecture. The data processing node control method includes:

[0082] S701: Receive data transmitted from the first independent communication board and the second independent communication board, store the data processing results in the memory, and monitor the first health status of the first independent communication board and the second independent communication board respectively.

[0083] It should be noted that, in practical application scenarios, the data transmitted by the first independent communication board and the second independent communication board can be the parsing result output by the first independent communication board after performing protocol parsing on the data to be collected in the first ring network, and the parsing result output by the second independent communication board after performing protocol parsing on the data to be collected in the second ring network.

[0084] It should be noted that, in actual application scenarios, the processing result of the above data is the result of the first processor board performing a preset data processing task on the data.

[0085] In one possible implementation, in addition to storing the processing results of the above data in the memory, the processing results can also be sent to the corresponding ring network (first ring network or second ring network) through the corresponding independent communication board (first independent communication board or second independent communication board) based on the specific type of data processing task.

[0086] It should be noted that, in practical applications, the aforementioned monitoring of the first health status of the first independent communication board and the second independent communication board can be achieved through a pre-installed status detection program in the first processor board. This status detection program can be configured by developers based on the actual device model, and this application does not impose further limitations or elaborate on it.

[0087] In one possible implementation, the aforementioned first health status can also be captured by the status self-test program built into the first independent communication board and the second independent communication board and sent to the first processor board.

[0088] S702, when the monitoring result of the first health status of the first independent communication board or the second independent communication board indicates a fault status, control the first independent communication board or the second independent communication board corresponding to the fault status to switch off, and output a communication fault prompt command.

[0089] It should be noted that in actual application scenarios, when the first independent communication board or the second independent communication board corresponding to the above-mentioned control fault state is switched off, the first independent communication board or the second independent communication board responds to the control signal, switches itself out of the connected ring network through an optical switch, and connects the optical bypass branch to the corresponding ring network to maintain the normal data transmission of the corresponding ring network.

[0090] In one possible implementation, it is also applied to a second processor board, which is the second processor board of the data processing node in one implementation of the first aspect of this application. The data processing node control method further includes:

[0091] Monitor the second health status of the first processor board;

[0092] When the monitoring results of the second health state indicate a fault state, the first processor board is controlled to terminate operation, and the communication link between the second processor board and the memory is enabled.

[0093] The system controls the first and second independent communication boards to interrupt the main communication link with the first processor board, and controls the first and second independent communication boards to enable the secondary communication link with the second processor board, outputting a processor fault prompt command.

[0094] It should be noted that, in practical application scenarios, the second health status of the first processor board mentioned above can be collected by the fault detection program preset by the second processor board.

[0095] In one possible implementation, the second health status of the first processor board can also be detected by the status self-test program of the first processor board and sent to the second processor board.

[0096] It should be noted that this application configures the first processor board to terminate operation when the monitoring results of the second health state characterize the fault state, enables the communication link between the second processor board and the memory, controls the first and second independent communication boards to interrupt the main communication link with the first processor board, and controls the first and second independent communication boards to enable the secondary communication link with the second processor board. Thus, the second processor board takes over the data processing function from the first processor board, avoiding the risk of missing critical data processing and improving the operational reliability of the dual-ring network data transmission architecture.

[0097] In one possible implementation, it is also applied to the target data processing node, which is the target data processing node in one implementation of the first aspect of this application. The data processing node control method further includes:

[0098] Monitor the second health status of the data processing node to be inspected;

[0099] When the monitoring results of the second health state characterize a fault state, the control system terminates the operation of the data processing node under test and enables the communication link between the target data processing node and the memory.

[0100] The system controls the first and second independent communication boards to interrupt the main communication link with the data processing node under test, and controls the first and second independent communication boards to enable the secondary communication link with the target data processing node, outputting a processor fault prompt command.

[0101] It should be noted that, in practical application scenarios, the second health status of the aforementioned data processing node to be inspected can be collected by a fault detection program preset by the target data processing node.

[0102] In one possible implementation, the second health status of the data processing node to be inspected can also be detected by the status self-test program of the first processor board of the data processing node to be inspected and sent to the first processor board of the target data processing node.

[0103] It should be noted that this application, by configuring the monitoring results of the second health state to characterize the fault state, controls the data processing node under test to terminate operation, enables the communication link between the target data processing node and the memory, controls the first independent communication board and the second independent communication board to interrupt the main communication link with the data processing node under test, and controls the first independent communication board and the second independent communication board to enable the secondary communication link with the target data processing node. Thus, the first processor board of the target data processing node takes over the data processing function from the first processor board of the data processing node under test, avoiding the risk of missing critical data processing and improving the operational reliability of the dual-ring network data transmission architecture.

[0104] One possible implementation also includes:

[0105] Monitor the reset signal of the first processor board;

[0106] Upon receiving a reset signal, the communication link between the first processor board and the memory is activated;

[0107] The system controls the first and second independent communication boards to enable the main communication link with the first processor board, and controls the first and second independent communication boards to interrupt the secondary communication link with the second processor board, and interrupts the communication link between the second processor board and the memory.

[0108] It should be noted that, in actual application scenarios, the reset signal of the first processor board can be sent to the second processor board after the first processor board is powered on for the first time after replacement, or it can be detected by the preset status detection program of the second processor board.

[0109] It should be noted that this application configures the communication link between the first processor board and the memory to be enabled upon receiving a reset signal, controls the first independent communication board and the second independent communication board to enable the main communication link with the first processor board, and controls the first independent communication board and the second independent communication board to interrupt the secondary communication link with the second processor board, and interrupts the communication link between the second processor board and the memory. This shortens the usage time of the second processor board, reduces the risk of damage to the second processor board, and improves the reliability of the second processor board in the event of a failure of the first processor board, thereby improving the operational reliability of the dual-ring network data transmission architecture.

[0110] One possible implementation also includes:

[0111] Monitor the reset signal of the data processing node under inspection;

[0112] Upon receiving a reset signal, the communication link between the data processing node under test and the memory is activated;

[0113] The system controls the first and second independent communication boards to enable the main communication link with the data processing node under test, and controls the first and second independent communication boards to interrupt the secondary communication link with the target data processing node, and interrupts the communication link between the target data processing node and the memory.

[0114] It should be noted that, in actual application scenarios, the reset signal of the first processor board can be sent to the second processor board after the first processor board is powered on for the first time after replacement, or it can be detected by the preset status detection program of the second processor board.

[0115] It should be noted that this application, by configuring the communication link between the data processing node under test and the memory to be enabled upon receiving a reset signal, controls the first and second independent communication boards to enable the main communication link with the data processing node under test, and controls the first and second independent communication boards to interrupt the secondary communication link with the target data processing node, and interrupts the communication link between the target data processing node and the memory, thereby shortening the usage time of the first processor board of the target data processing node, reducing the risk of damage to the first processor board of the target data processing node, and reducing the occupation of the computing resources of the first processor board of the target data processing node itself. This improves the reliability of the replacement of the first processor board of the target data processing node in the event of a failure of the first processor board of the data processing node under test, and improves the operational reliability of the dual-ring network data transmission architecture.

[0116] A third aspect of this application provides a computer storage medium carrying one or more computer programs, which, when executed by a data processing node, enables the data processing node to control a data processing node in a multi-ring network data transmission architecture as described in the first aspect or any implementation thereof.

[0117] It should also be noted that the device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. In addition, in the device embodiment drawings provided in this application, the connection relationship between modules indicates that they have a communication connection, which can be implemented as one or more communication buses or signal lines.

[0118] Through the above description of the embodiments, those skilled in the art can clearly understand that this application can be implemented by means of software plus necessary general-purpose hardware, or it can be implemented by special-purpose hardware including application-specific integrated circuits, special-purpose CPUs, special-purpose memory, special-purpose components, etc. Generally, any function performed by a computer program can be easily implemented by corresponding hardware, and the specific hardware structure used to implement the same function can also be diverse, such as analog circuits, digital circuits, or special-purpose circuits. However, for this application, software program implementation is more often the preferred implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a readable storage medium, such as a computer floppy disk, USB flash drive, mobile hard disk, ROM, RAM, magnetic disk, or optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, training equipment, or network device, etc.) to execute the methods described in the various embodiments of this application.

[0119] In the above embodiments, implementation can be achieved, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented in software, it can be implemented, in whole or in part, as a computer program product.

[0120] The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions may be transmitted from one website, computer, training device, or data center to another website, computer, training device, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium may be any available medium that a computer can store or a data storage device such as a training device or data center that integrates one or more available media. The available media may be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., DVDs), or semiconductor media (e.g., solid-state drives (SSDs)).

Claims

1. A multi-ring network data transmission architecture, characterized in that, include: Multiple data processing nodes and at least two ring networks, wherein the two ring networks include a first ring network and a second ring network; The data processing node includes at least a first independent communication board, a second independent communication board, a first processor board, a backplane, and a memory. The first independent communication board is connected in series with the first ring network, and the second independent communication board is connected in series with the second ring network. The first independent communication board, the second independent communication board, the first processor board, and the memory are all hot-swappable on the backplane. The first independent communication board, the second independent communication board, and the memory are all communicatively connected to the first processor board.

2. The multi-ring network data transmission architecture according to claim 1, characterized in that, The data processing node further includes: A second processor board with the same configuration as the first processor board is hot-swappable and mounted on the backplane; The second processor board is communicatively connected to the first independent communication board, the second independent communication board, the first processor board, and the memory.

3. The multi-ring network data transmission architecture according to claim 1, characterized in that, The first processor board of the target data processing node is communicatively connected to the first independent communication board, the second independent communication board, the first processor board, and the memory of the data processing node under test. The data processing node under test is any one of the plurality of data processing nodes, and the target data processing node is any one of the plurality of data processing nodes other than the data processing node under test.

4. The multi-ring network data transmission architecture according to any one of claims 1 to 3, characterized in that, The backplane in the data processing node includes: The base, at least four slots, a power distribution module, and an audible and visual alarm are disposed on the base; The power distribution module is electrically connected to the slot and the audible and visual alarm, respectively. The slot shape is adapted to the data transmission ends of the first independent communication board, the second independent communication board, the first processor board, and the second processor board.

5. A data processing node control method for a multi-ring network data transmission architecture, characterized in that, A first processor board applied to a data processing node in a multi-ring network data parameter architecture as described in any one of claims 1 to 4, wherein the data processing node control method comprises: Receive data transmitted from the first independent communication board and the second independent communication board, store the processing result of the data in the memory, and monitor the first health status of the first independent communication board and the second independent communication board respectively; When the monitoring result of the first health status of the first independent communication board or the second independent communication board indicates a fault status, the first independent communication board or the second independent communication board corresponding to the fault status is switched off, and a communication fault prompt command is output.

6. The data processing node control method according to claim 5, characterized in that, It is also applied to a second processor board, which is the second processor board of the data processing node in claim 2, and the data processing node control method further includes: Monitor the second health status of the first processor board; When the monitoring result of the second health status indicates a fault state, the first processor board is controlled to terminate operation, and the communication link between the second processor board and the memory is enabled. The system controls the first and second independent communication boards to interrupt the main communication link with the first processor board, and controls the first and second independent communication boards to enable the secondary communication link with the second processor board, outputting a processor fault prompt command.

7. The data processing node control method according to claim 5, characterized in that, It is also applied to a target data processing node, wherein the target data processing node is the target data processing node described in claim 3, and the data processing node control method further includes: Monitor the second health status of the data processing node to be inspected; When the monitoring result of the second health state indicates a fault state, the control of the data processing node under test is terminated, and the communication link between the target data processing node and the memory is enabled. The system controls the first and second independent communication boards to interrupt the main communication link with the data processing node under test, and controls the first and second independent communication boards to enable the secondary communication link with the target data processing node, outputting a processor fault prompt command.

8. The data processing node control method according to claim 6, characterized in that, Also includes: Monitor the reset signal of the first processor board; Upon receiving the reset signal, the communication link between the first processor board and the memory is enabled; The system controls the first independent communication board and the second independent communication board to enable the main communication link with the first processor board, and controls the first independent communication board and the second independent communication board to interrupt the secondary communication link with the second processor board, and interrupts the communication link between the second processor board and the memory.

9. The data processing node control method according to claim 7, characterized in that, Also includes: Monitor the reset signal of the data processing node under test; Upon receiving the reset signal, the communication link between the data processing node under test and the memory is activated; The system controls the first independent communication board and the second independent communication board to enable the main communication link with the data processing node under test, and controls the first independent communication board and the second independent communication board to interrupt the secondary communication link with the target data processing node, thereby interrupting the communication link between the target data processing node and the memory.

10. A computer storage medium, characterized in that, The storage medium carries one or more computer programs, which, when executed by the data processing node, enable the data processing node to implement the data processing node control method of the multi-ring network data transmission architecture as described in any one of claims 5 to 9.

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