A silicon wafer, its preparation method and use

Abstract

This invention provides a silicon wafer, its preparation method, and its applications. The silicon wafer of this invention includes a boron-containing layer and a phosphorus-containing layer. The boron-containing layer extends from the outer surface of the silicon wafer to its center, and the spatial distribution of the boron-containing layer and the phosphorus-containing layer within the silicon wafer does not overlap. In the boron-containing layer, the concentration of boron gradually decreases from the outer surface of the silicon wafer to its center. In the phosphorus-containing layer, phosphorus is uniformly distributed. The silicon wafer of this invention can possess both excellent surface conductivity and a long bulk minority carrier lifetime.

Description

Technical Field

[0001] This invention relates to the field of solar cells, and in particular to a silicon wafer, its preparation method, and its applications. Background Technology

[0002] The fabrication of substrate materials for high-efficiency photovoltaic (PV) cells (such as back-contact cells, tunneling oxide passivated contact cells, and heterojunction cells) is a core technological aspect of the current photovoltaic industry. Silicon wafers, as the core substrate material for these cells, directly affect the photoelectric conversion efficiency of high-efficiency PV cells due to their surface conductivity and bulk minority carrier lifetime. In high-efficiency PV cells, the substrate material must simultaneously satisfy high surface conductivity (to reduce electrode contact resistance) and long bulk minority carrier lifetime (to reduce recombination losses of photogenerated carriers). For example, back-contact cells require a high degree of matching between the electrical performance of the back electrode and the emitter; tunneling oxide passivated contact cells rely on a low bulk recombination rate to improve carrier lifetime; and heterojunction cells need to balance surface passivation and conductivity.

[0003] However, traditional doping processes for monocrystalline silicon wafers struggle to balance these conflicting requirements: while single boron doping can improve the surface conductivity of the silicon wafer, it results in low bulk carrier concentration and short minority carrier lifetime; while single phosphorus doping can optimize the bulk minority carrier lifetime, it leads to insufficient surface conductivity. Furthermore, existing co-doping technologies suffer from uneven dopant distribution and insufficient lattice defect repair, resulting in a mismatch between the electrical performance of the silicon wafer and the demands of high-efficiency solar cells.

[0004] With the continuous pursuit of high photoelectric conversion efficiency in high-efficiency photovoltaic cells, there is an urgent need for a silicon wafer that can meet the needs of large-scale production of high-efficiency photovoltaic cells. Summary of the Invention

[0005] This invention provides a silicon wafer that combines high surface conductivity with a long bulk minority carrier lifetime, enabling photovoltaic cells incorporating the silicon wafer to have superior photoelectric conversion efficiency.

[0006] This invention provides a method for preparing a silicon wafer, which can produce the aforementioned silicon wafer. This silicon wafer can have both high surface conductivity and long minority carrier lifetime in bulk, resulting in photovoltaic cells containing the silicon wafer having superior photoelectric conversion efficiency.

[0007] This invention provides a photovoltaic cell comprising the aforementioned silicon wafer, exhibiting excellent photoelectric conversion efficiency.

[0008] A first aspect of the present invention provides a silicon wafer, wherein the silicon wafer includes a boron-containing layer and a phosphorus-containing layer, the boron-containing layer extending from the outer surface of the silicon wafer to the center of the silicon wafer, and the spatial distribution of the boron-containing layer and the phosphorus-containing layer in the silicon wafer does not overlap;

[0009] In the boron-containing layer, the concentration of boron gradually decreases from the outer surface of the silicon wafer to the center of the silicon wafer; in the phosphorus-containing layer, phosphorus is uniformly distributed.

[0010] The silicon wafer described above, wherein the concentration of boron decreases exponentially from the outer surface of the silicon wafer to the center of the silicon wafer.

[0011] In the silicon wafer described above, the concentration of boron in the boron-containing layer is 1.2 × 10⁻⁶. 19 ~5.8×10 20 atoms / cm 3 ; and / or,

[0012] The thickness of the boron-containing layer is 0.5~2μm; and / or,

[0013] The phosphorus concentration in the phosphorus-containing layer is 3.5 × 10⁻⁶. 16 ~8.9×10 17 atoms / cm 3 ; and / or,

[0014] The thickness of the phosphorus-containing layer is 5~20μm.

[0015] The silicon wafer described above has the following characteristics: minority carrier lifetime ≥ 350 μs, sheet resistance 80~150 Ω / □, sheet resistance uniformity ≤ 3%, room temperature conductivity 2.5~6.8 S / m, and surface defect density ≤ 5 × 10⁻⁶. 3 cm -2 .

[0016] A second aspect of the present invention provides a method for preparing the above-described silicon wafer, comprising:

[0017] Boron-doped silicon wafers are obtained by implanting boron into silicon substrates.

[0018] The boron-doped silicon wafer is subjected to phosphorus implantation to obtain a boron-phosphorus-doped silicon wafer;

[0019] The boron-phosphorus-doped silicon wafer is subjected to low-temperature thermal diffusion treatment to obtain the silicon wafer;

[0020] The energy required for the boron injection treatment is less than that required for the phosphorus injection treatment.

[0021] In the preparation method described above, boron implantation is performed using an ion implanter, wherein the boron implantation energy is 80~150 keV and the implantation dose is 5×10⁻⁶. 13 ~2×10 14 ions / cm 2 The chamber vacuum of the ion implanter is 2 × 10⁻⁶. -5~5×10 -5 Pa, the temperature of the silicon substrate is 25~40℃; and / or,

[0022] Phosphorus implantation was performed using an ion implanter, with an implantation energy of 300-500 keV and an implantation dose of 1×10⁻⁶. 12 ~5×10 13 ions / cm 2 The chamber vacuum of the ion implanter is 2 × 10⁻⁶. -5 ~5×10 -5 Pa, the temperature of the silicon substrate is 25~40℃.

[0023] The preparation method described above, wherein the low-temperature thermal diffusion treatment is carried out in a first gas;

[0024] The first gas includes nitrogen and argon, wherein the volume percentage of argon is 70-85% and the volume percentage of nitrogen is 15-30%.

[0025] In the low-temperature thermal diffusion treatment, the total flow rate of the first gas is 200~300 sccm, the temperature is 750~850℃, and the time is 2~4h.

[0026] The preparation method described above further includes annealing and passivating the silicon wafer in a second gas.

[0027] The second gas includes nitrogen and hydrogen, wherein the volume percentage of hydrogen is 5-10% and the volume percentage of nitrogen is 90-95%.

[0028] The annealing and passivation process includes: heating the boron-phosphorus doped silicon wafer to 900-1000°C at a heating rate of 20-30°C / s, holding it at that temperature for 30-60s, and then cooling it to room temperature at a cooling rate of ≥50°C / s.

[0029] The preparation method described above further includes, before the boron implantation process, pre-treating the silicon wafer substrate;

[0030] The pretreatment includes: sequentially texturing and acid washing the silicon wafer substrate.

[0031] A third aspect of the present invention provides a photovoltaic cell comprising the silicon wafer described above.

[0032] This invention provides a silicon wafer with non-overlapping boron-containing and phosphorus-containing layers, wherein the concentration of boron in the boron-containing layer gradually decreases from the outer surface of the silicon wafer to the center, and the phosphorus in the phosphorus-containing layer is uniformly distributed. This reduces carrier recombination losses, enabling the silicon wafer to have both high surface conductivity and long minority carrier lifetime in the bulk phase, thereby giving the photovoltaic cell containing the silicon wafer a superior photoelectric conversion efficiency. Attached Figure Description

[0033] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0034] Figure 1 This is a flowchart illustrating the silicon wafer fabrication process in some embodiments of the present invention. Detailed Implementation

[0035] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. In the absence of conflict, the following embodiments and features can be combined with each other.

[0036] A silicon wafer typically consists of a surface layer and a bulk phase. Due to exposure to air and the influence of processing technology, the silicon atoms in the surface layer no longer follow a complete silicon crystal structure, making it prone to forming an oxide layer, adsorbing impurities, and containing dangling bonds and defects. The bulk phase occupies most of the volume of the silicon wafer. The silicon atoms in the bulk phase have a regular diamond-type crystal structure, are densely arranged, and possess the intrinsic physicochemical properties of silicon. It is the main area of ​​the silicon wafer that realizes the core functions of conductivity and photoelectric conversion.

[0037] Existing silicon wafers suffer from the problem of easy carrier recombination, making it impossible to simultaneously achieve high surface conductivity and long minority carrier lifetime in bulk. The inventors discovered in their research that adjusting the distribution of boron and phosphorus elements in silicon wafers can improve the surface conductivity and extend the bulk minority carrier lifetime of silicon wafers, providing a suitable substrate material for high-efficiency photovoltaic cells.

[0038] A first aspect of the present invention provides a silicon wafer including a boron-containing layer and a phosphorus-containing layer, the boron-containing layer extending from the outer surface of the silicon wafer to the center of the silicon wafer, and the spatial distribution of the boron-containing layer and the phosphorus-containing layer in the silicon wafer not overlapping.

[0039] In the boron-containing layer, the concentration of boron gradually decreases from the outer surface of the silicon wafer to the center of the silicon wafer; in the phosphorus-containing layer, phosphorus is evenly distributed.

[0040] In this invention, the boron-containing layer and phosphorus-containing layer are not independent, separate films. Specifically, the boron-containing layer refers to boron atoms directly incorporated into the silicon lattice, and the phosphorus-containing layer refers to phosphorus atoms directly incorporated into the silicon lattice. The phosphorus-containing layer and boron-containing layer form an integral structure with the silicon wafer; they do not have an independent, layered physical structure. They are merely descriptions of the doping distribution at different spatial locations along the thickness direction of the silicon wafer. In this invention, the "outer surface" refers to the light-receiving surface of the silicon wafer (i.e., the surface near the antireflection layer in photovoltaic modules).

[0041] In this invention, the boron-containing layer extends from the outer surface of the silicon wafer towards the center of the wafer, and is located on the surface layer of the silicon wafer; the phosphorus-containing layer and the boron-containing layer have no spatial overlap in their spatial distribution within the silicon wafer, and the phosphorus-containing layer is located in the bulk phase of the silicon wafer. Because the boron-containing layer and the phosphorus-containing layer have no overlap in their distribution within the silicon wafer's lattice, the neutralization and cancellation of holes provided by boron and electrons provided by phosphorus can be prevented, suppressing carrier recombination losses and improving the conductivity of the silicon wafer.

[0042] In the boron-containing layer, the concentration of boron can decrease systematically (e.g., decreasing in an arithmetic or geometric sequence) or irregularly from the outer surface to the center of the silicon wafer. When the boron concentration gradually decreases from the outer surface to the center of the silicon wafer, the outer surface has more boron, while the concentration is lower near the center. The higher boron concentration on the outer surface improves the conductivity of the silicon wafer, optimizes the contact characteristics between electrodes in the photovoltaic cell, and thus reduces the series resistance of the photovoltaic cell. Conversely, the lower boron concentration at the center of the silicon wafer reduces carrier recombination losses on the surface, allowing more carriers to be transported smoothly from the surface to the bulk phase.

[0043] Uniform distribution of phosphorus in a phosphorus-containing layer can be understood as a phosphorus concentration uniformity of ≤2%. When the phosphorus concentration in the phosphorus-containing layer is uniformly distributed, a stable and consistent doping electric field can be formed within the bulk phase of the silicon wafer. This allows charge carriers to transport in a regular and stable lattice environment, with minimal recombination losses during transport. This extends the carrier survival time in the bulk phase and thus improves the minority carrier lifetime of the silicon wafer.

[0044] This invention enables a silicon wafer to possess both high surface conductivity and a long bulk minority carrier lifetime by spatially including non-overlapping boron-containing and phosphorus-containing layers in the silicon wafer and designing the elemental distribution in the boron-containing and phosphorus-containing layers. This reduces the impedance and loss of carrier (generated by light) transmission to the electrodes, allowing more carriers to be collected by the electrodes, thereby increasing the open-circuit voltage (Voc) and short-circuit current (Jsc) of the photovoltaic cell and thus improving the photoelectric conversion efficiency of the photovoltaic cell.

[0045] The silicon wafer of this invention can be adapted to the junction fabrication and electrode preparation requirements of high-efficiency photovoltaic cells such as back contact cells and tunnel oxide passivated contact cells.

[0046] This invention does not impose any particular limitation on the silicon wafer; any silicon wafer commonly used in the art can be used. For example, the silicon wafer can be an N-type or P-type Czochralski single-crystal silicon wafer. In some embodiments, the total thickness of the silicon wafer can be 130~180μm.

[0047] In some embodiments of the present invention, the concentration of boron decreases exponentially in the direction from the outer surface of the silicon wafer toward the center of the silicon wafer.

[0048] The exponential decrease in boron concentration allows for a higher boron concentration on the outer surface of the silicon wafer, resulting in superior conductivity. This also reduces the resistance to carrier transport from the surface to the bulk phase, allowing for more carriers to exist in the bulk phase, thereby improving the minority carrier lifetime and carrier collection efficiency of the silicon wafer.

[0049] In some embodiments of the present invention, the concentration of boron in the boron-containing layer is 1.2 × 10⁻⁶. 19 ~5.8×10 20 atoms / cm 3 At this stage, a highly doped p+ type conductive layer can be formed, improving the local conductivity of the silicon wafer, reducing the contact resistance between the metal electrode and the silicon wafer, and minimizing series resistance losses during current transmission. Specifically, atoms / cm 3 It indicates the number of atoms of the doping element contained in a unit cubic centimeter volume.

[0050] In some embodiments of the present invention, the concentration of phosphorus in the phosphorus-containing layer is 3.5 × 10⁻⁶. 16 ~8.9×10 17 atoms / cm 3 When this is done, a more uniform electric field distribution can be formed in the bulk phase of the silicon wafer, giving the silicon wafer a longer minority carrier lifetime and higher carrier transport efficiency.

[0051] The thickness of the boron-containing layer refers to the distribution range of boron in the silicon wafer along the thickness direction of the silicon wafer. In some embodiments of the present invention, when the thickness of the boron-containing layer is 0.5~2μm, it can ensure that the outer surface of the silicon wafer has stronger conductivity, meeting the conductivity requirements of the silicon wafer in photovoltaic cells; on the other hand, it can ensure that more charge carriers are transferred from the surface layer of the silicon wafer to the bulk phase, increasing the number of charge carriers in the bulk phase.

[0052] Similarly, the thickness of the phosphorus-containing layer refers to the distribution range of phosphorus in the silicon wafer along the thickness direction of the silicon wafer. In some embodiments of the present invention, when the thickness of the phosphorus-containing layer is 5~20μm, the phosphorus can form a stable and large-scale uniform conductive region while reducing carrier recombination in the bulk phase, thus ensuring more efficient long-distance transport of carriers in the bulk phase.

[0053] In some implementations, secondary ion mass spectrometry (SIMS) can be used to test the concentration of boron in the boron-containing layer. The method in "Determination of Group III and V Impurities in Silicon Single Crystals by Low Temperature Fourier Transform Infrared Spectroscopy" (GB / T24581-2022) can be used as an auxiliary verification basis.

[0054] In some implementations, the test methods in GB / T 29852-2013 can be used to test the phosphorus doping concentration and the thickness of the phosphorus-containing layer.

[0055] In silicon wafers, minority carrier lifetime refers to the average time it takes for minority carriers to recombine from generation. A higher value indicates slower minority carrier recombination and higher carrier transport efficiency. Sheet resistance refers to the sheet resistance of a thin layer of conductive material on the surface of the silicon wafer, characterizing the conductivity of the conductive layer on the surface of the silicon wafer. Sheet resistance uniformity refers to the degree of deviation between the sheet resistance value at different locations on the silicon wafer and the average sheet resistance value. A smaller value indicates better conductivity of the silicon wafer surface. The higher the room temperature conductivity of the silicon wafer, the more freely migrating carriers are inside the silicon wafer, and the better the conductivity of the silicon wafer. Surface defect density refers to the number of lattice defects, dangling bonds, and other defects existing in a unit square centimeter area on the surface of the silicon wafer. A lower value indicates better silicon lattice integrity on the surface of the silicon wafer.

[0056] In some embodiments of the present invention, the silicon wafer has a minority carrier lifetime ≥350μs, a sheet resistance of 80~150Ω / □, a sheet resistance uniformity ≤3%, a room temperature conductivity of 2.5~6.8S / m, and a surface defect density ≤5×10⁻⁶. 3 cm -2At the same time, it can reduce recombination losses of charge carriers, ensuring that photogenerated charge carriers generated under illumination can be efficiently collected and transported; at the same time, it can enable silicon wafers to meet the requirements of good contact between electrodes of photovoltaic cells, allowing silicon wafers to transmit current more quickly in actual working environments; furthermore, silicon wafers have excellent electrical stability. When silicon wafers are used in subsequent manufacturing processes such as junction formation and coating, their electrical performance will not be significantly degraded due to surface defects, giving silicon wafers better process adaptability and fully meeting the performance requirements of photovoltaic cells and other devices. This provides an excellent material basis for photovoltaic cells to achieve high photoelectric conversion efficiency and high stability.

[0057] In some implementations, the minority carrier lifetime of the silicon wafer can be tested using the test methods in GB / T 26065-2010 or GB / T 31855-2015.

[0058] In some implementations, the test methods in GB / T 11073 can be used to test the sheet resistance and sheet resistance uniformity of the silicon wafer.

[0059] In some implementations, the room temperature conductivity of silicon wafers can be tested using one of the methods in GB / T 1551-2021, GB / T 6616-2023, or GB / T 6617-2009; wherein, conductivity = 1 / resistivity, and the resistivity is measured first and then converted to conductivity during the test.

[0060] In some implementations, the surface defect density of the silicon wafer can be tested using the method in GB / T 37051-2018.

[0061] A second aspect of the present invention provides a method for preparing a silicon wafer, comprising:

[0062] Boron-doped silicon wafers are obtained by implanting boron into silicon substrates.

[0063] Boron-doped silicon wafers are subjected to phosphorus implantation to obtain boron-phosphorus-doped silicon wafers;

[0064] Boron-phosphorus doped silicon wafers were subjected to low-temperature thermal diffusion treatments in sequence to obtain silicon wafers;

[0065] The energy required for boron injection treatment is less than that required for phosphorus injection treatment.

[0066] Specifically, boron is implanted into a silicon substrate at a lower energy level, whereby boron is implanted into the outer surface lattice of the silicon wafer, forming a stable doping bond with silicon atoms to obtain a boron-doped silicon wafer. Then, phosphorus is implanted into the boron-doped silicon wafer at a higher energy level. This higher energy allows phosphorus to penetrate the boron-doped region, forming a spatial boundary and implanting into the bulk lattice of the silicon wafer, forming a stable doping bond with silicon atoms to obtain a boron-phosphorus-doped silicon wafer. Subsequently, during a low-temperature thermal diffusion process, both boron and phosphorus diffuse from the outer surface of the boron-phosphorus-doped silicon wafer towards the center. Driven by heat, boron diffuses from the outer surface towards the center. Due to the irregular arrangement of the silicon lattice in the surface layer, the diffusion resistance of boron is relatively high. As the diffusion distance increases, the concentration of boron decreases from the outer surface towards the center, forming a boron-containing layer. Simultaneously, because the silicon lattice in the bulk phase is uniformly arranged, phosphorus can migrate rapidly within the bulk phase, forming a phosphorus-containing layer with a uniform phosphorus distribution, thus obtaining the silicon wafer.

[0067] This invention injects boron and phosphorus into a silicon wafer substrate by using different injection energies. Through low-temperature thermal diffusion, the concentration of boron gradually decreases from the outer surface of the silicon wafer towards the center, while phosphorus is uniformly distributed in the bulk phase. This improves the conductivity of the silicon wafer surface and extends the minority carrier lifetime in the bulk phase, resulting in photovoltaic cells containing silicon wafers with superior photoelectric conversion efficiency.

[0068] Furthermore, the silicon wafer preparation method of the present invention is compatible with existing mature equipment in the photovoltaic industry, requiring no large-scale line modification, and is suitable for large-scale mass production.

[0069] In some embodiments, a boron source is used for boron injection treatment. The present invention does not particularly limit the boron source, and it can be any boron source commonly used in the art. For example, the boron source can be diborane.

[0070] In some embodiments, a phosphorus source is used for phosphorus injection treatment. The present invention does not particularly limit the phosphorus source, and it can be a phosphorus source commonly used in the art. For example, the phosphorus source can be phosphine.

[0071] In some embodiments, the silicon substrate of the present invention has a thickness of 130~180μm and a resistivity of 1~5Ω·cm.

[0072] In some embodiments of the present invention, boron implantation is performed using an ion implanter, with an implantation energy of 80-150 keV and an implantation dose of 5 × 10⁻⁶. 13 ~2×10 14 ions / cm 2 The chamber vacuum of the ion implanter is 2×10⁻⁶. -5 ~5×10-5 When the temperature of the silicon wafer substrate is 25~40℃, boron doping can be ensured to start from the outer surface of the silicon wafer towards the center, thus achieving stable and controllable thickness of the boron doped region in the silicon wafer.

[0073] In some embodiments of the present invention, an ion implanter is used for phosphorus implantation, the phosphorus implantation energy is 300~500 keV, and the implantation dose is 1×10⁻⁶. 12 ~5×10 13 ions / cm 2 The chamber vacuum of the ion implanter is 2×10⁻⁶. -5 ~5×10 -5 When the temperature of the silicon substrate is 25~40℃, phosphorus can fully penetrate the boron-doped region of the silicon wafer, forming a clear boundary with the boron-doped region; at the same time, it provides favorable conditions for the efficient transport of charge carriers in the silicon wafer, extending the minority carrier lifetime of the silicon wafer.

[0074] In some embodiments of the present invention, the low-temperature thermal diffusion treatment is carried out in a first gas, which includes nitrogen and argon, wherein the volume percentage of argon in the first gas is 70-85% and the volume percentage of nitrogen is 15-30%.

[0075] In the low-temperature thermal diffusion process, the total flow rate of the first gas is 200~300 sccm, the temperature is 750~850℃, and the time is 2~4h.

[0076] The first gas atmosphere uses a mixture of nitrogen and argon, which isolates reactive gases such as oxygen during thermal diffusion, preventing oxidation, contamination, or impurity introduction on the silicon wafer surface. This protects the silicon lattice in the boron-doped and phosphorus-doped regions from damage and maintains a stable thermal diffusion environment. Furthermore, by controlling the argon volume percentage to 70-85% and the nitrogen volume percentage to 15-30%, the high thermal stability and inertness of argon further enhance the purity and safety of the heat treatment atmosphere. Combined with nitrogen, this creates a suitable diffusion environment, allowing phosphorus to diffuse effectively into the silicon wafer. More uniform diffusion within the crystal lattice results in a longer bulk minority carrier lifetime for the silicon wafer. Simultaneously, when the total flow rate of the first gas is 200-300 sccm, the temperature is 750-850℃, and the time is 2-4 hours, a gradually decreasing gradient concentration distribution of boron can be formed on the surface layer, creating a boron-containing layer, while conserving energy. Phosphorus can also be uniformly distributed in the bulk phase, forming a phosphorus-containing layer. Furthermore, this ensures the stability of the silicon wafer's crystal lattice structure, thereby guaranteeing the stability of carrier transport within the silicon wafer and providing a structural basis for the high photoelectric conversion efficiency of photovoltaic cells.

[0077] In some implementations, the heating rate during low-temperature thermal diffusion treatment is 5~8℃ / min, which can further ensure that the spatial distribution of the boron-containing layer and the phosphorus-containing layer in the silicon wafer does not overlap.

[0078] In some embodiments of the present invention, the silicon wafer is further subjected to annealing and passivation treatment in a second gas.

[0079] The second gas includes nitrogen and hydrogen, wherein the volume percentage of hydrogen is 5-10% and the volume percentage of nitrogen is 90-95%.

[0080] Annealing and passivation treatment includes: heating the boron-phosphorus doped silicon wafer to 900-1000℃ at a heating rate of 20-30℃ / s, holding it at that temperature for 30-60s, and then cooling it to room temperature at a cooling rate of ≥50℃ / s.

[0081] Annealing and passivation can repair lattice defects generated during element implantation of silicon wafers, further improving the conductivity of the silicon wafer surface and extending the minority carrier lifetime of the bulk phase.

[0082] When the volume percentage of hydrogen in the second gas is 5-10% and the volume percentage of nitrogen is 90-95%, hydrogen can provide a reducing and passivating atmosphere, effectively saturating the dangling bonds on the silicon wafer surface (unsaturated valence bonds on the silicon atom surface that have not formed covalent bonds become carrier recombination centers, reducing the conductivity of the silicon wafer), thus giving minority carriers a longer lifetime. Combined with nitrogen as an inert carrier gas, this ensures both the passivation effect of boron-phosphorus doped silicon wafers and a safe and controllable annealing passivation process. Simultaneously, a heating rate of 20-30℃ / s enables rapid heating, ensuring that the already formed boron and phosphorus doping distribution is not disrupted. This process not only breaks down the silicon wafer but also improves the efficiency of silicon wafer fabrication. Furthermore, raising the temperature of the boron-phosphorus doped silicon wafer to 900-1000℃ and holding it at that temperature for 30-60 seconds can quickly repair lattice defects caused by element injection and thermal diffusion within the silicon wafer, reduce carrier recombination centers, and further improve the minority carrier lifetime of the silicon wafer. Moreover, the high-temperature short-time treatment does not cause significant changes in the element doping distribution in the silicon wafer. After holding at that temperature, cooling it to room temperature at a rate of ≥50℃ / s can quickly "freeze" and fix the lattice structure and boron and phosphorus element distribution repaired at high temperature, preventing secondary oxidation and lattice distortion of the silicon wafer during the cooling process.

[0083] In some embodiments of the present invention, the process further includes: pre-treatment of the silicon wafer substrate prior to the boron implantation process;

[0084] Pretreatment includes texturing and acid washing of the silicon wafer substrate.

[0085] Texturing can create a rough structure on the surface of the silicon wafer substrate, increasing the doping area of ​​boron in the silicon lattice on the outer surface of the silicon wafer substrate; pickling can remove metal impurities and natural oxide layers from the surface of the silicon wafer substrate, ensuring the cleanliness of the silicon wafer surface and providing excellent substrate conditions for subsequent boron and phosphorus implantation.

[0086] In some implementations, when the root roughness of the silicon wafer substrate surface is 0.8~1.5μm after texturing, light reflection from the silicon wafer in the photovoltaic cell can be reduced, the light absorption efficiency of the photovoltaic cell can be improved, and the photovoltaic cell can have a better photoelectric conversion efficiency.

[0087] In some embodiments, the pickling treatment uses a mixture of hydrofluoric acid and nitric acid with a volume ratio of 1:(5~8), and the pickling time is 2~5 minutes.

[0088] like Figure 1 As shown, Figure 1 This is a flowchart illustrating the preparation process of a silicon wafer according to some embodiments of the present invention. The silicon wafer of the present invention can be prepared by including the following steps:

[0089] The silicon wafer substrate is texturized using an alkaline solution, then acid-washed using a mixture of hydrofluoric acid and nitric acid, followed by washing the silicon wafer substrate with pure water until it is neutral, and then dried in hot air to obtain a clean silicon wafer substrate.

[0090] A clean silicon wafer substrate is placed in an ion implanter, and boron is implanted using diborane as the boron source to obtain a boron-doped silicon wafer.

[0091] Using phosphine as the phosphorus source, phosphorus implantation was performed to obtain boron-phosphorus doped silicon wafers;

[0092] A boron-phosphorus doped silicon wafer is placed in a tube diffusion furnace, and a first gas, including argon and nitrogen, is introduced into the tube diffusion furnace to perform thermal diffusion treatment, thereby obtaining a silicon wafer precursor.

[0093] The silicon wafer precursor is transferred to a rapid annealing furnace, and a second gas, including hydrogen and nitrogen, is introduced to perform annealing and passivation treatment, thereby obtaining the silicon wafer of the present invention.

[0094] In some implementations, the silicon wafer can be removed from the rapid annealing furnace when the temperature cools to below 100°C.

[0095] A third aspect of the present invention provides a photovoltaic cell comprising the aforementioned silicon wafer. Because the boron-containing layer and the phosphorus-containing layer in the silicon wafer of the present invention do not overlap, and the boron concentration in the boron-containing layer gradually decreases from the outer surface of the silicon wafer towards the center, while the phosphorus is uniformly distributed in the phosphorus-containing layer, the photovoltaic cell can simultaneously possess high surface conductivity and long minority carrier lifetime in the bulk phase. This reduces carrier recombination losses, improves the transport and collection efficiency of photogenerated carriers, and thus improves the photoelectric conversion efficiency of the photovoltaic cell.

[0096] In some embodiments, the silicon wafer of the present invention can be fabricated into a battery by referring to the preparation steps in T / CIET 634-2024 or T / CPIA 0055.3-2025, and then the battery conversion efficiency can be tested according to the methods in GB / T 6495.1-2021 or GB / T 6495.3-2023.

[0097] In some embodiments, the photoelectric conversion efficiency of the photovoltaic cell of the present invention can be improved by 0.4 to 0.8% compared to photovoltaic cells that include existing single-element doped silicon wafers.

[0098] The technical solution of the present invention will be further described below with reference to specific embodiments.

[0099] Example 1

[0100] The silicon wafer fabrication method of this embodiment includes the following steps:

[0101] (a) A P-type Czochralski single-crystal silicon wafer with a thickness of 150 μm and a resistivity of 3 Ω·cm was selected as the silicon wafer substrate. A sodium hydroxide solution (sodium hydroxide mass percentage of 2%) was used to perform texturing treatment at 80 °C for 18 min. After texturing, the root mean square roughness of the silicon wafer substrate surface was 1.2 μm. Then, a mixture of hydrofluoric acid and nitric acid with a volume ratio of 1:6 was used to acid wash for 3 min (hydrofluoric acid mass percentage of 40% and nitric acid mass percentage of 68%). The silicon wafer substrate was washed with pure water until neutral and dried in hot air at 100 °C to obtain a clean silicon wafer substrate.

[0102] (b) Place the clean silicon wafer substrate in an ion implanter with a chamber vacuum of 3 × 10⁻⁶. -5 Pa, the temperature of the silicon substrate is 30℃, diborane is used as the boron source, the implantation energy is 100keV, and the implantation dose is 1×10⁻⁶. 14 ions / cm 2 Boron-doped silicon wafers were obtained;

[0103] (c) Maintain a vacuum level of 3 × 10⁻⁶ in the ion implanter chamber. -5 Pa, using phosphine as the phosphorus source, with an injection energy of 400 keV and an injection dose of 2 × 10⁻⁶. 13ions / cm 2 Boron-phosphorus-doped silicon wafers were obtained;

[0104] (d) The boron-phosphorus doped silicon wafer is placed in a tube diffusion furnace for thermal diffusion treatment. A first gas is introduced into the tube diffusion furnace, wherein the volume percentage of argon is 80% and the volume percentage of nitrogen is 20%, and the total flow rate of the first gas is 250 sccm. The tube diffusion furnace is heated to 800°C at a rate of 6°C / min and held at that temperature for 3 hours to obtain the silicon wafer precursor.

[0105] (e) The silicon wafer precursor is transferred to a rapid annealing furnace and a second gas is introduced, wherein the volume percentage of hydrogen in the second gas is 8% and the volume percentage of nitrogen is 92%. The rapid annealing furnace is heated to 950°C at a heating rate of 25°C / s, held at that temperature for 45s, and then cooled to room temperature at a rate of 60°C / s to obtain the silicon wafer.

[0106] Example 2

[0107] The silicon wafer fabrication method of this embodiment includes the following steps:

[0108] (a) An N-type Czochralski single-crystal silicon wafer with a thickness of 130 μm and a resistivity of 1 Ω·cm was selected as the silicon wafer substrate. A sodium hydroxide solution (sodium hydroxide mass percentage of 2%) was used to perform texturing treatment at 80 °C for 18 min. After texturing, the root mean square roughness of the silicon wafer substrate surface was 0.8 μm. Then, a mixture of hydrofluoric acid and nitric acid with a volume ratio of 1:5 was used to acid wash for 3 min (hydrofluoric acid mass percentage of 40% and nitric acid mass percentage of 68%). The silicon wafer substrate was washed with pure water until neutral and dried in hot air at 90 °C to obtain a clean silicon wafer substrate.

[0109] (b) Place the clean silicon wafer substrate in an ion implanter with a chamber vacuum of 2 × 10⁻⁶. -5 Pa, the temperature of the silicon substrate is 25℃, diborane is used as the boron source, the implantation energy is 80keV, and the implantation dose is 5×10⁻⁶. 13 ions / cm 2 Boron-doped silicon wafers were obtained;

[0110] (c) Maintain a vacuum level of 2 × 10⁻⁶ in the ion implanter chamber. -5 Pa, using phosphine as the phosphorus source, with an injection energy of 300 keV and an injection dose of 1 × 10⁻⁶. 12 ions / cm 2 Boron-phosphorus-doped silicon wafers were obtained;

[0111] (d) The boron-phosphorus doped silicon wafer is placed in a tube diffusion furnace for thermal diffusion treatment. A first gas is introduced into the tube diffusion furnace, wherein the volume percentage of argon is 70% and the volume percentage of nitrogen is 30%, and the total flow rate of the first gas is 200 sccm. The tube diffusion furnace is heated to 750°C at a rate of 5°C / min and held at that temperature for 4 hours to obtain the silicon wafer precursor.

[0112] (e) The silicon wafer precursor is transferred to a rapid annealing furnace and a second gas is introduced, wherein the volume percentage of hydrogen in the second gas is 5% and the volume percentage of nitrogen is 95%. The rapid annealing furnace is heated to 900°C at a heating rate of 20°C / s, held at that temperature for 60s, and then cooled to room temperature at a rate of 50°C / s to obtain the silicon wafer.

[0113] Example 3

[0114] The silicon wafer fabrication method of this embodiment includes the following steps:

[0115] (a) A P-type Czochralski single-crystal silicon wafer with a thickness of 180 μm and a resistivity of 5 Ω·cm was selected as the silicon wafer substrate. A sodium hydroxide solution (sodium hydroxide mass percentage of 2%) was used to perform texturing treatment at 80 °C for 18 min. After texturing, the root mean square roughness of the silicon wafer substrate surface was 1.5 μm. Then, a mixture of hydrofluoric acid and nitric acid with a volume ratio of 1:8 was used to acid wash for 5 min (hydrofluoric acid mass percentage of 40% and nitric acid mass percentage of 68%). The silicon wafer substrate was washed with pure water until neutral and dried in hot air at 110 °C to obtain a clean silicon wafer substrate.

[0116] (b) Place the clean silicon wafer substrate in an ion implanter with a chamber vacuum of 5 × 10⁻⁶. -5 Pa, the temperature of the silicon substrate is 40℃, diborane is used as the boron source, the implantation energy is 150keV, and the implantation dose is 5×10⁻⁶. 13 ions / cm 2 Boron-doped silicon wafers were obtained;

[0117] (c) Maintain a vacuum level of 2 × 10⁻⁶ in the ion implanter chamber. -5 Pa, using phosphine as the phosphorus source, with an injection energy of 300 keV and an injection dose of 1 × 10⁻⁶. 12 ions / cm 2 Boron-phosphorus-doped silicon wafers were obtained;

[0118] (d) The boron-phosphorus doped silicon wafer is placed in a tube diffusion furnace for thermal diffusion treatment. A first gas is introduced into the tube diffusion furnace, wherein the volume percentage of argon is 85% and the volume percentage of nitrogen is 15%, and the total flow rate of the first gas is 300 sccm. The tube diffusion furnace is heated to 850°C at a rate of 8°C / min and held at that temperature for 2 hours to obtain the silicon wafer precursor.

[0119] (e) The silicon wafer precursor is transferred to a rapid annealing furnace and a second gas is introduced, wherein the volume percentage of hydrogen in the second gas is 10% and the volume percentage of nitrogen is 90%. The rapid annealing furnace is heated to 1000°C at a heating rate of 30°C / s, held at that temperature for 30s, and then cooled to room temperature at a rate of 70°C / s to obtain the silicon wafer.

[0120] Example 4

[0121] The method for preparing the silicon wafer in this embodiment is basically the same as that in Example 1, except that:

[0122] In step (d), the tubular diffusion furnace is heated to 1100°C.

[0123] Comparative Example 1

[0124] The preparation method of the silicon wafer in this comparative example is basically the same as that in Example 1, except that:

[0125] There is no step (c), i.e., no phosphorus injection treatment is performed.

[0126] Performance testing

[0127] The following performance tests were performed on the examples and comparative examples respectively:

[0128] (1) Test of boron doping concentration and boron-containing layer thickness

[0129] In the silicon wafers tested in Examples 1-4, the boron doping concentration and thickness of the boron-containing layer were determined using secondary ion mass spectrometry (SIMS). The specific operation was performed according to the ISO 14237:2010 standard. The testing instrument was a CAMECA IMS 7f secondary ion mass spectrometer (SIMS), equipped with a stylus profilometer (for depth calibration). The standard reference material was SRM-2137 (boron-doped silicon standard sample), used for instrument relative sensitivity factor (RSF) calibration. The testing reagents were acetone and anhydrous ethanol (analytical grade), used for cleaning the samples. Auxiliary equipment included an ultrasonic cleaner, a Class 100 clean bench, and a nitrogen dryer.

[0130] Test steps:

[0131] The silicon wafer to be tested was cut into 10mm×10mm square samples using a diamond cutter to ensure that the edges of the silicon wafer were free of damage and cracks.

[0132] The cut silicon wafers were placed in acetone and anhydrous ethanol in sequence and ultrasonically cleaned for 5 minutes each time. After cleaning, the silicon wafers were removed, the surface moisture was dried with high-purity nitrogen (purity ≥99.999%), and then placed on a Class 100 clean bench for 10 minutes for later use.

[0133] The standard reference material (SRM-2137) was placed in a secondary ion mass spectrometer, and the same test parameters as the silicon wafer under test were set according to the standard requirements of ISO 14237:2010. Boron element ( 10 B + , 11 B + ) and silicon element ( 28 Si + The relative sensitivity factor (RSF) is calculated from the signal strength of the signal.

[0134] A stylus profilometer is used to measure the sputtering craters of the standard reference material, set the sputtering rate, and complete the depth calibration to ensure the accuracy of the boron-containing layer thickness test.

[0135] Start the secondary ion mass spectrometer and evacuate the chamber to a vacuum level of ≤5×10⁻⁶. -7 After stabilizing at Pa for 30 minutes, the instrument vacuum level was confirmed to meet the test requirements.

[0136] The pretreated silicon wafer to be tested is placed on the sample stage of the secondary ion mass spectrometer, the position of the silicon wafer is adjusted to ensure that the surface of the silicon wafer is perpendicular to the ion beam, and the silicon wafer is fixed.

[0137] Set the primary ion beam type to O2 + The energy was set to 5~10 keV, and the beam current density was 0.5~2 μA / cm. 2 The scanning area is selected from the center of the silicon wafer as the test area, and the area of ​​the scanning area is more than three times that of the test and analysis area to avoid edge effects affecting the test results; alternating acquisition is used. 10 B + , 11 B + and 28 Si + The ion signal was collected with a single-point acquisition time of ≤1s and an acquisition cycle count of ≥100 times; the chamber vacuum level was monitored in real time during the test and maintained at <5×10⁻⁶. -7 Pa; set the linear sputtering rate to 0.05~0.1μm / min.

[0138] The test program is started, and the instrument automatically performs sputtering and signal acquisition, recording boron element levels in real time. 10 B + , 11 B + ) and silicon element ( 28 Si + The curve showing the change in signal intensity of boron over sputtering time; when the boron signal intensity drops to less than 10% of the background signal intensity, the test is stopped, and the sputtering depth at this point is the thickness of the boron-containing layer.

[0139] Based on the relative sensitivity factor (RSF) obtained from instrument calibration, combined with the boron element collected by the test ( 10 B + , 11 B + ) and silicon element ( 28 Si + The signal strength is used to calculate the boron doping concentration using the following formula:

[0140] C i =RSF×(J i11 -J1B1G)+(RSF / δ)×(J i10 -J1B0G)

[0141] Where C i The boron doping concentration at the i-th sampling point (atoms / cm³) 3 RSF is the relative sensitivity factor; J i11 For the i-th collection point 11 B + Signal strength; J1B1G is 11 B + Background signal strength; δ is 10 B and 11 B isotopic abundance ratio; J i10 For the i-th collection point 10 B + Signal strength; J1B0G is 11 B + Background signal strength;

[0142] Using a linear sputtering rate model, the depth of each sampling point is calculated based on the sputtering time and the set sputtering rate. The formula is: d i =(i-1)×(d t / N); where d i d represents the depth (μm) of the i-th acquisition point. t The total sputtering depth is (μm); N is the total number of data collections.

[0143] Based on the calculated concentration and depth at each sampling point, a boron element concentration-depth distribution curve was plotted, taking a concentration ≥1.0×10⁻⁶. 18 atoms / cm 3 The region is the boron-containing layer, and the maximum depth of this region is the thickness of the boron-containing layer, while the highest concentration is the doping concentration of boron on the outer surface of the silicon wafer.

[0144] Three different test areas of the silicon wafer to be tested were selected for parallel testing. The relative deviation of the three test results was ≤±3%, and the average value of the three test results was taken as the final test result.

[0145] The test results are shown in Table 1.

[0146] (2) Phosphorus doping concentration test

[0147] According to the test methods in GB / T 29852-2013, the phosphorus doping concentration and thickness of the phosphorus-containing layer in the silicon wafers of Examples 1-4 were tested. The test results are shown in Table 1.

[0148] (3) Minority birth lifetime test

[0149] The minority carrier lifetime of the silicon wafers in Examples 1-4 and Comparative Example 1 were tested according to the test methods in GB / T 31855-2015. The test results are shown in Table 1.

[0150] (4) Sheet resistance and sheet resistance uniformity

[0151] The sheet resistance and sheet resistance uniformity of the silicon wafers in Examples 1-4 and Comparative Example 1 were tested according to the test methods in GB / T 11073. The test results are shown in Table 1.

[0152] (5) Room temperature conductivity

[0153] The room temperature resistivity of the silicon wafers in Examples 1-4 and Comparative Example 1 was tested according to the method in GB / T 1551-2021. The test results are shown in Table 1.

[0154] (6) Surface defect density

[0155] The surface defect density of the silicon wafers in Examples 1-4 and Comparative Example 1 was tested according to the method in GB / T 37051-2018. The test results are shown in Table 1.

[0156] (7) Battery conversion efficiency

[0157] Following the preparation steps in T / CIET 634-2024, the silicon wafers of Example 1 and Comparative Example 1 were fabricated into BC cells. Then, the cell conversion efficiency of the BC cells was tested according to the method in GB / T 6495.1-2021. The test results are shown in Table 1.

[0158] Table 1

[0159]

[0160] As shown in Table 1, the minority carrier lifetime, sheet resistance, sheet resistance uniformity, room temperature conductivity, and surface defect density of the silicon wafers in Examples 1-4 are all superior to those in Comparative Example 1. This is because: in the silicon wafers of the present invention, the boron-containing layer and the phosphorus-containing layer do not overlap in their distribution, thereby reducing carrier recombination losses in the silicon wafer; at the same time, since the concentration of boron in the silicon wafer decreases from the outer surface to the center, and phosphorus is uniformly distributed in the phosphorus-containing layer, the conductivity of the silicon wafer surface is improved, the recombination losses of carriers in the surface layer are reduced, and the minority carrier lifetime in the bulk phase is extended; furthermore, when the silicon wafers of the present invention are used in photovoltaic cells, more carriers can be collected by the electrodes, thus improving the cell conversion efficiency of the photovoltaic cell.

[0161] Finally, it should be noted that other embodiments of the invention will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This invention is intended to cover any variations, uses, or adaptations of the invention that follow the general principles of the invention and include common knowledge or customary techniques in the art not disclosed herein, and is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of the invention is limited only by the appended claims.

Claims

1. A silicon wafer, characterized in that, The silicon wafer includes a boron-containing layer and a phosphorus-containing layer. The boron-containing layer extends from the outer surface of the silicon wafer to the center of the silicon wafer, and the spatial distribution of the boron-containing layer and the phosphorus-containing layer in the silicon wafer does not overlap. In the boron-containing layer, the concentration of boron gradually decreases from the outer surface of the silicon wafer to the center of the silicon wafer; in the phosphorus-containing layer, phosphorus is uniformly distributed.

2. The silicon wafer according to claim 1, characterized in that, The concentration of boron decreases exponentially from the outer surface of the silicon wafer to its center.

3. The silicon wafer according to claim 1 or 2, characterized in that, The boron concentration in the boron-containing layer is 1.2 × 10⁻⁶. 19 ~5.8×10 20 atoms / cm 3 ; and / or, The thickness of the boron-containing layer is 0.5~2μm; and / or, The phosphorus concentration in the phosphorus-containing layer is 3.5 × 10⁻⁶. 16 ~8.9×10 17 atoms / cm 3 ; and / or, The thickness of the phosphorus-containing layer is 5~20μm.

4. The silicon wafer according to any one of claims 1-3, characterized in that, The silicon wafer has a minority carrier lifetime ≥350μs, a sheet resistance of 80~150Ω / □, a sheet resistance uniformity ≤3%, a room temperature conductivity of 2.5~6.8S / m, and a surface defect density ≤5×10⁻⁶. 3 cm -2 .

5. A method for preparing a silicon wafer according to any one of claims 1-4, characterized in that, include: Boron-doped silicon wafers are obtained by implanting boron into silicon substrates. The boron-doped silicon wafer is subjected to phosphorus implantation to obtain a boron-phosphorus-doped silicon wafer; The boron-phosphorus-doped silicon wafer is subjected to low-temperature thermal diffusion treatment to obtain the silicon wafer; The energy required for the boron injection treatment is less than that required for the phosphorus injection treatment.

6. The preparation method according to claim 5, characterized in that, Boron was implanted using an ion implanter at an implantation energy of 80–150 keV and an implantation dose of 5 × 10⁻⁶ keV. 13 ~2×10 14 ions / cm 2 The chamber vacuum of the ion implanter is 2 × 10⁻⁶. -5 ~5×10 -5 Pa, the temperature of the silicon substrate is 25~40℃; and / or, Phosphorus implantation was performed using an ion implanter, with an implantation energy of 300-500 keV and an implantation dose of 1×10⁻⁶. 12 ~5×10 13 ions / cm 2 The chamber vacuum of the ion implanter is 2 × 10⁻⁶. -5 ~5×10 -5 Pa, the temperature of the silicon substrate is 25~40℃.

7. The preparation method according to claim 5 or 6, characterized in that, The low-temperature thermal diffusion treatment is carried out in the first gas; The first gas includes nitrogen and argon, wherein the volume percentage of argon is 70-85% and the volume percentage of nitrogen is 15-30%. In the low-temperature thermal diffusion treatment, the total flow rate of the first gas is 200~300 sccm, the temperature is 750~850℃, and the time is 2~4h.

8. The preparation method according to any one of claims 5-7, characterized in that, It also includes annealing and passivating the silicon wafer in a second gas; The second gas includes nitrogen and hydrogen, wherein the volume percentage of hydrogen is 5-10% and the volume percentage of nitrogen is 90-95%. The annealing and passivation process includes: heating the boron-phosphorus doped silicon wafer to 900-1000°C at a heating rate of 20-30°C / s, holding it at that temperature for 30-60s, and then cooling it to room temperature at a cooling rate of ≥50°C / s.

9. The preparation method according to any one of claims 5-8, characterized in that, Prior to the boron implantation process, the process further includes: pre-treatment of the silicon wafer substrate; The pretreatment includes: sequentially texturing and acid washing the silicon wafer substrate.

10. A photovoltaic cell, characterized in that, Includes the silicon wafer as described in any one of claims 1-4.

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