Silicon carbide schottky diode wafer level clip packaging method and apparatus

Abstract

This invention relates to the field of diode packaging technology, and discloses a wafer-level CLIP packaging method and apparatus for silicon carbide Schottky diodes. The method involves: performing magnetron sputtering and Schottky anode region photolithography on a silicon carbide wafer, reserving CLIP connection areas during electrode evaporation, and performing mask windowing and pulse current adjustment to obtain an electroplated boss wafer; after spin-coating and curing a polyimide passivation layer on the electroplated boss wafer, ablation openings are made in the top and back pad areas of the boss; copper-based CLIP clips are positioned above the selected windowed wafer bosses; the clamping force in each area is adjusted, and reflow soldering is performed to obtain a clip-interconnected wafer; the clip-interconnected wafer is subjected to epoxy resin transfer molding and laser scribing to obtain a double-sided interconnected packaged chip. This invention achieves wafer-level batch double-sided metallized interconnection, reduces package parasitic inductance and double-sided thermal resistance, and improves the electrical performance and thermal management capabilities of silicon carbide Schottky diodes in high-frequency, high-power applications.

Description

Technical Field

[0001] This invention relates to the field of diode packaging technology, and in particular to a wafer-level CLIP packaging method and apparatus for silicon carbide Schottky diodes. Background Technology

[0002] Silicon carbide Schottky diodes are widely used in high-power power electronic systems such as electric vehicle charging modules and photovoltaic inverters due to their excellent high-frequency switching characteristics and high-temperature resistance. However, the parasitic inductance introduced by traditional wire bonding packaging severely restricts the performance of silicon carbide devices under high-frequency operating conditions, and single-sided heat dissipation structures are difficult to meet the stringent thermal management requirements of high-power-density applications. Traditional constant-current electroplating processes result in boss height deviations exceeding ±8μm, causing interface contact impedance fluctuations between the CLIP clip and the boss to exceed 1.2mΩ, increasing the device's conduction losses and thermal resistance. Simultaneously, the thin-film stress accumulated during the back metal stack deposition process can generate microcracks at the interface, degrading the ohmic contact quality. Summary of the Invention

[0003] The main objective of this invention is to provide a wafer-level CLIP packaging method and apparatus for silicon carbide Schottky diodes. This invention achieves wafer-level mass production of double-sided metallized interconnects, reduces package parasitic inductance and double-sided thermal resistance, and improves the electrical performance and thermal management capabilities of silicon carbide Schottky diodes in high-frequency, high-power applications.

[0004] To achieve the above objectives, the present invention provides a wafer-level CLIP packaging method for silicon carbide Schottky diodes, comprising the following steps: A back-side metallized wafer is obtained by magnetron sputtering of a silicon carbide wafer. Schottky anode region photolithography is performed on the back metallized wafer, and CLIP connection areas are reserved during electrode evaporation to obtain a double-sided electrode wafer; A mask window is opened and a pulse current is adjusted in the CLIP connection area of ​​the double-sided electrode wafer to obtain an electroplated boss wafer. After the low-temperature curable polyimide passivation layer is spin-coated and cured on the electroplated boss wafer, windows are ablated in the top and back pad areas of the boss to obtain a selectively windowed wafer. The copper-based CLIP clips are positioned above the selected windowed wafer bosses, the clamping force of each area is adjusted and reflow soldering is performed to obtain the clip interconnect wafers. The interlocking wafer is subjected to epoxy resin transfer molding and laser scribing to obtain a double-sided interconnect packaged chip.

[0005] Optionally, in a first implementation of the first aspect of the present invention, the step of magnetron sputtering the silicon carbide wafer to obtain a back-side metallized wafer includes: The back side of the silicon carbide wafer is ground and polished to obtain a polished wafer; Electron beam evaporation of a titanium-nickel-silver three-layer cathode stack is performed on the back side of the polished wafer, while a stress sensor collects the thin film stress detection value in real time. When the detected value of the thin film stress exceeds the stress threshold, the substrate temperature adjustment amount is calculated and the temperature of the heating stage is adjusted to the set range for heat preservation, thereby obtaining the back metallized wafer.

[0006] Optionally, in a second implementation of the first aspect of the present invention, the step of performing Schottky anode region photolithography on the back metallized wafer and reserving CLIP connection areas during electrode evaporation to obtain a double-sided electrode wafer includes: After growing an oxide mask on the front side of the back metallized wafer, a Schottky anode active region pattern is formed by photolithography and the oxide layer is etched to obtain a patterned wafer. A four-layer aluminum-titanium-nickel-gold anode stacked electrode structure is deposited on the front side of the patterned wafer by electron beam evaporation to obtain a front electrode wafer. A CLIP connection area of ​​a predetermined width is reserved at the edge of the front electrode wafer to obtain a double-sided electrode wafer.

[0007] Optionally, in a third implementation of the first aspect of the present invention, reserving a CLIP connection region of a predetermined width at the edge of the front electrode wafer to obtain a double-sided electrode wafer includes: Calculate the reserved width and boundary position parameters of the CLIP connection area based on the chip size and the area of ​​the Schottky anode active region; According to the boundary position parameters, an electroplating mask is set at the edge of the front electrode wafer and a rectangular array window is opened in the CLIP connection area to obtain a mask pattern wafer. Based on the window size of the mask pattern wafer, an electroplating solution is prepared and the initial process parameters of the plating solution are set to obtain a double-sided electrode wafer.

[0008] Optionally, in a fourth implementation of the first aspect of the present invention, the step of performing mask windowing and pulse current adjustment on the CLIP connection region of the double-sided electrode wafer to obtain an electroplated boss wafer includes: A boss growth rate model is established for the CLIP connection region of the double-sided electrode wafer, and a target trajectory height value is set. Real-time boss height values ​​are collected from multiple monitoring points using a laser displacement sensor; The real-time boss height value at each monitoring point is compared with the target trajectory height value at the corresponding time point by point, and the integral and differential terms of the current height deviation are calculated. The pulse current adjustment amount and the plating solution temperature compensation amount are calculated based on the integral and differential terms of the current height deviation. The pulse current and the plating solution temperature are then synchronously adjusted based on the pulse current adjustment amount and the plating solution temperature compensation amount to obtain the electroplated boss wafer.

[0009] Optionally, in a fifth implementation of the first aspect of the present invention, after the low-temperature curable polyimide passivation layer is spin-coated and cured on the electroplated boss wafer, windows are ablated in the top and back pad areas of the boss to obtain a selected windowed wafer, comprising: A low-temperature curable polyimide precursor solution is spin-coated onto the surface of the electroplated boss wafer, and imidization is completed at a set temperature to obtain a cured passivation layer wafer. The ultraviolet laser wavelength pulse energy density and repetition frequency parameters are set for the top of the boss and the back pad area of ​​the solidified passivation layer wafer. Laser ablation is performed using a bidirectional grating scanning path and the accuracy of the windowed edge contour is monitored in real time to obtain a laser-windowed wafer. The bottom metal surface of the laser-windowed wafer is cleaned with oxygen plasma to remove polyimide residue, resulting in a selectively windowed wafer.

[0010] Optionally, in a sixth implementation of the first aspect of the present invention, the step of positioning the copper-based CLIP clip above the selected area windowed wafer boss, adjusting the clamping force in each area, and performing heat reflow soldering to obtain the clip interconnect wafer includes: The pre-formed copper-based CLIP clip is positioned above the selected windowed wafer boss, and the contact pressure values ​​of multiple monitoring points are collected in real time through a pressure sensor array, and the pressure uniformity index of each monitoring point is calculated. When the pressure uniformity index exceeds the set pressure threshold, the pressure adjustment scheme corresponding to the minimum value of the sum of squares of the deviations between the pressure at each monitoring point and the target pressure is solved, and the servo system is controlled to adjust the clamping force in each area to obtain the positioning wafer after pressure equalization. The positioning wafer after pressure equalization is subjected to a preheating stage, a linear heating stage, and a high-temperature reflow stage in sequence, and the solder is melted to form an intermetallic compound interface layer to obtain a clip interconnect wafer.

[0011] Optionally, in a seventh implementation of the first aspect of the present invention, the step of performing epoxy resin transfer molding and laser scribing on the interlocking wafer to obtain a double-sided interconnect packaged chip includes: A release film is attached to the top and back pad areas of the CLIP clips of the interconnect wafer to keep them exposed. The interconnect wafer is then placed in a mold cavity, and preheated epoxy molding compound is injected into the cavity to obtain a molded filled wafer. The molded filled wafer is heated to a set curing temperature and held for a set time to complete the epoxy group crosslinking reaction and then the release film is removed to obtain the packaged wafer. The packaging wafer is scanned along the dicing path, and the laser beam is focused on the middle layer of the packaging wafer to form a through dicing groove, thereby obtaining a double-sided interconnect packaged chip.

[0012] Optionally, in an eighth implementation of the first aspect of the present invention, scanning the packaging wafer along the dicing path to focus a laser beam at the middle layer position of the packaging wafer to form a through-cut groove, thereby obtaining a double-sided interconnect packaged chip, includes: The coordinate sequence of the dicing centerline is obtained based on the thickness of the packaged wafer and the chip spacing, and the scanning path arrangement order is generated according to the spiral order from the outside to the inside. The required number of scans is calculated based on the ratio of the thickness of the packaged wafer to the single scan cutting depth, and a different focus depth position is assigned for each scan. According to the scanning path arrangement order and the focusing depth position, the laser head is driven to move along each dicing groove path in sequence, and multiple scans are performed on each scanning path according to the focusing depth position to accumulate and form a through dicing groove, thereby obtaining a diced wafer; A blue film is attached to the back of the diced wafer, and then a radial expansion force is applied to break the chip along the dicing groove to obtain a double-sided interconnect packaged chip.

[0013] The present invention also provides a silicon carbide Schottky diode wafer-level CLIP packaging device, comprising: The magnetron sputtering unit is used to perform magnetron sputtering on silicon carbide wafers to obtain back-side metallized wafers. The photolithography unit is used to perform Schottky anode region photolithography on the back metallized wafer and reserve CLIP connection areas during electrode evaporation to obtain a double-sided electrode wafer. An electroplating unit is used to perform mask windowing and pulse current adjustment on the CLIP connection area of ​​the double-sided electrode wafer to obtain an electroplated boss wafer. The ablation windowing unit is used to ablate windows in the top and back pad areas of the boss after the low-temperature curing polyimide passivation layer is spin-coated and cured on the electroplated boss wafer, to obtain a selectively windowed wafer. The heating reflow soldering unit is used to position the copper-based CLIP clips above the selected windowed wafer boss, adjust the clamping force of each area and perform heating reflow soldering to obtain clip interconnect wafers. The laser scribing unit is used to perform epoxy resin transfer molding and laser scribing on the interlocking wafer to obtain a double-sided interconnect packaged chip.

[0014] In summary, the technical solution provided by this invention establishes a closed-loop control system for dynamic height tracking of electroplated bosses and an adaptive pressure distribution mechanism for CLIP clips. During the back metallization stage, stress sensors collect real-time film stress detection values ​​and dynamically adjust the substrate temperature according to a stress release function, effectively releasing the accumulated stress at the interface between the metal stack and silicon carbide, ensuring stable ohmic contact interface quality. During the preparation of electroplated bosses, laser displacement sensors collect real-time height data at set time intervals. The height values ​​at each monitoring point are compared with the target trajectory point by point, and the integral and differential terms of the deviation are calculated. A proportional-integral-differential algorithm is used to synchronously adjust the pulse current and plating solution temperature compensation, achieving a significant improvement in boss height accuracy and effective control of top flatness. In the CLIP clip welding stage, a pressure sensor array collects multi-point contact pressure in real time and calculates the pressure uniformity index. When the pressure exceeds a set threshold, an optimization objective function is established to solve for the optimal pressure adjustment scheme and drive the servo system to adjust the clamping force in each area, ensuring the uniformity and consistency of the interface contact resistance. This invention enables wafer-level mass production of double-sided metallized interconnects, reduces package parasitic inductance and double-sided thermal resistance, and improves the electrical performance and thermal management capabilities of silicon carbide Schottky diodes in high-frequency, high-power applications. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of the wafer-level CLIP packaging method for silicon carbide Schottky diodes in one embodiment of the present invention; Figure 2 This is a structural block diagram of a silicon carbide Schottky diode wafer-level CLIP packaging device in one embodiment of the present invention.

[0016] The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0017] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0018] Reference Figure 1 This embodiment provides a wafer-level CLIP packaging method for silicon carbide Schottky diodes, including the following steps: S1, magnetron sputtering is performed on the silicon carbide wafer to obtain a back-side metallized wafer; The process involves mechanical pretreatment of the back surface of the silicon carbide wafer. This pretreatment involves using precision back-side grinding to reduce the original wafer thickness to approximately 120±3 μm, minimizing vertical heat conduction and resistance paths while maintaining sufficient mechanical strength. Following this, chemical mechanical polishing (CMP) is performed to remove any residual subsurface damage layer. The polishing process uses an alkaline SiO2 colloidal polishing slurry with a mass ratio of 1:0.3:8.7, operating at a pressure of 35 kPa and a rotation speed of 65 rpm for 12 minutes, reducing the back surface roughness to Ra < 0.5 nm. The polished wafer is then transferred to a high-vacuum magnetron sputtering system, where the chamber is evacuated to a base pressure < 5 × 10⁻⁶. -6 Under the condition of Pa, three back cathode metal stacks of titanium (50 nm), nickel (100 nm), and silver (200 nm) were sequentially deposited. The titanium layer was used to enhance the adhesion between the metal and the SiC substrate and to act as a diffusion barrier interface. The nickel layer constructed an ohmic contact interface, and the silver layer served as a low-resistance current propagation path. During the entire metal sputtering process, three resistive stress sensors were deployed at the wafer edge and collected stress detection values ​​during the thin film deposition process at a period of 0.5 seconds. When the real-time stress detection data indicated that the current stress exceeded the set stress threshold of 150 MPa, the stress was detected. At this time, the embedded control system calculates the required substrate temperature adjustment based on the preset stress release function ΔT=σ / (α·E), where σ represents the residual stress of the thin film, α is the thermal expansion coefficient of silicon carbide, and E is the Young's modulus of silicon carbide. It also controls the heating stage temperature to rise to between 340°C and 360°C in real time and maintains a constant temperature for 8 minutes. By using the stress release mechanism caused by thermal expansion, the total residual stress is released to below 50MPa, ensuring the adhesion reliability and electrical stability of the back metal stack structure during multiple thermal cycles, thus obtaining a back metallized wafer.

[0019] S2, perform Schottky anode region photolithography on the back metallized wafer and reserve CLIP connection area during electrode evaporation to obtain a double-sided electrode wafer; Specifically, an oxide mask for selective pattern transfer is constructed on the front side of the back-side metallized wafer. The oxide layer is grown in situ on the silicon carbide wafer surface through thermal oxidation or plasma-enhanced chemical vapor deposition to form a SiO2 thin film with a thickness of approximately 200 nm, which serves as a masking medium for anode pattern etching. Positive photoresist is spin-coated onto the oxide layer surface, and the active region of the Schottky anode is patterned on the front side through ultraviolet exposure and development processes. This region occupies approximately 62% to 68% of the total chip area to achieve an optimal balance between forward conduction characteristics and reverse voltage withstand performance. A wet etching process is then performed on the SiO2 mask layer using a buffered oxide etchant. Under controlled conditions of 23°C and 3 minutes of etching time, the oxide layer in the patterned area is selectively removed, forming a precisely patterned Schottky contact window on the front side. After mask etching and photoresist stripping, the patterned wafer is loaded into a high-vacuum electron beam evaporation apparatus. Four metal thin films of aluminum, titanium, nickel, and gold are deposited sequentially to form a front anode stacked electrode structure. The aluminum layer is about 200 nm thick and directly contacts SiC to form a Schottky barrier. The titanium layer acts as a diffusion barrier to prevent aluminum atoms from migrating into the crystal. The nickel layer is used to improve the solderability of the electrode, and the gold layer is used to enhance the surface oxidation resistance and improve conductivity. During the deposition process, the evaporation rate of each metal layer and the substrate temperature parameters are controlled to ensure that the metal grain structure is uniform and dense. At the same time, during the electrode evaporation process, an electrode-free deposition area of ​​about 3 to 5 mm is reserved in the edge area of ​​the front side of the wafer. This reserved design effectively avoids the electrode metal covering the CLIP connection area and affecting the subsequent interconnect quality, resulting in a double-sided electrode wafer.

[0020] S3, mask windowing and pulse current adjustment are performed on the CLIP connection area of ​​the double-sided electrode wafer to obtain an electroplated boss wafer; It should be noted that a theoretical model for the boss growth rate in the CLIP connection region is established. This model is based on Faraday's law of electrolysis, considering physical parameters such as the molar mass of copper, electron transfer number, Faraday constant, density, and unit opening area. A functional expression is constructed to represent the deposition thickness of metallic copper per unit time under a specific current. Based on this, a target trajectory height function is set, such as a function that increases linearly or non-linearly with time, to guide the deposition rate in the actual electroplating process. Mask coating and photolithography windowing are performed on the wafer surface, forming a standardized rectangular opening array in the CLIP connection region. A non-contact laser displacement sensor array is deployed above the electroplating platform to collect real-time boss height data from multiple typical windows at high frequency. The spatial resolution of the laser displacement sensor is better than 0.1 μm, with a sampling period of 0.3 seconds, dynamically tracking the height change trend throughout the electroplating process. The actual boss height value collected at each monitoring point is compared with the target trajectory height value point by point. The height deviation at each point is calculated in real time, and the integral and derivative terms are dynamically solved in the embedded control system. The integral term is used to evaluate the historical cumulative deviation, and the derivative term reflects the current height change rate, forming a closed-loop feedback signal. Based on the closed-loop feedback signal, the adjustment amount of the pulse current is calculated and the compensation amount of the plating solution temperature is generated simultaneously to counteract the Joule heat accumulation effect caused by current fluctuations and avoid the impact of nonlinear changes in plating solution viscosity and ion mobility on deposition consistency. The control system corrects the amplitude and duty cycle of the pulse current in real time according to the proportional-integral-derivative adjustment model. At the same time, it predicts and adjusts the plating solution temperature according to the current change trend, so that the pulse current and temperature form a highly coordinated linkage mechanism. Throughout the electroplating process, the copper boss deposition rate is kept synchronized with the target trajectory height change, resulting in an electroplated boss wafer.

[0021] S4. After the polyimide passivation layer is spin-coated and cured on the electroplated boss wafer, windows are ablated in the top and back pad areas of the boss to obtain a selected windowed wafer. Specifically, a polyimide precursor solution is spin-coated onto the front side of the wafer to form a cover layer. The precursor solution has a polyimide solid content of 18 wt% and uses N-methylpyrrolidone as a solvent. A passivation film of uniform thickness is formed on the wafer surface through a two-stage spin-coating process. In the first stage, the wafer is pre-spinned at 500 rpm for 5 seconds to remove air bubbles. In the second stage, the wafer is spin-coated at 3000 rpm for 30 seconds to form a film layer of about 8 μm thickness. After spin-coating, the wafer is placed on a hot stage in a nitrogen atmosphere for segmented temperature-curing treatment. The temperature curve is set to 80℃ for 10 minutes to completely remove residual solvent, 150℃ for 15 minutes to initiate the imidization reaction, and 350℃ for 60 minutes to complete the cross-linking and curing of the polyimide network structure. The temperature rate is controlled within 2℃ / min to avoid cracking or blistering of the passivation layer due to changes in thermal gradient, resulting in a wafer with a cured passivation layer. After the passivation layer has cured, laser selective windowing is performed on the top area of ​​the electroplated bosses and the pad area on the back of the wafer. A 355nm ultraviolet nanosecond laser system is used with a single pulse energy density of 1.2J / cm². 2 Laser parameters with a repetition frequency of 20kHz, a pulse width of 10ns, and a scanning speed of 800mm / s are used to precisely ablate the target area through a bidirectional grating path. The ablation process is based on the photochemical interaction between the laser and the polyimide surface. In the laser-irradiated area, CN and CO bonds are directionally broken, releasing small molecule volatile products, thus achieving non-thermal material removal. At the same time, the window boundary is monitored and adjusted in real time through an edge tracking algorithm to ensure that the window size covers the top area of ​​the 1.6mm×0.5mm boss and the edge gap is controlled within 50±10μm. After the laser windowing is completed, oxygen plasma cleaning is performed on the metal area at the bottom of the wafer window. Oxygen plasma is excited with 300W radio frequency power and the residual organic polyimide fragments are completely removed within 45 seconds to obtain a selectively windowed wafer.

[0022] S5, Position the copper-based CLIP clip above the selected windowed wafer boss, adjust the clamping force of each area and perform heating reflow soldering to obtain the clip interconnect wafer; Specifically, pre-formed CLIP clips are prepared. The CLIP clips use C11000 oxygen-free copper as the base material with a thickness of 0.4 mm. The bottom surface is precision milled to form a groove structure that corresponds one-to-one with the boss array. The groove depth is about 42 μm and the single-sided gap is controlled to be 0.025 mm to ensure uniform flow and sufficient wetting of the solder during the welding process. Ni / Sn double-layer solderable metal is pre-plated on the groove surface to enhance the interface solderability and prevent oxidation failure. The CLIP clip is positioned above the front-side boss of the selected windowed wafer and loaded into a vacuum reflow soldering system integrating a multi-channel pressure monitoring module. The system is equipped with a 16-channel pressure sensor array, which is arranged in the corresponding area on the back of the CLIP clip to collect the contact pressure value of each monitoring point in real time. The controller calculates the pressure uniformity index to evaluate the spatial consistency of the current clamping state. When the pressure uniformity index exceeds the preset pressure threshold of 12%, the clamping force optimization program is automatically triggered. By constructing an objective function to minimize the sum of squares of pressure deviation, the optimal clamping force adjustment between each monitoring point and the target pressure is solved by a simplex optimization algorithm. The pneumatic servo system synchronously adjusts the clamping force of each area at a rate of 0.2 MPa / s according to the calculation results. After 3 to 5 rounds of iteration, the pressure uniformity index is converged to within 8%, so that a good and balanced physical contact interface is formed between the wafer and the clip. After pressure adjustment, the process enters the temperature-controlled reflow soldering stage, sequentially executing the preheating stage, the linear heating stage, and the high-temperature reflow stage with thermal profile control. In the preheating stage, the temperature is held at 150℃ for 60 seconds to eliminate the temperature gradient. Then, the temperature is linearly increased to 240℃ at a rate of 1.5℃ / s and held at this temperature for 60 seconds, allowing the Sn layer to completely melt and form a Ni3Sn4 intermetallic compound interface layer with a thickness of approximately 3±0.3μm with the Ni metal on the boss surface. After the high-temperature reflow is completed, the control system slowly cools down to below 180℃ to solidify the solder joints and release the clamping force, achieving a low-void, high-strength, and high-conductivity interconnect structure between the CLIP clip and the wafer boss. The resulting clip interconnect wafer has a solder contact resistance controlled at 0.45±0.05mΩ.

[0023] S6. The interlocking wafer is subjected to epoxy resin transfer molding and laser scribing to obtain a double-sided interconnect packaged chip.

[0024] Specifically, the wafers that have completed CLIP bonding are pre-treated by applying a 0.1mm thick polytetrafluoroethylene release film to the top area of ​​the CLIP bonding on the front side and the metal pad area on the back side of the wafer. During the molding process, these two types of key interconnect interfaces remain exposed to avoid being covered by resin and affecting the bonding or electrical connection. The interlocking wafer with the release film attached is placed in the center positioning groove of the lower mold cavity. The upper and lower molds are then closed to form a completely sealed mold cavity. The cavity volume is designed based on the wafer size and required encapsulation layer thickness, calculated as wafer area multiplied by the total wafer thickness plus a 0.6mm margin. This ensures that the resin layer completely covers the wafer edge area after injection molding and provides sufficient mechanical strength. Epoxy resin molding compound, preheated to 120℃ for 15 minutes, is injected into the mold cavity through an injection unit heated to 170℃. The epoxy resin possesses excellent properties such as a glass transition temperature of 175℃, a coefficient of thermal expansion of 12ppm / K, and a thermal conductivity of 0.8W / m·K. The resin pressure during injection is controlled via a closed-loop sensor feedback system and maintained at a constant value of 8MPa, while the injection rate is controlled at 15cm / s. 3 The mold employs a central gate structure to achieve a radial flow pattern from the center of the wafer to the edge, significantly reducing air bubbles and stress concentration within the mold. After resin filling, the entire mold is heated to 175°C and held at this temperature for 90 seconds to promote a full cross-linking reaction between the epoxy groups and the curing agent molecules, forming a three-dimensional network structure. After the curing reaction is complete, the temperature is slowly lowered to 80°C, and the mold is removed. After removing the release films on both sides, a molded encapsulation structure is obtained, with exposed metal pads on both sides of the wafer and complete epoxy resin encapsulation on the periphery. The packaged wafer is transferred to a laser dicing platform. Under the action of a 1064nm infrared nanosecond laser beam, it is repeatedly scanned according to the 80μm wide dicing groove path preset in the photolithography stage. The laser power is controlled at 15W, the scanning speed at 200mm / s, and the pulse frequency at 40kHz, so that the laser energy is focused on the middle layer of the packaged wafer. After 6 scans, a through-cut groove with a width of less than 30μm is formed on each dicing channel to avoid thermal cracking damage to the CLIP bumps or pads. After laser dicing, the wafer is uniformly stretched using a blue film expansion process to achieve chip separation, resulting in a silicon carbide Schottky diode chip with neat edges, complete packaging, and double-sided interconnection.

[0025] In one example, magnetron sputtering is performed on a silicon carbide wafer to obtain a back-side metallized wafer, including: The back side of the silicon carbide wafer is ground and polished to obtain a polished wafer; A titanium-nickel-silver three-layer cathode stack was magnetron sputtered on the back of the polished wafer, while the thin film stress detection value was collected in real time by a stress sensor. When the detected thin film stress exceeds the stress threshold, the substrate temperature adjustment amount is calculated and the heating stage temperature is adjusted to the set range for heat preservation, thus obtaining the back metallized wafer.

[0026] In this example, the back surface of the original silicon carbide wafer is thinned and polished. A high-precision back-side grinding process reduces the wafer thickness from the initial value to 120±3 μm, lowering the device's series resistance and vertical thermal resistance. Chemical mechanical polishing (CMP) is then performed to eliminate the subsurface damage layer caused by mechanical polishing, ensuring a clean, dense, and low-defect interface for metal deposition. The polishing slurry uses an alkaline mixture of SiO2 colloid, H2O2, and deionized water in a mass ratio of 1:0.3:8.7. Polishing is carried out continuously for 12 minutes at a polishing pressure of 35 kPa and a disk speed of 65 rpm, reducing the back surface roughness Ra to less than 0.5 nm, resulting in a polished wafer with ultra-low surface roughness. The polished wafer is then transferred to a high-vacuum magnetron sputtering chamber, where the chamber pressure is reduced to a base value of 5 × 10⁻⁶. -6 Under conditions below Pa, three back cathode metal stacks of titanium (Ti), nickel (Ni), and silver (Ag) were sequentially deposited. The Ti layer thickness was set to 50 nm, serving as an adhesion and diffusion barrier between the metal and silicon carbide interface. The Ni layer thickness was 100 nm, used to form a stable, low-resistance ohmic contact interface. The Ag layer thickness was 200 nm, providing a low-resistance conductive channel and improving solder wettability and current spread capability. Throughout the sputtering deposition process, three high-sensitivity resistive stress sensors were deployed at the wafer edge to collect real-time data on thin film deposition stress changes every 0.5 seconds. When the cumulative thin film stress exceeded the set stress threshold of 150 MPa, the stress response control module was invoked to calculate the required substrate temperature compensation based on the stress release function ΔT = σ / (α·E), where σ is the current stress value and α is the thermal expansion coefficient of silicon carbide (2.77 × 10⁻⁶). -6 / K), E is the Young's modulus of silicon carbide (448GPa), and the embedded thermal control unit dynamically raises the temperature of the heating stage to the range of 340℃ to 360℃ and maintains it at a constant temperature for 8 minutes. This introduces an active thermal regulation mechanism into the wafer during the deposition process to release stress gradients and stabilize the wafer structure, achieving low residual stress bonding between the metal and the substrate. This enables the back metal stack structure to have good stability and low contact resistance characteristics in multi-temperature zone post-processing, resulting in a highly consistent back metallized wafer that meets the requirements of high-current double-sided interconnect packaging.

[0027] In one example, a Schottky anode region photolithography is performed on the back-side metallized wafer, and a CLIP connection region is reserved during electrode evaporation to obtain a double-sided electrode wafer, including: After growing an oxide mask on the front side of the back-side metallized wafer, a Schottky anode active region pattern is formed by photolithography and the oxide layer is etched to obtain a patterned wafer. A four-layer anode stacked electrode structure of aluminum-titanium-nickel-gold is deposited on the front side of a patterned wafer by electron beam evaporation to obtain a front electrode wafer. By reserving a CLIP connection area of ​​a set width at the edge of the front electrode wafer, a double-sided electrode wafer is obtained.

[0028] In this example, a mask structure is constructed on the front side of the back-side metallized wafer. A 200nm thick silicon dioxide oxide layer is grown on the front surface of the silicon carbide wafer using thermal oxidation or plasma-enhanced chemical vapor deposition (PECVD). This silicon dioxide oxide layer serves as the mask medium for photolithography pattern transfer, exhibiting excellent dielectric stability and etching resistance, effectively protecting non-anodine areas from accidental etching. A layer of positive photoresist is spin-coated onto the silicon dioxide oxide layer, and an exposure dose of 135mJ / cm is applied using a photolithography machine. 2 The pattern is exposed to ultraviolet light and developed with a developer to form an active region pattern corresponding to the Schottky anode on the front side of the wafer. The active region area accounts for 62% to 68% of the total chip area to achieve the optimal trade-off between forward conduction characteristics and reverse voltage withstand performance. After the photolithography pattern is defined, the SiO2 mask layer is wet-etched using a buffered oxide etchant (volume ratio NH4F:HF=6:1) at 23°C for 3 minutes at an etching rate of approximately 65 nm / min. This transfers the mask pattern into the oxide layer and exposes the anode contact window of the SiC substrate. Subsequently, the pattern is cleaned by stripping the photoresist to obtain the patterned wafer. A patterned wafer is placed in a high-vacuum electron beam evaporation system, where four metal thin films—aluminum, titanium, nickel, and gold—are sequentially deposited to form an anode multilayer electrode structure. The aluminum layer is 200 nm thick and forms a Schottky contact directly with SiC, with a barrier height between 0.95 and 1.05 eV. The titanium layer is 50 nm thick to prevent aluminum atoms from migrating into SiC, avoiding interface degradation. The nickel layer is 100 nm thick as an intermediate solder compatibility layer to improve solderability. The gold layer is 150 nm thick for oxidation protection and to improve surface conductivity. During the evaporation process, the chamber pressure is maintained below 8 × 10⁻⁶ eV. -5 The evaporation rates of the various metals were controlled at 0.3 nm / s, 0.15 nm / s, 0.2 nm / s, and 0.18 nm / s, respectively, and the substrate temperature was stabilized at 150 °C to optimize the film density and grain structure, resulting in a front metal electrode structure with good Schottky contact characteristics and welding compatibility. During the metal evaporation process, an undeposited area with a width of 3 to 5 mm was reserved at the edge of the wafer's front side as an electroplating platform for CLIP interconnection. This area was not patterned in the previous photolithography stage, ensuring the formation of a continuous metal-covered connection area outside the front electrode. Thus, after the front electrode construction was completed, a double-sided electrode wafer with both a central Schottky anode region and an edge CLIP connection region was obtained.

[0029] In one example, a CLIP connection area of ​​a predetermined width is reserved at the edge of the front electrode wafer to obtain a double-sided electrode wafer, including: Calculate the reserved width and boundary position parameters of the CLIP connection area based on the chip size and the area of ​​the Schottky anode active region; Based on the boundary position parameters, an electroplating mask is set at the edge of the front electrode wafer and a rectangular array window is opened in the CLIP connection area to obtain a mask pattern wafer. Based on the window size of the mask pattern wafer, an electroplating solution is prepared and the initial process parameters of the plating solution are set to obtain a double-sided electrode wafer.

[0030] In this example, parameters are calculated based on the chip's geometry and the area of ​​the active region of the Schottky anode to ensure that the CLIP connection area has sufficient structural strength and current carrying capacity. The reserved design of the interconnect platform is completed without interfering with the main functional area of ​​the chip. The active region of the anode occupies 62% to 68% of the total chip area. The maximum available bandwidth of the outer boundary area is calculated based on this area ratio, and the width of the CLIP connection area that can be reserved for each chip unit is calculated accordingly, set to 3 to 5 mm. The boundary position parameters are determined by comprehensively positioning the actual distance from the chip edge to the outer edge of the active region to ensure that the electroplating area does not cross the Schottky contact metal and has array consistency. After calculating the boundary position parameters, a matching electroplating mask pattern is set on the edge of the front side of the wafer. The electroplating mask is initially covered by spin-coating a 12μm thick photoresist. A rectangular window array is then formed in the reserved area using standard photolithography, with window sizes of 1.8mm × 0.6mm and a center-to-center spacing of 2.5mm, to achieve optimal solder boss density and thermal stress buffering structure. High-fidelity transfer of the pattern edge is achieved through exposure dose control, development time adjustment, and developer concentration adjustment, forming a window matrix on the front electrode metal, resulting in the mask pattern wafer. Based on the mask pattern wafer, the copper deposition rate per unit time is calculated by combining the total area of ​​the mask windows, the area of ​​each individual window, and the target deposition height. The required current density and current waveform characteristics are then deduced. A suitable electroplating solution formulation is selected based on the required copper layer thickness and thermal management capabilities, with a preferred copper sulfate electroplating solution system consisting of CuSO4·5H2O 220g / L, H2SO4 55g / L, and Cl... - Ions 65mg / L, and a brightener of polyethylene glycol and thiourea compound 3.5mL / L was added to stabilize the coating grains and smoothness. The initial electroplating parameters were set, including plating bath temperature 25℃, pulse current frequency 50Hz, initial duty cycle 50%, and deposition current density calculated based on window area and target thickness. This formed the process preparation conditions with synchronized temperature and electrical control, and a double-sided electrode wafer was obtained.

[0031] In one example, mask windowing and pulse current adjustment are performed on the CLIP connection region of the double-sided electrode wafer to obtain an electroplated boss wafer, including: A boss growth rate model is established for the CLIP connection region of the double-sided electrode wafer, and the target trajectory height value is set. Real-time boss height values ​​are collected from multiple monitoring points using a laser displacement sensor; The real-time boss height value at each monitoring point is compared with the target trajectory height value at the corresponding time point by point, and the integral and differential terms of the current height deviation are calculated. The pulse current adjustment amount and the plating solution temperature compensation amount are calculated based on the integral and differential terms of the current height deviation. The pulse current and the plating solution temperature are then synchronously adjusted based on the pulse current adjustment amount and the plating solution temperature compensation amount to obtain the electroplated boss wafer.

[0032] In this example, a dynamic rate model for copper layer growth during electroplating is established based on the principle of electrochemical deposition. The model is based on Faraday's law and considers parameters such as the molar mass of copper, electron transfer number, Faraday constant, material density, and single window area. An expression for the thickness change caused by copper ion reduction deposition per unit time under a fixed current is constructed, and this expression is discretized into a time function. A target height trajectory function is set in conjunction with the target thickness distribution. This target height trajectory function is an acceleration curve with a compensation term to correct for the interference of plating solution concentration decay and edge effects on the deposition rate over time. During wafer electroplating, a non-contact laser displacement sensor array is deployed at key locations above the wafer to collect the actual boss heights of multiple plating windows in the CLIP connection area in real time. The collection process is performed at 0.3-second intervals and 0.1 μm resolution, continuously acquiring the current height values ​​of each monitoring point and dynamically comparing them with the target height. The control system calculates the current deviation in real time based on the height error and performs integral and derivative operations on it to form the integral and derivative terms in the PID control loop, obtaining the dynamic error signal used for feedback adjustment. Based on the integral and differential terms, and combined with the proportional, integral, and differential gain coefficients in the calibration parameters, the pulse current adjustment and the temperature adjustment caused by Joule thermal compensation are calculated. The pulse current adjustment controls the amplitude and duty cycle of the pulse current waveform to directly affect the copper ion reduction rate, while the temperature adjustment is used to adjust the plating bath temperature to indirectly affect the ion diffusion rate and interfacial reactivity. The combined effect of these two factors achieves dynamic control of the boss height growth rate. The pulse current and temperature adjustments are applied to the electroplating power supply and the constant-temperature plating bath system, respectively. Real-time adjustment of the pulse current output and the circulating heating of the plating bath gradually brings the actual deposition height closer to the target trajectory, resulting in electroplated boss wafers.

[0033] In one example, after the polyimide passivation layer is spin-coated and cured on the electroplated boss wafer, windows are ablated in the pad areas on the top and back of the boss to obtain a selected windowed wafer, including: A low-temperature curable polyimide precursor solution is spin-coated onto the surface of the electroplated boss wafer, and imidization is completed at a set temperature to obtain a cured passivation layer wafer. The ultraviolet laser wavelength pulse energy density and repetition frequency parameters are set for the top of the boss and the back pad area of ​​the solidified passivation layer wafer. Laser ablation is performed using a bidirectional grating scanning path and the accuracy of the windowed edge contour is monitored in real time to obtain a laser-windowed wafer. Oxygen plasma cleaning is performed on the bottom metal surface of the laser-windowed wafer to remove polyimide residues, resulting in a selectively windowed wafer.

[0034] In this example, a polyimide precursor solution is spin-coated onto the wafer surface. The precursor solution is a high-temperature thermosetting solution system with N-methylpyrrolidone as the solvent and a polyimide solids content of 18wt%. It is uniformly spread onto the wafer surface using a two-stage spin-coating method. Initially, spin-coating at 500 rpm for 5 seconds is used for degassing and uniform spread of the precursor. Then, spin-coating at 3000 rpm for 30 seconds achieves thickness control and forms a polyimide film layer with a thickness of approximately 8 μm. After spin-coating, the wafer is transferred to a hot-stage system under an inert nitrogen atmosphere for further processing. A stepped temperature-curing process was employed, with the temperature curve designed as follows: 80℃ for 10 minutes to ensure complete solvent evaporation, 150℃ for 15 minutes to complete the prepolymerization stage of the imidization reaction, and 350℃ for 60 minutes to promote the full cross-linking of polyimide molecular chains to form a three-dimensional network structure. Throughout this process, the temperature rise rate was controlled below 2℃ / min to prevent stress cracking or film blistering caused by internal thermal gradients, resulting in a cured passivation layer wafer with a dense surface, continuous edges, high mechanical strength, and excellent insulation and heat resistance properties. The top of the electroplated bosses and the metal pad area on the back of the wafer were selected as the target windowing areas on the cured passivation layer wafer. Key parameters of the ultraviolet laser system were set, including a laser source with a wavelength of 355nm and a single-pulse energy density of 1.2J / cm². 2The pulse repetition frequency is 20kHz, the pulse width is 10ns, and the laser scanning speed is controlled at 800mm / s. A bidirectional grating scanning strategy is employed to achieve symmetrical coverage and uniform energy control of the laser beam in the target area. Simultaneously, edge recognition and shape tracking algorithms are used to monitor the boundary contour changes of the laser windowing area in real time during processing. Feedback is used to adjust the laser spot path and correct accumulated errors, resulting in an ablation window structure with regular edges and precisely defined dimensions on the polyimide surface. The opening size at the top of the boss is controlled to be 1.6mm × 0.5mm, and the edge spacing is 50±... Within a 10μm range, residual polyimide fragments formed during the ablation process adhere to the metal surface. The organic residues are completely removed by plasma cleaning. The laser-windowed wafer is then placed in an oxygen plasma cleaning chamber with a radio frequency power of 300W and a processing time of 45 seconds. This causes the polyimide residues to undergo oxidation and breakage due to the action of high-energy oxygen free radicals in the plasma, generating small molecule gases such as CO, CO2, and H2O that escape. This reduces the surface residue thickness at the bottom of the window, resulting in a clean and flat bottom metal surface with good solder wettability and interfacial bonding, thus obtaining a selectively windowed wafer.

[0035] In one example, copper-based CLIP clips are positioned above selected windowed wafer bosses, the clamping forces in each area are adjusted, and reflow soldering is performed to obtain clip interconnect wafers, including: The pre-formed copper-based CLIP clip is positioned above the selected windowed wafer boss, and the contact pressure values ​​of multiple monitoring points are collected in real time through a pressure sensor array, and the pressure uniformity index of each monitoring point is calculated. When the pressure uniformity index exceeds the set pressure threshold, the pressure adjustment scheme corresponding to the minimum value of the sum of squares of the deviations between the pressure at each monitoring point and the target pressure is solved, and the servo system is controlled to adjust the clamping force in each area to obtain the positioning wafer after pressure equalization. After pressure equalization, the positioning wafer is sequentially subjected to a preheating stage, a linear heating stage, and a high-temperature reflow stage, which melts the solder to form an intermetallic compound interface layer, thus obtaining a clip-on interconnect wafer.

[0036] In this example, a copper-based CLIP clip with a thickness of 0.4 mm is placed on the front side of the wafer, so that the pre-made groove array on the bottom of the clip is aligned and vertically attached to the electroplated boss array. The groove structure has a depth of 42 μm and a size that is 0.05 mm larger than the boss, so as to provide an effective gap for the flow of molten solder during the soldering process. At the same time, a 3 μm nickel layer and an 8 μm tin layer are pre-plated on the bottom of the clip as the solder interface metal. After the clips and wafers are initially aligned, the entire assembly is installed into a vacuum reflow soldering system. The system integrates a 16-channel pressure sensor array, with sensors evenly distributed in the contact area between the back of the clips and the positioning stage. These sensors collect the contact pressure values ​​at each monitoring point in real time under pre-loading conditions. All monitoring data is input into an embedded controller for processing. The system calculates a pressure uniformity index to assess whether the current clamping state meets the spatial equilibrium standard for pressure distribution. When the pressure uniformity index exceeds a set pressure threshold of 12%, an optimization algorithm module is automatically activated. This module constructs a pressure adjustment scheme with the goal of minimizing the sum of squares of the deviations between the pressure at each monitoring point and the target pressure. A simplex algorithm is used to solve for the adjustment amount of the pneumatic clamping unit in each region. The servo system is then controlled to adjust the clamping force of the corresponding region at a rate of 0.2 MPa / s according to the solution results. This gradually brings the contact pressure at each sensor monitoring point closer to the global target value. After multiple rounds of iterative calculations and force feedback adjustments, the pressure uniformity index converges to within the threshold, resulting in a positioning wafer with highly consistent pressure distribution and stable structural alignment. After pressure balance adjustment, the thermal control welding process begins. The preheating stage involves constant heating at 150°C for 60 seconds to ensure uniform temperature distribution across the wafer and interposer, and to activate the flux. A linear heating stage is then initiated, slowly raising the temperature to 240°C at a rate of 1.5°C / s and maintaining it on the high-temperature platform for 60 seconds. This allows the tin layer at the bottom of the interposer to completely melt and wet the nickel metal surface, while simultaneously reacting with the nickel metal at the top of the boss to form a stable intermetallic compound interface layer. This eutectic interface layer possesses high conductivity and good mechanical bonding strength. In the subsequent cooling stage, the temperature drop rate is controlled to within 5°C / min. Once the entire wafer cools to below 180°C, all clamping forces are released, resulting in a firmly welded, uniformly interfaced interposer wafer with good interconnect impedance consistency.

[0037] In one example, epoxy transfer molding and laser scribing are performed on the interlocking wafer to obtain a double-sided interconnect packaged chip, including: A release film is attached to the top and back pad areas of the CLIP clips of the interconnect wafer to keep them exposed. The interconnect wafer is then placed in the mold cavity, and preheated epoxy molding compound is injected into the cavity to obtain a molded filled wafer. The molded filling wafer is heated to the set curing temperature and held for a set time to complete the epoxy group crosslinking reaction and then the release film is removed to obtain the packaged wafer; The packaged wafer is scanned along the dicing path, and the laser beam is focused on the middle layer of the packaged wafer to form a through dicing groove, thus obtaining a double-sided interconnect packaged chip.

[0038] In this example, the interconnect interface area of ​​the clip interconnect wafer is protected. Specifically, a 0.1mm thick PTFE release film is applied to the top and back metal pad areas of the clip. The PTFE release film has excellent temperature resistance and release properties, effectively preventing epoxy resin from seeping into the metal contact area during molding, maintaining the exposed state of the interconnect interface and compatibility with subsequent processes. After the release film is applied, the wafer is positioned within the cavity positioning groove of the lower mold, and the upper and lower molds are closed to form a sealed molding space. The geometry of the mold cavity is designed based on the total thickness of the wafer plus a 0.6mm encapsulation allowance to ensure that the epoxy resin, after injection, covers all device edges and surface structures except for the interconnect interface. Epoxy molding compound, preheated to 120°C for 15 minutes, is injected into the cavity using a constant pressure injection method. The injection pressure is controlled at 8MPa, and the injection rate is approximately 15cm. 3 The resin flows radially from the center of the wafer outwards using a central gate design, effectively reducing stress concentration and dead zones within the mold. The entire filling process is monitored by a closed-loop pressure and flow rate control system to ensure that the resin fully fills the wafer gaps and forms a good fit with the mold cavity wall, resulting in a molded filled wafer with complete encapsulation and a uniform interface. After filling, the mold system continues to heat to 175°C and maintains this curing temperature for 90 seconds, allowing the epoxy groups in the epoxy resin to fully cross-link with the curing agent, forming a three-dimensional thermosetting cross-linked network structure. This three-dimensional thermosetting cross-linked network structure maintains a balance between thermal conductivity and electrical insulation while improving the overall mechanical strength and environmental sealing of the device. After curing, the mold is slowly cooled to 80°C. After opening the mold, the previously attached release film is manually or automatically peeled off, restoring the top and back pad areas of the CLIP clips to their bare state, resulting in a packaged wafer with a complete packaging structure and a clean interconnect interface. In the chip separation stage, single-chip cutting is completed by laser dicing. An infrared nanosecond laser system with a wavelength of 1064nm is used, with the laser power controlled at 15W, the scanning speed at 200mm / s, and the pulse frequency at 40kHz. The laser is focused on the middle layer of the packaged wafer thickness and scanned multiple times along the dicing groove path preset in the previous photolithography. A continuous thermal decomposition through-cut groove is formed at the focal position, so that the wafer can be mechanically separated without damaging the metal interconnect structure, resulting in an independent chip with neat edges, complete packaging, and double-sided interconnect capability.

[0039] In one example, the packaged wafer is scanned along the dicing path, and a laser beam is focused on the middle layer of the packaged wafer to form a through-cut groove, resulting in a double-sided interconnect packaged chip, including: The coordinate sequence of the dicing groove centerline is obtained based on the thickness of the packaged wafer and the chip spacing, and the scanning path arrangement order is generated according to the spiral order from the outside to the inside. The required number of scans is calculated based on the ratio of the thickness of the packaged wafer to the cutting depth of a single scan, and a different focus depth position is assigned to each scan. According to the scanning path arrangement order and the focus depth position, the laser head is driven to move along each dicing groove path in sequence, and multiple scans are performed on each scanning path according to the focus depth position to accumulate and form a through dicing groove, thus obtaining the diced wafer; A blue film is attached to the back of the diced wafer, and then a radial expansion force is applied to break the chip along the dicing groove to obtain a double-sided interconnect packaged chip.

[0040] In this example, the centerline coordinate sequence of all dicing slots is obtained based on the total thickness of the wafer and the reserved spacing between chips. Combining the principles of density and cutting sequence optimization, a spiral path algorithm from the outside in is used to generate the corresponding laser scanning path arrangement, thereby avoiding edge cracking or off-cutting problems caused by localized heat buildup and focus drift. Based on the ratio of the wafer thickness to the actual cutting depth achievable in a single laser scan, the number of scans required to complete a full-thickness cut is calculated, and a different focus depth position is assigned to each scan. This ensures that the laser focus always acts on the physical center layer of the area to be cut, achieving effective control of layer-by-layer cumulative ablation and guaranteeing that each ablation results in sufficient energy deposition in the target layer rather than just surface carbonization. Based on the pre-generated scanning path arrangement and corresponding focus depth settings, the laser head is sequentially driven to reciprocate along each dicing groove path, continuously performing multiple focused layer scans on each path. Through high-frequency laser beam superposition and ablation, the epoxy encapsulation material is peeled away from the wafer body structure layer by layer, forming a deep through-cutting groove structure in the middle layer of the wafer. The kerf width is controlled within 30μm, with clean edges and no obvious heat-affected zone, resulting in a diced wafer structure. After laser dicing, a high-viscosity blue film is attached to the back of the wafer to support individual chips during subsequent physical separation, preventing slippage or displacement. Radial expansion force is applied by external fixtures, concentrating stress at the center of the dicing groove and guiding the wafer to break along the predetermined cutting path, completing the physical separation of the chips and obtaining a double-sided interconnect packaged chip.

[0041] Reference Figure 2 This embodiment provides a silicon carbide Schottky diode wafer-level CLIP packaging device, including: Magnetron sputtering unit 1 is used to perform magnetron sputtering on silicon carbide wafers to obtain back-side metallized wafers; Photolithography unit 2 is used to perform Schottky anode region photolithography on the back metallized wafer and reserve CLIP connection area during electrode evaporation to obtain a double-sided electrode wafer. Electroplating unit 3 is used to perform mask windowing and pulse current adjustment on the CLIP connection area of ​​the double-sided electrode wafer to obtain an electroplated boss wafer. The ablation windowing unit 4 is used to ablate windows on the top and back pad areas of the boss after the polyimide passivation layer is spin-coated and cured on the electroplated boss wafer, to obtain a selected windowed wafer. The heating reflow soldering unit 5 is used to position the copper-based CLIP clips above the selected windowed wafer boss, adjust the clamping force of each area and perform heating reflow soldering to obtain clip interconnect wafers. Laser scribing unit 6 is used to perform epoxy resin transfer molding and laser scribing on the interlocking wafer to obtain a double-sided interconnect packaged chip.

[0042] In this embodiment, the specific implementation of each unit in the above device embodiment is described in the above method embodiment, and will not be repeated here.

[0043] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, apparatus, article, or method that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, apparatus, article, or method. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, apparatus, article, or method that includes that element.

[0044] The above description is only a preferred embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent structural or procedural transformations made based on the content of the present invention specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of the present invention.

Claims

1. A wafer-level CLIP packaging method for silicon carbide Schottky diodes, characterized in that, include: A back-side metallized wafer is obtained by magnetron sputtering of a silicon carbide wafer. Schottky anode region photolithography is performed on the back metallized wafer, and CLIP connection areas are reserved during electrode evaporation to obtain a double-sided electrode wafer; A mask window is opened and a pulse current is adjusted in the CLIP connection area of ​​the double-sided electrode wafer to obtain an electroplated boss wafer. After the low-temperature curable polyimide passivation layer is spin-coated and cured on the electroplated boss wafer, windows are ablated in the top and back pad areas of the boss to obtain a selectively windowed wafer. The copper-based CLIP clips are positioned above the selected windowed wafer bosses, the clamping force of each area is adjusted and reflow soldering is performed to obtain the clip interconnect wafers. The interlocking wafer is subjected to epoxy resin transfer molding and laser scribing to obtain a double-sided interconnect packaged chip.

2. The silicon carbide Schottky diode wafer-level CLIP packaging method according to claim 1, characterized in that, The process of magnetron sputtering a silicon carbide wafer to obtain a back-side metallized wafer includes: The back side of the silicon carbide wafer is ground and polished to obtain a polished wafer; Electron beam evaporation of a titanium-nickel-silver three-layer cathode stack is performed on the back side of the polished wafer, while a stress sensor collects the thin film stress detection value in real time. When the detected value of the thin film stress exceeds the stress threshold, the substrate temperature adjustment amount is calculated and the temperature of the heating stage is adjusted to the set range for heat preservation, thereby obtaining the back metallized wafer.

3. The silicon carbide Schottky diode wafer-level CLIP packaging method according to claim 1, characterized in that, The process of performing Schottky anode region photolithography on the back-side metallized wafer and reserving CLIP connection areas during electrode evaporation to obtain a double-sided electrode wafer includes: After growing an oxide mask on the front side of the back metallized wafer, a Schottky anode active region pattern is formed by photolithography and the oxide layer is etched to obtain a patterned wafer. A four-layer aluminum-titanium-nickel-gold anode stacked electrode structure is deposited on the front side of the patterned wafer by electron beam evaporation to obtain a front electrode wafer. A CLIP connection area of ​​a predetermined width is reserved at the edge of the front electrode wafer to obtain a double-sided electrode wafer.

4. The silicon carbide Schottky diode wafer-level CLIP packaging method according to claim 3, characterized in that, The process of reserving a CLIP connection area of ​​a predetermined width at the edge of the front electrode wafer to obtain a double-sided electrode wafer includes: Calculate the reserved width and boundary position parameters of the CLIP connection area based on the chip size and the area of ​​the Schottky anode active region; According to the boundary position parameters, an electroplating mask is set at the edge of the front electrode wafer and a rectangular array window is opened in the CLIP connection area to obtain a mask pattern wafer. Based on the window size of the mask pattern wafer, an electroplating solution is prepared and the initial process parameters of the plating solution are set to obtain a double-sided electrode wafer.

5. The silicon carbide Schottky diode wafer-level CLIP packaging method according to claim 1, characterized in that, The process of performing mask windowing and pulse current adjustment on the CLIP connection region of the double-sided electrode wafer to obtain an electroplated boss wafer includes: A boss growth rate model is established for the CLIP connection region of the double-sided electrode wafer, and a target trajectory height value is set. Real-time boss height values ​​are collected from multiple monitoring points using a laser displacement sensor; The real-time boss height value at each monitoring point is compared with the target trajectory height value at the corresponding time point by point, and the integral and differential terms of the current height deviation are calculated. The pulse current adjustment amount and the plating solution temperature compensation amount are calculated based on the integral and differential terms of the current height deviation. The pulse current and the plating solution temperature are then synchronously adjusted based on the pulse current adjustment amount and the plating solution temperature compensation amount to obtain the electroplated boss wafer.

6. The silicon carbide Schottky diode wafer-level CLIP packaging method according to claim 1, characterized in that, After the low-temperature curable polyimide passivation layer is spin-coated and cured on the electroplated boss wafer, windows are ablated in the top and back pad areas of the boss to obtain a selected windowed wafer, including: A low-temperature curable polyimide precursor solution is spin-coated onto the surface of the electroplated boss wafer, and imidization is completed at a set temperature to obtain a cured passivation layer wafer. The ultraviolet laser wavelength pulse energy density and repetition frequency parameters are set for the top of the boss and the back pad area of ​​the solidified passivation layer wafer. Laser ablation is performed using a bidirectional grating scanning path and the accuracy of the windowed edge contour is monitored in real time to obtain a laser-windowed wafer. The bottom metal surface of the laser-windowed wafer is cleaned with oxygen plasma to remove polyimide residue, resulting in a selectively windowed wafer.

7. The silicon carbide Schottky diode wafer-level CLIP packaging method according to claim 1, characterized in that, The process of positioning the copper-based CLIP clips above the selected windowed wafer boss, adjusting the clamping force in each area, and performing reflow soldering to obtain the clip interconnect wafer includes: The pre-formed copper-based CLIP clip is positioned above the selected windowed wafer boss, and the contact pressure values ​​of multiple monitoring points are collected in real time through a pressure sensor array, and the pressure uniformity index of each monitoring point is calculated. When the pressure uniformity index exceeds the set pressure threshold, the pressure adjustment scheme corresponding to the minimum value of the sum of squares of the deviations between the pressure at each monitoring point and the target pressure is solved, and the servo system is controlled to adjust the clamping force in each area to obtain the positioning wafer after pressure equalization. The positioning wafer after pressure equalization is subjected to a preheating stage, a linear heating stage, and a high-temperature reflow stage in sequence, and the solder is melted to form an intermetallic compound interface layer to obtain a clip interconnect wafer.

8. The silicon carbide Schottky diode wafer-level CLIP packaging method according to claim 1, characterized in that, The process of performing epoxy resin transfer molding and laser scribing on the interlocking wafer to obtain a double-sided interconnect packaged chip includes: A release film is attached to the top and back pad areas of the CLIP clips of the interconnect wafer to keep them exposed. The interconnect wafer is then placed in a mold cavity, and preheated epoxy molding compound is injected into the cavity to obtain a molded filled wafer. The molded filled wafer is heated to a set curing temperature and held for a set time to complete the epoxy group crosslinking reaction and then the release film is removed to obtain the packaged wafer. The packaging wafer is scanned along the dicing path, and the laser beam is focused on the middle layer of the packaging wafer to form a through dicing groove, thereby obtaining a double-sided interconnect packaged chip.

9. The silicon carbide Schottky diode wafer-level CLIP packaging method according to claim 8, characterized in that, The process of scanning the packaged wafer along the dicing path, focusing a laser beam at the middle layer of the packaged wafer to form a through-cut groove, and obtaining a double-sided interconnect packaged chip includes: The coordinate sequence of the dicing centerline is obtained based on the thickness of the packaged wafer and the chip spacing, and the scanning path arrangement order is generated according to the spiral order from the outside to the inside. The required number of scans is calculated based on the ratio of the thickness of the packaged wafer to the single scan cutting depth, and a different focus depth position is assigned for each scan. According to the scanning path arrangement order and the focusing depth position, the laser head is driven to move along each dicing groove path in sequence, and multiple scans are performed on each scanning path according to the focusing depth position to accumulate and form a through dicing groove, thereby obtaining a diced wafer; A blue film is attached to the back of the diced wafer, and then a radial expansion force is applied to break the chip along the dicing groove to obtain a double-sided interconnect packaged chip.

10. A silicon carbide Schottky diode wafer-level CLIP packaging device, characterized in that, The steps for implementing the silicon carbide Schottky diode wafer-level CLIP packaging method according to any one of claims 1 to 9 include: The magnetron sputtering unit is used to perform magnetron sputtering on silicon carbide wafers to obtain back-side metallized wafers. The photolithography unit is used to perform Schottky anode region photolithography on the back metallized wafer and reserve CLIP connection areas during electrode evaporation to obtain a double-sided electrode wafer. An electroplating unit is used to perform mask windowing and pulse current adjustment on the CLIP connection area of ​​the double-sided electrode wafer to obtain an electroplated boss wafer. The ablation windowing unit is used to ablate windows in the top and back pad areas of the boss after the low-temperature curing polyimide passivation layer is spin-coated and cured on the electroplated boss wafer, to obtain a selectively windowed wafer. The heating reflow soldering unit is used to position the copper-based CLIP clips above the selected windowed wafer boss, adjust the clamping force of each area and perform heating reflow soldering to obtain clip interconnect wafers. The laser scribing unit is used to perform epoxy resin transfer molding and laser scribing on the interlocking wafer to obtain a double-sided interconnect packaged chip.

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