Gate oxide process and method of forming semiconductor structure

Abstract

A gate oxide process, first dry oxidation treatment, wet oxidation treatment and second dry oxidation treatment are carried out on the substrate in sequence, so that the silicon-chlorine bond is formed between the third oxide layer and the substrate, compared with only reducing the light doping leakage ion implantation dose and increasing the light doping leakage energy, the hydroxyl introduced by the wet oxidation treatment not only improves the chlorine activity, but also as a transport carrier makes the chlorine efficiently enriched in the new oxide layer, the high concentration of chlorine fills the oxygen vacancies, reduces the bulk trap density, the silicon-chlorine bond formed by the second dry oxidation treatment has a deeper trap energy level, which can reduce the interface state density and improve the device's ability to resist hot carrier damage. Moreover, the hydrogen introduced by the wet oxidation treatment is removed in the second dry oxidation treatment, thereby avoiding the situation that the silicon-hydrogen bond is broken, the hot carrier injection is intensified, and then the degradation chain reaction is triggered, thereby achieving the effect of improving the hot carrier injection effect.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor processes, and more particularly to a gate oxide process and a method for forming a semiconductor structure. Background Technology

[0002] With the development of Very Large Scale Integration (VLSI) technology and the continuous advancement of semiconductor manufacturing technology, driven by Moore's Law, the number of transistors on a chip quadruples every three years, the chip area increases by 1.5 times, and the critical dimensions of the device shrink by two-thirds. While maintaining a constant power supply voltage, the reduction in critical dimensions and the thinning of the gate oxide layer lead to a continuous increase in the electric field at the device drain, both laterally and longitudinally. This makes the hot carrier degradation effect a prominent issue for device reliability.

[0003] Hot carrier injection (HCI) is a reliability problem in metal-oxide-semiconductor field-effect transistors (MOSFETs) where high-energy carriers (hot carriers) accelerated by a strong electric field are injected into the gate oxide layer. This injection causes interface states and oxide charge traps, leading to irreversible degradation of device electrical parameters (such as threshold voltage and transconductance). It is one of the major challenges facing the continuous miniaturization of integrated circuits, directly impacting chip lifespan and performance stability.

[0004] The hot carrier injection effect in N-type metal-oxide-semiconductor (NMOS) transistors is currently optimized using light-doped drain (LDD) technology. However, simply changing the dose and energy of light-doped drain ion implantation to improve the hot carrier injection effect has limitations. Summary of the Invention

[0005] The problem solved by the embodiments of the present invention is to provide a gate oxide process and a method for forming a semiconductor structure, which can form a silicon-chlorine bond and improve the device's resistance to thermal carrier damage.

[0006] To address the aforementioned problems, embodiments of the present invention provide a gate oxide process, comprising: providing a substrate; performing a first dry oxidation treatment on the substrate in a chlorine-containing atmosphere to form a first oxide layer on the substrate; after forming the first oxide layer, performing a wet oxidation treatment on the substrate in the chlorine-containing atmosphere to form a second oxide layer between the first oxide layer and the substrate; after forming the second oxide layer, performing a second dry oxidation treatment on the substrate in the chlorine-containing atmosphere to form a third oxide layer between the second oxide layer and the substrate, wherein silicon-chlorine bonds are formed at the interface between the third oxide layer and the substrate.

[0007] Optionally, in the first dry oxidation step of the substrate, the chlorine-containing atmosphere is provided by introducing trans-1,2-dichloroethylene.

[0008] Optionally, the step of forming a first oxide layer on the substrate includes: the process temperature range of the first oxide layer is 600°C to 800°C; in the step of performing a wet oxidation process on the substrate, the process temperature range of the second oxide layer is 600°C to 800°C; in the step of performing a second dry oxidation process on the substrate, the process temperature of the second oxide layer is 800°C to 900°C.

[0009] Optionally, the process temperature of the first oxide layer is the same as that of the second oxide layer.

[0010] Optionally, in the step of wet oxidation of the substrate, water vapor provides hydroxyl groups as a transport carrier for chlorine, prompting nitrogen atoms to fill oxygen vacancies in the second oxide layer; the second dry oxidation process is also used to expel hydrogen atoms and hydroxyl groups introduced into the substrate or oxide layer during the wet oxidation process.

[0011] Optionally, the thickness of the first oxide layer ranges from 10 Å to 15 Å; the thickness of the second oxide layer ranges from 35 Å to 55 Å; and the thickness of the third oxide layer ranges from 10 Å to 15 Å.

[0012] Optionally, the substrate may be made of silicon.

[0013] This invention also provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including a substrate, a dummy gate structure formed on the substrate, source and drain doped layers formed in substrates on both sides of the dummy gate structure, and an interlayer dielectric layer covering the sidewalls of the dummy gate structure; removing the dummy gate structure to form a gate opening exposing the substrate; performing a gate oxide process as described in any one of claims 1 to 7 on the substrate within the gate opening; and forming a metal gate in the gate opening after performing the gate oxide process.

[0014] Optionally, in the step of providing the substrate, lightly doped drain structures are formed in the substrates on both sides of the pseudo-gate structure.

[0015] Optionally, the substrate includes a fin located on the substrate, and the dummy gate structure spans the fin and covers a portion of the top wall and a portion of the sidewalls of the fin. In the step of removing the dummy gate structure, the gate opening exposes the top and a portion of the sidewalls of the fin.

[0016] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages: The gate oxide process provided in this embodiment of the invention includes: providing a substrate; performing a first dry oxidation treatment on the substrate in a chlorine-containing atmosphere to form a first oxide layer on the substrate; after forming the first oxide layer, performing a wet oxidation treatment on the substrate in the chlorine-containing atmosphere to form a second oxide layer between the first oxide layer and the substrate; after forming the second oxide layer, performing a second dry oxidation treatment on the substrate in the chlorine-containing atmosphere to form a third oxide layer between the second oxide layer and the substrate; wherein silicon-chlorine bonds are formed at the interface between the third oxide layer and the substrate. This invention, through sequential dry oxidation, wet oxidation, and a second dry oxidation process on a substrate, forms silicon-chlorine bonds between the third oxide layer and the substrate. Compared to simply reducing the light-doped drain ion implantation dose and increasing the light-doped drain energy, the hydroxyl groups introduced by the wet oxidation process not only enhance chlorine activity but also act as transport carriers, allowing chlorine to be efficiently enriched in the newly formed oxide layer. The high concentration of chlorine fills oxygen vacancies, reducing the bulk trap density. The silicon-chlorine bonds formed by the second dry oxidation process have deeper trap energy levels, reducing the interface state density and improving the device's resistance to hot carrier damage. Furthermore, the hydrogen introduced by the wet oxidation process is removed in the second dry oxidation process, thus avoiding the exacerbation of hot carrier injection and the subsequent degradation chain reaction caused by silicon-hydrogen bond breakage, thereby improving the hot carrier injection effect.

[0017] This invention also provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including a substrate, a dummy gate structure formed on the substrate, source / drain doped layers formed in the substrates on both sides of the dummy gate structure, and an interlayer dielectric layer covering the sidewalls of the dummy gate structure; removing the dummy gate structure to form a gate opening exposing the substrate; performing a gate oxide process as described in any one of the embodiments on the substrate within the gate opening; and forming a metal gate in the gate opening after performing the gate oxide process. This invention, by performing a gate oxide process as described in any one of the embodiments on the substrate within the gate opening after removing the dummy gate structure and before forming the metal gate, generates a high-quality gate oxide layer on the substrate surface. This generates chemical bonds with deeper trap energy levels at the interface between the gate oxide layer and the substrate, thereby reducing the irreversible degradation of device performance caused by high-energy carrier injection into the gate oxide layer, thus improving the hot carrier injection effect. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the structure of the substrate after undergoing a first dry oxidation treatment in a chlorine-containing atmosphere, as described in an embodiment of the present invention. Figure 2 This is a schematic diagram of the structure of the substrate after wet oxidation treatment in a chlorine-containing atmosphere in an embodiment of the present invention; Figure 3 This is a schematic diagram of the structure of the substrate after a second dry oxidation treatment in a chlorine-containing atmosphere, as described in an embodiment of the present invention.

[0019] Figures 4 to 7 This is a schematic diagram of the semiconductor structure after key steps in an embodiment of the present invention. Detailed Implementation

[0020] As the background technology indicates, the hot carrier injection effect refers to the injection of high-energy carriers (hot carriers) accelerated by a strong electric field into the gate oxide layer of a metal-oxide-semiconductor field-effect transistor, causing interface states and oxide layer charge traps, resulting in irreversible degradation of device electrical parameters (such as threshold voltage and transconductance), a reliability problem. It is one of the major challenges facing the continuous miniaturization of integrated circuits, directly affecting chip lifespan and performance stability.

[0021] The main problem with existing technologies is that the industry commonly uses lightly doped drain processes to optimize the hot carrier injection effect in N-type metal-oxide-semiconductor transistors. However, simply changing the dose and energy of lightly doped drain ions to improve the hot carrier injection effect has limitations. Specifically, reducing the dose of lightly doped drain ions and increasing the injection energy lowers the peak electric field near the gate to drain. The lightly doped drain structure acts as a transition region, causing a gradual change in the electric field and weakening the peak electric field intensity, thus improving the hot carrier injection effect. However, this enhances the short channel effect (SCE), leading to a degradation in the device's DC characteristics.

[0022] To solve the aforementioned technical problem, the gate oxide process provided in this embodiment of the invention includes: providing a substrate; performing a first dry oxidation treatment on the substrate in a chlorine-containing atmosphere to form a first oxide layer on the substrate; after forming the first oxide layer, performing a wet oxidation treatment on the substrate in the chlorine-containing atmosphere to form a second oxide layer between the first oxide layer and the substrate; after forming the second oxide layer, performing a second dry oxidation treatment on the substrate in the chlorine-containing atmosphere to form a third oxide layer between the second oxide layer and the substrate; wherein silicon-chlorine bonds are formed at the interface between the third oxide layer and the substrate. This invention, through sequential dry oxidation, wet oxidation, and a second dry oxidation process on a substrate, forms silicon-chlorine bonds between the third oxide layer and the substrate. Compared to simply reducing the light-doped drain ion implantation dose and increasing the light-doped drain energy, the hydroxyl groups introduced by the wet oxidation process not only enhance chlorine activity but also act as transport carriers, allowing chlorine to be efficiently enriched in the newly formed oxide layer. The high concentration of chlorine fills oxygen vacancies, reducing the bulk trap density. The silicon-chlorine bonds formed by the second dry oxidation process have deeper trap energy levels, reducing the interface state density and improving the device's resistance to hot carrier damage. Furthermore, the hydrogen introduced by the wet oxidation process is removed in the second dry oxidation process, thus avoiding the situation where silicon-hydrogen bond breakage exacerbates hot carrier injection and triggers a degradation chain reaction, thereby improving the hot carrier injection effect.

[0023] The technical solutions in the disclosed embodiments will be clearly and completely described below with reference to the accompanying drawings. Obviously, the embodiments described are only some embodiments of the invention, not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without creative effort are within the scope of protection of the invention.

[0024] This invention provides a gate oxide process. Figure 1 This is a schematic diagram of the structure of the substrate after undergoing a first dry oxidation treatment in a chlorine-containing atmosphere, as described in an embodiment of the present invention. Figure 2This is a schematic diagram of the structure of the substrate after wet oxidation treatment in a chlorine-containing atmosphere, as described in an embodiment of the present invention. Figure 3 This is a schematic diagram of the structure of the substrate after a second dry oxidation treatment in a chlorine-containing atmosphere, as described in an embodiment of the present invention.

[0025] In some embodiments, the gate oxide process includes providing a substrate. In the gate oxide process, the substrate directly participates in the reaction to form an oxide layer, the oxide layer being grown on the surface of the substrate.

[0026] In some embodiments, the substrate is made of silicon. The substrate provides silicon atoms, and a silicon dioxide (SiO2) oxide layer is formed on the surface of the substrate during an oxidation process.

[0027] refer to Figure 1 , Figure 1 This is a schematic diagram of the structure of the substrate 10 after undergoing a first dry oxidation treatment in a chlorine-containing atmosphere, as described in an embodiment of the present invention. The chlorine-containing atmosphere provides chlorine during the formation of the oxide layer.

[0028] As an example, the substrate 10 is made of silicon, and the dry oxidation process refers to the process of using pure oxygen to chemically react with the silicon surface at high temperature to generate high-quality silicon dioxide. Specifically, oxygen is first introduced into a high-temperature furnace tube and transported to the silicon wafer surface through gas flow. After reaching the existing silicon dioxide surface, oxygen molecules need to penetrate the already formed thermal oxide layer and diffuse into the internal silicon-silicon dioxide interface. When oxygen molecules successfully diffuse to the silicon-silicon dioxide interface, they react with silicon atoms to generate new silicon dioxide.

[0029] It should be noted that as the oxide layer thickness increases, the thermal oxide layer thickness that oxygen molecules need to traverse to reach the silicon-silica interface also increases, making oxygen molecule diffusion increasingly difficult. The relationship between oxide layer thickness and oxidation time gradually changes from a linear relationship (surface reaction control) to a parabolic relationship (diffusion control). Therefore, dry oxidation processes are characterized by slow oxide layer growth rates, making it difficult to generate thick oxide layers. However, the slow oxide layer growth rate allows for precise control of oxide layer thickness and enables the growth of dense, uniform, and high-quality oxide layers.

[0030] Furthermore, oxygen molecules diffuse very slowly within the dense silica network. As the oxide layer thickens, oxygen struggles to reach the silicon-silica interface in a timely manner. Oxygen molecules must first dissociate into oxygen atoms before reacting with silicon; this process involves high activation energy and a slow reaction rate. Therefore, in areas with insufficient oxygen supply, silicon-silicon bonds are covered by a new oxide layer before they can be completely oxidized. Simultaneously, dry oxidation generates significant compressive stress at the silicon-silica interface, breaking some silicon-oxygen and silicon-silicon bonds and directly creating silicon dangling bonds. These silicon-silicon bonds and silicon dangling bonds constitute oxygen vacancies.

[0031] In some embodiments, during the first dry oxidation step of the substrate, the chlorine-containing atmosphere is provided by introducing trans-1,2-dichloroethylene (DCE). The lattice on the substrate surface is interrupted, generating numerous dangling bonds. These dangling bonds can trap charge carriers or cause leakage current during device operation, thereby exacerbating the hot carrier injection effect.

[0032] In the first dry oxidation step of the substrate, trans-1,2-dichloroethylene is introduced into an oxidizing atmosphere. The trans-1,2-dichloroethylene decomposes at high temperature, releasing chlorine. The high concentration of chlorine participates in the interfacial reaction, and the chlorine atoms can combine with unpaired silicon dangling bonds at the interface to form more stable and less easily broken silicon-chlorine bonds. Furthermore, the formation of these silicon-chlorine bonds can alleviate the mechanical stress caused by the lattice mismatch between silicon and silicon dioxide, providing a smooth starting interface for the second oxide layer generated by the wet oxidation process.

[0033] In some embodiments, the processing temperature range of the first oxide layer 11 is 600°C to 800°C. Within this temperature range, oxygen molecules gain significant kinetic energy, enabling them to move violently and diffuse through the already formed oxide layer to reach the silicon-silicon dioxide interface and react with silicon. This temperature range also provides the necessary activation energy for the chemical bonding of silicon and oxygen atoms, allowing the reaction to proceed continuously.

[0034] Furthermore, within the stated temperature range, silicon dioxide molecules possess sufficient energy to move to the lowest energy positions, forming an amorphous, random network structure. This random network structure is denser, more stable, and exhibits stronger breakdown strength. Simultaneously, within this temperature range, atoms have time to rearrange, effectively releasing the mechanical stress at the silicon-silicon dioxide interface and reducing dangling bonds caused by lattice mismatch.

[0035] It should be noted that the temperature of the first dry oxidation process should not be too low or too high. If the temperature is too low, the actual oxidation time will be too long, severely impacting production capacity and rendering the process unsuitable for mass production. Conversely, if the temperature is too high, it will exacerbate the diffusion of dopant impurities in the semiconductor structure, altering the original doping distribution of the device and leading to degradation of electrical performance. Furthermore, excessively high temperatures will cause significant wear and tear on equipment such as furnace tubes, and increase the difficulty of process control.

[0036] In some embodiments, the thickness of the first oxide layer 11 ranges from 10 angstroms to 15 angstroms. Dry oxidation processes are characterized by slow oxide layer growth rates, making it difficult to generate thick oxide layers. However, the slow oxide layer growth rate allows for precise control of the oxide layer thickness and enables the growth of dense, uniform, and high-quality oxide layers.

[0037] It should be noted that the thickness of the first oxide layer 11 should not be too thin or too thick. If the first oxide layer 11 is too thin, due to the slow intrinsic growth and dense film, the dangling bond defects caused by interfacial stress are even more difficult to completely eliminate through subsequent annealing, which has a significant impact on the channel carrier mobility. If the first oxide layer 11 is too thick, because dry oxidation has the problem of slow oxide layer growth rate, an excessively thick oxide layer will lead to several days of high-temperature occupation, completely limiting the equipment's production capacity.

[0038] refer to Figure 2 , Figure 2 This is a schematic diagram of the structure after the substrate undergoes a wet oxidation process in a chlorine-containing atmosphere to form the first oxide layer. The wet oxidation process forms a second oxide layer 12 between the first oxide layer 11 and the substrate 10. The chlorine-containing atmosphere provides chlorine during the oxide layer formation process.

[0039] As an example, the substrate 10 is made of silicon, and the wet oxidation process refers to the process of using water vapor mixed with oxygen to chemically react with the silicon surface at high temperature, thereby generating a silicon dioxide oxide layer. Specifically, water vapor is first introduced into a high-temperature furnace tube and transported to the silicon wafer surface through gas flow. After water molecules reach the existing silicon dioxide surface, they need to penetrate the already formed thermal oxide layer and diffuse into the internal silicon-silicon dioxide interface. When water molecules successfully diffuse to the silicon-silicon dioxide interface, they react with silicon atoms to generate new silicon dioxide.

[0040] It should be noted that water molecules diffuse extremely quickly, and interfacial reactions are also rapid, thus wet oxidation processes typically do not have an oxygen shortage problem. When water molecules diffuse to the silicon-silica interface and react, they release hydrogen gas and hydrogen atoms. These hydrogen atoms or hydrogen gas have reducing properties and can attack the already formed silicon-oxygen bonds to generate silanol groups and silicon-hydrogen bonds. When subsequent thermal stress or electric field breaks the silicon-hydrogen bonds, active silicon dangling bonds are left behind, which then form oxygen vacancies.

[0041] The wet oxidation process introduces hydrogen. Specifically, the water vapor undergoes thermal dissociation to generate hydrogen atoms and hydroxyl groups. The water vapor reacts with the silicon substrate to generate silicon dioxide and hydrogen. The hydroxyl groups not only enhance the activity of chlorine but also act as a transport carrier to efficiently enrich chlorine in the newly formed oxide layer. The high concentration of chlorine fills oxygen vacancies, thereby reducing the bulk trap density.

[0042] Furthermore, at the oxide layer or silicon-silica interface, hydrogen ions and hydroxyl groups can form silicon-hydrogen bonds and silanol groups with silicon dangling bonds. These hydrogen phase bonds are prone to breakage during subsequent processes or device operation, generating dangling bonds and interface states, thereby exacerbating the hot carrier injection effect. Therefore, hydrogen introduced by wet oxidation requires a subsequent dry oxidation process to remove it.

[0043] It should be noted that water molecules are smaller than oxygen molecules and have a higher diffusion coefficient in silica, allowing them to penetrate the existing oxide layer more quickly to reach the silicon-silica interface and react with silicon. Therefore, wet oxidation is often used in applications requiring rapid growth of thicker oxide layers.

[0044] In addition, introducing only water vapor to participate in the reaction has problems such as excessively fast oxidation rate, severe hydrogen-related defects, and excessively high hydrogen concentration in the furnace tube, which may cause an explosion. Introducing oxygen can appropriately reduce the oxidation rate, make thickness control more precise, and make the oxide layer more compact by participating in the reaction, reducing hydrogen-related defects introduced by water vapor. At the same time, it can reduce the hydrogen concentration in the furnace tube to prevent explosion.

[0045] In some embodiments, during the wet oxidation step of the substrate 10, the chlorine-containing atmosphere is provided by introducing trans-1,2-dichloroethylene. High concentrations of chlorine participate in interfacial reactions, and the chlorine atoms can combine with unpaired silicon dangling bonds at the interface to form more stable and less easily broken silicon-chlorine bonds.

[0046] In some embodiments, the processing temperature range for the second oxide layer 12 is 600°C to 800°C. Within this temperature range, water molecules gain significant kinetic energy, enabling them to move violently and diffuse through the already formed oxide layer to reach the silicon-silicon dioxide interface and react with silicon. This temperature range also provides the necessary activation energy for the hydrogen phase, allowing the reaction to proceed continuously.

[0047] In some embodiments, the process temperature of the first oxide layer 11 is the same as the process temperature of the second oxide layer 12. Specifically, the oxidation rate is extremely sensitive to temperature. If the first dry oxidation process and the wet oxidation process are performed at different process temperatures, the furnace tube needs time to heat up or cool down. Within this temperature range, the first dry oxidation process can form a high-quality first oxide layer 11, while the wet oxidation process has an appropriate growth rate, thereby maximizing production efficiency.

[0048] It should be noted that the temperature of the wet oxidation process should not be too high or too low. If the temperature is too high, the oxidation rate is too fast, resulting in a loose structure in the second oxide layer 12, with a density far inferior to that of the second oxide layer 12 formed within the specified temperature range. If the temperature is too low, the reaction between water vapor and silicon is incomplete, resulting in a second oxide layer 12 with high pinhole density, numerous defects, and poor electrical insulation properties. Furthermore, the structure of the second oxide layer 12 grown at low temperatures is very poor, offering weak masking and passivation protection for subsequent processes.

[0049] In some embodiments, the water vapor provides hydroxyl groups as transport carriers for chlorine, prompting chlorine atoms to fill oxygen vacancies in the second oxide layer 12. The hydroxyl groups have a strong electron-withdrawing ability; by attacking silicon-silicon bonds, they generate silicon dangling bonds and silanol groups. These silicon dangling bonds can form silicon-chlorine bonds with chlorine atoms, or they can form silanol groups and silicon-hydrogen bonds with hydroxyl and hydrogen atoms, thereby filling oxygen vacancies in the second oxide layer 12.

[0050] In some embodiments, the thickness of the second oxide layer 12 is 40 angstroms to 60 angstroms.

[0051] It should be noted that the thickness of the second oxide layer 12 should not be too thin or too thick. If the second oxide layer 12 is too thin, the initial growth rate of wet oxidation is fast and uneven, which can easily cause film discontinuity and a large number of pinholes, leading to a direct short circuit in the second oxide layer 12. If the second oxide layer 12 is too thick, as the thickness increases, the inherent loose structure of the second oxide layer 12 generated by wet oxidation will be amplified, resulting in high bulk defect density and large interface roughness.

[0052] refer to Figure 3 After the second oxide layer 12 is formed, the substrate 10 is subjected to a second dry oxidation treatment in the chlorine-containing atmosphere to form a third oxide layer 13 between the second oxide layer 12 and the substrate 10. Silicon-chlorine bonds are formed at the interface between the third oxide layer 13 and the substrate 10.

[0053] In some embodiments, during the second dry oxidation step of the substrate 10, the chlorine-containing atmosphere is provided by introducing trans-1,2-dichloroethylene.

[0054] In some embodiments, the second dry oxidation process is further used to expel hydrogen atoms or hydroxyl groups introduced into the substrate or oxide layer during the wet oxidation process. The silicon-hydrogen bonds formed by the hydrogen atoms and silicon dangling bonds are susceptible to the hot carrier injection effect. Taking an N-type metal-oxide semiconductor as an example, high-energy electrons in the channel collide with the lattice, generating electron-hole pairs. The holes then attack the interface. At the silicon-silicon dioxide interface, a high-energy hole strikes a silicon-hydrogen bond, generating a silicon dangling bond and releasing a neutral hydrogen atom. This neutral hydrogen atom then strikes another silicon-hydrogen bond, generating a silicon dangling bond and releasing hydrogen gas. This hydrogen gas can be dissociated by other high-energy carriers, generating neutral hydrogen atoms again, which continue to attack the next silicon-hydrogen bond. Thus, the breaking of a single silicon-hydrogen bond can trigger a chain reaction. As the silicon-hydrogen bonds at the interface are largely consumed, the resulting interface state density becomes increasingly high, leading to a decrease in transconductance, a shift in threshold voltage, and a decrease in drain current, resulting in a severe degradation of the device's DC characteristics.

[0055] It should be noted that the second dry oxidation process removes hydrogen introduced by the wet oxidation process by removing silicon-hydrogen bonds. At high temperature, oxygen molecules or oxygen atoms attack the silicon-hydrogen bonds, and oxygen inserts into the silicon-hydrogen bonds. The silicon-hydrogen bonds are converted into silanol groups, and adjacent silanol groups undergo dehydration condensation reactions to convert the silanol groups into a stable silicon-oxygen network. This completes the removal of hydrogen introduced by the wet oxidation process, avoids the breaking of silicon-hydrogen bonds and the initiation of chain reactions, and thus achieves the effect of improving the hot carrier effect.

[0056] In the step of performing the second dry oxidation treatment on the substrate, the process temperature of the third oxide layer 13 is 800℃-900℃.

[0057] Specifically, the process temperature of the third oxide layer 13 is higher than that of the first oxide layer 11, ensuring that a sufficiently thick third oxide layer 13 is grown at the silicon-silicon dioxide interface, thereby improving the overall density and electrical reliability of the oxide layer.

[0058] The silicon-chlorine bonds formed within the specified temperature range have deeper trap energy levels, which can reduce the interface state density and improve the device's resistance to hot carrier damage. Specifically, the processing temperature of the third oxide layer 13 provides the energy to overcome the activation energy barrier for the dehydration condensation reaction that expels hydrogen, exponentially accelerating the rate of the dehydration condensation reaction. After the hydrogen is expelled, the silicon dangling bonds bond with chlorine atoms to form silicon-chlorine bonds that are not easily broken, thereby reducing the interface state density and improving the device's resistance to hot carrier damage.

[0059] It should be noted that the temperature of the second dry oxidation process should not be too low or too high. If the temperature is too low, the actual oxidation time will be too long, severely impacting production capacity and rendering it unsuitable for mass production. Conversely, if the temperature is too high, it will exacerbate the diffusion of dopant impurities in the semiconductor structure, altering the original doping distribution of the device and leading to degradation of electrical performance. Furthermore, excessively high temperatures will cause significant wear and tear on equipment such as furnace tubes, and increase the difficulty of process control.

[0060] In some embodiments, the thickness of the third oxide layer 13 ranges from 10 angstroms to 15 angstroms. Dry oxidation processes are characterized by slow oxide layer growth rates, making it difficult to generate thick oxide layers. However, the slow oxide layer growth rate allows for precise control of the oxide layer thickness and enables the growth of dense, uniform, and high-quality oxide layers.

[0061] It should be noted that the thickness of the third oxide layer 13 should not be too thin or too thick. If the thickness of the third oxide layer 13 is too thin, due to the slow intrinsic growth and dense film, the dangling bond defects caused by interfacial stress are even more difficult to completely eliminate through subsequent annealing, which has a significant impact on the channel carrier mobility. If the thickness of the third oxide layer 13 is too thick, because dry oxidation has the problem of slow oxide layer growth rate, an excessively thick oxide layer will lead to several days of high-temperature occupation, completely limiting the equipment's production capacity.

[0062] This invention also provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including a substrate, a dummy gate structure formed on the substrate, source / drain doped layers formed in substrates on both sides of the dummy gate structure, and an interlayer dielectric layer covering the sidewalls of the dummy gate structure.

[0063] Figures 4 to 7 This is a schematic diagram of the semiconductor structure after key steps in an embodiment of the present invention.

[0064] refer to Figure 4 , Figure 4 This is a schematic diagram of the structure after the pseudo-gate structure 22 is formed on the substrate 10.

[0065] The substrate provides the technological basis for the subsequent formation of the metal gate.

[0066] The pseudo-gate structure 22 occupies physical space for the subsequent formation of the metal gate. The pseudo-gate structure 22 includes a pseudo-gate oxide layer 221 that conformally covers part of the top surface and part of the sidewalls of the fin 21, and the pseudo-gate structure 22 also includes a pseudo-gate layer 222 located on the pseudo-gate oxide layer 221.

[0067] In some embodiments, the pseudo-gate structure 22 is made of pseudo-polycrystalline silicon (Poly).

[0068] In some embodiments, the dummy gate oxide layer 221 is made of silicon oxide. In other embodiments, the dummy gate oxide layer may also be made of silicon oxynitride.

[0069] In some embodiments, the dummy gate layer 222 is made of polycrystalline silicon. In other embodiments, the dummy gate layer may also be made of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon carbonitride, or amorphous carbon.

[0070] It should be noted that a sidewall layer 23 is also formed on the sidewall of the pseudo-gate structure 22. The material of the sidewall layer 103 includes one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon carbonitride, and amorphous carbon.

[0071] The source and drain doped layers 24 form the source and drain of the transistor and ensure low resistance and self-alignment between the source and drain and the replacement metal gate.

[0072] The interlayer dielectric layer 25 covers the pseudo-gate structure, which is used for electrical isolation of adjacent devices and also for preparing for the subsequent formation of the gate opening.

[0073] The interlayer dielectric layer 25 is made of an insulating material. As an example, the material of the interlayer dielectric layer 25 includes silicon oxide, and the interlayer dielectric layer 25 is formed using flowable chemical vapor deposition (FCVD).

[0074] In some embodiments, during the step of providing the substrate, lightly doped drain structures are formed in the substrate on both sides of the dummy gate structure 22. The lightly doped drain structures introduce a low-concentration buffer region between the source and drain and the channel, which can effectively reduce the electric field strength near the drain, thereby suppressing the hot carrier injection effect.

[0075] The lightly doped drain structure is formed by a lightly doped drain (LDD) ion implantation process. By reducing the dose of lightly doped drain ions and increasing the lightly doped drain implantation energy, the peak electric field near the gate to drain of the device is reduced to improve the hot carrier injection effect.

[0076] In some embodiments, the substrate includes a substrate 10 and a fin 21 located on the substrate, wherein the pseudo-gate structure 22 spans the fin 21 and covers a portion of the top wall and a portion of the side wall of the fin 21.

[0077] The fin 21 serves as a conductive channel for the transistor. In some embodiments, an anisotropic plasma dry etching process is used to form the substrate 10 and the fin 21 located on the substrate 10.

[0078] The pseudo-gate structure 22 is closely attached to part of the top wall and part of the side wall of the fin 21, achieving three-dimensional encapsulation of the conductive channel. Furthermore, the physical structure of the pseudo-gate structure 22, which surrounds the transistor on three sides, can suppress leakage current.

[0079] refer to Figure 5 Remove the pseudo-gate structure 22 to form a gate opening 26 that exposes the substrate.

[0080] The gate opening 26 provides process space for the subsequent formation of the metal gate.

[0081] In some embodiments, a wet etching process is used to remove the dummy gate structure. Wet etching processes have a high etching rate, are quick to operate, and have low processing costs.

[0082] In some embodiments, during the step of removing the dummy gate structure, the gate opening 26 exposes the top and part of the sidewalls of the fin 21. The gate opening 26 exposes the top and part of the sidewalls of the fin 21, providing process space for the subsequent formation of a metal gate that surrounds one end of the fin 21 on three sides.

[0083] refer to Figure 6 The substrate 10 is subjected to any of the aforementioned gate oxide processes. The gate oxide process grows an atomically precise, dense, and defect-free high-quality insulating layer in the gate opening, reducing the risk of short circuits or large leakage currents between the metal gate and the fin 21.

[0084] In some embodiments, after the gate oxide process is performed, a metal gate is formed in the gate opening.

[0085] The metal grid covers part of the sidewall and part of the topwall of the fin 21 and is used to control the opening and closing of the channel area.

[0086] In some embodiments, the metal gate includes a work function layer, an electrode layer, and a second barrier layer.

[0087] refer to Figure 7 The step of forming a metal gate 30 in the gate opening after performing the gate oxide process includes forming a first barrier layer 29 that conformally covers the gate oxide layer 28. The first barrier layer 29 prevents the material of the work function layer subsequently formed thereon from diffusing into the gate oxide layer 28, thus maintaining the good performance of the gate oxide layer 28. Furthermore, it also prevents the material of the work function layer from diffusing into the channel region, thereby improving the performance of the semiconductor device.

[0088] In some embodiments, the material of the first barrier layer 29 includes one or more of TaN, Ta, Ti, TiN, ZrN, and ZrTiN.

[0089] In some embodiments, the first barrier layer 29 is formed using a physical vapor deposition (PVD) process. PVD has advantages such as low deposition temperature, fast deposition rate, controllable composition and structure of the deposited layer, simple operation, high efficiency, and low cost. In other embodiments, chemical vapor deposition or atomic layer deposition can also be used to form the first barrier layer.

[0090] In some embodiments, forming a metal gate 30 in the gate opening further includes forming a multilayer film on the substrate, wherein at least one of the multilayer films is a single-element layer.

[0091] The multilayer film may contain a single-element layer, i.e., a layer composed of only one element, or a layer composed of multiple elements.

[0092] In some embodiments, multilayer films are formed layer by layer on a substrate used to form transistors via sputtering. When fabricating a single-layer film, the substrate for forming the transistor is provided to a corresponding process chamber. A target of the corresponding element is used to form a single-element layer, while a target of the corresponding alloy is used to form a multi-element film. Sputtering technology has advantages such as low deposition temperature, fast deposition rate, controllable composition and structure of the deposited layer, simple operation, high efficiency, and low cost, and it is highly compatible with existing equipment and processes.

[0093] As an example, the multilayer film has three layers: the first and second layers are single-element layers, wherein the first layer is composed of a first element, the second layer is composed of a second element, and the third layer is an element layer composed of the first element and the second element.

[0094] The first element is Ti, the second element is Al, and correspondingly, the material of the third layer is TiAl.

[0095] In other embodiments, atomic layer deposition (ALD) can be used to form multilayer films. ALD has good conformal coverage and also helps to improve the thickness uniformity of the individual film layers.

[0096] The multilayer film is heated to form a work function layer. This work function layer is used to adjust the threshold voltage of the subsequently formed transistor.

[0097] Heat treatment can improve the interdiffusion of atoms or ions of corresponding elements in multilayer films, thereby improving the formation quality of work function layers.

[0098] In some embodiments, a reflow process is used to heat the multilayer film. Through the reflow process, the multilayer film is brought to a molten state. Utilizing the surface tension and neutrality of the multilayer film, the material flows towards the bottom voids, achieving bottom-up, void-free filling and preventing abnormal device resistance or short circuits.

[0099] The step of forming the metal gate 30 further includes forming an electrode layer on the work function layer.

[0100] The steps of forming the electrode layer include: forming a conformally wetted metal layer covering the work function layer; and after forming the wetted metal layer, forming a conductive layer that fills the gate opening.

[0101] The wetted metal layer can improve the adhesion of the conductive layer and achieve a better filling effect. Specifically, the material of the wetted metal layer is one or more of Al, W, Ti, and Co.

[0102] In some embodiments, an atomic layer deposition (ALD) process is used to form the wetted metal layer. ALD has good conformal coverage, which helps ensure that the wetted metal layer conformally covers the work function layer during the formation process. ALD also improves the thickness uniformity of the wetted metal layer. In other embodiments, a chemical vapor deposition (CVD) process can also be used to form the wetted metal layer.

[0103] In some embodiments, the conductive layer is made of Al. In other embodiments, the conductive layer may also be made of Cu or W.

[0104] In some embodiments, the conductive layer is formed using a chemical vapor deposition process. In other embodiments, the conductive layer may also be formed using a physical vapor deposition process or an atomic layer deposition process.

[0105] The method for forming the semiconductor structure further includes: forming a second barrier layer on the work function layer after forming the work function layer and before forming the electrode layer. The second barrier layer is used to prevent easily diffusing ions in the electrode layer from diffusing into the work function layer, causing a change in the work function in the work function layer, which in turn prevents the work function layer from effectively adjusting the threshold voltage of the transistor structure.

[0106] Specifically, the material of the second barrier layer includes one or more of TaN, Ta, Ti, TiN, ZrN, and ZrTiN. In this embodiment, the material of the second barrier layer is TiN.

[0107] In some embodiments, an atomic layer deposition (ALD) process is used to form the second barrier layer. ALD has good conformal coverage, which helps ensure that the second barrier layer conformally covers the bottom and sidewalls of the work function layer during its formation. ALD also improves the thickness uniformity of the second barrier layer. In other embodiments, a chemical vapor deposition (CVD) process can also be used to form the second barrier layer.

[0108] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A gate oxide process, characterized in that, include: Provide substrate; The substrate is subjected to a first dry oxidation treatment in a chlorine-containing atmosphere to form a first oxide layer on the substrate; After the first oxide layer is formed, the substrate is subjected to wet oxidation treatment in the chlorine-containing atmosphere to form a second oxide layer between the first oxide layer and the substrate; After the second oxide layer is formed, the substrate is subjected to a second dry oxidation process in the chlorine-containing atmosphere to form a third oxide layer between the second oxide layer and the substrate. Silicon-chlorine bonds are formed at the interface between the third oxide layer and the substrate.

2. The gate oxide process as described in claim 1, characterized in that, In the first dry oxidation process of the substrate, the chlorine-containing atmosphere is provided by introducing trans-1,2-dichloroethylene.

3. The gate oxide process as described in claim 1, characterized in that, The step of forming a first oxide layer on the substrate includes: the process temperature range of the first oxide layer is 600°C to 800°C; In the step of performing wet oxidation on the substrate, the process temperature range of the second oxide layer is 600°C to 800°C. In the step of performing a second dry oxidation process on the substrate, the process temperature of the second oxide layer is 800°C to 900°C.

4. The gate oxide process as described in claim 1, characterized in that, The process temperature of the first oxide layer and The second oxide layer is processed at the same temperature.

5. The gate oxide process as described in claim 1, characterized in that, In the step of wet oxidation of the substrate, water vapor provides hydroxyl groups as a transport carrier for chlorine, which promotes chlorine atoms to fill oxygen vacancies in the second oxide layer; The second dry oxidation process is also used to expel hydrogen atoms or hydroxyl groups introduced into the substrate or oxide layer during the wet oxidation process.

6. The gate oxide process as described in claim 1, characterized in that, The thickness of the first oxide layer ranges from 10 angstroms to 15 angstroms; the thickness of the second oxide layer ranges from 35 angstroms to 55 angstroms; and the thickness of the third oxide layer ranges from 10 angstroms to 15 angstroms.

7. The gate oxide process as described in claim 1, characterized in that, The substrate is made of silicon.

8. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate comprising a substrate, a dummy gate structure formed on the substrate, source and drain doped layers formed in substrates on both sides of the dummy gate structure, and an interlayer dielectric layer covering the sidewalls of the dummy gate structure; Remove the dummy gate structure to form a gate opening that exposes the substrate; Within the gate opening, the substrate is subjected to the gate oxide process as described in any one of claims 1 to 7; After the gate oxide process is performed, a metal gate is formed in the gate opening.

9. The method for forming a semiconductor structure as described in claim 8, characterized in that, In the step of providing the substrate, lightly doped drain structures are formed in the substrates on both sides of the pseudo-gate structure.

10. The method for forming a semiconductor structure as described in claim 8, characterized in that, The substrate includes: a fin located on the substrate, wherein the pseudo-gate structure spans the fin and covers a portion of the top wall and a portion of the side wall of the fin; In the step of removing the pseudo-gate structure, the gate opening exposes the top and part of the sidewall of the fin.

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