Real-time clock chip detection method and device, electronic equipment and storage medium

Abstract

The application provides a real-time clock chip detection method and device, electronic equipment and storage medium. The detection method comprises the following steps: after the state value of a state check register built in a real-time clock chip is detected, the following operations are continuously performed: reading the state value of the state check register and the time value output by the real-time clock chip; if the state value is detected each time and the time interval of adjacent operations is very small, the real-time clock chip is detected. The detection method can detect whether the in-chip register data of the real-time clock chip is valid.

Description

Technical Field

[0001] This invention relates to the field of real-time clock chip technology, and in particular to a method, apparatus, electronic device, and storage medium for detecting real-time clock chips. Background Technology

[0002] In high-security industrial products, the RTC (Real-Time Clock) chip serves as the core time reference source for the entire system. Its timing accuracy, time continuity, and operational reliability directly determine the effectiveness and reliability of a series of key business functions, such as event logging, timing control, security auditing, fault tracing, and data synchronization. At the event recording level: Industrial site operation logs, alarm events, and fault occurrence times all rely on RTC to provide accurate timestamps. Once the time is inaccurate or jumps, it will directly lead to the disorder of event sequence, failure of fault tracing, and even cause disputes over the determination of safety responsibility. At the timing control level: core processes such as production line automation control, equipment start-up and shutdown sequence, periodic inspection, and protection action triggering are all based on RTC time as the execution benchmark. Time deviation or interruption will cause control logic to be disordered and equipment to malfunction, seriously threatening production safety. At the security audit level: security audits, compliance verifications, and data tamper-proofing traceability of industrial control systems all rely on RTC time as the core verification basis. Unreliable time will directly lead to the invalidation of audit data, failing to meet the requirements of information security level protection and industry compliance.

[0003] While current mainstream industrial-grade RTC chips have integrated basic functions such as power-down retention (battery / supercapacitor backup), temperature compensation (high-precision crystal oscillator temperature compensation), interrupt output (timer / alarm interrupt), and write protection, and can meet basic timing needs in conventional civilian and low-interference scenarios, they still have significant reliability shortcomings in harsh environments such as strong electromagnetic interference, complex power fluctuations, extreme temperature and humidity, and frequent start-stops in industrial settings. Electromagnetic interference can easily cause false interrupt triggering and abnormal reading and writing of the time register, leading to time jumps and timing inaccuracies. Power surges and ESD impacts may cause abnormal chip states and crystal oscillator stoppage, disrupting time continuity. Traditional single-check logic cannot distinguish between transient interference and real faults, easily resulting in misjudgments and missed judgments, and cannot meet the stringent requirements of high-security products. Therefore, how to test real-time clock chips has become an urgent problem to be solved. Summary of the Invention

[0004] The purpose of this invention is to provide a method, apparatus, electronic device, and storage medium for detecting real-time clock chips.

[0005] To achieve one of the aforementioned objectives, an embodiment of the present invention provides a method for detecting a real-time clock chip, comprising the following steps: reading the state value S1 of the state verification register built into the real-time clock chip; if the state value S1 does not meet a preset condition, the real-time clock chip passes the detection; otherwise, waiting for a first preset time, reading the state value S2 of the state verification register built into the real-time clock chip; if the state value S2 meets a preset condition, the real-time clock chip passes the detection; if the state value S2 does not meet the preset condition, setting i=1, and continuously performing the following operation N times: reading the state value of the state verification register. and the time value output by the real-time clock chip. The value of i is incremented by 1, and the operation ends after a second preset time. Calculation ;if , ,..., All meet the preset conditions, and , ,..., When the absolute value of the difference between any two values ​​in the range is less than or equal to a preset threshold, the real-time clock chip passes the detection; where i, j and N are all natural numbers, N≥2, i=1,2,...,N, j=1,2,...,N-1, and the preset threshold>0.

[0006] As a further improvement of one embodiment of the present invention, the status verification register is specifically an OSF register; the status value S1 not meeting the preset condition specifically includes: when the status value S1 is 1, the preset condition is not met; the status value S2 meeting the preset condition specifically includes: when the status value S2 is 0, the preset condition is met; the status value S2 not meeting the preset condition specifically includes: when the status value S2 is 1, the preset condition is not met.

[0007] As a further improvement of one embodiment of the present invention, the status verification register is specifically an EBF register; the status value S1 not meeting the preset condition specifically includes: when the status value S1 is 1, the preset condition is not met; the status value S2 meeting the preset condition specifically includes: when the status value S2 is 0, the preset condition is met; the status value S2 not meeting the preset condition specifically includes: when the status value S2 is 1, the preset condition is not met.

[0008] As a further improvement of one embodiment of the present invention, the status verification register is specifically a CALIB register; the status value S1 not meeting the preset condition specifically includes: when the status value S1 is 1, the preset condition is not met; the status value S2 meeting the preset condition specifically includes: when the status value S2 is 0, the preset condition is met; the status value S2 not meeting the preset condition specifically includes: when the status value S2 is 1, the preset condition is not met.

[0009] As a further improvement of one embodiment of the present invention, after determining that the real-time clock chip has passed the detection, the method further includes: removing the write protection bit of the real-time clock chip.

[0010] As a further improvement of one embodiment of the present invention, the interrupt pin of the real-time clock chip is connected to an anti-interference circuit.

[0011] As a further improvement of one embodiment of the present invention, the anti-interference circuit includes a cascaded structure of an RC low-pass filter network and a Schmitt trigger.

[0012] As a further improvement of one embodiment of the present invention, the anti-interference circuit includes: an absorption circuit, a π-type filter circuit, and a noise suppression element; the absorption circuit is used for surge protection and ESD protection.

[0013] This invention also provides a detection device for a real-time clock chip, comprising the following modules: a status value detection module, used to read the status value S1 of the status verification register built into the real-time clock chip; if the status value S1 does not meet a preset condition, the real-time clock chip passes the detection; otherwise, after waiting for a first preset time, the status value S2 of the status verification register built into the real-time clock chip is read; if the status value S2 meets the preset condition, the real-time clock chip passes the detection; and a time detection module, used to, when the status value S2 does not meet the preset condition, set i=1 and continuously perform the following operation N times: read the status value of the status verification register. and the time value output by the real-time clock chip. The value of i is incremented by 1, and the operation ends after a second preset time. Calculation ;if , ,..., All meet the preset conditions, and , ,..., When the absolute value of the difference between any two values ​​in the range is less than or equal to a preset threshold, the real-time clock chip passes the detection; where i, j and N are all natural numbers, N≥2, i=1,2,...,N, j=1,2,...,N-1, and the preset threshold>0.

[0014] This invention also provides an electronic device, including: a memory for storing executable instructions; and a processor for implementing the above-described detection method when executing the executable instructions stored in the memory.

[0015] This invention also provides a storage medium storing a computer program that, when executed by a processor, implements the steps of the detection method described above.

[0016] Compared to existing technologies, the technical advantages of this invention are as follows: This invention provides a method, apparatus, electronic device, and storage medium for detecting a real-time clock chip. The detection method includes the following steps: after the status value of the status check register built into the real-time clock chip passes the detection, the following operations are performed consecutively: reading the status value of the status check register and the time value output by the real-time clock chip; if the status value passes the detection each time, and the time interval between adjacent operations is very small, the real-time clock chip passes the detection. This detection method can detect whether the on-chip register data of the real-time clock chip is valid. Attached Figure Description

[0017] Figure 1 This is a flowchart illustrating the detection method for a real-time clock chip in an embodiment of the present invention. Figure 2 This is a test hardware diagram of the real-time clock chip detection method in this embodiment of the invention; Figure 3 This is an experimental result diagram of the detection method for the real-time clock chip in an embodiment of the present invention. Detailed Implementation

[0018] The present invention will now be described in detail with reference to the embodiments shown in the accompanying drawings. However, these embodiments do not limit the present invention, and any structural, methodological, or functional modifications made by those skilled in the art based on these embodiments are included within the scope of protection of the present invention.

[0019] The terms used herein, such as “above,” “over,” “below,” and “under,” indicating spatial relative position, are for illustrative purposes to describe the relationship of one unit or feature relative to another unit or feature as shown in the accompanying drawings. The terms of spatial relative position may be intended to include different orientations of the device in use or operation other than those shown in the figures. For example, if the device in the figures is flipped, a unit described as being “below” or “under” other units or features would be located “above” other units or features. Therefore, the exemplary term “under” can encompass both above and below orientations. The device may be oriented in other ways (rotated 90 degrees or otherwise), and the spatially related descriptive terms used herein shall be interpreted accordingly.

[0020] Embodiment 1 of the present invention provides a method for detecting a real-time clock chip, such as... Figure 1 As shown, it includes the following steps: Step 101: Read the status value S1 of the status verification register built into the real-time clock chip. If the status value S1 does not meet the preset conditions, the real-time clock chip passes the test; otherwise, wait for a first preset time, read the status value S2 of the status verification register built into the real-time clock chip, and if the status value S2 meets the preset conditions, the real-time clock chip passes the test. Step 102: When the state value S2 does not meet the preset condition, set i=1 and continuously perform the following operation N times: read the state value of the state verification register. and the time value output by the real-time clock chip. The value of i is incremented by 1, and the operation ends after a second preset time. Calculation ;if , ,..., All meet the preset conditions, and , ,..., When the absolute value of the difference between any two values ​​in the range is less than or equal to a preset threshold, the real-time clock chip passes the detection; where i, j and N are all natural numbers, N≥2, i=1,2,...,N, j=1,2,...,N-1, and the preset threshold>0.

[0021] Here, in practice, such as Figure 2 As shown, real-time clock chips are typically connected to microcontrollers (MCUs). These chips provide time signals to the MCU. This detection method can be executed by a microcontroller (MCU). The MCU can read the status values ​​in the real-time clock chip. For example, this detection method can be executed when the power supply Vbat of the real-time clock chip is abnormal, or when the clock stop flag ST≠0, or the data valid flag OSF≠0, or the read / write conflict flag≠0. This detection method can also be executed when the real-time clock chip is first powered on or initialized.

[0022] This detection method uses a three-step progressive approach to determine whether the chip is functioning correctly: 1. First layer: Quick initial screening, read the status value S1 of the RTC status check register. If S1 does not meet the preset conditions (such as OSF / EBF / CALIB abnormality) → directly determine that the chip passes the test (no fault). If S1 meets the preset conditions (suspected abnormality) → wait for the first preset time and reread the status value S2.

[0023] 2. Second layer: Secondary state confirmation. If S2 meets the preset conditions (abnormality disappears), the chip is determined to pass the test (it is a momentary interference). If S2 still meets the preset conditions (abnormality continues), the third layer deep verification is entered.

[0024] 3. Third layer: N consecutive depth checks, performing N consecutive operations: each time reading the status value. i +Time value i At a second preset time interval, calculate the time difference between adjacent times. The two core conditions for passing are: all... All meet the preset conditions (status remains normal). The absolute value of the difference between the two conditions must be less than or equal to a preset threshold (timekeeping is stable and there are no jumps). If both conditions are met simultaneously, the chip passes the test; otherwise, it is considered faulty.

[0025] The advantages of this detection method include: 1. Significantly improves RTC time stability: Actual measurements show that, under the conditions of superimposed ±2kV ESD interference and 100ns / 5V spike pulse, the number of abnormal RTC settings is reduced from an average of 17 times / hour in the traditional scheme to ≤1 time / 72 hours, and the time jump amplitude is controlled within ±0.5s; 2. Enhance system fault self-recovery capability: Introduce delayed rereading and multi-value comparison mechanism to automatically filter transient errors caused by brief interference, avoiding manual intervention or whole machine reset; 3. Excellent compatibility and portability: The hardware circuit requires only a few passive components, without the need to change the RTC chip model or main control peripheral resources; the software logic is implemented in C language and is compatible with mainstream MCU platforms such as ARM Cortex-M and RISC-V. 4. Supports fault tracing and security auditing: Optional write operation audit log function, which records the trigger conditions, verification results, timestamps and environmental parameters (such as VDD voltage and temperature) for each RTC write, meeting the log integrity requirements of high security standards such as IEC 62443 and EN 50128.

[0026] The preset threshold Δt is dynamically calculated based on the nominal daily drift error specified in the RTC crystal oscillator datasheet and the current cumulative system running time t (in seconds): The maximum allowable time difference Δt is relaxed to a certain time, balancing long-term drift tolerance and short-term interference suppression. Meanwhile, for devices with time synchronization capabilities, timed synchronization can be performed to eliminate absolute errors.

[0027] In this embodiment, the status verification register is specifically an OSF register; the status value S1 not meeting the preset condition specifically includes: when the status value S1 is 1, the preset condition is not met; the status value S2 meeting the preset condition specifically includes: when the status value S2 is 0, the preset condition is met; the status value S2 not meeting the preset condition specifically includes: when the status value S2 is 1, the preset condition is not met.

[0028] OSF stands for Oscillator Stop Flag.

[0029] The OSF (Optical State Flag) is the most basic status flag of a real-time clock chip, used to indicate whether the internal crystal oscillator / oscillator is working properly. It is the first threshold for determining the reliability of the time. When the OSF status value is 1 (valid), it means that the oscillator in the real-time clock chip has stopped (e.g., due to power failure, crystal oscillator malfunction, or abnormal power supply), the current time may be inaccurate and needs to be recalibrated / synchronized. When the OSF status value is 0 (valid), it means that the oscillator in the real-time clock chip is continuously operating normally, and the timing basis is reliable.

[0030] After power-on / reset, the main controller must first read the OSF bit: if it is 1, it means that the real-time clock chip has been restarted after power failure and the time is out of accuracy, and the correct time must be rewritten; if it is 0, it means that the timing has not been interrupted and the time can be read directly.

[0031] In this embodiment, the status verification register is specifically the EBF register; the status value S1 not meeting the preset condition specifically includes: when the status value S1 is 1, the preset condition is not met; the status value S2 meeting the preset condition specifically includes: when the status value S2 is 0, the preset condition is met; the status value S2 not meeting the preset condition specifically includes: when the status value S2 is 1, the preset condition is not met.

[0032] EBF stands for Event Buffer Flag, and its Chinese name is Event Buffer Flag / Battery Backup Flag. The core function of the EBF register is to indicate the power status and event buffer status of the real-time clock chip. Specifically, it is used to indicate whether there are unprocessed events in the internal event buffer (such as alarm, interrupt, power failure events) of the real-time clock chip, or whether the buffer has overflowed.

[0033] When the EBF register's status value is 1, it indicates that the real-time clock chip has an unprocessed abnormal event (such as power failure, false interrupt triggering, or low battery voltage). The time may jump due to the abnormality, and the abnormality needs to be investigated before reading and writing the time again.

[0034] When the EBF register has a status value of 0, it indicates that the real-time clock chip is operating normally, the event / power status is normal, and time read / write is safe.

[0035] In this embodiment, the status verification register is specifically the CALIB register; the status value S1 not meeting the preset condition specifically includes: when the status value S1 is 1, the preset condition is not met; the status value S2 meeting the preset condition specifically includes: when the status value S2 is 0, the preset condition is met; the status value S2 not meeting the preset condition specifically includes: when the status value S2 is 1, the preset condition is not met.

[0036] The CALIB register indicates the RTC calibration status and calibration operation status, and is a key indicator for ensuring time accuracy. When the CALIB register value is 1, it means that the RTC is performing a calibration operation (such as temperature compensation calibration, manual frequency calibration), or the calibration parameters have taken effect. At this time, the time register is in an unstable state, and reading, writing, or modifying the time is prohibited. When the CALIB register value is 0, it means that the calibration operation has been completed, the time register is stable, and it can be read and written normally.

[0037] These three flag bits are the core judgment basis for the software's three-level verification. The complete verification logic is as follows: Step 1: Status Register Check. After the main controller receives an interrupt, it first reads the OSF, EBF, and CALIB bits: If OSF=1, it indicates an oscillator malfunction, time inaccuracy, write rejection, and synchronization trigger; if EBF=1, it indicates an abnormal event, write rejection, and troubleshooting; if CALIB=1, it indicates calibration is in progress, delay and wait, and read / write is prohibited. Step 2: Delayed Reread + Multiple Consecutive Reads. After the status is normal, a delay is used to avoid the interference window, and the time value is read multiple times consecutively. Step 3: Time Comparison. If the deviation of multiple read values ​​is ≤ a preset threshold, the time is considered valid, write protection is released, and writing is allowed.

[0038] In this embodiment, after determining that the real-time clock chip has passed the test, the method further includes: removing the write protection bit of the real-time clock chip.

[0039] The write protection bit on a real-time clock chip is a dedicated control switch in its internal register. Its core function is to physically lock the time writing operation, preventing accidental modification (unauthorized time changes) due to misoperation or interference. When the write protection bit is 1 (locked / unlocked), the real-time clock chip is in a locked state. At this time, writing any data to the time register is prohibited. Even if the host issues a "modify time" command, the chip will automatically ignore it and not execute the write operation. When the write protection bit is 0, the real-time clock chip is in an unlocked state. At this time, writing time is allowed.

[0040] In normal operation (locked), after system startup, the RTC write-protect bit is set to 1 by default (locked). The master controller cannot modify the time at this time. Upon successful verification (unlocking), and confirming that the write operation was legitimate, valid, and non-interfering, the following actions are performed: Action 1: Write a specific unlock key to the write-protect bit (different chips use different unlocking methods; some write 0, others write a specific sequence). This changes the write-protect bit to 0, unlocking the system; Action 2: Perform the write (time change). After the write-protect bit is unlocked, the master controller immediately writes the new time data; Action 3: Immediately relock (security closed loop). The key action: After writing the time, the write-protect bit must be immediately written back to 1 (locked). Reason: To ensure that the system immediately returns to a secure state after the operation, leaving no opportunity for interference / misoperation.

[0041] In this embodiment, the interrupt pin of the real-time clock chip is connected to an anti-interference circuit.

[0042] RTC stands for Real-Time Clock.

[0043] Here, the interrupt pins can be specifically defined as follows: 1. INT pin (Interrupt output): Its function is to send an interrupt signal to the MCU, indicating that a certain RTC event has occurred. Common trigger conditions include: alarm timeout (Alarm Match), second pulse trigger (1Hz, etc.), or counter overflow. It is usually an open-drain output, requiring a pull-up resistor; active low (pull-down indicates interrupt trigger); it can be left floating or connected high when not in use. 2. SQW pin (Square Wave output): Its function is to output a continuous square wave signal at a fixed frequency. Common frequencies (configurable via registers) are: 32.768kHz, 1Hz, 4kHz, 8kHz, or 32kHz, etc. Its characteristics are: pure hardware output, synchronized with time; independent of the CPU, stable and reliable; some chips multiplex SQW and INT on the same pin. 3. Pins (SDA+SCL, IIC communication interface), the data interface for communication between the RTC and the MCU; most RTCs are... Interface. SDA (Serial Data) is used for serial data input / output, with an open-drain structure, and requires a pull-up. SCL (Serial Clock) is used for the serial clock line, provided by the host (MCU, Microcontroller Unit), and controls the communication timing.

[0044] Weak hardware-level noise immunity: The interrupt pins of the RTC chip (such as INT / SQW / IIC) are sensitive to power supply noise. When there is switching power supply ripple, relay operation surge or ESD (Electrostatic Discharge) transient interference in the main system, it is easy to generate glitch pulses with a width of <100ns on the INT line. Although such glitch is not enough to trigger normal interrupt logic, it may be sampled as a valid edge by the GPIO (General Purpose Input / Output) input circuit of the main control MCU, thus mistakenly starting the RTC time read and write process.

[0045] In this embodiment, the anti-interference circuit includes a cascaded structure of an RC low-pass filter network and a Schmitt trigger.

[0046] Here, the anti-interference circuit can physically shield interference spikes with a width smaller than a preset threshold (preferably ≤50ns) and perform level shaping to ensure that only valid interrupt signals that meet the timing and amplitude requirements can be sent to the main controller. Specifically, the low-pass filter removes high-frequency noise, power supply ripple, and ESD spikes, and shields narrow spikes ≤50ns. The Schmitt trigger shapes the irregular levels of the interfered signal into a clean, standard square wave, preventing misjudgment by the MCU.

[0047] The application scenarios here are mainly for digital signal ports, so it is used for anti-interference design of digital signals such as / INT and IIC of real-time clock chips.

[0048] In this embodiment, the anti-interference circuit includes: an absorption circuit, a π-type filter circuit, and a noise suppression element; the absorption circuit is used for surge protection and ESD protection.

[0049] Here, the core function of the absorption circuit is to provide port-level strong interference protection, resist large-energy transient interference from external input, and protect the subsequent circuits from being damaged.

[0050] The core function of the π-type filter circuit is to filter power supply noise, remove differential / common mode electromagnetic interference, and smooth power supply ripple, which is a core component of power supply EMC.

[0051] The core function of noise suppression components is to perform fine noise suppression and signal shaping, filter out high-frequency noise and spike interference left over from the previous stage, and shape digital signals to improve anti-interference capabilities.

[0052] Signal flow: VCC In / GND In → First stage: Protection and absorption circuit → Second stage: π-type filter circuit → Third stage: Noise suppression component → VCC Out / GND Out (powers the back-end circuit). The three-stage circuits each perform their own functions, forming a complete closed loop of "surge protection → ripple filtering → residual noise suppression", covering the entire frequency band of interference from high voltage transients to high frequency noise.

[0053] 1. First level: Surge + ESD protection absorption circuit (first line of defense) Its core function is to withstand extreme transient high-voltage surges, acting as a "fuse" for the entire circuit, protecting all downstream components from breakdown. It is designed to handle interference types such as ESD (±8kV / ±15kV), surge pulses (lightning strikes / switching transients), and overvoltage spikes. Typical implementation components include: TVS transient voltage suppressor diodes, varistors (MOV), gas discharge tubes, and ESD protection chips. Operating principle: Under normal voltage, the device is in a high-resistance state, not affecting normal power transmission; when a transient high voltage (such as ESD or surge) occurs, the device instantly conducts, clamping the high voltage to a safe value while simultaneously discharging the large current to ground, preventing high voltage from impacting the precision circuitry downstream. Its key functions are: physically blocking extreme high voltages, preventing damage to RTC, main control, and other chips from electrostatic discharge / surge damage, eliminating high-energy transient interference on the power line, and creating safe operating conditions for subsequent filtering circuits.

[0054] 2. Second stage: π-type filter circuit (core filter unit) The core function is to filter out low-frequency ripple and intermediate-frequency noise on the power supply line, and suppress differential-mode / common-mode interference, making it a crucial component of power supply purification. It targets the following types of interference: power supply ripple (50 / 60Hz mains frequency, 10kHz~1MHz noise from switching power supplies), differential-mode interference, and common-mode interference. A typical circuit structure consists of two capacitors (input / output to ground) and one inductor (connected in series with the VCC main circuit). Working principle: The series inductor provides high impedance to high-frequency noise, preventing noise transmission to the downstream circuit; it provides low impedance to DC / low-frequency power, not affecting normal power supply. The parallel capacitor bypasses high-frequency / intermediate-frequency noise to ground, filtering out ripple on the power supply line. The combination of the two capacitors and the intermediate inductor forms a "low-pass filter," allowing only effective DC / low-frequency power to pass through, filtering out most mid-to-high-frequency interference. Its key functions are: significantly reducing power supply ripple, providing a stable and clean DC power supply to the downstream RTC, preventing timing inaccuracies caused by power fluctuations; and suppressing differential-mode / common-mode interference, preventing power supply noise from coupling to the signal link and causing false interruptions.

[0055] 3. Third stage: Noise suppression components (the final purification barrier) The core function is to eliminate residual high-frequency noise and common-mode interference from the pre-amplifier stage, further improving power supply purity; this is the "refined" stage. It targets the following interference types: high-frequency residual noise (above 1MHz), common-mode interference, and electromagnetic radiation interference. Typical implementation components include: common-mode inductors, ferrite beads, high-frequency filter capacitors, and EMI suppression chips. The working principle is as follows: Common-mode inductors: present high impedance to common-mode interference (noise in the same direction between two wires and ground), effectively suppressing common-mode noise; present low impedance to differential-mode power supply, without affecting power supply. Ferrite beads: present high impedance to high-frequency noise, converting high-frequency noise into heat energy for dissipation, specifically filtering out high-frequency interference above 100MHz. High-frequency capacitors: bypass residual ultra-high-frequency noise, further purifying the power supply. Its key functions are: to completely eliminate the high-frequency "glitch" left after the pre-stage filter, so that the power supply output is close to ideal DC; to suppress electromagnetic radiation, prevent power supply noise from radiating to the outside, and at the same time prevent external electromagnetic interference from entering the system through the power supply.

[0056] Figure 2 It is a circuit diagram used by the inventor in his experiments. Figure 3 The corresponding test result diagram is shown. This circuit diagram is based on a microcontroller (MCU), and the functions and connections of each module are as follows: The power supply and basic control are handled by a power switch that controls the switching of VCC and GND to provide the main power to the circuit. The power module is responsible for voltage conversion or regulation, outputting a stable VCC to power core components such as the MCU. C1 is used for power filtering. The reset circuit is connected to the MCU reset pin via R1, which can trigger the MCU reset upon power-on or in case of an abnormality, ensuring stable system startup.

[0057] The core control and time management are handled by the MCU, which provides the operating clock through a crystal oscillator circuit composed of X1, C2, and C3, and is responsible for logic operations and module scheduling. The RTC chip provides clock signals to the real-time clock chip through C4 and C5, enabling time recording after power failure, with backup battery power ensuring that the clock is not lost during power outages.

[0058] The anti-interference and backup power supply circuit filters out power supply noise through capacitors and resistors, improving circuit stability. The backup battery is connected to the RTC chip via R2 to provide continuous power when the main power supply is disconnected.

[0059] In the inventor's experiments, the RTC chip selected was the BLX8563 ( The interface includes an external 32.768kHz crystal oscillator and detection circuit, with its interrupt output pin INT connected to the main control GPIO. The anti-interference hardware module is configured as follows: RC low-pass filter network: R=10kΩ±5% (surface mount thick film resistor), C=100pF±10% (NPO ceramic capacitor), theoretical cutoff frequency fc≈1 / (2πRC)≈159MHz, which can effectively attenuate high-frequency noise above ≥500MHz; and absorption and filtering circuit composed of common mode inductor, TVS diode, etc.

[0060] Wiring requirements: RC components should be placed close to the RTCINT pin, with a trace length ≤ 5mm, and the ground of the anti-interference circuit should be isolated from the digital ground plane.

[0061] The specific procedure is as follows: #define RTC_RETRY_COUNT3u #define RTC_MAX_DRIFT_MS2000u / / Δt = 2s, corresponding to daily drift error × runtime dynamic calculation typedef enum { RTC_CHECK_IDLE, RTC_CHECK_FLAG, RTC_DELAY_RETRY, RTC_CONSISTENCY_VERIFY, RTC_WRITE_ALLOWED, RTC_WRITE_REJECTED } rtc_check_state_t; \nstatic rtc_check_state_t g_rtc_state = RTC_CHECK_IDLE;\nstaticuint32_t g_rtc_readings[RTC_RETRY_COUNT];\nstatic uint8_t g_retry_idx = 0; \nvoid RTC_Interrupt_Handler(void) { switch(g_rtc_state) { case RTC_CHECK_IDLE: if (RTC_Read_Status_Reg()&RTC_STATUS_OSF_MASK) { / / Check status bits g_rtc_state = RTC_CHECK_FLAG; HAL_Delay(1); / / To avoid metastability, wait 1ms } break case RTC_CHECK_FLAG: if (RTC_Read_Status_Reg()&RTC_STATUS_OSF_MASK) { g_rtc_state = RTC_DELAY_RETRY; g_retry_idx = 0; HAL_Delay(10); / / Delay 10ms to avoid interference window } else { g_rtc_state = RTC_CONSISTENCY_VERIFY; } break case RTC_DELAY_RETRY: g_rtc_readings[g_retry_idx++] = RTC_Read_Seconds(); if (g_retry_idx>= RTC_RETRY_COUNT) { if (IsConsistent(g_rtc_readings, RTC_RETRY_COUNT, RTC_MAX_DRIFT_MS)){ RTC_Unlock_Write(); / / Remove write protection g_rtc_state = RTC_WRITE_ALLOWED; } else { g_rtc_state = RTC_WRITE_REJECTED; } } break default: break; } } \nstatic bool IsConsistent(uint32_t vals, uint8_t cnt, uint32_t max_drift_ms) { for(uint8_t i=0; i <cnt; i++) { for(uint8_t j=i+1; j <cnt; j++) { if (abs((int32_t)(vals[i] - vals[j]))>max_drift_ms / 1000) { return false; } } } return true; } Embodiment 2 of the present invention provides a detection device for a real-time clock chip, comprising the following modules: The status value detection module is used to read the status value S1 of the status verification register built into the real-time clock chip. When the status value S1 does not meet the preset conditions, the real-time clock chip passes the detection; otherwise, it waits for a first preset time and reads the status value S2 of the status verification register built into the real-time clock chip. When the status value S2 meets the preset conditions, the real-time clock chip passes the detection. The time detection module is used to set i=1 and continuously perform the following operation N times when the state value S2 does not meet the preset condition: read the state value of the state verification register. and the time value output by the real-time clock chip. The value of i is incremented by 1, and the operation ends after a second preset time. Calculation ;if , ,..., All meet the preset conditions, and , ,..., When the absolute value of the difference between any two values ​​in the range is less than or equal to a preset threshold, the real-time clock chip passes the detection; where i, j and N are all natural numbers, N≥2, i=1,2,...,N, j=1,2,...,N-1, and the preset threshold>0.

[0062] Embodiment 3 of the present invention provides an electronic device, including: a memory for storing executable instructions; and a processor for implementing the detection method in Embodiment 1 when executing the executable instructions stored in the memory.

[0063] Embodiment 4 of the present invention provides a storage medium on which a computer program is stored, wherein the computer program, when executed by a processor, implements the steps of the detection method in Embodiment 1.

[0064] It should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This way of describing the specification is only for clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

[0065] The detailed descriptions listed above are merely specific descriptions of feasible embodiments of the present invention, and are not intended to limit the scope of protection of the present invention. All equivalent embodiments or modifications made without departing from the spirit of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for detecting a real-time clock chip, characterized in that, Includes the following steps: The status value S1 of the status verification register built into the real-time clock chip is read. If the status value S1 does not meet the preset condition, the real-time clock chip passes the test; otherwise, wait for a first preset time, read the status value S2 of the status verification register built into the real-time clock chip, and if the status value S2 meets the preset condition, the real-time clock chip passes the test. When the state value S2 does not meet the preset condition, set i=1 and perform the following operation N times consecutively: read the state value of the state verification register. and the time value output by the real-time clock chip. The value of i is incremented by 1, and the operation ends after a second preset time. Calculation ;if , ,..., All meet the preset conditions, and , ,..., When the absolute value of the difference between any two values ​​in the range is less than or equal to a preset threshold, the real-time clock chip passes the detection; where i, j and N are all natural numbers, N≥2, i=1,2,...,N, j=1,2,...,N-1, and the preset threshold>

0.

2. The detection method according to claim 1, characterized in that, The status verification register is specifically the OSF register; The specific inclusion of the state value S1 not meeting the preset condition includes: when the state value S1 is 1, the preset condition is not met; The state value S2 satisfying the preset condition specifically includes: when the state value S2 is 0, the preset condition is satisfied; The specific situation where the state value S2 does not meet the preset conditions includes: when the state value S2 is 1, the preset conditions are not met.

3. The detection method according to claim 1, characterized in that, The status verification register is specifically the EBF register; The specific inclusion of the state value S1 not meeting the preset condition includes: when the state value S1 is 1, the preset condition is not met; The state value S2 satisfying the preset condition specifically includes: when the state value S2 is 0, the preset condition is satisfied; The specific situation where the state value S2 does not meet the preset conditions includes: when the state value S2 is 1, the preset conditions are not met.

4. The detection method according to claim 1, characterized in that, The status verification register is specifically the CALIB register; The specific inclusion of the state value S1 not meeting the preset condition includes: when the state value S1 is 1, the preset condition is not met; The state value S2 satisfying the preset condition specifically includes: when the state value S2 is 0, the preset condition is satisfied; The specific situation where the state value S2 does not meet the preset conditions includes: when the state value S2 is 1, the preset conditions are not met.

5. The detection method according to claim 1, characterized in that, After determining that the real-time clock chip has passed the test, the method further includes: removing the write protection bit of the real-time clock chip.

6. The detection method according to claim 1, characterized in that, The interrupt pin of the real-time clock chip is connected to an anti-interference circuit.

7. The detection method according to claim 6, characterized in that, The anti-interference circuit includes a cascaded structure of an RC low-pass filter network and a Schmitt trigger.

8. The detection method according to claim 6, characterized in that, The anti-interference circuit includes: an absorption circuit, a π-type filter circuit, and a noise suppression element; The absorption circuit is used for surge protection and ESD protection.

9. A detection device for a real-time clock chip, characterized in that, Includes the following modules: The status value detection module is used to read the status value S1 of the status verification register built into the real-time clock chip. When the status value S1 does not meet the preset conditions, the real-time clock chip passes the detection; otherwise, it waits for a first preset time and reads the status value S2 of the status verification register built into the real-time clock chip. When the status value S2 meets the preset conditions, the real-time clock chip passes the detection. The time detection module is used to set i=1 and continuously perform the following operation N times when the state value S2 does not meet the preset condition: read the state value of the state verification register. and the time value output by the real-time clock chip. The value of i is incremented by 1, and the operation ends after a second preset time. Calculation ;if , ,..., All meet the preset conditions, and , ,..., When the absolute value of the difference between any two values ​​in the range is less than or equal to a preset threshold, the real-time clock chip passes the detection; where i, j and N are all natural numbers, N≥2, i=1,2,...,N, j=1,2,...,N-1, and the preset threshold>

0.

10. An electronic device, characterized in that, include: Memory, used to store executable instructions; A processor, when executing executable instructions stored in the memory, implements the detection method according to any one of claims 1 to 8.

11. A storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the detection method according to any one of claims 1 to 8.

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