A data processing method and related device for a multi-point shared register
By employing a multi-point shared register data processing method, and utilizing bit-level splitting and cache coordination mechanisms, the problem of register resource waste in Modbus applications is solved, achieving efficient data processing and resource utilization.
Patent Information
- Application Number
- CN202610518830.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-04-17
- Publication Date
- 2026-07-21
Smart Images
Figure CN122431726A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of software technology, and in particular to a data processing method and related apparatus for a multi-point shared register. Background Technology
[0002] In traditional Modbus applications, each logical point occupies a dedicated 16-bit register. Even if a logical point only needs to be represented by two or three bits, it still occupies a full 16 bits, resulting in a waste of a large number of register bit resources, increased equipment costs, and a limitation on the number of points that can be connected.
[0003] Therefore, how to automate the sharing of a single register among multiple logical points in Modbus communication has become an urgent problem to be solved at this stage. Summary of the Invention
[0004] In view of the above problems, this application provides a data processing method and related apparatus for multi-point shared registers to achieve the purpose of automated processing of multiple logic points sharing a single register. The specific solution is as follows:
[0005] The first aspect of this application provides a data processing method for a multi-point shared register, characterized in that the data processing method for the multi-point shared register includes:
[0006] Read the 16-bit integer values of each register in the Modbus slave device. Each register is occupied by at least one logical point, and each logical point is pre-configured with position occupancy information.
[0007] The sixteen-bit integer values of each register are converted into corresponding binary strings, and the binary strings of each register are extracted from the binary strings of the occupied registers according to the position occupancy information of each logical point.
[0008] Convert the binary string of each logical point to the corresponding decimal value, and store the decimal value of each logical point in the local cache.
[0009] In one possible implementation, the data processing method for the multi-point bit shared register further includes:
[0010] The write command is received in a single-threaded serial processing manner, and the write command contains a new decimal value of the target logical point to be written.
[0011] Determine the target register occupied by the target logic bit, and obtain the decimal values of each shared logic point bit of the target logic point under the target register from the current cache;
[0012] Convert the new decimal value of the target logical point and the decimal value of each shared logical point into the corresponding binary string;
[0013] According to the position occupancy information of the target logical point and each shared logical point, the binary strings of the target logical point and each shared logical point are concatenated to obtain a new binary string of the target register;
[0014] The new binary string in the target register is converted into a new 16-bit integer value, and the new 16-bit integer value in the target register is written into the target register.
[0015] In one possible implementation, the data processing method for the multi-point bit shared register further includes:
[0016] The new decimal value of the target logic point and the decimal value of each shared logic point are numerically verified, and the binary string of the target logic point and each shared logic point is bit-verified.
[0017] If the target logical point and each shared logical point pass the numerical verification and bit verification, the step of concatenating the binary strings of the target logical point and each shared logical point according to the position occupancy information of the target logical point and each shared logical point to obtain the new binary string of the target register is performed.
[0018] In one possible implementation, the data processing method for the multi-point bit shared register further includes:
[0019] After writing to the target register, wait for a preset time, and determine the writing result of the target logical point by reading back the target register;
[0020] If the write result of the target logical point is determined to be valid, the new decimal value of the target logical point is synchronized to the local cache.
[0021] In one possible implementation, determining the write result of the target logical point bit by reading back the target register includes:
[0022] Reread the sixteen-bit integer value of the target register;
[0023] The reread 16-bit integer value is converted back into the corresponding binary string, and the binary string of the target logical point is extracted from the reconverted binary string according to the position occupancy information of the target logical point.
[0024] The re-extracted binary string is converted back into the corresponding decimal value, and the converted decimal value is compared with the new decimal value of the target logical point.
[0025] If the reconverted decimal value is the same as the new decimal value of the target logical point, the write result of the target logical point is determined to be valid.
[0026] If the reconverted decimal value is different from the new decimal value of the target logical point, the write result of the target logical point is determined to be invalid.
[0027] In one possible implementation, the data processing method for the multi-point bit shared register further includes:
[0028] If the write result of the target logical point is determined to be invalid, the cumulative number of invalid entries is recorded, and the process of writing the new 16-bit integer value of the target register to the target register is returned to continue until the cumulative number of invalid entries reaches the corresponding threshold, at which point the corresponding log information is generated.
[0029] A second aspect of this application provides a data processing apparatus for a multi-point shared register, the data processing apparatus for the multi-point shared register comprising:
[0030] The read module is used to read the sixteen-bit integer values of each register in the Modbus slave device. Each register is occupied by at least one logical point, and each logical point is pre-configured with position occupancy information.
[0031] The conversion and caching module is used to convert the 16-bit integer values of each register into corresponding binary strings, and extract the binary strings of each logical point from the binary strings of the occupied registers according to the position occupancy information of each logical point; convert the binary strings of each logical point into corresponding decimal values, and store the decimal values of each logical point in the local cache.
[0032] A third aspect of this application provides a computer program product, characterized in that it includes computer-readable instructions, which, when executed on an electronic device, cause the electronic device to implement the data processing method of a multi-point shared register described in the first aspect or any implementation thereof.
[0033] A fourth aspect of this application provides an electronic device, including at least one processor and a memory connected to the processor, wherein:
[0034] The memory is used to store computer programs;
[0035] The processor is used to execute the computer program so that the electronic device can implement the data processing method of the multi-point shared register in the first aspect or any implementation thereof.
[0036] The fifth aspect of this application provides a computer storage medium carrying one or more computer programs, which, when executed by an electronic device, enable the electronic device to implement the data processing method of a multi-point shared register described in the first aspect or any implementation thereof.
[0037] By employing the above technical solution, this application provides a data processing method and related apparatus for multi-point shared registers, comprising: reading the 16-bit integer values of each register in a Modbus slave device, wherein each register is occupied by at least one logical point and each logical point is pre-configured with position occupancy information; converting the 16-bit integer values of each register into corresponding binary strings, and extracting the binary strings of each logical point from the binary strings of the occupied registers according to the position occupancy information of each logical point; converting the binary strings of each logical point into corresponding decimal values, and storing the decimal values of each logical point in a local cache. In this application, a single register can be occupied by multiple logical points, and based on the position occupancy information of each logical point, the binary strings of each logical point can be extracted from the binary strings of the registers to obtain the corresponding decimal values and store them in the local cache. This allows for accurate extraction of values from different logical points in multi-point shared register scenarios, improving the utilization rate of register bit resources, reducing equipment costs, and maximizing the number of accessible points. Attached Figure Description
[0038] The above and other features, advantages, and aspects of the embodiments of this disclosure will become more apparent from the accompanying drawings and the following detailed description. Throughout the drawings, the same or similar reference numerals denote the same or similar elements. It should be understood that the drawings are schematic, and the originals and elements are not necessarily drawn to scale.
[0039] Figure 1 A flowchart illustrating a data processing method for a multi-point shared register provided in an embodiment of this application;
[0040] Figure 2 An example of a register provided for an embodiment of this application;
[0041] Figure 3 This is a partial flowchart illustrating a data processing method for a multi-point shared register provided in an embodiment of this application.
[0042] Figure 4This is another part of the flowchart illustrating a data processing method for a multi-point shared register provided in an embodiment of this application;
[0043] Figure 5 A schematic diagram of the structure of a data processing device for a multi-point shared register provided in an embodiment of this application;
[0044] Figure 6 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation
[0045] The embodiments of this application are described below with reference to the accompanying drawings. The terminology used in the implementation section of this application is for explaining specific embodiments only and is not intended to limit the scope of this application.
[0046] The embodiments of this application will now be described with reference to the accompanying drawings. Those skilled in the art will recognize that, with technological advancements and the emergence of new scenarios, the technical solutions provided in the embodiments of this application are equally applicable to similar technical problems.
[0047] The terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such terms are interchangeable where appropriate; this is merely a way of distinguishing objects with the same attributes in the embodiments of this application. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion, so that a process, method, system, product, or apparatus that comprises a series of elements is not necessarily limited to those elements, but may include other elements not explicitly listed or inherent to those processes, methods, products, or apparatuses.
[0048] To enable multiple points to share a single register, this application provides a data processing method for a multi-point shared register. The data processing method for a multi-point shared register according to this application will be described in detail below with reference to the accompanying drawings.
[0049] See Figure 1 , Figure 1 This is a flowchart illustrating a data processing method for a multi-point shared register provided in an embodiment of this application. Figure 1 As shown in the figure, the data processing method for a multi-point shared register provided in this application embodiment may include steps S101 to S103, which are described in detail below.
[0050] S101, read the sixteen-bit integer values of each register in the Modbus slave device. Each register is occupied by at least one logical point, and each logical point is pre-configured with position occupancy information.
[0051] In this embodiment, bit-level splitting technology allows multiple logical points to occupy different bit segments of the same register. By configuring position occupancy information, a 16-bit register can be divided into multiple independent bit segments, each bit segment being occupied by a logical point.
[0052] Specifically, a Modbus slave device is configured with at least one register, each of which is occupied by at least one logical point. That is, each register may be exclusively occupied by one logical point or shared by multiple logical points. Each logical point is pre-configured with its position occupancy information within the register it occupies. This position occupancy information includes the address of the occupied register, the starting bit, and the bit length. For a single register, multiple logical points occupying that register occupy different consecutive bit segments of that register, and these segments do not overlap.
[0053] See Figure 2 , Figure 2 An example of a register provided for an embodiment of this application. For example... Figure 2 As shown, a 16-bit register can be occupied by three logical points. Logical point 1 occupies bits 0 to 3, logical point 2 occupies bits 4 to 9, and logical point 3 occupies bits 10 to 15. Taking logical point 1 as an example, its position occupancy information starts at bit 0 and has a bit length of 4, representing values from 0 to 15. This significantly improves register resource utilization, especially in building intelligent control scenarios. Modbus slave devices include a large number of building devices such as air conditioners, heat pumps, sensors, and lighting controllers, requiring the storage of a large amount of data from logical points such as temperature and humidity, on / off status, fan speed, and fault codes. This greatly reduces register occupancy, lowers equipment procurement costs, reduces communication overhead, and improves data acquisition efficiency.
[0054] In addition, in this embodiment of the application, a data acquisition thread is run, and read commands are sent to the Modbus slave device via the Modbus protocol at the configured frequency to obtain the original sixteen-bit integer values of each register, such as 0x0011.
[0055] S102 converts the sixteen-bit integer values of each register into corresponding binary strings, and extracts the respective binary strings from the binary strings of the occupied registers according to the position occupancy information of each logical point.
[0056] In this embodiment of the application, the sixteen-bit integer values of each register are converted to binary and then reversed to obtain the corresponding binary string. This is because the high bits of the register are on the left and the low bits are on the right. Therefore, the binary conversion and reversal can make bit 0 correspond to truncation index 0, bit 1 correspond to truncation index 1, bit 2 correspond to truncation index 2, and so on.
[0057] In addition, the binary string of each logical point can be extracted from the binary string of the occupied register according to the starting bit and bit length of each logical point. For example, the binary string of the register is "0000100000000000", the binary string of logical point 1 is "0000", the binary string of logical point 2 is "100000", and the binary string of logical point 3 is "000000".
[0058] S103 converts the binary strings of each logical point into corresponding decimal values and stores the decimal values of each logical point in the local cache.
[0059] In this embodiment, the binary string of each logical point is reversed again to restore the high bits to the left and the low bits to the right, and then converted into the corresponding decimal value. The decimal value of each logical point is then cached in a local cache as a key-value pair, where the point identifier of the logical point is the key and the decimal value of the logical point is the value. Continuing with the example, the binary string "0000" of logical point 1, after being reversed and converted, yields a decimal value of 0 for logical point 1. Similarly, the decimal value of logical point 2 is 1, and the decimal value of logical point 3 is 0.
[0060] In one possible implementation, in a multi-point shared register scenario, modifying a logical bit requires reading, modifying, and writing steps. However, if multiple programs operate simultaneously, it can lead to data overwriting. To address this, this application's embodiment solves the data overwriting problem through a cache coordination mechanism. When writing a bit, it does not read the values of other bits from the device, but instead reads the latest value from the local cache. See also... Figure 3 , Figure 3 This is a partial flowchart illustrating a data processing method for a multi-point shared register provided in an embodiment of this application. Figure 3 As shown in the figure, the data processing method for a multi-point shared register provided in this application embodiment further includes the following steps S201 to S205, which are described in detail below.
[0061] S201 receives write commands in a single-threaded serial processing manner. The write command contains the new decimal value of the target logical point to be written.
[0062] In this embodiment, for the Modbus channel with the Modbus slave device, a separate write thread can be run, and all writes are queued and executed sequentially, eliminating the possibility of concurrent overwriting from an architectural perspective. Upon receiving a write instruction for a target logical point, the new decimal value to be written to that target logical point can be parsed and obtained.
[0063] S202, determine the target register occupied by the target logic bit, and obtain the decimal values of each shared logic point bit under the target register from the current cache.
[0064] In this embodiment, the target register occupied by the target logical point can be determined based on the address of the register occupied by the target logical point, and then the other logical points under the target register, excluding the target logical point, are used as shared logical points. Further, the decimal values of each logical point are obtained from the local cache based on the point identifier of each shared logical point.
[0065] In practical applications, the target logical point and each shared logical point must have the same function code, the same slave device address, and the same register address.
[0066] S203 converts the new decimal value of the target logic point and the decimal values of each shared logic point into their respective binary strings.
[0067] In this embodiment, the new decimal value of the target logical point and the decimal values of each shared logical point are converted into corresponding binary strings. It should be noted that since truncation is not required when executing the write instruction, inversion is unnecessary.
[0068] S204: According to the position occupancy information of the target logical point and each shared logical point, the binary strings of the target logical point and each shared logical point are concatenated to obtain a new binary string of the target register.
[0069] In this embodiment of the application, according to the starting bit and bit length of the target logical point and each shared logical point, the binary strings of the target logical point and each shared logical point can be concatenated to obtain a new binary string of the target register.
[0070] S205 converts the new binary string in the destination register into a new 16-bit integer value and writes the new 16-bit integer value in the destination register into the destination register.
[0071] In this embodiment of the application, the new base string of the target register is converted into a new sixteen-bit integer value, and the new sixteen-bit integer value of the target register is written into the target register.
[0072] In practical applications, since the data in the target register other than the target logical bit does not need to be modified, the original data of the target logical bit can be cleared first by using bitwise AND and bitwise NOT operations, thereby limiting the new 16-bit integer value to a specified bit length, then shifting it left to the target logical bit, and finally merging it using bitwise OR operations.
[0073] In one possible implementation, to ensure the accuracy of the written data, this application embodiment can perform numerical verification and bit verification on the target logical point and each shared logical point before concatenating to obtain a new binary string. In this regard, the data processing method for a multi-point shared register provided by this application embodiment further includes the following steps:
[0074] Perform numerical verification on the new decimal value of the target logical point and the decimal values of each shared logical point, and perform bit verification on the binary strings of the target logical point and each shared logical point; if the target logical point and each shared logical point pass the numerical verification and bit verification, proceed to step S204.
[0075] In this embodiment of the application, the new decimal value of the target logic point and the decimal values of each shared logic point are numerically verified, such as whether they are within the corresponding data range. If the new decimal value of the target logic point is not within the corresponding data range, or the decimal value of a certain shared logic point is not within the corresponding value range, then it is determined that the numerical verification has failed.
[0076] In addition, the binary strings of the target logical point and each shared logical point are checked for bit length. For example, the sum of the number of bits in the binary strings of all logical points is checked to see if it exceeds sixteen bits. If it does, the bit length check is determined to have failed.
[0077] Step S204 is executed only if the target logical point and each shared logical point pass the numerical verification and bit verification to ensure the accuracy of the written data.
[0078] In one possible implementation, to ensure the correctness of write operations, embodiments of this application immediately read back the register for verification after each write. To this end, embodiments of this application provide a data processing method for a multi-point shared register, which further includes the following steps:
[0079] After writing to the target register, wait for a preset time, and determine the writing result of the target logical point by reading back the target register; if the writing result of the target logical point is determined to be valid, synchronize the new decimal value of the target logical point to the local cache.
[0080] In this embodiment, after writing to the target register, to ensure the write is effective in the Modbus slave device, a preset time is waited before reading back the target register. The write result of the target logical point is determined by comparing the readback result with the written data. If the write result of the target logical point is determined to be valid, the new decimal value of the target logical point is synchronized to the local cache, so as to replace the original data of the target logical point in the local cache with the new decimal value, thereby keeping the cache consistent with the device state. In addition, data is pushed to the Kafka message queue to notify the downstream system that the data has changed. Since the single-threaded serial operation ensures that the cache update of the previous instruction is completed before the next instruction reads the cache, the local cache read is always the latest.
[0081] In addition, if the write result of the target logical point is determined to be invalid, the invalid cumulative count is incremented by 1, and the process returns to step S205 to "write the new sixteen-bit integer value of the target register into the target register" until the invalid cumulative count reaches the corresponding threshold, at which point the writing ends and log information indicating an abnormal write to the target logical point is generated.
[0082] See Figure 4 , Figure 4 This is another part of the flowchart illustrating a data processing method for a multi-point shared register provided in an embodiment of this application. For example... Figure 4 As shown in the embodiment of this application, a data processing method for a multi-point shared register is provided. The step "determining the write result of the target logical point by reading back the target register" may include steps S301 to S305, which are described in detail below.
[0083] S301, reread the sixteen-bit integer value of the target register.
[0084] In this embodiment, the acquisition thread is rerun, and a read command is sent to the Modbus slave device via the Modbus protocol to reread the sixteen-bit integer value of the target register.
[0085] S302, the reread sixteen-bit integer value is converted back into the corresponding binary string, and the binary string of the target logical point is extracted from the converted binary string according to the position occupancy information of the target logical point.
[0086] In this embodiment of the application, the reread sixteen-bit integer value is directly converted to binary and then reversed to obtain the corresponding binary string. Then, the binary string of the target logical point is re-extracted from the re-converted binary string according to the starting bit and bit length of the target logical point.
[0087] S303 converts the re-extracted binary string back into the corresponding decimal value and compares the re-converted decimal value with the new decimal value of the target logic point.
[0088] In this embodiment, the re-extracted binary string is reversed again and converted into a corresponding decimal value. The re-converted decimal value is then compared with the new decimal value of the target logic point.
[0089] S304. If the reconverted decimal value is the same as the new decimal value of the target logical point, the write result of the target logical point is determined to be valid.
[0090] S305, if the reconverted decimal value is different from the new decimal value of the target logical point, the write result of the target logical point is determined to be invalid.
[0091] Based on the above description, the data processing method for multi-point shared registers provided in this application embodiment achieves multi-point shared registers through bit-level splitting, breaking through the traditional limitation of one point occupying one register, improving register resource utilization, and supporting flexible configuration. Furthermore, a bit extraction mechanism based on binary string reversal can achieve bit-level data extraction, simplifying the data parsing process in multi-point shared scenarios. Additionally, when writing to a point, the latest value is read from the local cache and merged, thereby achieving data consistency guarantees based on cache collaboration. Moreover, single-threaded concurrency elimination ensures that the same register is not written to by multiple instructions simultaneously at the architectural level. Finally, a post-write readback verification mechanism ensures that the write operation is truly effective, synchronizing the verified value to the cache and keeping the cache consistent with the device state.
[0092] Therefore, by using multi-point shared register technology and multi-layer data consistency guarantee mechanism, the resource utilization and data consistency problems of Modbus protocol in industrial IoT applications are effectively solved, providing an efficient and reliable data acquisition solution for scenarios such as building intelligent control.
[0093] The above describes a data processing method for a multi-point shared register provided by the embodiments of this application. The following will describe the apparatus for performing the above-described data processing method for a multi-point shared register.
[0094] See Figure 5 , Figure 5 This is a schematic diagram of a data processing device for a multi-point shared register provided in an embodiment of this application. Figure 5 As shown in the figure, an embodiment of this application provides a data processing apparatus for a multi-point shared register, comprising:
[0095] The read module 401 is used to read the sixteen-bit integer values of each register in the Modbus slave device. Each register is occupied by at least one logical point, and each logical point is pre-configured with position occupancy information.
[0096] The conversion and caching module 402 is used to convert the sixteen-bit integer values of each register into corresponding binary strings, and extract the binary strings of each logical point from the binary strings of the occupied registers according to the position occupancy information of each logical point; convert the binary strings of each logical point into corresponding decimal values, and store the decimal values of each logical point in the local cache.
[0097] In one possible implementation, the data processing apparatus for the multi-point bit shared register described above further includes:
[0098] The instruction receiving module is used to receive write instructions in a single-threaded serial processing manner. The write command contains the new decimal value of the target logical point to be written.
[0099] The conversion and write module is used to determine the target register occupied by the target logical bit, and obtain the decimal values of each shared logical point bit under the target logical point in the target register from the current cache; convert the new decimal value of the target logical point bit and the decimal value of each shared logical point bit into the corresponding binary string respectively; according to the position occupancy information of the target logical point bit and each shared logical point bit, concatenate the binary strings of the target logical point bit and each shared logical point bit to obtain the new binary string of the target register; convert the new binary string of the target register into a new 16-bit integer value, and write the new 16-bit integer value of the target register into the target register.
[0100] In one possible implementation, the above conversion and write module is also used for:
[0101] The system performs numerical verification on the new decimal value of the target logical point and the decimal values of each shared logical point, and performs bit verification on the binary strings of the target logical point and each shared logical point. If the target logical point and each shared logical point pass the numerical and bit verification, the system performs the step of concatenating the binary strings of the target logical point and each shared logical point according to their position occupancy information to obtain the new binary string of the target register.
[0102] In one possible implementation, the data processing apparatus for the aforementioned multi-point bit shared register further includes:
[0103] The readback and synchronization module is used to wait for a preset time after writing to the target register, and then read back the target register to determine the writing result of the target logical point; if the writing result of the target logical point is determined to be valid, the new decimal value of the target logical point is synchronized to the local cache.
[0104] In one possible implementation, the readback and synchronization module, used to determine the write result of the target logical point bit by reading back the target register, is specifically used for:
[0105] The process involves: rereading the 16-bit integer value of the target register; converting the reread 16-bit integer value back into the corresponding binary string; extracting the binary string representing the target logical point from the re-converted binary string according to the position occupancy information of the target logical point; converting the re-extracted binary string back into the corresponding decimal value; comparing the re-converted decimal value with the new decimal value of the target logical point; if the re-converted decimal value matches the new decimal value of the target logical point, the write result to the target logical point is considered valid; otherwise, the write result to the target logical point is considered invalid.
[0106] In one possible implementation, the readback and synchronization module is also used for:
[0107] If the write result of the target logical point is determined to be invalid, record the cumulative number of invalid entries and return to execute the step of writing the new 16-bit integer value of the target register to the target register. Continue until the cumulative number of invalid entries reaches the corresponding threshold, and then generate the corresponding log information.
[0108] It should be noted that the detailed functions of each module in the embodiments of this application can be found in the corresponding disclosure of the above-mentioned data processing method embodiments for multi-point shared registers, and will not be repeated here.
[0109] This application also provides an electronic device in its embodiments. See also... Figure 6 , Figure 6 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. The electronic device in this embodiment may include, but is not limited to, fixed terminals such as mobile phones, laptops, PDAs (personal digital assistants), PADs (tablet computers), desktop computers, etc. Figure 6 The electronic device shown is merely an example and should not impose any limitation on the functionality and scope of use of the embodiments of this application.
[0110] like Figure 6As shown, the electronic device may include a processing unit (e.g., a central processing unit, a graphics processing unit, etc.) 501, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 502 or a program loaded from a storage device 508 into a random access memory (RAM) 503. When the electronic device is powered on, the RAM 503 also stores various programs and data required for the operation of the electronic device. The processing unit 501, ROM 502, and RAM 503 are interconnected via a bus 504. An input / output (I / O) interface 505 is also connected to the bus 504.
[0111] Typically, the following devices can be connected to I / O interface 505: input devices 506 including, for example, touchscreens, touchpads, keyboards, mice, cameras, microphones, accelerometers, gyroscopes, etc.; output devices 507 including, for example, liquid crystal displays (LCDs), speakers, vibrators, etc.; storage devices 508 including, for example, memory cards, hard drives, etc.; and communication devices 509. Communication device 509 allows electronic devices to communicate wirelessly or wiredly with other devices to exchange data. Although Figure 6 Electronic devices with various devices are shown, but it should be understood that it is not required to implement or have all of the devices shown. More or fewer devices may be implemented or have alternatively.
[0112] This application also provides a computer program product including computer-readable instructions, which, when executed on an electronic device, cause the electronic device to implement any of the multi-point shared register data processing methods provided in this application.
[0113] This application also provides a computer-readable storage medium that carries one or more computer programs. When the one or more computer programs are executed by an electronic device, the electronic device can implement any of the multi-point shared register data processing methods provided in this application.
[0114] It should also be noted that the device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. In addition, in the device embodiment drawings provided in this application, the connection relationship between modules indicates that they have a communication connection, which can be implemented as one or more communication buses or signal lines.
[0115] Through the above description of the embodiments, those skilled in the art can clearly understand that this application can be implemented by means of software plus necessary general-purpose hardware, or it can be implemented by special-purpose hardware including application-specific integrated circuits, special-purpose CPUs, special-purpose memory, special-purpose components, etc. Generally, any function performed by a computer program can be easily implemented by corresponding hardware, and the specific hardware structure used to implement the same function can also be diverse, such as analog circuits, digital circuits, or special-purpose circuits. However, for this application, software program implementation is more often the preferred implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a readable storage medium, such as a computer floppy disk, USB flash drive, mobile hard disk, ROM, RAM, magnetic disk, or optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, training equipment, or network device, etc.) to execute the methods described in the various embodiments of this application.
[0116] In the above embodiments, implementation can be achieved, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented in software, it can be implemented, in whole or in part, as a computer program product.
[0117] The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions may be transmitted from one website, computer, training device, or data center to another website, computer, training device, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium may be any available medium that a computer can store or a data storage device such as a training device or data center that integrates one or more available media. The available media may be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., DVDs), or semiconductor media (e.g., solid-state drives (SSDs)).
Claims
1. A data processing method for a multi-point shared register, characterized in that, The data processing method for the multi-point shared register includes: Read the 16-bit integer values of each register in the Modbus slave device. Each register is occupied by at least one logical point, and each logical point is pre-configured with position occupancy information. The sixteen-bit integer values of each register are converted into corresponding binary strings, and the binary strings of each register are extracted from the binary strings of the occupied registers according to the position occupancy information of each logical point. Convert the binary string of each logical point to the corresponding decimal value, and store the decimal value of each logical point in the local cache.
2. The data processing method for a multi-point shared register according to claim 1, characterized in that, The data processing method for the multi-point shared register also includes: The write command is received in a single-threaded serial processing manner, and the write command contains a new decimal value of the target logical point to be written. Determine the target register occupied by the target logic bit, and obtain the decimal values of each shared logic point bit of the target logic point under the target register from the current cache; Convert the new decimal value of the target logical point and the decimal value of each shared logical point into the corresponding binary string; According to the position occupancy information of the target logical point and each shared logical point, the binary strings of the target logical point and each shared logical point are concatenated to obtain a new binary string of the target register; The new binary string in the target register is converted into a new 16-bit integer value, and the new 16-bit integer value in the target register is written into the target register.
3. The data processing method for a multi-point shared register according to claim 2, characterized in that, The data processing method for the multi-point shared register also includes: The new decimal value of the target logic point and the decimal value of each shared logic point are numerically verified, and the binary string of the target logic point and each shared logic point is bit-verified. If the target logical point and each shared logical point pass the numerical verification and bit verification, the step of concatenating the binary strings of the target logical point and each shared logical point according to the position occupancy information of the target logical point and each shared logical point to obtain the new binary string of the target register is performed.
4. The data processing method for a multi-point shared register according to claim 2, characterized in that, The data processing method for the multi-point shared register also includes: After writing to the target register, wait for a preset time, and determine the writing result of the target logical point by reading back the target register; If the write result of the target logical point is determined to be valid, the new decimal value of the target logical point is synchronized to the local cache.
5. The data processing method for a multi-point shared register according to claim 4, characterized in that, The step of determining the write result of the target logical point bit by reading back the target register includes: Reread the sixteen-bit integer value of the target register; The reread 16-bit integer value is converted back into the corresponding binary string, and the binary string of the target logical point is extracted from the reconverted binary string according to the position occupancy information of the target logical point. The re-extracted binary string is converted back into the corresponding decimal value, and the converted decimal value is compared with the new decimal value of the target logical point. If the reconverted decimal value is the same as the new decimal value of the target logical point, the write result of the target logical point is determined to be valid. If the reconverted decimal value is different from the new decimal value of the target logic point, the write result of the target logic point is determined to be invalid.
6. The data processing method for a multi-point shared register according to claim 4, characterized in that, The data processing method for the multi-point shared register also includes: If the write result of the target logical point is determined to be invalid, the cumulative number of invalid entries is recorded, and the process of writing the new 16-bit integer value of the target register to the target register is returned to continue until the cumulative number of invalid entries reaches the corresponding threshold, at which point the corresponding log information is generated.
7. A data processing apparatus for a multi-point shared register, characterized in that, The data processing device for the multi-point shared register includes: The read module is used to read the sixteen-bit integer values of each register in the Modbus slave device. Each register is occupied by at least one logical point, and each logical point is pre-configured with position occupancy information. The conversion and caching module is used to convert the 16-bit integer values of each register into corresponding binary strings, and extract the binary strings of each logical point from the binary strings of the occupied registers according to the position occupancy information of each logical point; convert the binary strings of each logical point into corresponding decimal values, and store the decimal values of each logical point in the local cache.
8. A computer program product, characterized in that, It includes computer-readable instructions that, when executed on an electronic device, cause the electronic device to implement the data processing method for a multi-point shared register as described in any one of claims 1 to 6.
9. An electronic device, characterized in that, It includes at least one processor and a memory connected to the processor, wherein: The memory is used to store computer programs; The processor is used to execute the computer program to enable the electronic device to implement the data processing method of the multi-point shared register as described in any one of claims 1 to 6.
10. A computer storage medium, characterized in that, The storage medium carries one or more computer programs that, when executed by an electronic device, enable the electronic device to implement the data processing method for a multi-point shared register as described in any one of claims 1 to 6.