A multi-channel neural signal compression circuit device, control method and storage device

Abstract

The application relates to a multi-channel neural signal compression circuit device, a control method and a storage device, and relates to the technical field of neural signal processing. The device comprises an analog-digital front-end group, a data packer and a data transmission baseband module. The analog-digital front-end group comprises N channel processing units arranged in parallel. Each channel processing unit is integrated with an analog conditioning circuit, an analog-digital converter and an adaptive differential compression module. The adaptive differential compression module is directly coupled to the digital output end of the corresponding analog-digital converter of the channel, and compression processing is completed in the local data path of the channel. By integrating the adaptive differential compression module in the channel processing unit, efficient compression is realized by utilizing the time domain correlation of neural signals. Meanwhile, the data transmission is optimized by adopting a three-state bus structure, the data transmission load and system power consumption are significantly reduced, and low-power wireless transmission of high-throughput neural signals is realized.

Description

Technical Field

[0001] This invention relates to the fields of neural signal processing and low-power integrated circuit design, specifically to a multi-channel neural signal compression circuit device, control method, and storage device. Background Technology

[0002] In high-throughput neuroscience research and free-behavioral animal experiments, real-time acquisition and wireless transmission of multi-channel, broadband neural signals have become core requirements for neural interface systems. Current mainstream technologies generally adopt a "sample first, transmit later" architecture, which involves synchronously or time-divisionally sampling N-channel neural signals using a high-resolution analog-to-digital converter (such as a 10-bit ADC) to generate raw digital data streams. These streams are then aggregated to a data packaging module via an on-chip bus and finally transmitted over long distances via a wireless baseband (such as a custom RF or Bluetooth). To alleviate the resulting high data rate pressure, existing systems often incorporate on-chip data compression. Typical methods include sparse reconstruction based on compressive sensing, mathematical transform coding such as wavelet or discrete cosine transform (DWT / DCT), event-driven compression centered on spike detection, and lightweight lossless / lossy compression strategies based on differential or entropy coding. Some of these solutions have already been integrated into commercial or research-grade neural recording chips, demonstrating engineering feasibility and algorithmic versatility.

[0003] However, the aforementioned existing technologies still face inherent contradictions when addressing embedded neural interface scenarios requiring ultra-low power consumption, high channel density, and meter-level line-of-sight wireless transmission: While compressed sensing and deep learning methods possess high theoretical compression ratios, they rely on iterative computations and numerous multiply-accumulate operations, resulting in high hardware complexity and power consumption, making stable operation under power constraints below 10mW; mathematical transformation algorithms are limited by floating-point operations and matrix processing requirements, significantly increasing area and power consumption in 65nm and below CMOS processes; and peak detection relying solely on fixed thresholds or... Simple differential coding schemes, while concise in structure, lack adaptive adjustment capabilities. In real-world scenarios with wide dynamic ranges of neural signals, significant baseline drift, and frequent artifact interference, they are prone to slope overflow, prediction inaccuracies, and quantization error accumulation, leading to decreased signal fidelity and loss of low-frequency components such as local field potentials (LFP) after decoding. Furthermore, traditional centralized data stream architectures require all raw sampled data to be polled and transmitted to the central compression unit via a shared bus (such as APB), causing on-chip communication power consumption to increase approximately linearly with the number of channels, severely restricting the system's energy efficiency density and scalability. Summary of the Invention

[0004] This invention relates to a multi-channel neural signal compression circuit device, control method, and storage device. The technical problem it addresses is that in neural interface and neuroscience research, the acquisition and wireless transmission of high-throughput neural signals place extremely high demands on system bandwidth, power consumption, and integration. Several technologies have attempted to effectively reduce data transmission rates through data compression, but these generally suffer from problems such as instability, high power consumption, and implementation complexity.

[0005] How can we achieve efficient compression of approximately 60% of the original data volume under high channel density (e.g., 256 channels) while ensuring the complete preservation of key features of neural signals (such as spike waveforms and local field potential LFP components), and at the same time significantly reduce on-chip data transmission power consumption and wireless transmission power consumption, to meet the requirements of low-power, high-reliability wireless neural interfaces in scenarios involving freely moving experimental animals with a line-of-sight distance of more than 5 meters and a total system power consumption of less than 10mW?

[0006] To achieve the above objectives, this application provides the following technical solution:

[0007] A multi-channel neural signal compression circuit device includes an analog-to-digital front-end group, an adaptive differential compression module, a tri-state bus, a data packetizer, and a data transmission baseband module;

[0008] The modular front-end group is used to receive and process N-channel neural signals;

[0009] The data packer is used to format the processed multi-channel data according to specified rules;

[0010] The data transmission baseband module is used for wireless transmission of formatted data; and

[0011] The analog-to-digital front-end group comprises N parallel channel processing units. Each channel processing unit integrates an analog conditioning circuit, an analog-to-digital converter, and an adaptive differential compression module.

[0012] The adaptive differential compression module is directly cascaded to the digital output of the analog-to-digital converter corresponding to the channel. The adaptive differential compression module is configured to perform differential operation based on the predicted value of the previous cycle before the original sampled data leaves the physical boundary of the channel. It obtains the step size extension parameter by looking up the table, completes nonlinear quantization and prediction value update by displacement and logic concatenation, and outputs 4-bit fixed-length compressed encoded data.

[0013] Optionally, the device further includes a tri-state bus, which is a dual-track structure, including a 4-bit high-speed data bus A for polling and transmitting compressed encoded data of each channel, and a 16-bit low-speed status bus B for synchronously transmitting predicted values ​​or raw sampled data of the corresponding channel.

[0014] Optionally, the tri-state bus adopts a multi-driver shared architecture, with each driver connected to the compression encoding output of a different channel processing unit, and its enable control signal generated by the same master clock through a precision delay chain, and the enable windows of adjacent drivers are strictly staggered on the time axis; the data packetizer is connected to the tri-state bus, receives and encapsulates data streams from bus A and bus B, and outputs them to the data transmission baseband module.

[0015] Optionally, the number of modular front-end groups mounted in the tri-state bus is M, where M is a positive integer; bus A and bus B work together, after bus A completes the polling transmission of all M×N channel compressed encoded data, bus B synchronously completes the one-time low-speed transmission of the predicted value or original sampled data of the corresponding channel.

[0016] Optionally, the analog conditioning circuit is a programmable low-noise amplifier, the analog-to-digital converter is a time-division multiplexed analog-to-digital converter, and the adaptive differential compression module is physically deployed after the digital output of the analog-to-digital converter and before the path of the data leaving the physical boundary of the corresponding channel processing unit.

[0017] Optionally, the adaptive differential compression module does not include a multiplier unit. Its differential operation, step size parameter acquisition, nonlinear quantization, and prediction value update are all implemented by combinational logic circuits, specifically including a 10-bit subtractor, a step size lookup table, a right shift and truncation circuit, a splicing logic unit, and a left shifter. All operations are completed based on shifting, logical operations, and table lookup.

[0018] Optionally, the drive enable control circuit of the tri-state bus includes a precision delay chain driven by the same master clock signal. The precision delay chain is composed of four cascaded delay units with consistent structure, used to generate multiple enable control signals with sequentially staggered phases, so that the effective drive windows of adjacent drivers are strictly separated on the time axis, and at most one driver is in the enabled drive state at any time.

[0019] Optionally, the multi-channel neural signal compression circuit device is integrated into the chip, manufactured using a low-power process, with an overall power consumption of less than 10mW, and the power consumption of a single-channel adaptive differential compression module is 2.5–3.5nW.

[0020] Optionally, the prediction model used by the adaptive differential compression module is a linear predictor, a nonlinear predictor, a lightweight recurrent neural network adaptive predictor, or a combination thereof, based on the value of the previous cycle. The output of the prediction model is used to perform differential operations with the current original sampled data, and the prediction process does not depend on external training data, and parameter updates are completed online in real time.

[0021] A control method for a multi-channel neural signal compression circuit device, the circuit device comprising an analog-to-digital front-end group, a tri-state bus, a data packetizer, and a data transmission baseband module, wherein the analog-to-digital front-end group includes N parallel channel processing units, each channel processing unit integrating an analog conditioning circuit, an analog-to-digital converter, and an adaptive differential compression module; the tri-state bus is a dual-rail structure, including a 4-bit high-speed data bus A and a 16-bit low-speed state bus B; the data packetizer is connected to the tri-state bus, and the data transmission baseband module is connected to the data packetizer; characterized in that the control method performs the following steps:

[0022] The N-channel neural signals were subjected to analog conditioning and analog-to-digital conversion to obtain N channels of 10-bit raw sampled data.

[0023] Before each original sampled data leaves the local data path of the corresponding channel processing unit, the adaptive differential compression module built into the channel performs differential operation based on the predicted value of the previous cycle, obtains the step size expansion parameter by looking up the table, generates 4-bit compressed encoded data by right shifting and truncating, and completes the prediction value update by splicing and left shifting.

[0024] The 4-bit high-speed data bus A of the three-state bus is controlled to enable the driver of each channel processing unit in a preset polling order, and the 4-bit compressed encoded data output by each channel is transmitted to the data packetizer channel by channel.

[0025] After the bus A completes the polling transmission of all M×N channel compressed encoded data, the 16-bit low-speed state bus B, which controls the tri-state bus, synchronously loads and transmits the predicted value or original sampled data of the corresponding channel.

[0026] Optionally, the step of updating the predicted value by the adaptive differential compression module specifically includes:

[0027] Calculate the difference between the current raw sampled data raw and the predicted value pred from the previous period, and the difference is expressed as dt = raw − pred;

[0028] The difference is compressed, and the compressed data is represented in a fixed-length format, wherein the encoded data is code = dt >> step_ext;

[0029] Calculate the predicted value for the next sampling point based on the encoded data;

[0030] Here, step_ext is the step size value calculated in the previous cycle; the step size value for the current cycle is updated by consulting the step size lookup table.

[0031] Optionally, in the step of transmitting data according to a preset polling order on bus A, the polling order is to traverse each modular front-end group according to channel number 0 to N−1, and then execute the process in a loop according to modular front-end group number 0 to M−1, forming an M×N dimensional polling sequence.

[0032] Optionally, in the step of synchronous loading of bus B, the parallel transmission of the predicted values ​​pred or raw sampled data corresponding to all channels in the current polling sequence is completed in a low-speed manner.

[0033] Optionally, the adaptive differential compression module performs differential operations, step-size lookup, nonlinear quantization, and prediction value updates without calling multiplier instructions or hardware units. All operations are completed collaboratively by a 10-bit subtractor, a read-only memory lookup table, a barrel right shifter, a logic concatenator, and a barrel left shifter.

[0034] Optionally, in the control of the tri-state bus, a phase-spacing control signal is introduced into the drive enable control circuit to keep the timing of multiple drivers effectively staggered, thereby preventing any two or more drivers from being enabled at the same time.

[0035] Optionally, the data streams from bus A and bus B are received through the data packetizer, and frame headers, frame sequence numbers, and check fields are added to encapsulate them into wireless transmission frames.

[0036] The encapsulated wireless transmission frame is sent to the data transmission baseband module, and after modulation and power amplification, it is transmitted wirelessly.

[0037] Optionally, the adaptive differential compression module is integrated into the chip, with an overall power consumption of less than 10mW; the power consumption of a single-channel adaptive differential compression module is 2.5–3.5nW, and the power consumption value is fed back in real time through the on-chip current monitoring circuit and used for dynamic power gating adjustment.

[0038] Optionally, the prediction model used by the adaptive differential compression module can be switched online to a linear predictor, a nonlinear predictor, a lightweight long short-term memory network predictor, or a weighted fusion predictor of both. The switching instruction is received by the on-chip configuration register. The predictor weight parameters are automatically updated based on the error statistics of the most recent 100 sampling points before the start of each polling cycle. The update process does not interrupt the data stream transmission.

[0039] A storage device includes a storage controller that performs data processing based on the control method described above.

[0040] An electronic device includes: a memory for storing a computer program; and a processor for executing the computer program to implement the steps of the control method described above.

[0041] A computer-readable storage medium storing a computer program, wherein the computer program, when executed by a processor, implements the steps of the above-described control method.

[0042] Compared with existing technologies, this application has at least the following beneficial effects: By achieving coordinated optimization of compression and communication at the architectural level, this invention not only improves the data compression rate and reduces communication bandwidth per unit signal precision, but also achieves order-of-magnitude energy savings in system power consumption. Its solution has significant advantages in scalability, power consumption control, and high signal fidelity, making it more suitable for high-density, low-power neural interface system applications than existing technologies. Attached Figure Description

[0043] Figure 1 It is a typical neural recording architecture;

[0044] Figure 2 This is a system block diagram of this application;

[0045] Figure 3 This is a schematic diagram of the adaptive differential compression circuit module of this application;

[0046] Figure 4 This is a schematic diagram of the simulated front-end group of this application;

[0047] Figure 5 This is a schematic diagram of the tri-state bus of this application;

[0048] Figure 6 This is a schematic diagram of the timing coordination between bus A and bus B in the tri-state bus of this application;

[0049] Figure 7 This is a schematic diagram of the multi-drive circuit and waveforms of this application; Detailed Implementation

[0050] The technical solutions of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. The components of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely represents selected embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application. It should be noted that similar reference numerals and letters in the following drawings indicate similar items; therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings. Furthermore, in the description of this application, the terms "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0051] Example 1

[0052] In neuroscience research using freely moving laboratory animals, high temporal and spatial resolution neural signal recording must balance low power consumption, high throughput, and reliable wireless transmission. In existing technologies, the raw data transmission rate in 256-channel simultaneous acquisition scenarios often exceeds 75 Mbps. Achieving stable wireless transmission at a line-of-sight distance greater than 5 meters while keeping the total system power consumption below 10 mW presents a severe challenge due to the triple constraints of bandwidth, power consumption, and hardware complexity. In typical architectures, direct transmission of raw data places excessive demands on the RF link and battery life. While on-chip compression can reduce the load, existing compression methods generally suffer from drawbacks such as complex hardware implementation (e.g., deep learning, wavelet transform), weak dynamic adaptability (e.g., slope overflow in fixed-length differential coding), or sacrifice of critical information integrity (e.g., loss of LFP components and peak waveforms in peak detection).

[0053] The inventive concept of this application lies in moving the data compression operation forward to the local data path after analog-to-digital conversion, that is, completing all compression operations within a single channel processing unit before the original sampled data leaves the local data path of that channel; through a four-stage pipelined processing chain of on-site compression—nearby transmission—instantaneous packaging—directional transmission, redundant handling of multi-channel raw data on the chip-level bus is eliminated, fundamentally reducing on-chip communication power consumption and back-end baseband bandwidth pressure. This architecture uses 4-bit fixed-length encoding as the output target, and while ensuring deterministic timing and low logic latency, relies on the inherent temporal correlation of neural signals to construct a lightweight adaptive differential compression mechanism that requires no multipliers and relies only on table lookup and bit operations, thereby supporting the implementation of ultra-low power (nW-level single channel), high integration, and high robustness (resistant to baseline drift and amplitude abrupt changes) neural interface systems.

[0054] Based on the above issues, please refer to Figure 2 As shown, this application provides a multi-channel neural signal compression circuit device, including an analog-to-digital front-end group, a data packetizer, and a data transmission baseband module.

[0055] The analog-to-digital front-end is used to receive and process N-channel neural signals;

[0056] The data packer is used to format processed multichannel data according to specified rules;

[0057] The data transmission baseband module is used to wirelessly transmit formatted data; and the analog-to-digital front-end group contains N parallel channel processing units, each integrating analog conditioning circuitry, an analog-to-digital converter, and an adaptive differential compression module.

[0058] The adaptive differential compression module is directly coupled to the digital output of the analog-to-digital converter corresponding to the channel. The adaptive differential compression module is configured to perform differential operation based on the predicted value of the previous cycle before the original sampled data leaves the physical boundary of the channel. It obtains the step size extension parameter by looking up the table, completes nonlinear quantization and prediction value update by displacement and logic concatenation, and outputs 4-bit fixed-length compressed encoded data.

[0059] The analog-to-digital front-end (ADC) consists of an array-type signal preprocessing subsystem composed of N identical, parallel-deployed channel processing units. Its overall function is to sequentially perform gain adjustment, noise suppression, anti-aliasing filtering, and analog-to-digital conversion on the N analog neural electrical signals from the external electrode array, forming N 10-bit digital sampling streams. The physical boundary of the ADC is defined by independent wiring areas and isolation rings allocated to each channel in the chip layout, ensuring that the signal paths of each channel are electrically and physically isolated from each other. Its role is to provide a high signal-to-noise ratio, low latency, and timing-aligned digital input source for subsequent compression. Through the tight coupling integration of the ADC and the adaptive differential compression module, the 10-bit raw sampling data enters the compression process immediately after generation without any cross-channel or cross-module bus transmission, thereby avoiding additional power consumption and timing uncertainties introduced by bus driving, signal reflection, and crosstalk.

[0060] The data packetizer is a streaming protocol encapsulation module. Its input port is connected to the data path on the output side of the analog-to-digital front-end group, receiving the compressed multi-channel 4-bit encoded stream. Its function is to perform time alignment, frame header addition, timestamp embedding, and cyclic redundancy check (CRC) field calculation on compressed data from different channels, and finally organize it into data packets that meet the requirements of wireless baseband modulation according to a fixed-length or variable-length frame structure. The data packetizer does not participate in signal compression or predictive modeling, but only undertakes the tasks of format standardization and fault tolerance enhancement.

[0061] The data transmission baseband module is a wireless physical layer transmission circuit. Its input terminal receives the encapsulated frames output by the data packetizer and performs modulation, up-conversion, power amplification, and antenna matching drive. Its function is to convert digital compressed frames into radio frequency signals that conform to the propagation characteristics of wireless channels. The packet error rate performance of this module is lower than that under the conditions of free space line-of-sight greater than 5 meters and unobstructed direct path. Its design is compatible with various radio frequency front-end topologies, such as a fully integrated transmit chain integrating a voltage-controlled oscillator (VCO) and a phase-locked loop (PLL), or a semi-integrated scheme with external discrete PAs and filters. This application does not impose any special limitations on this.

[0062] The analog-to-digital front-end group contains N parallel channel processing units. Each channel processing unit integrates analog conditioning circuitry, an analog-to-digital converter, and an adaptive differential compression module. Each channel processing unit is a minimum functional closed loop consisting of analog input pins, a programmable low-noise amplifier (LNA), an anti-aliasing filter (AAF), a time-division multiplexed successive approximation register analog-to-digital converter (SAR ADC), and an adaptive differential compression module connected in series. Its physical boundary is defined by the metal shielding layer and power isolation ring defined around the unit in the chip layout. The purpose of this structure is to achieve localization of the entire sampling-compression-output process, preventing the original data from flowing out of the local data path. N is a positive integer and can be set to 8, 16, 32, 64, or 128 according to the application scenario requirements. For example, 32 channels are used for recording local field potentials in the mouse hippocampus, or 128 channels are used for multi-point synchronous monitoring of the macaque cortex. This application embodiment does not make any special limitation on this.

[0063] like Figure 3As shown, the adaptive differential compression module is directly coupled to the digital output of the corresponding analog-to-digital converter of the channel. The module is configured to perform differential operations based on the previous cycle's predicted value before the raw sampled data leaves the physical boundary of the channel. It then obtains the step size extension parameter through a lookup table, completes nonlinear quantization and predictive value updates through shifting and logical concatenation, and outputs 4-bit fixed-length compressed encoded data. The input to this adaptive differential compression module is 10 bits of raw sampled data (raw) and 10 bits of the previous cycle's predicted value (pred), and the output is 4 bits of fixed-length encoded code and the updated 10-bit predicted value (pred_new). Its functional meaning is... Leveraging the strong correlation between adjacent sampling points of neural signals, the dynamic range of the original data is compressed to a 4-bit representation. Simultaneously, an adaptive step-size mechanism addresses amplitude abrupt changes and baseline drift. Its direct coupling with the analog-to-digital converter (ADC) means there are no intermediate registers, FIFOs, or bus buffers between them; the ADC digital output bus is directly connected to the compression module's input register. Its operational constraints before the original sampled data leaves the channel's physical boundary mean that the module's timing path is entirely within the layout area of ​​the same channel processing unit, and all signal traces do not cross the unit's metal isolation band. The module's nonlinear quantization process specifically includes: calculating the difference dt = raw − pred; and looking up the step-size lookup table (LUT) to obtain the current step-size extension parameter step_ext.

[0064] Perform a right-shift truncation operation: code = dt >> step_ext, resulting in a 4-bit unsigned code; then update the predicted value through concatenation and left shift.

[0065] pred_new = {code, 1′b1} << (step_ext[4:2] − 1);

[0066] The effective value range of step_ext is [min_step, 31], and min_step is a configurable parameter with a value of 0, 4, 8 or 12. This module does not contain any multiplier unit. All operations are completed by a 10-bit subtractor, a read-only memory (ROM) lookup table, a barrel right shifter, a logic splicer, and a barrel left shifter. Its implementation is a fully custom digital circuit using low-power CMOS technology, or an RTL netlist generated by standard cell library synthesis. This application does not impose any special limitations on this.

[0067] See Figure 4 The proposed architecture effectively reduces bus data transmission power consumption by integrating an adaptive differential compression mechanism within the distributed compressor. The design incorporates tri-state bus technology, such as... Figure 5As shown, data is transmitted to the data packetizer via a multi-driver data stream, avoiding frequent multiplexer polling operations and further improving system efficiency. This design employs a dual-bus architecture: a 4-bit bus A enables high-speed access to the compressed channel output, while a 16-bit bus B supports flexible, configurable transmission of raw or predicted data. The number of analog front-end groups mounted on this tri-state bus is M, where M is an integer. This invention utilizes distributed analog front-end compression and tri-state bus collaborative optimization to optimize power consumption. By processing data internally within the analog front-end, on-chip communication power consumption is reduced. Distributed processors can reduce communication power consumption by 53%. Compared to the APB bus, the tri-state bus reduces transmission power consumption by 96%.

[0068] In a tri-state bus system, a multi-driver architecture is typically used to achieve shared access to the bus. The timing diagram for the coordination between bus A and bus B in a tri-state bus is shown below. Figure 6 As shown in the diagram. Bus A is used to transmit compressed data from each channel and polls the designated channels of each analog front-end group in a preset order. After completing the transmission of the designated channel of the current analog front-end group, it switches to the next channel to continue polling until the data transmission of M×N channels is completed. Each polling cycle is sequential, continuously transferring data from each analog front-end group to the data packer. Bus B is used to continuously transmit the predicted value (pred) or raw data (raw) of the designated channel at a low speed.

[0069] Under ideal operating conditions, only one driver is allowed to be enabled at any given time, thus avoiding drive conflicts. However, due to non-ideal factors such as phase noise and clock jitter, the timing of the enable control signals of different drivers may overlap, causing multiple drivers to drive the bus at the same time. When some drivers output high levels while others output low levels, short circuits can easily form on the bus nodes, leading to transient current surges, significantly increasing chip power consumption, and even adversely affecting reliability.

[0070] To address the aforementioned technical issues, this solution proposes a tri-state bus control method with an anti-clock overlap mechanism. This method introduces phase-shifted control signals into the driver enable control circuit, ensuring effective timing separation between multiple drivers. This prevents any two or more drivers from being enabled simultaneously, significantly reducing short-circuit current caused by signal overlap and improving system power efficiency and stability. Figure 7 The diagram illustrates the multi-driver structure used in an embodiment of the present invention and its corresponding drive control waveform. From... Figure 7As can be seen, by introducing an anti-clock strategy, the enable time windows of each driver are separated from each other. Even if there are some non-ideal factors such as phase noise and clock jitter, the generation of short circuit can still be effectively prevented.

[0071] The core innovation of this application lies in constructing a three-level energy efficiency optimization architecture of compression within the local data path, dual-track heterogeneous bus collaboration, and baseband streaming encapsulation: by embedding the compression engine inside each channel processing unit, the entire process of differential-table lookup-shifting-splitting-updating is immediately started at the ADC digital output, so that 60% of the data volume is reduced without the 10-bit original data leaving the domain; this local compression mechanism forms a tightly coupled closed loop with the subsequent tri-state bus (see Embodiment 2 below) and data packer, so that the compressed 4-bit code can directly drive bus A, greatly reducing the drive load and switching power consumption; and the 4-bit fixed-length output characteristic ensures the determinism of bus access timing, providing a physical basis for multi-driver time-out enable under precision delay chain control.

[0072] The working process and principle of this application are as follows: After the external N-channel neural electrical signal is coupled into the chip via electrodes, it first enters the processing units of each channel in the analog-to-digital front-end group: the analog conditioning circuit performs programmable gain adjustment and low-noise amplification of the signal; the time-division multiplexed ADC performs analog-to-digital conversion on the amplified signal at a sampling rate of 10 kHz, and outputs a 10-bit digital sample value; this 10-bit value is immediately sent to the adaptive differential compression module built into the same channel. The module calculates the difference dt based on the built-in prediction value pred, looks up the table to obtain step_ext, performs right shift truncation to obtain a 4-bit code, and updates pred_new synchronously; the entire compression process is completed within a single clock cycle, and all signal paths do not cross the physical boundary of the channel; the compressed 4-bit code is transmitted to the data packetizer via the tri-state bus A polling; the data packetizer adds a frame header, timestamp, and CRC check field to the received multi-channel encoded stream and encapsulates it into a wireless transmission frame; this frame is sent to the data transmission baseband module, and the on-chip antenna completes the wireless transmission.

[0073] The adaptive differential compression module mentioned in this invention reduces the data rate while preserving the signal in high-density recording, achieving a 60% compression of the 10-bit ADC output. Furthermore, the multiplier-free operation, based on a 65nm process, achieves ultra-low power consumption of approximately 3nW / channel (approximately 0.1nW / kHz).

[0074] Through the above technical solution, this application achieves the following beneficial effects: Since the adaptive differential compression module is directly coupled to the digital output of the analog-to-digital converter and compression is completed before the original sampled data leaves the physical boundary of the channel, the transmission of 10-bit original data over long distances on the on-chip bus is avoided, reducing on-chip communication power consumption and signal integrity risks; Since the compression process is based on lookup tables and shift operations rather than multiplication, the combinational logic depth and switching power consumption are significantly reduced, lowering single-channel power consumption to the 2.5–3.5 nW range, meeting the ultra-low power consumption constraints of implantable neural interfaces; Since the output is a 4-bit fixed-length code, it provides timing guarantees for the subsequent deterministic polling scheduling of the three-state bus and the streaming frame encapsulation of the data packetizer, improving system real-time performance and wireless transmission reliability; Since the step size extension parameter is dynamically updated through a lookup table, it can adapt to changes in neural signal amplitude, suppressing slope overflow while retaining high-frequency components of the spike signal, thus improving signal reconstruction fidelity.

[0075] This invention proposes an adaptive differential compression module for high-throughput neural signal recording and a distributed analog front-end internal compression cooperative three-state bus mechanism, demonstrating significant advantages in data compression efficiency and system energy efficiency. Through comparison and reasoning analysis of specific technical solutions, this invention mainly possesses the following technical advantages and corresponding effects:

[0076] 1. Adaptive Differential Compression Module: Improves compression efficiency and ensures high signal fidelity.

[0077] Existing high-density neural interfaces or EEG acquisition systems often face the challenges of massive data volumes and high transmission and storage pressures. Traditional compression methods often rely on computationally complex and power-intensive algorithms (such as multiplication, DWT, wavelet transform, etc.), making them difficult to deploy in resource-constrained implantable chips.

[0078] In contrast, the adaptive differential compression module proposed in this invention employs a design that eliminates the need for high-power multiplication operations, achieving a 60% compression rate for the 10-bit ADC output signal. This compression strategy not only significantly reduces the data output rate and alleviates the load on the back-end data link, but also ensures that key signal features are preserved through differential and adaptive error adjustment, meeting the recognition and interpretation requirements of neural signal processing.

[0079] Meanwhile, this module is implemented using CMOS technology, with a single-channel power consumption of approximately 3nW (equivalent to 0.1nW / kHz), demonstrating extremely high energy efficiency. This is particularly crucial because system power consumption is often the core bottleneck limiting the deployment and lifespan of wearable and implantable systems.

[0080] Conclusion: After processing by this compression module, the system can reduce communication bandwidth requirements and overall power consumption without sacrificing data integrity, which is an optimization solution that balances performance and resource constraints.

[0081] 2. Distributed analog front-end in-chip compression and tri-state bus collaborative control architecture: reducing on-chip polling power consumption.

[0082] In the architecture of traditional neural interface chips, the data collected by the analog front end needs to be transmitted completely to the data packer, which leads to a continuous increase in on-chip communication power consumption.

[0083] To address this issue, the second major innovation of this invention lies in moving the compression process forward to within the analog front-end, achieving near-source data preprocessing. The compressed data undergoes format conversion directly at local nodes and is distributed via a tri-state bus protocol, replacing the traditional APB or on-chip shared data bus.

[0084] This design offers two energy efficiency advantages: the distributed internal compression architecture eliminates the need for cross-module transmission of large amounts of redundant data, reducing unnecessary communication overhead. Simulation tests show that this structure reduces communication power consumption by 53%. The tri-state bus mechanism, through the introduction of high-impedance control and conflict-free access strategies, further reduces bus transmission power consumption by 96% compared to the standard APB architecture, significantly improving system energy efficiency density.

[0085] Example 2

[0086] By moving the compression logic forward and cooperating with a low-power tri-state bus, this invention thoroughly optimizes the communication path and power distribution at the structural design level, making it particularly suitable for large-scale, parallel neural channel data processing.

[0087] like Figure 2 As shown, this application also provides a multi-channel neural signal compression circuit device. The tri-state bus has a dual-rail structure, including a 4-bit high-speed data bus A for polling and transmitting compressed encoded data of each channel, and a 16-bit low-speed state bus B for synchronously transmitting the predicted value or raw sampled data of the corresponding channel.

[0088] The tri-state bus adopts a multi-driver shared architecture. Each driver is connected to the compression encoding output of a different channel processing unit, and its enable control signal is generated by the same master clock through a precision delay chain. The enable windows of adjacent drivers are strictly staggered on the time axis. The data packetizer is connected to the tri-state bus, receives and encapsulates the data streams from bus A and bus B, and outputs them to the data transmission baseband module.

[0089] The 4-bit high-speed data bus A of the tri-state bus is used to transmit the 4-bit fixed-length compressed encoded data output by each channel processing unit in a preset polling order. This polling order can be set according to the system configuration as a nested traversal sequence of channel numbers 0 to N−1 and modulo-digital front-end group numbers 0 to M−1, forming an M×N dimensional timing index. Each data line of bus A supports high-swing CMOS level, and the driving capability meets the timing requirements of 65 nm process, load capacitance ≤50 fF, and transmission delay ≤80 ps. Bus A does not contain address decoding logic, and its data path is a direct physical channel, relying only on the driver enable signal to achieve channel selection, thereby avoiding the static power consumption and switching noise caused by traditional address decoding and multiplexers.

[0090] The 16-bit low-speed status bus B is used to synchronously load and transmit the predicted value pred or raw sampled data of the corresponding channel at one time after the polling transmission of all M×N channel compressed encoded data is completed on bus A. The data width of bus B is 16 bits, of which the lower 10 bits carry the raw sampled data (10-bit ADC output), and the higher 6 bits are used to identify the data type (bit[15:14] = 2′b00 represents raw, 2′b01 represents pred, and the rest of the encoding is reserved) and channel ownership information. Bus B operates under the handshake protocol, and the status data latch is triggered by the ready signal issued by the data packetizer. Its clock domain is synchronized with the main sampling clock, and the maximum operating frequency does not exceed 1 MHz to reduce the switching power consumption. The wiring of bus B uses low impedance metal layers first, and decoupling capacitors are inserted at key nodes to suppress the crosstalk of low-speed signal edge ringing to the adjacent high-speed bus A.

[0091] The tri-state bus adopts a multi-driver shared architecture. Each channel processing unit's compressed encoding output is connected to a dedicated driver, which integrates a tri-state output buffer, enable latch, and level conversion circuit. All drivers share the same power rail and ground line, but their output ports are connected to the same 4-bit physical line on bus A. The enable control signals EN_i (i=0,1,…,M×N−1) of each driver are generated by the same master clock CLK through four cascaded precision delay units. Each delay unit provides a precisely controllable fixed delay Δt, ensuring that EN_0, EN_1, …, EN_{M×N−1} are evenly distributed on the time axis, with the rising edge interval of adjacent enable signals strictly equal to Δt, and Δt ≥ 2×t_pd_max + t_setup, where t_pd_max is the maximum propagation delay of the driver and t_setup is the setup time of the tri-state buffer; this design ensures that at most one driver is in a high-level enabled state at any time, fundamentally eliminating the power-to-ground short circuit path caused by multiple drivers driving bus A at the same time, and suppressing the dynamic short-circuit current to <100 nA (measured at 25°C).

[0092] The data packetizer connects to bus A and bus B via dedicated interfaces: its A-side interface is a 4-bit wide, source-synchronous input, with the sampling clock provided by the buffered feedback edge of the bus A driver enable signal to achieve zero-skew data acquisition; its B-side interface is a 16-bit wide, handshake input, internally integrating a FIFO buffer and a cross-clock domain synchronizer to temporarily store B-side data and align it with the latest round of M×N compressed codes from the A-side. After receiving a complete round of M×N 4-bit compressed codes and a corresponding set of 16-bit status data, the data packetizer performs frame encapsulation: adding a 2-byte frame header (including the synchronization word 0x55AA and version number), a 1-byte channel count field, a 4-byte timestamp (based on the on-chip 64 MHz baseband PLL counter), and a 2-byte CRC-16 check field, finally outputting a wireless transmission frame of fixed length 4×M×N+16+12 bytes, which is then sent to the data transmission baseband module.

[0093] The working process of the tri-state bus is as follows: At the beginning of each main sampling cycle, the analog-to-digital front-end group completes the analog conditioning and 10-bit analog-to-digital conversion of the N-channel neural signals, and the adaptive differential compression module built into each channel generates a 4-bit compressed code in real time before the data leaves the physical boundary; then, the precision delay chain activates the drivers of each channel in sequence, so that bus A outputs the compressed code channel by channel in a continuous M×N clock cycle; when the M×Nth compressed code is transmitted, the data packetizer immediately sends a ready request to bus B, triggering all channels to synchronously load the current predicted value pred or the raw sampled data raw to bus B; after bus B confirms that all data is stable, the data packetizer latches the entire group of 16-bit state information, completing a complete high-speed data stream + low-speed state snapshot collaborative transmission.

[0094] As an optional embodiment, the specific implementation of the scheme in this application is as follows: In a 256-channel (N=16) and single-mode digital front-end group (M=16) configuration, the main sampling rate is 30 kHz, bus A operates at 40 MHz, transmitting one 4-bit code per cycle, and it takes 6.4 μs to complete polling of all 256 channels; bus B starts after the 256th code is transmitted, and completes the parallel loading and latching of 16-bit status data within 1 μs; the data packetizer completes the frame header addition, timestamp writing and CRC calculation within 7.4 μs, and outputs a wireless frame with a length of 1036 bytes; the entire process has no bus contention, no address decoding overhead, and no cross-module multiplexer switching, and the on-chip data aggregation power consumption is reduced by 96% compared with the traditional APB bus architecture.

[0095] Through the above technical solutions, this application achieves the following: Due to the adoption of a dual-rail tri-state bus structure shared by multiple drivers, and the strict staggering of each driver's enable signal via a precision delay chain, power-to-ground short circuits caused by simultaneous enabling of multiple drivers are avoided, significantly reducing power consumption; Since bus A is dedicated to high-speed compressed code polling and bus B is dedicated to low-speed status information synchronous loading, their functions and timing are decoupled, thus improving the flexibility of data flow scheduling and the determinism of throughput; By eliminating the centralized multiplexer and address decoding circuit, and relying solely on driver enable control to achieve channel selection, wiring resource usage and switching capacitors are reduced, further lowering on-chip communication power consumption.

[0096] Furthermore, in an optional embodiment, this application also provides a multi-channel neural signal compression circuit device, wherein the programmable low-noise amplifier is an analog conditioning circuit, the time-division multiplexed analog-to-digital converter is an analog-to-digital converter, and the adaptive differential compression module is physically deployed after the digital output of the analog-to-digital converter and before the path of the data leaving the physical boundary of the corresponding channel processing unit.

[0097] Optionally, the programmable low-noise amplifier has a gain range of 20 dB to 60 dB, an adjustable bandwidth range of 0.1 Hz to 15 kHz, an input reference noise density of no more than 5 nV / kHz (at 1 kHz), and an input impedance of no less than 100 MΩ. This programmable low-noise amplifier receives gain and bandwidth control words through an on-chip configuration register, supporting dynamic adaptation under different electrode-tissue interface impedances (e.g., approximately 0.5 MΩ for microfilament electrodes and approximately 2 MΩ for silicon-based array electrodes) and signal-to-noise ratios, thereby improving the robustness of the front-end link for acquiring various types of neural signals (such as action potentials, local field potentials, and gamma oscillations). Its functional positioning is to provide analog preprocessing for amplitude adaptation, noise suppression, and impedance matching for subsequent analog-to-digital conversion, and to form the front-end foundation of a high-fidelity sampling path in conjunction with the analog-to-digital converter.

[0098] Optionally, the analog-to-digital converter (ADC) is a time-division multiplexed analog-to-digital converter, employing a single-core ADC core combined with an N-channel analog switch array and sample-and-hold circuitry to achieve N-channel polling sampling. This ADC core is a successive approximation (SAR) ADC with a resolution of 10 bits, a sampling rate of 30 kS / s / channel, and an effective number of bits (ENOB) of no less than 9.2 bits. Its time-division multiplexing mechanism is driven by a global sampling clock through multi-level frequency division and phase allocation logic, with the sampling times of each channel strictly staggered. Optionally, the sampling interval between adjacent channels is no less than 1 μs to avoid crosstalk and charge injection effects between channels. Compared to deploying N independent ADCs in parallel, this structure can save approximately 72% of silicon area and 58% of static power consumption, while improving channel consistency by sharing a reference voltage source and reference circuitry.

[0099] Optionally, the adaptive differential compression module is physically deployed after the digital output of the analog-to-digital converter (ADC) and before the path where the data leaves the physical boundary of the corresponding channel processing unit. This can mean that the input data interface of the module is directly connected to the 10-bit digital output bus of the ADC, and its output data interface is directly coupled to the local data path at the boundary of the channel processing unit (i.e., a private data path that is not connected to the cross-channel shared bus or on-chip interconnect network). This physical location ensures that the original 10-bit sampled data enters the differential operation and nonlinear quantization process immediately after generation without any buffering, temporary storage, or format conversion, and immediately enters the next stage of transmission after completing 4-bit fixed-length encoding. Its functional meaning is to realize the near-source processing paradigm of sampling and compression, and to prevent uncompressed data from flowing across modules. This is a key spatial constraint supporting the low-power, low-redundancy transmission architecture of this application. This deployment method makes the compression operation completely closed-loop within the single-channel processing unit, forming a tightly coupled signal flow with the programmable low-noise amplifier and time-division multiplexed ADC: analog signal → programmable LNA conditioning → time-division multiplexed ADC sampling → local adaptive differential compression → 4-bit encoded output, with no cross-channel data exchange intervention throughout the process.

[0100] Optionally, the gain configuration word of the programmable low-noise amplifier is automatically loaded by the on-chip state machine according to a preset experimental protocol, or it can be dynamically rewritten through an external interface; the channel switching sequence of the time-division multiplexed ADC is fixed as 0→1→…→N−1 cycle, and the switching delay is precisely calibrated to within ±50 ps by the on-chip phase-locked loop (PLL); the adaptive differential compression module starts differential operation in the second clock cycle after the ADC output stabilizes, and the entire compression process (including differential, lookup table, right shift, splicing, and left shift) is completed within ≤8 system clock cycles, meeting the real-time constraint of a sampling rate of 30 kS / s; the three are arranged in a vertical pipeline in the layout: the LNA is located on the chip input side, the ADC is in the middle, the compression module is adjacent to the ADC digital output and close to the metal layer boundary of the channel processing unit, the interconnect length between the three does not exceed 150 μm, and the parasitic capacitance is controlled within 30 fF.

[0101] As an optional embodiment, the specific implementation of this application is as follows: During 256-channel synchronous recording, an external microfilament electrode array couples the neural signals to the chip input; considering the impedance differences of the electrodes connected to different channels (measured range 0.3–2.1 MΩ), the on-chip configuration register loads a 12-bit gain control word for each channel's LNA, so that the output swing is uniformly maintained at 65%–85% of the ADC's full scale; the 256 signals are sampled in a time-division multiplexing manner by the same 10-bit SAR ADC core in the order 0→1→…→255, with a sampling window width of 95 ns for each channel and a channel switching interval of 105 ns. The 10-bit sampled data is immediately sent to the adaptive differential compression module of the corresponding channel. Differential operation is triggered on the second clock edge after the ADC digital output latch is completed. After step lookup table indexing, barrel right shift truncation, 4-bit code concatenation and prediction value left shift update, a 4-bit compressed code is output on the 9th clock edge. This 4-bit code is always routed in the metal layer inside the corresponding channel processing unit without crossing any global bus, and directly enters the subsequent tri-state bus driver stage, realizing full-link localization, zero redundancy and low-latency closed-loop processing from analog input to 4-bit encoded output.

[0102] Through the above technical solutions, this application achieves the following: The use of a programmable low-noise amplifier enables dynamic adjustment of gain and bandwidth based on electrode-tissue interface characteristics, enhancing the system's adaptability and experimental versatility for acquiring various types of neural signals; the use of a time-division multiplexed analog-to-digital converter significantly reduces chip area and static power consumption while maintaining 10-bit resolution and 30 kS / s / channel sampling capability; and the strict deployment of an adaptive differential compression module after the digital output of the analog-to-digital converter and before the physical boundary of the channel ensures that the original sampled data is compressed before delocalization, avoiding power consumption and signal integrity degradation caused by long-distance transmission of uncompressed data within the chip, thereby substantially supporting the overall technical effect of the ultra-low power multi-channel neural signal compression circuit device described in the above embodiments.

[0103] Optionally, this application also provides that the prediction model used by the adaptive differential compression module is a linear predictor based on the value of the previous cycle, a lightweight recurrent neural network adaptive predictor, or a combination thereof. The output of the prediction model is used to perform differential operations with the current original sampled data, and the prediction process does not depend on external training data, and parameter updates are completed online in real time.

[0104] Among them, a linear predictor based on the value of the previous period can refer to one that uses only the predicted value pred from the previous period. n ₋1 is the current cycle prediction value pred n The direct output, i.e., pred n = pred n ₋1; can also refer to using a two-point linear extrapolation form, i.e., pred n= 2 × pred n ₋1 − pred n ₋2, where pred n ₋2 represents the predicted value of the previous period; this linear predictor has a simple structure, extremely low latency, and near-zero hardware overhead, making it suitable for rapid modeling of slowly varying components (such as local field potentials, LFP) in neural signals. Its function is to provide a basic prediction benchmark and serve as a low-power backbone path in the combined model; this predictor works in conjunction with the 10-bit subtractor, step lookup table, and splicing logic unit in the adaptive differential compression module to form the initial input source for differential operations; through cooperation with subsequent nonlinear quantization stages, it forms a stable, low-jitter 4-bit encoded output stream.

[0105] Optionally, the lightweight recurrent neural network adaptive predictor can be a simplified Elman-type RNN or a continuous-time RNN (CTRNN) with no more than 8 hidden neurons, a weight matrix dimension no higher than 8×8, and an activation function using a piecewise linear approximation or a lookup table-based Sigmoid function. This predictor can be deployed in a dedicated logic region within the channel processing unit, and its input is the K most recent raw sample values. n ₋1, raw n ₋2, …, raw n ₋ k (K ranges from 3 to 10), the output is the single-point prediction value pred. n The predictor's function is to capture short-term nonlinear dynamics in neural signals (such as spike bursts and postsynaptic potential superposition). Its name is based on its state memory capability and online feedback regulation characteristics. This predictor collaborates with a linear predictor through a weighted fusion method: pred n = α × pred n ˡ 1n + (1−α) × pred n ᴿᴺᴺ, where the fusion weight α is set by the on-chip configuration register, with a value range of [0.0, 1.0], supporting static configuration or dynamic switching; this predictor is linked to the step lookup table: when the RNN outputs the residual |raw n - pred n When ᴿᴺᴺ| is continuously greater than the threshold, the step size expansion parameter step_ext is accelerated and updated, thereby improving the quantization granularity to adapt to sudden signal changes. This linkage enables the prediction update and nonlinear quantization to form a closed-loop feedback, maintaining the stability of the compressed code within the dynamic range.

[0106] The combination of a linear predictor and a lightweight recurrent neural network adaptive predictor can refer to a form where the outputs of the two are fused with fixed weights; it can also refer to a form where the dominant predictor is automatically selected based on real-time signal statistical characteristics (such as the standard deviation σ of the last 100 sampling points, the zero-crossing rate ZCR, or the energy entropy E); or it can refer to a dynamic weighted fusion form using a gating mechanism, where the gating signal g is determined by the current difference dt = raw n - pred n ˡ 1n Generated after low-pass filtering, the weights of the RNN pathway are enhanced when g > 0.5, otherwise the linear pathway is strengthened. The functional positioning of this combined structure is to balance prediction accuracy and hardware energy efficiency. While ensuring that the power consumption of a single channel is still within the constraint range of 2.5–3.5 nW, it improves the generalization modeling ability of neural signals of multiple brain regions and multiple behaviors. Together with all combinational logic units (including subtractors, right shifters, concatenation logic and left shifters) in the adaptive differential compression module, it forms a unified data flow processing link. All operations do not call multiplier instructions or hardware units, and are all completed based on bit operations, table lookup and logic concatenation.

[0107] Specifically, the online parameter update process of the prediction model does not rely on external training data; it is entirely based on the local sampling sequence of the current channel and completed in real time. For linear predictors, their coefficients (such as coefficients 2 and -1 in two-point extrapolation) are fixed logic and do not need to be updated. For lightweight RNNs, their weight updates use a simplified variant of error backpropagation—only the output weights of the last layer are updated, and the gradient calculation uses a sign function approximation, with the update step size η fixed at 2⁻. 4 Before each polling cycle begins, a conditional trigger is performed based on the mean absolute value of the prediction error of the most recent 100 sampling points, |ε|: when |ε| > 0.8 × Vref (Vref is the full-scale reference voltage of the ADC), a single weight fine-tuning is initiated; otherwise, it remains frozen. This mechanism ensures that parameter updates respond to signal mutations while avoiding logic oscillations caused by high-frequency jitter.

[0108] The present invention discloses a control method for a multi-channel neural signal compression circuit device. The circuit device includes an analog-to-digital front-end group, a tri-state bus, a data packetizer, and a data transmission baseband module. The analog-to-digital front-end group comprises N parallel channel processing units. Each channel processing unit integrates an analog conditioning circuit, an analog-to-digital converter, and an adaptive differential compression module. The tri-state bus has a dual-rail structure, including a 4-bit high-speed data bus A and a 16-bit low-speed state bus B. The data packetizer is connected to the tri-state bus, and the data transmission baseband module is connected to the data packetizer. The control method is characterized by performing the following steps:

[0109] The N-channel neural signals were subjected to analog conditioning and analog-to-digital conversion to obtain N channels of 10-bit raw sampled data.

[0110] Before each raw sampled data leaves the physical boundary of the corresponding channel processing unit, the adaptive differential compression module built into the channel performs differential operation based on the predicted value of the previous cycle, obtains the step size expansion parameter by looking up the table, generates 4-bit compressed encoded data by right shifting and truncating, and completes the prediction value update by splicing and left shifting.

[0111] The 4-bit high-speed data bus A of the three-state bus is controlled to enable the driver of each channel processing unit in a preset polling order, and the 4-bit compressed encoded data output by each channel is transmitted to the data packetizer channel by channel.

[0112] After the bus A completes the polling transmission of all M×N channel compressed encoded data, the 16-bit low-speed state bus B, which controls the tri-state bus, synchronously loads and transmits the predicted value or original sampled data of the corresponding channel.

[0113] Optionally, the step of updating the predicted value by the adaptive differential compression module specifically includes:

[0114] Calculate the difference between the current raw sampled data raw and the predicted value pred from the previous period, and the difference is expressed as dt = raw − pred;

[0115] The difference is compressed, and the compressed data is represented in a fixed-length format, wherein the encoded data is code = dt >> step_ext; the current step size extension parameter step_ext is obtained by looking up the step size lookup table (LUT);

[0116] Perform a right-shift truncation operation: code = dt >> step_ext, to obtain a 4-bit unsigned code; then update the predicted value by concatenation and left shift:

[0117] pred_new = {code, 1′b1} << (step_ext[4:2] − 1);

[0118] Where step_ext is the step size value calculated in the previous cycle; the valid value range of step_ext is [min_step, 31], and min_step is a configurable parameter with a value of 0, 4, 8 or 12; this module does not contain any multiplier units, and all operations are completed by a 10-bit subtractor, read-only memory (ROM) lookup table, barrel right shifter, logic splicer and barrel left shifter working together; its implementation is a fully custom digital circuit using low-power CMOS technology, or an RTL netlist generated by standard cell library synthesis.

[0119] Optionally, in the step of transmitting data according to a preset polling order on bus A, the polling order is to traverse each modular front-end group according to channel number 0 to N−1, and then execute the process in a loop according to modular front-end group number 0 to M−1, forming an M×N dimensional polling sequence.

[0120] In the step of synchronous loading of bus B, the parallel transmission of the predicted value pred or the raw sampled data raw corresponding to all channels in the current polling sequence is completed in a low-speed manner.

[0121] Optionally, the adaptive differential compression module performs differential operations, step-size lookup, nonlinear quantization, and prediction value updates without calling multiplier instructions or hardware units. All operations are completed collaboratively by a 10-bit subtractor, a read-only memory lookup table, a barrel right shifter, a logic concatenator, and a barrel left shifter.

[0122] Optionally, in the control of the tri-state bus, a phase-spacing control signal is introduced into the drive enable control circuit to keep the timing of multiple drivers effectively staggered, thereby preventing any two or more drivers from being enabled at the same time.

[0123] Optionally, the data streams from bus A and bus B are received through the data packetizer, and a frame header, timestamp, and check field are added to encapsulate them into a wireless transmission frame;

[0124] The encapsulated wireless transmission frame is sent to the data transmission baseband module, and after modulation and power amplification, it is transmitted wirelessly.

[0125] Optionally, the adaptive differential compression module is integrated into a 65nm CMOS chip, with an overall power consumption of less than 10mW; the power consumption of a single-channel adaptive differential compression module is 2.5–3.5nW, and the power consumption value is fed back in real time through an on-chip current monitoring circuit and used for dynamic power gating adjustment.

[0126] Optionally, the prediction model used by the adaptive differential compression module can be switched online to a linear predictor, a lightweight long short-term memory network predictor, or a weighted fusion predictor of both. The switching instruction is received by the on-chip configuration register. The predictor weight parameters are automatically updated based on the error statistics of the most recent 100 sampling points before the start of each polling cycle. The update process does not interrupt the data stream transmission.

[0127] Optionally, the technical solution of this application is adaptable to a variety of experimental animals, a variety of neural electrodes, implantable in any brain region or neural tissue, adaptable to any analog-to-digital converter architecture, and any combination of analog front-end channels.

[0128] Optionally, in the technical solution of this application, the decompression can be placed in the communication baseband or in the computer terminal, adapting to any legal wireless transmission frequency band, and is not limited to fully custom integrated circuits or discrete electronic components.

[0129] Optionally, the adaptive signal compression algorithm and hardware architecture used in this application can also be adapted to systems with similar signal characteristics, such as EEG, ECG, and various sensors. The same signal compression processing purpose can be achieved simply by adjusting the compressor parameters.

[0130] Optionally, the compression stage of this technical solution uses numerical prediction from the previous cycle and differential compression, the core of which is to reduce the amount of data by utilizing the temporal correlation of the signal. For different signal characteristics, other predictor structures such as linear predictors and neural network adaptive predictors can be used instead, achieving the same compression objective.

[0131] In one exemplary embodiment, this application provides a storage device, including: a storage controller, wherein the storage performs data processing based on the control method described above in this application.

[0132] In one exemplary embodiment, this application provides an electronic device, including: a memory for storing a computer program; and a processor for executing the computer program to implement the steps of the control method described in the above embodiments.

[0133] The electronic device can be a brain-computer interface terminal, a portable neural signal acquisition device, an edge AI computing box, a wearable neural monitoring device, or the main control unit in an implantable closed-loop control system. The memory includes non-volatile storage media (such as embedded flash memory eFlash, EEPROM, or an external SD card) and internal memory (such as SRAM or LPDDR). The non-volatile storage media stores the operating system, the computer program corresponding to the control method described in the embodiments, and configuration parameters; the internal memory provides temporary data caching and an instruction execution environment for the computer program. The processor can be a general-purpose microcontroller (MCU), a digital signal processor (DSP), a reduced instruction set multi-core processor (RISC-V SoC), an AI acceleration coprocessor, or a combination thereof. It is configured to call and execute the computer program stored in the memory to complete all operational processes such as analog conditioning of N-channel neural signals, analog-to-digital conversion, adaptive differential compression, tri-state bus polling control, data packaging, and wireless transmission baseband driving.

[0134] In another aspect, this application also provides a computer-readable storage medium, which may be included in the electronic device described in the above embodiments, or may exist independently and not assembled into the electronic device. The computer-readable storage medium stores one or more programs that, when used by one or more processors, execute the control method of the multi-channel neural signal compression circuit device described in this application.

[0135] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A multi-channel neural signal compression circuit device, comprising an analog-to-digital front-end group, a data packetizer, and a data transmission baseband module, characterized in that, The modular front-end group is used to receive and process N-channel neural signals; The data packer is used to format the processed multi-channel data according to specified rules; The data transmission baseband module is used for wireless transmission of formatted data; and The analog-to-digital front-end group comprises N parallel channel processing units. Each channel processing unit integrates an analog conditioning circuit, an analog-to-digital converter, and an adaptive differential compression module. The adaptive differential compression module is directly coupled to the digital output of the analog-to-digital converter corresponding to the channel. The adaptive differential compression module is configured to perform differential operation based on the predicted value of the previous cycle before the original sampled data leaves the physical boundary of the channel. It obtains the step size extension parameter by looking up the table, completes nonlinear quantization and prediction value update by displacement and logic concatenation, and outputs 4-bit fixed-length compressed encoded data.

2. The multi-channel neural signal compression circuit device according to claim 1, characterized in that, The device also includes a tri-state bus, which has a dual-rail structure and includes: The 4-bit high-speed data bus A is used for polling and transmitting compressed encoded data from each channel; and 16-bit low-speed status bus B is used for synchronous transmission of the corresponding channel's predicted value or raw sampled data. The tri-state bus adopts a multi-driver shared architecture. Each driver is connected to the compression encoding output terminal of a different channel processing unit, and its enable control signal is generated by the same master clock through a precision delay chain. The enable windows of adjacent drivers are strictly staggered on the time axis. The data packetizer is connected to the tri-state bus, receives and encapsulates data streams from bus A and bus B, and outputs them to the data transmission baseband module.

3. The multi-channel neural signal compression circuit device according to claim 1, characterized in that, The analog conditioning circuit is a programmable low-noise amplifier, the analog-to-digital converter is a time-division multiplexed analog-to-digital converter, and the adaptive differential compression module is physically deployed after the digital output of the analog-to-digital converter and before the path of the data leaving the physical boundary of the corresponding channel processing unit.

4. The multi-channel neural signal compression circuit device according to claim 2, characterized in that, The number of modular front-end groups connected to the tri-state bus is M, where M is a positive integer; Bus A and Bus B work together. After Bus A completes the polling transmission of all M×N channel compressed encoded data, Bus B synchronously completes the one-time low-speed transmission of the predicted value or original sampled data of the corresponding channel.

5. The multi-channel neural signal compression circuit device according to claim 1, characterized in that, The adaptive differential compression module does not contain a multiplier unit. Its differential operation, step size parameter acquisition, nonlinear quantization and prediction value update are all implemented by combinational logic circuits, specifically including: a 10-bit subtractor, a step size lookup table, a right shift and truncation circuit, a splicing logic unit and a left shifter. All operations are completed based on shifting, logic operations and table lookup.

6. The multi-channel neural signal compression circuit device according to claim 2, characterized in that, The tri-state bus drive enable control circuit includes a precision delay chain driven by the same master clock signal. The precision delay chain is composed of four cascaded delay units with consistent structure, used to generate multiple enable control signals with sequentially staggered phases, so that the effective drive windows of adjacent drivers are strictly separated on the time axis, and at most one driver is in the enabled drive state at any time. The data transmission baseband module supports wireless transmission of the encapsulated wireless transmission frame after modulation and power amplification. The adaptive differential compression module is integrated into the CMOS chip, and the overall power consumption is less than 10mW. The power consumption of a single-channel adaptive differential compression module is 2.5–3.5 nW; The prediction model used by the adaptive differential compression module is a linear predictor based on the value of the previous cycle, a lightweight recurrent neural network adaptive predictor, or a combination thereof. The output of the prediction model is used to perform a difference operation with the current original sampled data, and the prediction process does not depend on external training data, and the parameter updates are completed online in real time.

7. A control method for a multi-channel neural signal compression circuit device, wherein, The circuit device includes an analog-to-digital front-end group, a tri-state bus, a data packetizer, and a data transmission baseband module. The analog-to-digital front-end group contains N parallel channel processing units. Each channel processing unit integrates an analog conditioning circuit, an analog-to-digital converter, and an adaptive differential compression module. The tri-state bus has a dual-rail structure, including a 4-bit high-speed data bus A and a 16-bit low-speed status bus B. The data packetizer is connected to the tri-state bus, and the data transmission baseband module is connected to the data packetizer. The control method executes the following steps: The N-channel neural signals were subjected to analog conditioning and analog-to-digital conversion to obtain N channels of 10-bit raw sampled data. Before each original sampled data leaves the local data path of the corresponding channel processing unit, the adaptive differential compression module built into the channel performs differential operation based on the predicted value of the previous cycle, obtains the step size expansion parameter by looking up the table, generates 4-bit compressed encoded data by right shifting and truncating, and completes the prediction value update by splicing and left shifting. The 4-bit high-speed data bus A of the three-state bus is controlled to enable the driver of each channel processing unit in a preset polling order, and the 4-bit compressed encoded data output by each channel is transmitted to the data packetizer channel by channel. After the bus A completes the polling transmission of all M×N channel compressed encoded data, the 16-bit low-speed state bus B, which controls the tri-state bus, synchronously loads and transmits the predicted value or original sampled data of the corresponding channel. The steps for updating the predicted value by the adaptive differential compression module specifically include: Calculate the difference between the current raw sampled data raw and the predicted value pred from the previous period, and the difference is expressed as dt = raw − pred; The difference is compressed, and the compressed data is represented in a fixed-length format, wherein the encoded data is code = dt >> step_ext; Calculate the predicted value for the next sampling point based on the encoded data; Where step_ext is the step size value calculated in the previous cycle; the step size value in the current cycle is updated by consulting the step size lookup table; In the step of transmitting data according to a preset polling order, the polling order is to traverse each modular front-end group according to the channel number 0 to N−1, and then execute the process in a loop according to the modular front-end group number 0 to M−1, forming an M×N dimensional polling sequence. In the step of synchronous loading of bus B, the parallel transmission of the predicted value pred or the raw sampled data raw of the corresponding channel in the current polling sequence is completed in a low-speed manner. The adaptive differential compression module performs differential operations, step-size lookup, nonlinear quantization, and prediction value updates without calling multiplier instructions or hardware units. All operations are completed collaboratively by a 10-bit subtractor, read-only memory lookup, barrel right shifter, logic concatenation unit, and barrel left shifter. In the control of the tri-state bus, a phase-spacing control signal is introduced into the drive enable control circuit to keep the timing of multiple drivers effectively staggered, thereby preventing any two or more drivers from being enabled at the same time. The data packetizer receives data streams from bus A and bus B, adds frame headers, timestamps, frame sequence numbers and check fields, and encapsulates them into wireless transmission frames. The encapsulated wireless transmission frame is sent to the data transmission baseband module, and after modulation and power amplification, it is transmitted wirelessly. The adaptive differential compression module is integrated into the chip, with an overall power consumption of less than 10mW; The power consumption of a single-channel adaptive differential compression module is 2.5–3.5 nW; The prediction model used by the adaptive differential compression module can be switched online to a linear predictor, a lightweight long short-term memory network predictor, or a weighted fusion predictor of both. The switching instruction is received by the on-chip configuration register. The predictor weight parameters are automatically updated based on the error statistics of the most recent 100 sampling points before the start of each polling cycle. The update process does not interrupt the data stream transmission.

8. A storage device, characterized in that, include: A storage controller that performs data processing based on the control method as described in claim 7.

9. An electronic device, characterized in that, Includes: memory, used to store computer programs; A processor for implementing the steps of the control method as described in claim 7 when executing the computer program.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, wherein the computer program, when executed by a processor, implements the steps of the control method as described in claim 7.

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