A method and system for improving error correction capability of LDPC code

Abstract

The application belongs to the technical field of magnetic tape storage coding, and discloses a coding and decoding method and system for improving the error correction capability of LDPC code, wherein the coding scheme comprises the following steps: first, using LDPC code to encode to obtain a coded code word; interleaving a plurality of obtained coded code words; and performing AMD code encoding on the data matrix after interleaving processing row by row. The decoding scheme comprises the following steps: first, performing AMD code decoding on the received data matrix row by row; performing deinterleaving on the data matrix obtained after AMD code decoding to restore the LDPC code word; performing LDPC code decoding to obtain the original information. The application introduces AMD code for error detection, locates the burst error, improves the correction capability of the LDPC code for the burst error, improves the error correction capability of the AMD code through interleaving processing of the LDPC code, effectively improves the error correction capability under a high probability, and realizes significant technical progress.

Description

Technical Field

[0001] This invention belongs to, but is not limited to, the field of magnetic tape storage encoding technology, and particularly relates to an encoding and decoding method and system for improving the error correction capability of LDPC codes. Background Technology

[0002] Error-correcting codes are a technique used to improve the reliability of information transmission in noisy channels and are now widely used in communication and storage systems. Since all storage media have certain defects, data may face various error risks during storage and retrieval, thus necessitating mechanisms to enhance storage reliability. It is against this backdrop that error-correcting codes are widely used in storage systems to provide effective data protection.

[0003] As memory cell sizes shrink (e.g., NAND Flash) or track densities increase (e.g., HDD), the number of bits stored per cell increases, exacerbating inter-cell interference and making the system more sensitive to noise and interference, resulting in a significant increase in the original bit error rate (BER). Modern memory systems often use LDPC codes as error correction codes, such as those using NAND Flash media. LDPC codes are linear block codes based on sparse parity-check matrices. With longer code lengths, their performance approaches the Shannon theoretical limit, exhibiting very strong error correction capabilities. The error correction capability of LDPC codes is typically characterized by a threshold value under a specific decoding algorithm. If the channel parameters (which vary depending on the channel) are better than the corresponding threshold, the BER can approach a certain level as the code length increases. LDPC codes, due to their strong error correction capabilities, have been widely used in communication and storage fields. However, in some storage systems, such as disk and tape storage systems, large-scale burst errors frequently occur, such as bad sectors and bad tracks. Therefore, Reed-Solomon codes, which have strong burst error correction capabilities, are often used instead of LDPC codes. If LDPC codes are to be used in such storage systems, other mechanisms need to be introduced to improve their ability to correct large-scale burst errors.

[0004] Information is often subject to malicious algebraic tampering by adversaries during storage and transmission. Consider an abstract device. It can be used to store data from fixed, publicly known finite Abelian groups. single element The attacker, by using a selected element Add to storage device, make The value stored in becomes This type of attack is called algebraic manipulation. In 2008, Crammer et al. generalized and summarized existing schemes, proposing the concept of Algebraic Manipulation Detection Codes (AMD codes). AMD codes consist of a randomized probabilistic coding function and a deterministic decoding function, where the probabilistic coding map encodes plaintext into ciphertext. Let... It is a size of The set, It is For an order-order commutative group, consider a probabilistic encoding mapping. With a deterministic decoding map ,in , , and if ,but ,like ,but If for any , , The probability is at most Then it is called for - Algebraic manipulation codes. Optimal AMD codes can detect any algebraic tampering with a very high probability.

[0005] Based on the above analysis, the urgent technical problems that need to be solved in the existing technology are: (1) Insufficient error correction capability: Traditional methods are ineffective when the total number of sudden errors exceeds the threshold of binary symmetric channels. At that time, it is impossible to guarantee that the bit error rate will approach 0.

[0006] (2) Limited applicability: When faced with large-scale burst errors or poor channel conditions, the total number of errors caused by burst errors accounts for more than the binary symmetric channel threshold. At that time, traditional encoding and decoding schemes are no longer applicable. Summary of the Invention

[0007] To address the problems existing in the prior art, this invention provides an encoding and decoding method and system for improving the error correction capability of LDPC codes.

[0008] This invention is implemented as follows: a coding and decoding method for improving the error correction capability of LDPC codes, characterized in that the coding and decoding method for improving the error correction capability of LDPC codes specifically includes: S1: LDPC encoding stage: Encode the information using LDPC codes.

[0009] S2: Interleaving stage: Take multiple codewords obtained by encoding the above LDPC code and interleave them.

[0010] S3: AMD code encoding stage: The data obtained after the above interleaving is encoded using the system AMD code.

[0011] S4: AMD code decoding stage: Decode the AMD codeword obtained after encoding. If the AMD decoding fails, mark the entire codeword as erased.

[0012] S5: Deinterleaving stage: Deinterleave the data obtained after AMD decoding to restore each LDPC codeword.

[0013] S6: LDPC code decoding stage: Perform LDPC code decoding to obtain the original information.

[0014] Furthermore, the information is encoded using LDPC codes, and the specific steps are as follows: (1) Selecting a finite field The above parameters are LDPC code.

[0015] (2) Take A length of Information , .

[0016] (3) Encode the information using LDPC code to obtain the encoded codeword. .

[0017] Furthermore, the interleaving of the codewords obtained by LDPC encoding is carried out in the following specific steps: (1) Take LDPC codewords After transposing, the columns are arranged to form a size of matrix .

[0018] (2) with each Divide the data into groups, then rearrange the groups sequentially by column to obtain a result of size [value]. matrix .

[0019] Furthermore, the specific steps for encoding the interleaved data using the AMD code system code are as follows: (1) Selecting a finite field The above parameters are AMD code, for matrix Each line is encoded using the AMD code system code.

[0020] (2) For any row According to each Divide into groups of 10 elements, represented as follows: Each group is considered Vectors on, and isomorphic to them The elements on the vector are obtained. .

[0021] (3) Let Take a random element ,calculate .

[0022] (4) The codeword after AMD encoding is ; The obtained data matrix is .

[0023] Furthermore, the specific steps for decoding using the AMD code system code are as follows: (1) Assume the data matrix read is ,in .

[0024] (2) For any row ,calculate ,judge Is it equal to .

[0025] (3) If Then determine That is, the original data Output the decoding result ;like Then determine Not the original data Mark the entire line as an erase error and output the decoding result. , For length and The same vector, but all positions are marked as erased.

[0026] like ,but If an error occurs but is not detected, the AMD code decoding fails, and the probability of failure is... If there is If all AMD codewords are completely wrong, then the probability of being completely detected is: .

[0027] The matrix output after decoding all rows using AMD code is: to isomorphize its elements to The above yields the data matrix. .

[0028] Furthermore, the specific steps for deinterleaving the data matrix after AMD code decoding into LDPC codewords are as follows: Data matrix Each column Each column is grouped into a set of columns, and the resulting matrix is... Represented as Rearrange the groups by row to obtain the data matrix. ; obtained That is, each corrupted LDPC codeword read.

[0029] Furthermore, the decoding using the LDPC code decoder involves the following specific steps: Decoding is performed using an LDPC code decoder. If the percentage of erased bits in the total number of bits is less than the threshold for LDPC codes in a binary erase channel... If the bit error rate approaches 0, then the bit error rate will be close to 0.

[0030] Another objective of this invention is to provide an encoding and decoding system for improving the error correction capability of LDPC codes, the system specifically comprising: The LDPC code encoding module is used to encode information. Encode using LDPC code.

[0031] The interleaving module is used to interleave multiple LDPC codewords.

[0032] The AMD code encoding module is used to encode the interleaved data matrix using AMD codes.

[0033] The AMD code decoding module is used to decode the received data matrix into AMD code, and marks any errors as to be erased.

[0034] The deinterleaving module is used to deinterleave and restore LDPC codewords.

[0035] The LDPC code decoding module is used for decoding with an LDPC code decoder.

[0036] Based on the above technical solutions and the technical problems solved, the advantages and positive effects of the technical solution to be protected by this invention are as follows: This invention constructs a coding and decoding algorithm for constructing product codes using AMD codes and LDPC codes, which can improve the error correction capability of LDPC codes in magnetic tape storage systems.

[0037] This invention fully utilizes the high error detection capability of AMD codes and the error correction capability of LDPC codes, combining AMD and LDPC codes to improve the ability of LDPC codes in storage systems to correct large-scale burst errors. It effectively enhances the ability to correct burst errors, ensuring that even in channels prone to large-scale burst errors, the total number of burst errors can still be corrected even if the proportion of burst errors reaches the binary erase channel threshold. Sometimes, it is also possible The probability of this makes the bit error rate approach 0. The technical advantages of this invention are as follows: (1) Enhanced error correction capability: The encoding and decoding algorithm combining AMD code and LDPC code can obtain error location information by using AMD code to locate errors and convert errors into erasure, thereby improving the error correction capability of LDPC code. The proportion of the total number of errors corrected with a bit error rate approaching 0 is determined by the binary symmetric channel threshold. Increase to binary erase channel threshold In particular, this encoding / decoding algorithm is especially suitable for scenarios involving large-scale burst errors, such as in tape or disk storage systems where several sequences of storage units often fail. The encoded data matrix... Using a single AMD codeword as the basic storage sequence, if several storage sequences are corrupted, all data reads will fail, resulting in the following: Several lines of code contained errors. This encoding / decoding algorithm can correct these errors with an error rate approaching 0. The number of lines with errors has reached However, using only LDPC codes, under the requirement of a bit error rate approaching 0, can only correct [a certain number of errors]. One line with an error.

[0038] (2) Low data redundancy: By using AMD code, only 2 bits of redundancy need to be added in the extended field to achieve a high probability of detecting errors. In the case of large-scale data, the redundancy added by using AMD code is almost negligible.

[0039] (3) Low complexity: The encoding and decoding complexity of AMD code is quasi-linear, and it can use very mature encoder and decoder designs, with very low time and hardware complexity; the decoder of LDPC code uses an erase decoder, which has lower complexity than the usual LDPC code decoder such as the BP algorithm decoder.

[0040] (4) Wide applicability: This invention is applicable to industrial storage systems with high requirements for encoding and decoding time complexity or various complex parallel channel application scenarios that require high error correction capabilities, including but not limited to disk storage, tape storage, array communication and other fields.

[0041] (5) The expected benefits and commercial value of the technical solution of this invention after transformation are as follows: By combining AMD codes and LDPC codes, information is transformed from a binary symmetric channel to a binary erasure channel in the scenario of large-scale burst errors, thereby greatly improving the error correction capability of LDPC codes. This encoding method allows the proportion of burst errors to reach a certain percentage of the total number of bits under high probability. That is, the threshold of the LDPC code in a binary erase channel, and with The probability of this can bring the bit error rate close to 0. This operation enhances the ability to correct large-scale burst errors. This technology can be used in fields such as disk storage, tape storage, and array communication.

[0042] (6) The technical solution of the present invention fills a technical gap in the industry at home and abroad: the traditional LDPC code is not good enough at correcting large-scale burst errors. When the total number of burst errors exceeds the threshold of LDPC code in binary symmetric channel, However, it is not possible to guarantee obtaining the original information with a near-zero bit error rate. To address this issue, this invention combines AMD codes and LDPC codes, fully utilizing the high error detection capability of AMD codes and the error correction capability of LDPC codes. An innovative encoding and decoding scheme is designed that effectively enhances the error correction capability for large-scale burst errors, ensuring that even in channels prone to burst errors, the total number of burst errors can be corrected even if the proportion reaches the binary erase channel threshold. Sometimes, it is also possible The probability of this makes the bit error rate approach 0.

[0043] (7) The technical solution of the present invention solves a technical problem that people have long wanted to solve but have never been able to solve: Before this, LDPC codes could not effectively cope with the scenario of large-scale burst errors, and could only withstand the total number of errors as a percentage of the binary symmetric channel threshold. The following. However, this method's error rate exceeds the binary symmetric channel threshold when dealing with large-scale burst errors. Even if the binary erase channel threshold is reached... , also The probability of this makes the bit error rate approach 0. Attached Figure Description

[0044] Figure 1 This is a flowchart of an encoding and decoding method for improving the error correction capability of LDPC codes provided in an embodiment of the present invention.

[0045] Figure 2 This is a block diagram of an encoding and decoding system for improving the error correction capability of LDPC codes, provided in an embodiment of the present invention.

[0046] Figure 3This is a comparison curve of the symbol error rate between the method of the present invention and the traditional method under a burst error channel provided by the embodiments of the present invention.

[0047] Figure 4 This is a graph showing the bit error rate performance of the LDPC code in a BSC channel, as provided in an embodiment of the present invention.

[0048] Figure 5 This is a graph showing the bit error rate performance of the LDPC code in the BEC channel provided in this embodiment of the invention. Detailed Implementation

[0049] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0050] This invention addresses the issue of degraded error correction performance of Low-Density Parity-Check (LDPC) codes under burst errors and high-noise channels by proposing a layered coding-decoding scheme that combines system AMD (Algebraic Manipulation Detection Code) codes with interleaving techniques. The design concept involves introducing a detectable algebraic manipulation check structure before LDPC code decoding. Cross-codeword redundancy protection is achieved through AMD encoding of the interleaved data blocks, significantly reducing the probability of undetected error propagation during decoding. This scheme addresses the high-reliability data transmission requirements in fields such as satellite communication, vehicular wireless links, quantum noise-resistant communication, and secure distributed storage, and is particularly suitable for environments with strong interference, burst erasure, or hostile channels.

[0051] In terms of working principle, the information sequence is first structured sparse matrix encoded using LDPC codes to generate codewords under a low-density parity-check matrix. The LDPC coding layer is responsible for implementing iterative error correction based on the belief propagation (BP) algorithm. However, under conditions of high erasure ratios or burst errors, the convergence of the BP algorithm will be severely compromised. To overcome this local trap effect, this method introduces an interleaving stage after encoding. Through matrix transpose and rearrangement operations, the bit order of multiple codewords is randomly mixed, making the spatially adjacent bits more evenly distributed during transmission over the channel, thereby effectively suppressing the concentration of burst errors within a single codeword.

[0052] On the interleaved data matrix, this method introduces a system AMD code encoding mechanism. The basic principle of AMD codes is to construct a system code with manipulation detection capability using algebraic isomorphism over a finite field F_(2^l). An additional authentication symbol is formed by calculating a random element x_i and its corresponding polynomial f_(s_i)(x_i). If arbitrary bit tampering or undetected interference occurs during channel transmission or node buffering, the decoder can identify the error by recalculating the polynomial value. Since AMD codes have a provable detection probability limit, they form an "algebraic protective shell" on the outer layer of the LDPC structure, significantly reducing the joint probability of false detection and false correction.

[0053] During the decoding process, the receiving end first performs AMD code decoding. If the decoding verification fails, the data line is determined to be corrupted and marked as erased. This erasure strategy, at the system level, is equivalent to removing unreliable information from the LDPC decoding input, allowing the LDPC decoder to iterate only on bits with high confidence, thus improving the convergence speed of confidence propagation and the accuracy of the final decision. Subsequently, the original LDPC codeword structure is restored through deinterleaving, so that each line of codewords corresponds again to the original information block arrangement. At this point, even if some AMD codewords are erased, the sparse structure of the LDPC code can still use its redundancy relationship for error correction.

[0054] During the LDPC decoding stage, the system utilizes a decoding threshold determination based on the Binary Erase Channel (BEC) model. If the proportion of erased bits is lower than this threshold ε_BEC, the bit error rate can theoretically approach zero. Compared to traditional joint coding schemes, this method introduces some randomness into the error determination mechanism through an AMD detection layer, weakening the local loop traps caused by error aggregation in high-noise channels and improving the decoding capacity under signal-to-noise threshold conditions from an information theory perspective. Therefore, the error correction capability of the entire system not only depends on the degree distribution design of the LDPC code but also on the detection probability control of the AMD layer, achieving multi-level reliability enhancement.

[0055] In summary, this method achieves robust error correction against burst errors and adversarial interference through a layered structure of "interleaving-AMD encoding-erasing-LDPC decoding". Its essence lies in adding an algebraic consistency check to the probabilistic graphical decoding mechanism, transforming the error from a random noise model to a controllable erasure model. This structure is easily implemented in parallel on hardware and can be integrated into existing FPGA or ASIC encoders, providing a feasible error correction enhancement approach for next-generation high-reliability communication systems.

[0056] like Figure 1 As shown, this embodiment of the invention provides an encoding and decoding method to improve the error correction capability of LDPC codes. The method specifically includes: Step 1, LDPC code encoding stage: 1.1) Selecting a finite field The above parameters are LDPC code, take A length of Information , .

[0057] 1.2) Encode the information using LDPC code to obtain the encoded codeword. .

[0058] Step 2, Interweaving Phase: 2.1) Take LDPC codewords After transposing, the columns are arranged to form a size of matrix .

[0059] 2.2) with each Divide the data into groups, then rearrange the groups sequentially by column to obtain a result of size [value]. matrix .

[0060] Step 3, AMD code encoding stage: 3.1) For any row According to each Divide the elements into groups, and each group is considered as... Vectors on the finite field are isomorphic to the finite field. The elements on the vector are obtained. .

[0061] 3.2) Let Take a random element ,calculate .

[0062] 3.3) The codeword after AMD encoding is... The final data matrix is .

[0063] By using LDPC encoding and interleaving, error correction capability is guaranteed while increasing the total data volume and improving the error detection probability after AMD encoding. After AMD encoding, storage or transmission is based on individual AMD codewords, which can resist large-scale burst errors when several AMD codewords are completely corrupted.

[0064] Step 4, AMD code decoding stage: 4.1) Assume the read data matrix is For any row ,calculate ,judge Is it equal to .

[0065] 4.2) If Then determine That is, the original data Output the decoding result ;like Then determine Not the original data Mark the entire line as an erase error and output the decoding result. , For length and The same vector, but all positions are marked as erased. If ,but If an error occurs but is not detected, the AMD code decoding fails, and the probability of failure is... If there is If an AMD codeword is corrupted, the probability of it being completely detected is: .

[0066] 4.3) The matrix output after decoding all rows using the AMD code is: to isomorphize its elements to The above yields the data matrix. .

[0067] Step 5, Uninterruption Phase: 5.1) Data matrix Each column Each column is grouped into a set of columns, and the resulting matrix is... Represented as Rearrange the groups by row to obtain the data matrix. , obtained That is, each corrupted LDPC codeword read.

[0068] Step 6, LDPC code decoding stage: 6.1) As can be seen from the above steps, in any data read... In this process, all errors have been marked as erased, and the data not marked as erased is considered correct. Decoding is performed using an LDPC code erase decoder. If the percentage of erased bits in the total number of bits is less than the threshold for LDPC codes in a binary erase channel... If the bit error rate approaches 0, then the bit error rate will be close to 0.

[0069] like Figure 2 As shown, an embodiment of the present invention provides an encoding and decoding system for improving the error correction capability of LDPC codes, specifically comprising: The LDPC code encoding module is used to encode information. Encode using LDPC code.

[0070] The interleaving module is used to interleave multiple LDPC codewords.

[0071] The AMD code encoding module is used to encode the interleaved data matrix using AMD codes.

[0072] The AMD code decoding module is used to decode the received data matrix into AMD code, and marks any errors as to be erased.

[0073] The deinterleaving module is used to deinterleave and restore LDPC codewords.

[0074] The LDPC code decoding module is used for decoding with an LDPC code decoder.

[0075] This invention combines algebraic manipulation codes with LDPC codes to provide a reliable solution for storage and communication scenarios with large-scale burst errors. It features low redundancy and low complexity, significantly improves error correction performance, and is suitable for fields or products prone to large-scale burst errors, such as magnetic tape, hard disk storage, and parallel communication systems.

[0076] This invention has significant advantages over existing technologies. The following is a specific example to demonstrate the error correction process and the probability of correction: Step 1, LDPC code encoding stage: 1.1) Selecting a finite field The above parameters are of Rule LDPC code, extract Information , .

[0077] 1.2) Encode the information using LDPC code to obtain the encoded codeword. .

[0078] Step 2, Interweaving Phase: 2.1) Take LDPC codewords After transposing, the columns are arranged to form a size of matrix .

[0079] 2.2) with each Divide the data into groups, then rearrange the groups sequentially by column to obtain a result of size [value]. matrix .

[0080] Step 3, AMD code encoding stage: 3.1) For any row According to each Divide the elements into groups, and each group is considered as... Vectors on, and isomorphic to them The elements on the vector are obtained. .

[0081] 3.2) Let Take a random element ,calculate .

[0082] 3.3) The codeword after AMD encoding is... The final data matrix is .

[0083] Will Each line, i.e., each AMD codeword, is transmitted or stored as a basic transmission or storage sequence. A large-scale burst error manifests as a complete error in the entire transmission or storage sequence. In this scenario, the received data is decoded.

[0084] Step 4, AMD code decoding stage: 4.1) Assume the read data matrix is For any row ,calculate ,judge Is it equal to .

[0085] 4.2) If Then determine That is, the original data Output the decoding result ;like Then determine Not the original data Mark the entire line as an erase error and output the decoding result. , For length and The same vector, but all positions are marked as erased. If ,but If an error occurs but is not detected, the AMD code decoding fails, and the probability of failure is... If there is If an AMD codeword is corrupted, the probability of it being completely detected is: , approximately 1.

[0086] 4.3) The matrix output after decoding all rows using the AMD code is: to isomorphize its elements to The above yields the data matrix. .

[0087] Step 5, Uninterruption Phase: 5.1) Data matrix Each column Each column is grouped into a set of columns, and the resulting matrix is... Represented as Rearrange the groups by row to obtain the data matrix. , obtained That is, each corrupted LDPC codeword read.

[0088] Step 6, LDPC code decoding stage: 6.1) As can be seen from the above steps, in any data read... In this process, all errors have been marked as erased, and the data not marked as erased is considered correct. Decoding is performed using an LDPC code erase decoder. If the percentage of erased bits in the total number of bits is less than the threshold for LDPC codes in a binary erase channel... Then the bit error rate approaches 0. In this example, for - Regular LDPC code, binary erase channel threshold The binary symmetric channel threshold is only This encoding / decoding scheme can at most... In the event of a large-scale burst error in a basic transmission or storage sequence, The probability of this makes the bit error rate approach 0. If only the traditional LDPC code scheme is used, then at most... In the event of a large-scale burst error in a basic transmission or storage sequence, the bit error rate approaches 0.

[0089] like Figure 3 As shown, the relationship curve between the probability of burst errors δ and the symbol error rate after decoding under burst error channel conditions is presented, comparing the performance difference between the method used in this embodiment and the traditional LDPC decoding method. It can be seen that throughout the entire range of δ values, the symbol error rate of the method of this invention is consistently lower than that of the traditional method, and the performance gap gradually widens as δ increases. Especially in the high burst error probability region, the method of this invention can still maintain the symbol error rate at a low level, while the symbol error rate of the traditional method increases significantly. This indicates that the method of this invention has stronger suppression capability and better decoding stability when dealing with highly correlated, clustered burst errors, thereby effectively improving the reliability of the system under harsh channel conditions.

[0090] like Figure 4As shown, the performance curves of the LDPC code of this invention under a binary symmetric channel (BSC) as a function of the crossover probability p are presented. It can be seen that when p is large, the system bit error rate is high, but as p gradually decreases, the bit error rate shows a significant and rapid decreasing trend. When p decreases below a certain threshold, the bit error rate quickly enters the range of 10. -4 At and below the level, it exhibits typical waterfall characteristics, indicating that the encoding and decoding structure of this invention can effectively utilize channel redundancy, achieve efficient error correction in random independent error environments, and ensure rapid performance improvement of the system when channel conditions improve.

[0091] like Figure 5 As shown, the performance curves of the LDPC code of this invention under binary erase channel (BEC) conditions, as a function of the erase probability ε, are presented. It can be seen that as the erase probability decreases, the bit error rate also exhibits a rapid decreasing trend. Even at a high erase ratio, the system still possesses a certain recovery capability. Furthermore, when the erase probability is further reduced, the system can achieve reliable transmission with near-zero bit errors. This demonstrates that the code structure of this invention has good recovery capability and stable iterative convergence characteristics for erased information, thus ensuring the applicability and robustness of the system in erase-type channel environments.

[0092] comprehensive Figures 3 to 5 It can be seen that the method of the present invention not only has significant advantages in sudden error scenarios, but also maintains good performance in random error and erasure error environments, demonstrating the versatility, stability and superiority of the present invention under various channel conditions.

[0093] It should be noted that embodiments of the present invention can be implemented in hardware, software, or a combination of both. The hardware portion can be implemented using dedicated logic; the software portion can be stored in memory and executed by a suitable instruction execution system, such as a microprocessor or dedicated-design hardware. Those skilled in the art will understand that the above-described devices and methods can be implemented using computer-executable instructions and / or included in processor control code, for example, such code provided on a carrier medium such as a disk, CD, or DVD-ROM, a programmable memory such as read-only memory (firmware), or a data carrier such as an optical or electronic signal carrier. The devices and modules of the present invention can be implemented by hardware circuitry such as very large-scale integrated circuits or gate arrays, semiconductors such as logic chips, transistors, or programmable hardware devices such as field-programmable gate arrays, programmable logic devices, etc., or by software executed by various types of processors, or by a combination of the above-described hardware circuitry and software, such as firmware.

[0094] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any modifications, equivalent substitutions, and improvements made by those skilled in the art within the scope of the technology disclosed in the present invention, and within the spirit and principles of the present invention, should be covered within the scope of protection of the present invention.

Claims

1. A method for improving the error correction capability of LDPC codes, characterized in that, Includes the following steps: (1) Encode the input information using a low-density parity check code to generate the corresponding codeword; (2) Interleave the multiple codewords to form an interleaving matrix; (3) Systematically encode each row of the interleaving matrix using algebraic manipulation detection codes to generate a data matrix with random verification parameters; (4) Decode the algebraic manipulation detection code at the decoding end. If the detection fails, mark the data in that row as erased. (5) Perform deinterleaving operation on the decoded data to recover the original low-density parity check codeword; (6) Use a low-density parity-check code decoder for iterative decoding. If the percentage of erased bits is lower than the binary erase channel threshold, output the decoding result.

2. The method of claim 1, wherein, The low-density parity-check code is an [n,k] code defined on a binary finite field. The input information is divided into u sequences of length k, and each sequence is encoded to obtain u codewords of length n.

3. The method according to claim 1, characterized in that, In the interleaving step, the u codewords are arranged in columns to form an n×u matrix, and then recombined in columns with each M row to generate an interleaving matrix of size M×(nu / M), which is used to equalize the distribution of burst errors.

4. An algebraic manipulation detection coding method for improving error correction and detection capabilities, characterized in that, Includes the following steps: (1) Select a finite field F_(2^l) and divide each row of the interleaving matrix into several groups of length l; (2) Convert each set of bit vectors isomorphic to the elements in the finite field F_(2^l) to obtain a vector of length r; (3) Randomly select an element x_i for each row and calculate the check value f_i, where f_i is equal to x_i raised to the power of r+2 plus the sum of the products of each group of elements and the powers of x_i; (4) Expand the obtained encoding result into a vector (s_i, x_i, f_i) to form the system algebraic manipulation detection codeword.

5. The algebraic manipulation detection coding method according to claim 4, characterized in that, The probability of failure in algebraically manipulated detection codes is (r+1) / 2^l. When t codewords are completely wrong, the probability of perfect detection is (1 / 2)^l. (r+1) / 2^l) raised to the power of t.

6. A decoding method based on algebraic consistency verification, characterized in that, Each line of data received by the receiving end contains an information vector, a random element, and a check value. The decoding process is as follows: (1) Calculate the theoretical verification value based on the received random elements; (2) Compare the calculation result with the received check value. If they match, output the information line. If they do not match, mark the information line as an erasure vector. (3) The erase vector consists of erase markers of the same length as the information line, used to indicate that the data in that line is unbelievable.

7. A method for interleaving and deinterleaving based on matrix column grouping, characterized in that: Interleaving operations distribute multiple low-density parity check codewords evenly across different data blocks by grouping matrix rows and rearranging columns. The deinterleaving operation reverses the order of the decoded matrix columns to recover the original low-density parity-check code structure.

8. A low-density parity check code decoding method incorporating an erasure flag input, characterized in that: Before iterative decoding, the bit positions marked as to be erased by algebraic manipulation detection decoding are used as fixed zero-confidence inputs; The decoder is iteratively updated based on the belief propagation algorithm. When the proportion of erased bits is less than the erase threshold of the low-density parity check code, the output decoding error rate approaches zero.

9. A coding and decoding system for improving the error correction capability of low-density parity-check codes, characterized in that, include: The LDPC code encoding module is used to perform low-density parity check encoding on the input information. The interleaving module is used to interleave and arrange multiple codewords. The AMD code encoding module is used for algebraic manipulation detection encoding of interleaved data; The AMD code decoding module is used to perform algebraic verification on the received data and output an erasure flag. The deinterleaving module is used to recover the original LDPC codewords; The LDPC decoding module is used to perform belief propagation decoding and output the original information.

10. The system according to claim 9, characterized in that, The AMD code decoding module and the LDPC decoding module are connected through an intermediate erase buffer. The buffer is used to store the erase flag and corresponding data location after AMD decoding, so as to realize hardware and software collaborative error correction.

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