Doppler log power supply control method and system based on hierarchical intelligent control

Abstract

The application relates to the technical field of ocean exploration measurement, and discloses a Doppler log power supply control method and system based on hierarchical intelligent control, which comprises the following steps: acquiring and adaptively filtering original electrical and environmental signals by using a multi-parameter dynamic detection module; performing integration autoregressive moving average model identification based on load current sampling data by using a load adaptive adjustment module, and outputting predicted load current values; combining the prediction results to generate a feedforward instruction, so as to adjust the target switching frequency, duty cycle and working mode of a direct-current-to-direct-current conversion circuit; and using a stability verification layer to evaluate control loop indexes in real time based on a linear periodic time-varying Nyquist criterion, and sending an instruction change control parameter or a warning threshold at an instability critical point. The application improves the power conversion efficiency and dynamic response lag problem under a variable load environment, and improves the anti-disturbance capability and operation reliability of a Doppler log power supply system.

Description

Technical Field

[0001] This invention relates to the field of marine exploration and measurement technology, and more specifically, to a power control method and system for a Doppler log based on hierarchical intelligent control. Background Technology

[0002] As a core device for underwater navigation and ocean exploration, the Doppler log's echo signal-to-noise ratio and velocity measurement accuracy are highly dependent on the stability of the power supply. In actual mapping operations, the Doppler log switches frequently between high-power acoustic transmission, data processing, and standby / sleep modes according to a fixed sequence, causing the power supply's load current to exhibit significant periodic jumps and large dynamic range surges. Currently, most industry solutions use linear regulators with fixed parameter configurations or conventional pulse-width modulation switching power supplies. These solutions suffer from high switching losses under light load conditions, resulting in low overall conversion efficiency. Furthermore, when faced with sudden load reduction or addition, they can only rely on the error integral of the feedback closed loop for hysteresis compensation, resulting in inherent response delays that can easily trigger unacceptable voltage overshoots or transient drops on the bus.

[0003] Furthermore, traditional power supply systems often employ frequency domain evaluation methods based on small-signal linear time-invariant models when calibrating stability. However, Doppler log power supplies, under the aforementioned variable load conditions, are essentially linear periodic time-varying systems. Using traditional static frequency domain criteria to evaluate design margins often leads to overly optimistic assessments. Especially under the instantaneous high-current surge during acoustic wave emission, the existing control loop is easily excited to generate high-frequency oscillations. Existing power management solutions generally lack real-time fusion sensing of multi-source environmental parameters, forward-looking prediction of load change trends, and online verification mechanisms for control loop stability under variable operating conditions. This makes it difficult to simultaneously improve energy efficiency across the entire load range while ensuring long-term operational reliability in the harsh power supply environment of deep sea. Summary of the Invention

[0004] This invention provides a power control method and system for a Doppler log based on hierarchical intelligent control, which solves the technical problems mentioned in the background art.

[0005] Firstly, a power control method for a Doppler log based on hierarchical intelligent control includes:

[0006] The sensor data is filtered to obtain real-time electrical parameters and real-time environmental parameters. The real-time electrical parameters include load current sampling data and feedback voltage sampling data, and the real-time environmental parameters include ambient temperature parameters.

[0007] Based on the load current sampling data, an identification calculation is performed to obtain the predicted load current value and the prediction error amplitude.

[0008] The difference between the feedback voltage sampling data and the set output voltage reference value is calculated to generate an error signal, and the feedback duty cycle is obtained based on the error signal.

[0009] The feedforward compensation command is generated based on the predicted load current value and is used to control the target switching frequency, target duty cycle and target operating mode of the DC to DC conversion circuit by combining with the feedback duty cycle to form a closed-loop control loop.

[0010] The stability index of the closed-loop control loop is calculated. When the stability index reaches the set instability critical threshold, a correction command containing changes to control parameters or warning thresholds is sent to the intelligent control layer and the protection circuit.

[0011] Secondly, a Doppler odometer power supply control system based on hierarchical intelligent control executes any one of the described hierarchical intelligent control-based Doppler odometer power supply control methods, applied to a Doppler odometer power supply. The Doppler odometer power supply includes a power supply hardware module, an intelligent control layer, and a stability verification layer. The power supply hardware module includes an input filter circuit, a DC-DC conversion circuit, a feedback control circuit, and a protection circuit. The DC-DC conversion circuit includes a switching transistor, a freewheeling diode, and an energy storage inductor. The intelligent control layer includes a multi-parameter dynamic detection module, a load adaptive adjustment module, and a fuzzy proportional-integral-derivative control module. The system includes:

[0012] The sensor data is filtered using the multi-parameter dynamic detection module to obtain real-time electrical parameters and real-time environmental parameters. The real-time electrical parameters include load current sampling data and feedback voltage sampling data, and the real-time environmental parameters include ambient temperature parameters.

[0013] The load adaptive adjustment module performs identification calculations based on the load current sampling data to obtain the predicted load current value and the prediction error amplitude.

[0014] The fuzzy proportional-integral-derivative control module calculates the difference between the feedback voltage sampling data and the set output voltage reference value to generate an error signal, and the feedback duty cycle is obtained based on the error signal.

[0015] The load adaptive adjustment module generates a feedforward compensation command based on the predicted load current value, which is then fused with the feedback duty cycle to control the target switching frequency, target duty cycle, and target operating mode of the DC-DC converter circuit, forming a closed-loop control circuit.

[0016] The stability verification layer calculates the stability index of the closed-loop control loop. When the stability index reaches the set instability critical threshold, a correction command containing changes to control parameters or warning thresholds is sent to the intelligent control layer and the protection circuit.

[0017] Beneficial effects include: establishing a closed-loop hierarchical control system encompassing perception, decision-making, execution, and verification; introducing a load look-ahead prediction mechanism based on an integrated autoregressive moving average model; and combining this with feedforward duty cycle compensation and dynamic optimization of switching frequency to eliminate transient voltage drops and overshoots caused by high-frequency switching of the Doppler log's operating modes; significantly reducing switching and conduction losses over a wide load range by combining hysteresis switching determination of continuous and discontinuous conduction modes; and introducing real-time assessment of linear periodic time-varying Nyquist stability, dynamically triggering parameter adjustment and smooth derating when the system approaches the instability critical point, effectively suppressing high-frequency oscillations caused by multivariate coupled disturbances in complex marine environments, and improving the power supply stability and overall energy efficiency of the Doppler log across the entire operating range. Attached Figure Description

[0018] Figure 1 This is a waveform diagram of output voltage and load current under the multi-stage load step response of the present invention;

[0019] Figure 2 This is the target switching frequency adaptive adjustment curve under comprehensive disturbance conditions of the present invention;

[0020] Figure 3 This is the online tuning curve of the digital compensator parameters under multi-parameter coupled disturbance of the present invention;

[0021] Figure 4 This is a frequency domain comparison diagram of the disturbance suppression ratio of the present invention and traditional PID control under the combined disturbance conditions of the present invention;

[0022] Figure 5 This is a radar chart showing the combined performance of the present invention and traditional PID control under multivariable coupled disturbances. Detailed Implementation

[0023] The subject matter described herein will now be discussed with reference to exemplary embodiments. It should be understood that these embodiments are discussed only to enable those skilled in the art to better understand and implement the subject matter described herein, and changes may be made to the function and arrangement of the elements discussed without departing from the scope of this specification. Various processes or components may be omitted, substituted, or added as needed in the examples. Furthermore, features described in some examples may be combined in other examples.

[0024] Example 1: A power control method for a Doppler log based on hierarchical intelligent control, comprising:

[0025] The sensor data is filtered to obtain real-time electrical parameters and real-time environmental parameters. The real-time electrical parameters include load current sampling data and feedback voltage sampling data, and the real-time environmental parameters include ambient temperature parameters.

[0026] Based on the load current sampling data, an identification calculation is performed to obtain the predicted load current value and the prediction error amplitude.

[0027] The difference between the feedback voltage sampling data and the set output voltage reference value is calculated to generate an error signal, and the feedback duty cycle is obtained based on the error signal.

[0028] The feedforward compensation command is generated based on the predicted load current value and is used to control the target switching frequency, target duty cycle and target operating mode of the DC to DC conversion circuit by combining with the feedback duty cycle to form a closed-loop control loop.

[0029] The stability index of the closed-loop control loop is calculated. When the stability index reaches the set instability critical threshold, a correction command containing changes to control parameters or warning thresholds is sent to the intelligent control layer and the protection circuit.

[0030] S201 synchronously acquires raw electrical signals and raw environmental signals.

[0031] Specifically, multi-channel data synchronous extraction is performed based on a unified timer trigger pulse. In some optional implementations, a unified sampling period set by the system is acquired, specifically 50 microseconds. Further, an analog-to-digital converter is used to synchronously acquire the direct output status values ​​of the voltage and current sensors within this unified sampling period. The acquired set of digital real values ​​representing the input voltage status, output voltage status, and actual load current is collectively set and marked as the original electrical signal. Simultaneously, the direct output status values ​​of the temperature and pressure sensors deployed on the surface of the external water body and the heating components of the circuit are acquired. The acquired set of digital real values ​​representing the spatial depth of the water body and the associated ambient temperature is collectively set and marked as the original environmental signal. Finally, all sensor sampling and extraction actions are synchronously activated by a single parallel interrupt instruction triggered by the timer source, ultimately merging in the system memory to generate a data frame combination matrix with a unified timestamp alignment.

[0032] S202, Obtain the signal change rate of the original electrical signal.

[0033] Specifically, the corresponding value of the original electrical signal belonging to the current sampling time sequence is extracted from the system memory data buffer, and the corresponding value of the original electrical signal belonging to the previous adjacent sampling time sequence is retrieved from the memory and stored in the history register. In some optional embodiments, the obtained corresponding value of the original electrical signal belonging to the current sampling time sequence is used as the minuend, and the corresponding value of the original electrical signal belonging to the previous adjacent sampling time sequence is used as the subtrahend. A scalar subtraction operation is performed in the central arithmetic logic unit to obtain the difference real number value output by the scalar subtraction operation. Further, an absolute value extraction calculation is performed on the difference real number value in the mathematical domain to remove its negative sign attribute. The finally extracted absolute real number value without direction attribute is defined and marked as the signal change rate of the original electrical signal. Finally, if the recorded load data at the current moment corresponds to a value of 1.5 and the recorded load data at the previous moment corresponds to a value of 0.9, the value of 0.6, which is the combined output of the above scalar subtraction and absolute value calculation, is taken as the signal change rate corresponding to the specific numerical dimension.

[0034] S203, based on the comparison result between the signal change rate and the set signal change rate threshold, select the corresponding dynamic filtering coefficient.

[0035] Specifically, a constant value limit is set in the system's built-in initialization parameter configuration document to define whether the device is in a stable operating band or a transient transition band, and this preset constant value limit is designated as the signal change rate threshold. In some optional implementations, for a single-dimensional load parameter parsing and calculation channel, the fixed floating-point value of the signal change rate threshold is set to 0.5 amperes per sampling period. Further, the system extracts the single floating-point value of the signal change rate obtained from independent calculation and sends it as active input data to the logic comparison operator calculation unit, and performs a direction relationship determination based on the size hierarchy with the signal change rate threshold pre-stored in the static memory block. Finally, based on the Boolean flag result of the condition judgment of the logic comparison operator outputting a relationship greater than or equal to the hierarchy or less than the hierarchy, the system activates the corresponding preset condition allocation execution branch, assigns and extracts the corresponding floating-point coefficient value from the coefficient value array pre-loaded into the buffer pool, and marks the assigned and extracted floating-point coefficient value as the dynamic filtering coefficient.

[0036] S204, when the signal change rate is greater than or equal to the signal change rate threshold, select the first filter coefficient and set the first time constant of the first-order exponential weighted moving average filter.

[0037] Specifically, when the output status of the hardware logic comparison unit indicates that the rate of change of the independently calculated output signal is greater than or equal to the signal rate of change threshold initially set by the system, the system is determined to be in a transient phase where the load exhibits a step-like sudden increase or decrease due to a rapid mode switching action. In some optional implementations, during this transient phase, the control processing logic automatically activates the data update weight upper limit assignment process, directly calling a floating-point real constant with large weight characteristics from the numerical storage array as the first filter coefficient, and setting the specific floating-point value of the first filter coefficient to 0.8. Further, the first filter coefficient with the value of 0.8 is directly assigned to the dynamic filter coefficient as the only active variable of the current calculation cycle. Finally, under the dominant role of this floating-point real coefficient of a specific size, a network mapping architecture with arithmetic smoothing delay characteristics is constructed, and a specific response delay duration interval corresponding to a shorter lingering waiting process is generated on the time axis. The parameter time span combination configuration scheme, which covers a range of 2 to 3 cycles and corresponds to 100 to 150 microseconds, is defined as the first time constant of the first-order exponentially weighted moving average filter.

[0038] S205, when the signal rate of change is less than the signal rate of change threshold, a second filter coefficient is selected, and a second time constant of the first-order exponentially weighted moving average filter is set; the second filter coefficient is less than the first filter coefficient, and the second time constant is greater than the first time constant.

[0039] Specifically, when the output status of the hardware logic comparison unit indicates that the absolute value of the independently calculated signal change rate is less than the signal change rate threshold initially set by the system, the system is determined to be in a steady-state phase with a smooth working power consumption amplitude. In some optional implementations, during this steady-state phase, the control processing logic automatically activates the data update weight lower limit assignment process, calling another floating-point real constant with small weight characteristics from the numerical storage array as the second filter coefficient, and setting the specific floating-point value of the second filter coefficient to 0.2. Further, the second filter coefficient with a value of 0.2 is directly assigned to the dynamic filter coefficient as the only active variable of the current calculation cycle. Finally, under the dominant effect of the floating-point real coefficients of this specific size, another specific response delay duration interval corresponding to a longer memory retention waiting process is generated on the time axis. The parameter time span combination configuration scheme covering the numerical distribution within a range of 8 to 10 periods, corresponding to 400 to 500 microseconds, is defined as the second time constant of the first-order exponentially weighted moving average filter. Performing a direct comparison of the real number characteristics of the two sets of initialized parameters shows that the second filter coefficient with a floating-point value set to 0.2 is smaller than the first filter coefficient with a floating-point value set to 0.8 on the basic arithmetic logic scale, and the second time constant with a numerical distribution span of 8 to 10 time periods is larger than the first time constant with a numerical distribution span of only 2 to 3 time periods on the total duration measurement span.

[0040] S206, using the dynamic filtering coefficients, perform data processing steps on the original electrical signal through the first-order exponentially weighted moving average filter, and output the real-time electrical parameters.

[0041] Specifically, after obtaining the dynamic filter coefficients, which are directly assigned specific floating-point feature values, the digital signal processing module containing the floating-point processing kernel is invoked to perform a time-domain weighted smoothing cumulative extrapolation calculation process based on the principle of first-order difference equations. In some optional implementations, the real value of the original electrical signal acquired in real time under the current clock cycle sequence is used as the first multiplier input, and the dynamic filter coefficients effective in the current calculation loop are used as the second multiplier input. A scalar multiplication operator operation is performed to obtain a single first product real value. Further, a real digital constant 1 is extracted from the system read-only static constant data pool, and a subtraction operator operation is performed between the real digital constant 1 and the current dynamic filter coefficients to obtain their corresponding complementary weighted difference value. The historical calculation extrapolation data record result, which was finally output and retained in the previous calculation extrapolation loop, is retrieved from the register address, and the historical calculation extrapolation data record result is again subjected to a scalar multiplication operator operation with the complementary weighted difference value obtained in the previous step to obtain a single second product real value. Finally, the independently calculated first product real value and the second product real value are fed into the internal adder-accumulator in parallel to perform summation and addition operations. The final stable real value output by the internal adder-accumulator is written to the corresponding target memory address to complete the iterative overwrite operation of historical old data. The stable real value is then set to be output as the real-time electrical parameter generated by the overall processing within the current calculation cycle.

[0042] S301, perform first-order differential processing on the load current sampling data to eliminate the data trend term from satisfying the sequence stationarity condition.

[0043] Specifically, the real value of the load current sampling data corresponding to the current sampling clock cycle sequence is extracted from the system memory data buffer or history register. In some optional implementations, historical real values ​​of the load current sampling data stored in the previous adjacent sampling clock cycle sequence are extracted; the real value of the load current sampling data corresponding to the current sampling clock cycle sequence is used as the minuend, and the historical real value of the load current sampling data in the previous adjacent sampling clock cycle sequence is used as the subtrahend, and a scalar subtraction operation is performed in the central processing unit's arithmetic logic unit. Further, the difference real value directly output by this scalar subtraction operation is used as the first-order difference feature result corresponding to the current time node. Finally, the above-mentioned scalar subtraction operation based on adjacent data coordinate points is repeatedly performed on the continuously arriving load current sampling data to construct a differential feature sequence on the time axis. The difference distribution between adjacent original data is used to replace the absolute size distribution of the original values ​​themselves, weakening and stripping the unidirectional increasing or decreasing trend term characteristics formed by the slow drift accumulation of external physical conditions in the original acquisition sequence. This makes the expected value and variance mean of the overall evolution data sequence fluctuate within a fixed floating-point range close to a constant 0 on the time axis, thereby outputting a stationary dynamic data sequence without a fixed rising or falling slope. This realizes the first-order differential processing of the load current sampling data to eliminate the data trend term and satisfy the sequence stationarity condition.

[0044] S302, extract the load current value of the set number of historical periods as the autoregressive term, extract the prediction error of the set number of historical periods as the moving average term, and establish an integrated autoregressive moving average prediction model.

[0045] Specifically, in the system initialization parameter configuration list, a time span parameter limit range for characterizing the historical correlation and hysteresis effect of the load dynamics is set, and a constant of 4 is extracted as the number of historical periods controlling the autoregressive order. In some optional implementations, the first-order difference characteristic result real number sequence generated by performing first-order difference operation on the load current sampling data of the past four processing cycles is continuously traced and extracted in reverse chronological order in the memory buffer, and these four difference real number values ​​are collectively classified and combined and set as the autoregressive term. Further, a constant of 2 is extracted as the number of historical periods controlling the moving average order, and the residual floating-point values ​​between the actual measured data values ​​and the pre-calculated theoretical prediction values ​​of the past two processing cycles are continuously extracted from the register address where the system records the historical records of prediction behavior deviations, and these two residual floating-point values ​​are collectively classified and combined and set as the moving average term. Finally, a linear polynomial structure computational framework network is established in the digital signal processing kernel control logic. This polynomial structure computational framework network includes four autoregressive proportional coefficient factor channel branches that are multiplied by the numerical nodes corresponding to the autoregressive term, and two moving average coefficient factor channel branches that are multiplied by the numerical nodes corresponding to the moving average term. The original acquired values ​​of the load current sampling data of the current processing cycle are superimposed onto the end summation node of this computational framework network as the basic bias term reference. In this way, the above data structure entity parameter nodes and multiplication calculation channels are merged and integrated to establish the integrated autoregressive moving average prediction model.

[0046] S303, using the data observation vector and gain matrix, update the autoregressive coefficients and moving average coefficients of the integrated autoregressive moving average prediction model using the recursive least squares method with a forgetting factor.

[0047] Specifically, within the constructed integrated autoregressive moving average prediction model calculation framework, a one-dimensional real matrix data sequence entity with a total length dimension of constant 6 is obtained by sequentially concatenating the real number sequences of first-order difference feature results from four past periods and the floating-point residual values ​​from two past periods in chronological order. This one-dimensional real matrix data sequence entity with a total length dimension of constant 6 is set as the data observation vector. In some optional implementations, in the model parameter adaptive adjustment algorithm update module, a real floating-point diagonal structure matrix with a spatial dimension distribution of 6 rows and 6 columns is allocated and configured, and its label is set as the gain matrix; a floating-point coefficient is set to control the decay rate of historical old data in the calculation weights, and the floating-point coefficient has a value of constant 0.98. This floating-point coefficient with a value of constant 0.98 is used as the forgetting factor in the recursive least squares algorithm operation logic with forgetting factor. Furthermore, the forgetting factor is used to perform scaling division operations on the matrix positions of all elements of the inverse covariance matrix of the previous calculation processing cycle, and the distribution size of each numerical element of the gain matrix corresponding to the current processing cycle is recalculated by combining the projection result of the transpose dot product of the data observation vector corresponding to the current state cycle. Finally, the one-dimensional floating-point sequence of model coefficients retained from the previous calculation cycle is obtained. The scalar arithmetic residual difference between the actual change difference floating-point value of the current cycle and the theoretical change difference floating-point value predicted by the cumulative summation of the one-dimensional floating-point sequence of model coefficients is calculated. The newly updated gain matrix and the scalar arithmetic residual difference are then subjected to matrix-scalar multiplication to generate a one-dimensional parameter vector consisting of six floating-point directional compensation values. This one-dimensional parameter vector is then combined and summed with the one-dimensional floating-point sequence of model coefficients retained from the previous calculation cycle using corresponding vector addition based on the same index position. This completes the iterative coverage update operation of the numerical values ​​of the model's core running parameter queue. The first four floating-point values ​​from the parameter queue entity after the iterative coverage update are extracted in order and set as the autoregressive coefficients. The remaining two floating-point values ​​are extracted and set as the moving average coefficients. Thus, using the data observation vector and the gain matrix, the autoregressive coefficients and moving average coefficients of the integrated autoregressive moving average prediction model are updated using the recursive least squares method with a forgetting factor.

[0048] S304, input the updated autoregressive coefficients and moving average coefficients into the integrated autoregressive moving average prediction model, output the predicted load current value for the target period, and calculate the prediction error amplitude.

[0049] Specifically, the integrated autoregressive moving average prediction model, which has been constructed within the system and contains a linear network structure with multiple convergence channels for addition and multiplication operations, is retrieved. In some optional implementations, the autoregressive coefficients, which are generated through iterative updates and contain four floating-point values, are subjected to one-to-one scalar multiplication with the actual values ​​of the first-order difference feature results corresponding to the four historical stages in the autoregressive term, according to the matching rules of time extension depth, to obtain four independent real values ​​of the first product operation; the moving average coefficients, which are generated through iterative updates and contain two floating-point values, are subjected to one-to-one scalar multiplication with the residual floating-point values ​​corresponding to the two historical stages in the moving average term, according to the matching rules of time extension depth, to obtain two independent real values ​​of the second product operation. Furthermore, the four independent first product operation real values ​​generated by the above-mentioned multiplication separation operation and the two independent second product operation real values ​​are fed into the accumulator component with multiple input terminals to perform a summation addition operator operation to obtain a temporary summation real value. Then, the temporary summation real value is added and combined with the actual collected value of the load current sampling data collected at the current time node. Finally, the predicted floating-point calculation result obtained by the final addition is transmitted and released to the external control terminal, and set as the predicted load current value output by the system for the next extended time series calculation window, i.e., the target period. After the actual physical quantity analog-to-digital conversion acquisition action at the target period time node is completely completed, the load current sampling data that actually occurs in the target period is acquired. The load current sampling data that actually occurs is subtracted from the predicted load current value that the system pre-generated and temporarily cached in the previous period. The difference result obtained directly from the subtraction operation is subjected to absolute value negative sign stripping calculation in the mathematical domain. The spatial measurement result of the real number without positive or negative direction reference sign is written to the corresponding memory record dial and set as the prediction error amplitude.

[0050] S305, when the prediction error amplitude continuously crosses the set error threshold, the identification calculation of the autoregressive coefficient and the moving average coefficient is re-executed.

[0051] Specifically, within the main loop monitoring process of the control system kernel, a floating-point constant comparison standard scale is pre-written and allocated to define the physical limit of the collapse tolerance of the forward prediction accuracy. This floating-point constant comparison standard scale is set to a constant of 0.15 amperes, and this scale with a value of 0.15 amperes is set as the error threshold. In some optional implementations, an integer constant of 3 is set in the internal logic condition-triggered accumulator counter as a critical constraint condition for continuous accumulation. Further, the system clock-driven controller extracts the independently calculated prediction error amplitude for each time-delay cycle, and sends the pure absolute magnitude measurement of the prediction error amplitude and the error threshold with a value of 0.15 amperes read from memory in parallel to the hardware logic comparator circuit to perform a numerical magnitude relationship evaluation and judgment operation. Finally, when the hardware logic comparator circuit determines that the input prediction error amplitude has an arithmetic relationship greater than the error threshold, the system control logic performs an increment operation of adding a constant 1 to the memory value of the internal logic condition trigger accumulator counter. When, within multiple consecutive time cycles, the memory value of the internal logic condition trigger accumulator counter reaches a preset integer constant 3 after multiple increment operations, satisfying the specific triggering condition set by the system that the prediction error amplitude continuously crosses the set error threshold, the system calculation management kernel sends an instruction to the algorithm. The update module sends the highest priority reset interruption signal code combination; this reset interruption signal code combination forcibly clears and erases the failed historical covariance data matrix that the system has determined is no longer able to match the current rapidly changing physical operation law of ocean exploration and evaluation. Then, it replaces the old matrix storage address with a new empty data matrix initialized with diagonal elements that present extremely large numerical characteristic constants, forcibly discards the old historical residual weight distribution memory, and then re-executes the identification calculation of the autoregressive coefficient and moving average coefficient on the basis of the new and clean initial condition matrix and the current instantaneously acquired sudden increase in current data.

[0052] S401, based on the predicted load current value, the set heavy load current threshold, and the light load current threshold, extract the corresponding theoretical switching frequency.

[0053] Specifically, a floating-point constant value representing the boundary of the system entering a high-power full-load operation state is extracted from the initialization parameter configuration table of the system memory. This value is set to 2.0 amps and marked as the heavy-load current threshold. Simultaneously, a floating-point constant value representing the boundary of the system in a low-power sleep or standby state is extracted and set to 0.5 amps, marked as the light-load current threshold. In some optional embodiments, the maximum and minimum extreme constants of the switching control frequency, which are pre-set by the system for the switching losses and electromagnetic interference limits of the physical power devices, are obtained. The maximum extreme constant is set to 350,000 Hz, and the minimum extreme constant is set to 150,000 Hz. Further, the real value of the predicted load current is extracted, and the real value of the predicted load current is subtracted from the constant 0.5 amperes corresponding to the light load current threshold to obtain the first real difference between the two; the constant 2.0 amperes corresponding to the heavy load current threshold is subtracted from the constant 0.5 amperes corresponding to the light load current threshold to obtain the second real difference reflecting the entire variable load span; the maximum extreme value constant 350000 Hz is subtracted from the minimum extreme value constant 150000 Hz to obtain the system adjustable frequency span difference constant 200000 Hz. Finally, the first difference real number is divided by the second difference real number to obtain a normalized scaling factor floating-point number distributed between constant 0 and constant 1. This normalized scaling factor floating-point number is then multiplied by a scalar multiplication operator with the frequency span difference constant of 200,000 Hz to obtain a dynamic frequency adjustment increment real value for the current expected load fluctuation. The minimum extreme value constant of 150,000 Hz and the dynamic frequency adjustment increment real value are then fed into an internal adder accumulator for a summation operation to finally obtain a target frequency real number that directly indicates the expected matching state of the current physical load. This target frequency real number is then output to the external transfer channel and set as the theoretical switching frequency.

[0054] S402, the target switching frequency is obtained by performing a first-order low-pass filter on the theoretical switching frequency.

[0055] Specifically, a floating-point real number set to a constant of 0.8 is extracted from the system's digital signal control parameter storage block, and this floating-point real number with a specific size of constant 0.8 is set as the frequency smoothing coefficient. In some optional embodiments, the real value of the theoretical switching frequency obtained in the current computation cycle is extracted, and the frequency smoothing coefficient constant 0.8 is subtracted from the system's internal constant arithmetic reference constant 1 to calculate the complementary weight constant 0.2 used to control the weight of the instantaneous sampled data. Further, the complementary weight constant 0.2 is multiplied with the real value of the theoretical switching frequency to obtain a first smoothed product real number representing the current transient target tendency; the historical application value of the switching frequency recorded in the previous independent computation cycle is retrieved from the internal historical data cache address, and the frequency smoothing coefficient constant 0.8 is multiplied with the historical application value of the switching frequency to obtain a second smoothed product real number representing the system's historical inertial state tendency. Finally, the first smoothed product real number and the second smoothed product real number, which are independently calculated and output, are input into the addition operation core node to perform a summation and addition operation, and output a final control frequency real number that has undergone time-axis weighted transition processing and stripped of high-frequency abrupt transition components; write the final control frequency real number into the corresponding period control register address of the underlying pulse width modulation generator, and set the final control frequency real number as the target switching frequency.

[0056] S403, determine the critical current characterizing the working mode switching boundary by combining the inductance parameters of the energy storage inductor and the target switching frequency.

[0057] Specifically, the physical calibrated fixed constant value of the inductive energy storage components actually arranged in the system hardware topology circuit is extracted, and the fixed constant value of the inductive energy storage component is set to 10 microhenries. This fixed constant value is marked as the inductance parameter of the energy storage inductor. In some optional embodiments, the real value of the DC bus input voltage, which is transmitted back in real time by the system voltage sensor through the digital-to-analog conversion channel, is obtained, and the currently sampled real value of the input voltage is set to 24 volts; the target output voltage reference standard constant value set in the closed-loop control of the system voltage outer loop is obtained, and the target output voltage reference standard constant value is set to 12 volts. Further, the real value of the input voltage (24 volts) is subtracted from the target output voltage reference standard constant (12 volts) to obtain the real value of the DC drop. A scalar multiplication operation is then performed between this real value of the DC drop and the target output voltage reference standard constant (12 volts) to calculate the numerator product representing the energy transfer product. The floating-point real value of the target switching frequency, which is updated in real time, is then obtained. A series of multiplications are performed on these three variables: the floating-point real value of the target switching frequency, the real value of the input voltage (24 volts), and the fixed constant value of the inductance parameter of the energy storage inductor (10 microhenries). The resulting product is then multiplied by a constant 2 to obtain the combined real value of the denominator representing the combined elements of discharge time and inductor impedance. Finally, the real number of the numerator product obtained from the above calculation steps is divided by the real number of the denominator to obtain the boundary judgment real number value used to define whether the current flowing inside the inductor drops to a constant 0 at the end of each cycle, thus causing a physical interruption of current flow; this boundary judgment real number value is written into the judgment logic of the power state machine management chip and set as the critical current.

[0058] S404, when the predicted load current value changes from the light load current range to the heavy load current range and crosses the set first hysteresis switching threshold, the target operating mode is controlled to switch to continuous conduction mode.

[0059] Specifically, the real value of the critical current obtained from the aforementioned steps is extracted. This real value of the critical current is then multiplied and scaled using a scalar multiplication with a pre-configured constant scaling factor of 1.1 to obtain an action trigger boundary constraint value that is positioned high to resist high-frequency load noise oscillations in the system. This action trigger boundary constraint value is written into the state determination logic and marked as the first hysteresis switching threshold. In some optional implementations, the system central controller kernel monitors and reads the numerical evolution trajectory of the predicted load current value in real time according to the timer interrupt cycle. Further, when the internal monitoring logic determines that the predicted load current value shows a continuously rising trend in the time axis based on the positive slope of the differential rate of change, i.e., when it determines that it is rising from the light load current range to the heavy load current range, the specific real value of the predicted load current value corresponding to the current exact time node is extracted. Finally, the specific real value of the predicted load current is synchronously sent to the underlying hardware logic comparator component for size evaluation and comparison with the first hysteresis switching threshold stored in memory. When the hardware logic comparator component determines that the specific real value of the predicted load current is greater than or equal to the first hysteresis switching threshold on a mathematical scale, that is, when it determines that the set first hysteresis switching threshold has been crossed, the system central controller kernel sends an uninterrupted current conduction execution instruction to the power switch timing drive circuit, modifies the generation logic branch of the switch control duty cycle calculation architecture, and controls the target working mode to switch to continuous conduction mode.

[0060] S405, when the predicted load current value changes from the heavy load current range to the light load current range and crosses the set second hysteresis switching threshold, the target operating mode is controlled to switch to the discontinuous conduction mode; the first hysteresis switching threshold is greater than the second hysteresis switching threshold.

[0061] Specifically, the real value of the critical current is re-extracted, and a scalar multiplication scaling calculation is performed between this real value and another pre-configured constant scaling factor of 0.9 to obtain a lower-positioned hysteresis trigger boundary constraint value. This hysteresis trigger boundary constraint value is written into the state determination logic and marked as the second hysteresis switching threshold. In some optional implementations, on the absolute metric scale of the numerical space, a mathematical constraint relationship is formed by the constant scaling factor of 1.1 and the constant scaling factor of 0.9 acting on the same basic parameter, corresponding to a geometric separation condition in the control architecture configuration where the first hysteresis switching threshold is greater than the second hysteresis switching threshold. Further, the system central controller kernel continuously monitors the evolution trajectory of the predicted load current value in a time sequence. When the internal monitoring logic determines that the predicted load current value shows a hysteresis trend of continuously decreasing value based on the negative slope of the differential rate of change, that is, when it is determined to be falling from the heavy load current range to the light load current range, the specific real value of the predicted load current value at the current time node is extracted again. Finally, the specific real value of the predicted load current and the second hysteresis switching threshold are sent to the hardware logic comparator component to perform a value judgment operation. When the output signal of the hardware logic comparator component indicates that the specific real value of the predicted load current is less than or equal to the second hysteresis switching threshold on a mathematical scale, that is, when it is determined that the set second hysteresis switching threshold has been crossed, the system central controller kernel issues a cut-off freewheeling execution command to the power switch timing drive circuit. At the end of each switch conduction cycle, a fixed parasitic capacitance oscillation cutoff dead zone discharge time distribution interval is forcibly injected, changing the basic theoretical calculation formula of the switch control duty cycle, and controlling the target working mode to switch to discontinuous conduction mode.

[0062] S501, combining the predicted load current value, the output voltage reference value, the detected input voltage, the forward voltage drop of the freewheeling diode, and the on-state voltage drop of the switching transistor, generates a feedforward duty cycle that maintains the output voltage in the steady-state range.

[0063] Specifically, relevant electrical characteristic real values ​​are obtained from the sampling records of the system memory or external analog-to-digital conversion circuit. In some optional implementations, a pre-set constant value for defining the target stable voltage is extracted from the system, set to 12 volts, and marked as the output voltage reference value; the real value of the DC voltage input at the current time point is obtained from the input sampling channel, set to 24 volts, and marked as the detected input voltage; the fixed voltage drop parameters of the nonlinear semiconductor devices retained in the hardware physical device parameter table are extracted, the forward conduction voltage drop constant of the freewheeling device is set to 0.3 volts, and marked as the forward voltage drop of the freewheeling diode; the internal conduction voltage drop constant of the power switching device is set to 0.2 volts, and marked as the conduction voltage drop of the switching transistor. Further, within the central arithmetic logic unit, the real value of the predicted load current obtained from the aforementioned calculation step's look-ahead deduction is extracted. This real value is then multiplied by a pre-configured constant of 0.05 ohms, representing the parasitic equivalent resistance of the line, to obtain a real value representing the dynamic voltage drop compensation that dynamically changes with the load. This dynamic voltage drop compensation value, the constant of 12 volts corresponding to the output voltage reference value, and the constant of 0.3 volts corresponding to the forward voltage drop of the freewheeling diode are fed into an adder for summation to obtain the sum of the real numerators at the dividend position. Simultaneously, the constant of 24 volts corresponding to the detected input voltage, the constant of 12 volts corresponding to the output voltage reference value, and the constant of 0.3 volts corresponding to the forward voltage drop of the freewheeling diode are summed, and the constant of 0.2 volts corresponding to the on-state voltage drop of the switching transistor is subtracted from the summation result to obtain the sum of the real denominators at the divisor position. Finally, the sum of the real numbers in the numerator is divided by the sum of the real numbers in the denominator by a scalar division operator operation. A floating-point value of the proportional coefficient, distributed between the constant 0 and the constant 1, is calculated and output. This floating-point value of the proportional coefficient is set as a whole and output to the subsequent register as the feedforward duty cycle. Associative calculations are then performed to generate the feedforward duty cycle that maintains the output voltage in the steady-state range.

[0064] S502, obtain the feedback duty cycle obtained by the fuzzy proportional-integral-derivative control module.

[0065] Specifically, the closed-loop error adjustment calculation subsystem residing in the control processor core is initiated and invoked, and this calculation subsystem is associated with and marked as the fuzzy proportional-integral-derivative (PID) control module. In some optional implementations, the fuzzy PID control module continuously receives a sequence of absolute deviation values ​​between the actual physical sampling feedback result of the external output voltage and the internal output voltage reference value. Further, at the time node of the current calculation cycle, the comprehensive control compensation ratio real number, which is the result of the online adaptive reconstruction of parameters by the fuzzy PID control module based on multi-level fuzzy logic rules, is directly read from the memory information interaction bus. This comprehensive control compensation ratio real number is then combined with the results of proportional amplification, deviation time integral accumulation, and deviation change differential derivation calculations performed on the current deviation characteristics. The value of this comprehensive control compensation ratio real number extracted in the current system control cycle is set to 0.45. Finally, the specific extracted real number with a value of 0.45 is used as the closed-loop correction benchmark factor for the real-time random fluctuations of the response system. It is received and temporarily stored in the input buffer register corresponding to the current operation area. It is directly identified and marked as the feedback duty cycle on the underlying control data link. In this way, the internal communication reading action is performed to obtain the feedback duty cycle processed by the fuzzy proportional integral derivative control module.

[0066] S503, the feedforward duty cycle is weighted and adjusted using the set feedforward gain.

[0067] Specifically, in the initialization parameter configuration memory list of the system main control program, a floating-point coefficient constant is pre-allocated and defined to control the strength of the look-ahead prediction signal's intervention in the overall synthesis instructions. In some optional implementations, the specific value of this floating-point coefficient constant is set to 0.6. This floating-point value of 0.6 is extracted and loaded into the central arithmetic unit and marked as feedforward gain. Further, within the execution pipeline of the digital signal processing unit, the real value of the feedforward duty cycle, independently calculated using the division rules of the dividend and divisor, is retrieved from the previous address. This real value of the feedforward duty cycle and the newly acquired feedforward gain value set to a constant of 0.6 are fed in parallel into the hardware digital multiplier array, where the multiplier array performs mathematical scalar multiplication. Finally, through this scalar multiplication and product operation, the duty cycle driving value derived from the original purely theoretical environment is proportionally reduced according to the current system's dependence weight ratio on the feedforward action, and a reference real value of duty cycle change after attenuation scaling is output. This reference real value of duty cycle change obtained by numerical scaling is written to a specific temporary operation data retention area address as a correction basis. Thus, the arithmetic processing action of adjusting the weight of the feedforward duty cycle using the set feedforward gain is completed.

[0068] S504, the feedforward duty cycle with the adjusted weight is added and merged with the feedback duty cycle, and the target duty cycle applied to the DC to DC conversion circuit is output. The output voltage fluctuation in the steady state range is compensated by introducing a parameter with predictive properties.

[0069] Specifically, the reference real value of the duty cycle change after the constant 0.6 multiplication ratio decay processing is retrieved again from the address of the temporary operation data reservation area, and this reference real value of the duty cycle change is set as the feedforward duty cycle of the adjustment weight. In some optional embodiments, the pre-acquired real value of the feedback duty cycle is extracted synchronously from the input buffer register configured in the aforementioned steps. Further, the feedforward duty cycle of the adjustment weight and the feedback duty cycle are combined and input into the hardware addition arithmetic node logic gate inside the microcontroller, where a direct scalar addition operation is performed. To prevent the combined real number obtained by addition and summation from overflowing the limits of semiconductor device drive at the physical boundary, overflow prevention logic is applied to the combined real number based on the minimum and maximum safe range of the lower limit constant 0 and the upper limit constant 1. When it is determined that the combined real number is greater than constant 1, its internal value is forcibly overwritten and truncated to constant 1. When it is determined that the combined real number is less than constant 0, its internal value is forcibly overwritten and assigned to constant 0. Finally, the final floating-point real value after this upper and lower limit threshold isolation protection process is converted and sent down as the matching duty cycle given value of the pulse width modulation generator, and set as the target duty cycle; the target duty cycle is converted into a physical level square wave control signal using the digital output pin and output to the external DC to DC conversion circuit; in the above overall addition and merging calculation flow steps, the feedforward duty cycle derived from the predicted load current value from the time source can intervene in the addition and summing stage in advance and forcibly provide a basic pre-compensation bias real quantity with a positive proportional increase or a negative proportional decrease before the actual load of the system causes a measurable deviation in the line bus voltage. This operation mechanism establishes a forward control shortcut in the mathematical domain that does not rely on hysteresis error, that is, by introducing parameters with predictive properties to compensate for output voltage fluctuations in the steady state range.

[0070] S601, using the dual sampling branches set in the feedback control circuit, acquires the control feedback current signal for closed-loop control and the overcurrent protection current signal for triggering hardware protection, respectively.

[0071] Specifically, two sets of physically isolated electrical signal acquisition channels are deployed within the feedback control circuit at the bottom layer of the power supply to construct the dual-path sampling branch. In some optional embodiments, the first channel is configured as a high-precision analog-to-digital conversion sampling branch. A low-temperature drift precision resistor network with a constant resistance of 0.01 ohms is deployed on this high-precision analog-to-digital conversion sampling branch as a sensor to perform real-time voltage drop extraction and conversion on the physical current flowing through the bottom-layer inductor energy storage element. Subsequently, the acquired small voltage drop signal is sent to an analog-to-digital converter with a constant 16-bit resolution depth to perform discretization digital sampling operator operations. The high-precision real-digit sequence finally converted and output by the analog-to-digital converter is set and marked as the control feedback current signal in the system control bus transmission layer. Furthermore, the second channel is configured as a high-speed analog comparison sampling branch. A non-inductive current transformer and a high-speed comparator circuit with a response delay time shorter than a constant 50 nanoseconds are deployed on this branch. The real-time voltage mapping value of the transient peak current is obtained through the non-inductive current transformer and directly connected to the input comparison terminal of the high-speed comparator circuit. This value is then compared with the pre-set overload limit trigger reference voltage value in an internal register at the nanosecond level. Finally, when the real-time voltage mapping value is arithmetically greater than the overload limit trigger reference voltage value, the high-speed comparator circuit directly flips outward to output a logic high-level sudden change pulse waveform. This logic high-level sudden change pulse waveform, used to characterize the risk of short-circuit or other abnormal damage to the underlying power semiconductor components and to directly interrupt the normal flow of the main control program, is set and marked as the overcurrent protection current signal.

[0072] S602, the control feedback current signal and the error signal are input into a digital compensator with coefficient update function.

[0073] Specifically, the error signal obtained by performing a subtraction operation between the real value of the preset output voltage reference standard and the actual output voltage value obtained by physical sampling in the upper-level voltage outer loop control flow link is acquired, and the floating-point deviation real data carried in the error signal is extracted. In some optional embodiments, a separate data arithmetic processing area containing a sequence of extended buffer registers for historical data and a multi-channel multiplication and accumulation calculation hardware array structure is allocated in the system digital processing kernel module, and this data arithmetic processing area is configured and uniformly set as the digital compensator. Further, the digital compensator has a static random access memory address block that can be dynamically read, written, and erased by the central controller bus control instructions mounted on its internal storage interaction bus, enabling it to update the coefficients of the internal filter calculation matrix numerical array in real time according to external update control instructions. Finally, at the discrete computation advancement time node of the current clock cycle, the real digital sequence of the control feedback current signal generated and sent by the high-precision analog-to-digital conversion sampling branch is extracted; the real digital sequence of the control feedback current signal and the error signal containing floating-point deviation real data, which are synchronously extracted, are synchronously transmitted to the input data buffer register array port of the configured digital compensator through the internal digital parallel data bus of the system, and used as the reference independent variable data source for performing multi-level discrete difference equation filtering derivation arithmetic operations in the current operation cycle.

[0074] S603, based on the state machine information of the target switching frequency, the predicted load current value, and the target operating mode combination, extract the feedforward compensation coefficient and the feedback compensation coefficient from the coefficient lookup table.

[0075] Specifically, a static read-only data index array with multi-dimensional spatial structure mapping characteristics is initialized, constructed, and permanently loaded in the main control heap memory of the system control layer. This static read-only data index array is set as the coefficient lookup table, which is presented as a three-dimensional, third-order addressing matrix array in the underlying data space organization structure. In some optional implementations, the system clock drive task extracts in real time the specific fixed real number value of the target switching frequency that the underlying physical drive control terminal is actually applying in the current time period, extracts the floating-point real number value of the predicted load current value generated in advance by the look-ahead prediction algorithm module, and extracts the state digital integer code identifier corresponding to the target working mode corresponding to the judgment interval of the current physical hardware system. Furthermore, the specific fixed real value of the target switching frequency, the floating real value of the predicted load current, and the state digital integer encoding identifier corresponding to the target operating mode are extracted and collected, and bitmask binary bit shifting and splicing combination processing is performed in a fixed data frame sequence. The string of digital sequence scalar entities with specific format rules generated by the completed bitmask splicing and combination is defined and marked as the state machine information. Using the state machine information as the memory pointer offset addressing reference, the nearest neighbor coordinate node distance measurement and matching search operation is performed within the three-dimensional addressing matrix array space of the pre-arranged coefficient lookup table. Finally, after locking the corresponding three-dimensional matrix entity addressing node in the internal space, two sets of floating-point constant combinations with discrete pulse frequency response adjustment characteristics are continuously read from the location matching address space block; the first set of dimensionless floating-point real vectors containing three constants representing the magnitude of the weighted gain characteristics of the front signal path are extracted and marked as the feedforward compensation coefficients; similarly, the second set of dimensionless floating-point real vectors containing three constants representing the magnitude of the attenuation characteristics of the feedback path pole positions are extracted and marked as the feedback compensation coefficients.

[0076] S604, using the feedforward compensation coefficient and the feedback compensation coefficient, reconstruct the filtering parameters of the digital compensator, perform adjustment calculations on the digital compensator, and generate the feedback duty cycle.

[0077] Specifically, an enable transition instruction pulse signal for performing a memory overwrite operation is sent to the control register bus input channel of the digital compensator. This overwrites the feedforward compensation coefficients (containing three floating-point real number vectors) and the feedback compensation coefficients (containing three floating-point real number vectors) extracted from the coefficient lookup table memory address block, pushing them into the storage area of ​​the independent high-speed static memory working address block corresponding to the underlying multiplication-accumulation calculation array circuit of the digital compensator. This utilizes the two newly invoked floating-point real number constant combinations to replace and completely erase the residual coefficient value memory features of the historical old cycles, completing the operation step of reconstructing the filtering parameters of the digital compensator at the parameter configuration level. In some optional embodiments, after completing the coefficient value reconstruction assignment for all multiplier branches, the rising edge of the clock signal triggers the internal discrete difference arithmetic derivation and summation pipeline process of the arithmetic unit. Furthermore, the input feature real number generated by algebraically adding and merging the error signal and the control feedback current signal in the current time period, as well as the input feature real numbers of the past constant 1 historical period and the input feature real numbers of the past constant 2 historical periods stored in the historical delay line record queue stack, are respectively combined with the three floating-point real number vectors of the feedforward compensation coefficients that are reconstructed and written over the data. A scalar multiplication operation with each position coordinate bound is performed in the hardware multiplier. The three independent product real number values ​​of the constants generated by the product are then sent in parallel to the addition logic node for merging and summation to obtain the sum of the real numbers of the feedforward path. Synchronously extract the historical output duty cycle real numbers of one historical period and two historical periods stored in the historical delay line record queue stack. Perform scalar multiplication operation with each position coordinate bound to the two extracted historical output duty cycle real numbers and the corresponding two floating-point real number vectors of the feedback compensation coefficient written in the reconstruction. Then, send the two independent product real numbers of the multiplication to another addition logic node for merging and summation to obtain the sum of real numbers of the feedback path. Perform scalar subtraction arithmetic operation between the sum of real numbers of the feedforward path obtained by calculation and derivation and the sum of real numbers of the feedback path. Finally, the difference floating-point real number, which is the final combined output of the scalar subtraction arithmetic operation, is subjected to a numerical boundary interval extreme value interception and truncation protection condition processing mechanism based on the upper limit constant 1 and the lower limit constant 0. The effective floating-point numerical result, which is finally output after passing through this arithmetic logic numerical truncation protection mechanism and whose physical magnitude is fixed within the continuous interval of constant 0 and constant 1, is directly transferred to the outer stage pulse width modulation logic unit for output data stream transfer and distribution operation, and the effective floating-point numerical result is set and marked as the feedback duty cycle.

[0078] S701, the protection circuit is used to compare the device operating status parameters with the set warning threshold and hardware limit threshold.

[0079] Specifically, multiple high-speed analog comparator chips and digital logic decision arrays are deployed within the protection circuit at the system's underlying layer. In some optional implementations, the real values ​​of inductor current and output voltage, which are acquired and converted in real time by a Hall sensor and a voltage divider resistor network at the current time point, are combined and arranged to form a data array representing the system's real-time load-bearing status, and are set and marked as the device's operating status parameters. Furthermore, a first-level safety judgment scale constant is pre-configured and written into the static random access memory of the protection circuit. The first-level safety judgment scale constant for the current dimension is set to 2.5, and the first-level safety judgment scale constant for the voltage dimension is set to 13.5. This set of boundary values ​​used for preliminary judgment of operational risks is set as the warning threshold. Simultaneously, a second-level physical limit judgment scale constant is configured and written into the static random access memory. The second-level physical limit judgment scale constant for the current dimension is set to 3.5, and the second-level physical limit judgment scale constant for the voltage dimension is set to 15.0. This set of insurmountable boundary values ​​representing the risk of physical breakdown and burnout of the underlying power semiconductor components is set as the hardware limit threshold. Finally, using the multi-channel high-speed analog comparator chip and digital logic judgment array, the specific real values ​​of the extracted device operating status parameters are compared with the values ​​corresponding to the warning threshold and the hardware limit threshold in parallel to perform a numerical magnitude relationship evaluation operation, thereby completing the comparison calculation execution step.

[0080] S702, when the operating status parameter reaches the warning threshold, an interrupt signal is sent to the intelligent control layer.

[0081] Specifically, during the continuous parallel execution of the numerical magnitude relationship evaluation operation, when the result status output by the digital logic judgment array indicates that the specific real value of any dimension of the operating status parameters is greater than or equal to the set safety judgment scale constant of the corresponding dimension in the warning threshold on a mathematical scale, it is determined that the electrical signal load currently faced by the system has touched the initially set safety risk boundary. In some optional implementations, at this time, the pulse generator inside the protection circuit is immediately triggered and activated, forcibly generating a sudden electrical signal pulse with a duration of a constant 500 nanoseconds and a logic high level. Finally, this sudden electrical signal pulse is pushed and transmitted to the data receiving pin terminal corresponding to the central processing unit core responsible for global computational coordination through a dedicated printed circuit board trace transmission channel. This logic high-level electrical signal pulse, which has the highest priority and is used to forcibly cut off the current program sorting process, is set and marked as the interrupt signal, completing the hardware communication action of sending the interrupt signal to the intelligent control layer.

[0082] S703, combined with the predicted load current value, identifies the trigger source of the interrupt signal.

[0083] Specifically, upon receiving the interrupt signal, the intelligent control layer of the system's central processing unit core immediately suspends routine background non-essential loop calculation tasks and switches to a high-priority anomaly diagnosis and processing branch. In some optional implementations, the anomaly diagnosis and processing branch traces back to the memory cache address responsible for look-ahead calculations and retrieves the specific real value of the predicted load current, which was pre-generated in the previous calculation cycle by integrating an autoregressive moving average model; simultaneously, it retrieves the actual current sample value at the current moment that triggered the interrupt signal. Further, it performs a scalar subtraction arithmetic operation between the actual current sample value and the specific real value of the predicted load current, and extracts the absolute value of the subtraction result; it then compares this absolute value with a pre-set constant of 0.2 amperes, used by the system to characterize the prediction deviation tolerance. Finally, through this arithmetic operation mechanism that correlates and compares the actual sudden sampling physical quantities at the bottom layer with the theoretical predictions and extrapolations of the superstructure, it is possible to distinguish whether the sudden change that causes the system electrical signal to touch the boundary is caused by changes in the timing of the internally pre-planned detection commands or by external uncontrollable physical circuit insulation damage, thereby completing the diagnostic and identification operation and identifying the trigger source of the interrupt signal.

[0084] S704, if the trigger source corresponds to a load step condition within a set rate of change range, then the judgment range of the warning threshold is expanded.

[0085] Specifically, during the system initialization phase, a constant range representing a reasonable power jump rate span is pre-defined in the diagnostic configuration list. The lower limit of this constant range is set to a constant of 0.8 amperes per sampling period, and the upper limit is set to a constant of 2.0 amperes per sampling period. This continuous real-valued region, from 0.8 amperes per sampling period to 2.0 amperes per sampling period, is defined as the set rate of change interval. In some optional implementations, when the instantaneous current change rate calculated based on the absolute value of the scalar subtraction in the aforementioned steps falls within the set rate of change interval, and the current actual current's rising or falling physical direction trend is completely consistent with the predicted load current value, it is determined that the sudden change is a legitimate physical behavior of power extraction triggered by a high-power acoustic wave emission measurement task command routinely initiated by the Doppler log device. The state flag corresponding to this legitimate physical behavior of power extraction is set as the load step condition. Furthermore, after confirming the load step condition, the control logic sends a value rewrite instruction to the storage register of the protection circuit; the original warning threshold for the current dimension, set at 2.5 amps, is multiplied by a scaling factor of 1.5, resulting in a new temporary tolerance limit of 3.75 amps. Finally, this new temporary tolerance limit value overwrites the original static stored value. By increasing the judgment scale, the underlying electromagnetic induction link is allowed to withstand legally large current pulse impacts exceeding conventional limits for a specific, very short period without immediately triggering a global control network failure. Arithmetic judgment is then applied to extend the boundary of the configuration parameters to expand the judgment range of the warning threshold.

[0086] S705, if the trigger source corresponds to an overcurrent fault condition that exceeds the set rate of change range, then derating adjustment is performed to limit the output power boundary of the DC-to-DC conversion circuit.

[0087] Specifically, when the instantaneous current change rate calculated by the aforementioned subtraction is greater than the upper limit constant of 2.0 amperes per sampling period of the set change rate range, or when the calculated actual current change direction is completely opposite to the theoretically predicted rising or falling direction of the predicted load current value, it is determined that the surge in current is a catastrophic energy extraction caused by unexpected and illegal reasons such as high-pressure water vapor intruding into the sealed compartment of the equipment in the marine operation environment, resulting in short circuits in the internal wiring or physical breakdown of electrical components. The status flag corresponding to this catastrophic energy extraction is marked as the overcurrent fault condition. In some optional embodiments, after identifying and confirming the overcurrent fault condition, the control logic immediately starts the equipment's underlying survival defense calculation subroutine; extracts the real value of the control duty cycle currently being used by the pulse width modulation logic component responsible for power flow scheduling, multiplies the real value of the control duty cycle by an attenuation scaling factor of 0.5, and uses the arithmetic product result to forcibly reduce the proportion of on-time occupied by the power switching semiconductor device in each working cycle. Furthermore, the real value of the voltage reference tracking target in the outer loop closed-loop control parameter matrix is ​​simultaneously forced down from the initial constant of 12 volts to a constant of 8 volts. Finally, by implementing this derating operation strategy—which forcibly suppresses the continued vicious increase of the backbone network current at the cost of actively sacrificing the accuracy of the constant target voltage output—the comprehensive control intervention action, which includes both reducing the calculation duty cycle and lowering the target reference point through dual arithmetic constraints, is uniformly labeled as the aforementioned derating adjustment. In this way, a forced energy transfer operation ceiling is formed at the digital logic algorithm control level, preventing the disorderly expansion and spread of the total charge transfer, and executing derating adjustment to limit the output power boundary of the DC-to-DC conversion circuit.

[0088] S706, combining the device thermal model, the detected real-time power consumption and the ambient temperature parameters, obtains the predicted temperature rise of the switching transistor and the freewheeling diode. When the predicted temperature rise exceeds the set over-temperature protection threshold, the derating adjustment is executed.

[0089] Specifically, a partial differential equation solving matrix network containing multiple sets of fixed constant parameters for the thermal resistance and thermal capacity of semiconductor materials is pre-loaded into the central computing kernel. This matrix network system with the ability to extrapolate the spatiotemporal distribution of temperature is set as the device thermal model. In the device thermal model, the junction-case thermal resistance constant of the switching transistor is set to 1.2 degrees Celsius per watt, and the junction-case thermal resistance constant of the freewheeling diode is set to 1.5 degrees Celsius per watt. In some optional implementations, the system calculates the total input power by performing a scalar multiplication operator operation based on the real input voltage and current values ​​sampled in real time, and simultaneously calculates the total output power by performing a scalar multiplication operator operation based on the real output voltage and current values. The total input power is subtracted from the total output power to obtain the specific real value of the detected real-time power consumption, which is dissipated and converted into heat energy loss in the internal circuitry and magnetic core components. The real temperature value transmitted in real time by the digital temperature sensor deployed at the edge of the printed circuit board and far away from the direct radiation source heating device is extracted as the ambient temperature parameter. Furthermore, the real values ​​of the ambient temperature parameter, the real values ​​of the detected real-time power consumption, and the junction-case thermal resistance constants of the switching transistor and the freewheeling diode are synchronously input and mapped to the corresponding internal calculation nodes of the device thermal model matrix network; a combined thermodynamic deduction calculation logic consisting of scalar multiplication and addition is executed to calculate the real value of the absolute temperature that is expected to be reached inside the semiconductor physical silicon wafer after a constant time of 5 seconds in the future. This real value of the expected absolute temperature is set in the system and marked as the predicted temperature rise. Finally, a real constant temperature limit is pre-set in the system hardware security configuration library list to characterize the critical point of irreversible thermodynamic melting and collapse of semiconductor crystal structures. The value of this real constant temperature limit is set to 120 degrees Celsius, and this real constant temperature limit with a value of 120 degrees Celsius is marked as the over-temperature protection threshold. The real value of the predicted temperature rise obtained by matrix network deduction calculation is compared with the constant value of 120 degrees Celsius of the over-temperature protection threshold by hardware logic value evaluation. When the logic evaluation comparison result indicates that the calculated predicted value of the predicted temperature rise is arithmetically greater than the constant value of the over-temperature protection threshold, the system actively activates and calls the aforementioned comprehensive derating adjustment action, which includes the dual constraint means of reducing the proportion of the calculated duty cycle constant and forcibly reducing the voltage control reference value. By actively suppressing the overall charge transfer efficiency rate from the power source end to the load end, the computational root cause of the continuous accumulation and rise of heat energy is cut off from the physical source, thereby intervening and executing the derating adjustment in advance before the actual overheating damage occurs.

[0090] S707, When the operating status parameter reaches the hardware limit threshold, the output of the DC to DC conversion circuit is turned off.

[0091] Specifically, during the high-frequency comparison monitoring process continuously and independently executed in parallel by the multi-channel high-speed analog comparator chip and digital logic judgment array at the bottom layer of the protection circuit, when the output level of any bottom-layer analog comparator circuit undergoes a polarity reversal from low to high, indicating that the actual current sampling value in the currently acquired and extracted operating status parameters is equal to or greater than the second-level physical limit judgment scale constant of 3.5 Amperes for the current dimension pre-configured in the static random access memory, or indicating that the actual voltage sampling value is equal to or greater than the second-level physical limit judgment scale constant of 15.0 Volts for the voltage dimension, the energy storage electromagnetic element and high-power semiconductor field-effect device of the judgment system actually endure extreme destructive stress tearing that exceeds the factory physical structure's resistance to penetration and fracture. In some alternative implementations, when faced with such an extremely dangerous and irreversible physical damage state, the control architecture forcibly bypasses all non-real-time intervention steps such as software deduction calculations, timing buffering, and diagnostic identification at the instruction flow level, unconditionally transferring the final driving authority to the lowest-level anti-snap-through logic gate hardware circuit entity. Furthermore, this anti-snap-through logic gate hardware circuit entity instantaneously sends a pull-down low-level blocking suppression signal with a constant value of 0 to the input port of the signal amplification driver chip directly connected to the core gate of all internal power MOSFETs. Finally, by utilizing the solidified physical semiconductor structure to completely deprive the power switching device's internal conduction capability, it forcibly cuts off the directional flow and movement trajectory path of all electronic charges in the main power delivery circuit. With this physical-level forced current interception and blocking action that completely eliminates interference from upper-level software loop delay buffers, the charge flow state of the energy transmission channels spanning the beginning and end of the system is forcibly erased to zero within an extremely short time scale of hundreds of nanoseconds, thus completing the final device fuse action of shutting off the output of the DC-to-DC conversion circuit at the end of the timing flow.

[0092] S801 uses the linear periodic time-varying Nyquist stability criterion to perform frequency response analysis on the closed-loop control loop, and obtains the phase margin and gain margin as stability indicators.

[0093] Specifically, a set of state-space distribution matrices corresponding to the closed-loop control loop within a single flow simulation time period is obtained. In some optional implementations, the underlying model mapping architecture is extracted, and the state-space distribution matrix is ​​set to have a two-dimensional real-number space structure with a constant row dimension of 6 and a constant column dimension of 6. Further, a Fourier series expansion truncation constant containing a constant of 11 harmonic orders is set in the digital signal processing operation module; the frequency domain harmonic transformation operator operation is performed on the state-space distribution matrix using the expansion truncation constant to construct a harmonic transfer function entity that maps the underlying physical transformation state; the Laplace independent variables constructed based on the complex plane in the harmonic transfer function entity are replaced with an expression form in which the natural logarithm base, the imaginary unit, and the continuous frequency variables are multiplied by scalars. Furthermore, an arithmetic calculation process is performed iteratively across the frequency distribution range from 10 Hz to 100,000 Hz with a fixed increment of 10 Hz. All the iterative calculation results are projected onto a two-dimensional complex plane system to generate a polar coordinate complex plane mapping curve representing the open-loop frequency response trajectory of the closed-loop control loop. Finally, on this polar coordinate complex plane mapping curve, an addressing approximation algorithm is used to find the coordinates of the first geometric node corresponding to the intersection of the curve and a unit circle with a radius constant of 1 around the origin of the coordinate system. The magnitude of the real angle formed between the coordinates of this first geometric node and the negative real axis of the system is extracted, and this magnitude is directly set as the phase margin. Simultaneously, the real value of the abscissa of the second geometric node corresponding to the crossing of the negative real axis of the system by the polar coordinate complex plane mapping curve is found. The quotient between the results of dividing the absolute value of the second geometric node's abscissa by 1 is extracted. The value is calculated by performing a logarithmic operator operation on the quotient value with a base of 10 and multiplying the result by a constant of 20. The resulting real number with logarithmic scaling is set as the gain margin. The phase margin with angular dimension and the gain margin with logarithmic scale are combined and these two variables are set as the stability index. Through the above combination of frequency traversal addressing and spatial graph mapping truncation value calculation, the frequency response analysis of the closed-loop control loop is performed using the linear periodic time-varying Nyquist stability criterion.

[0094] S802, when the phase margin or the gain margin falls to the set safety margin threshold, it is determined that the closed-loop control loop has entered the instability risk range.

[0095] Specifically, a constant scale for defining the system's oscillation divergence baseline is pre-allocated and written into the initialization diagnostic configuration library section of the system's running memory. In some optional implementations, a safety lower limit evaluation constant value of 45 is set for the system phase response dimension, and a safety lower limit evaluation constant value of 6 is set for the system gain attenuation dimension. Further, this set of composite evaluation benchmark boundary digital queues containing constants 45 and 6 is set and marked as the safety margin threshold. Even further, within each discrete operation scheduling cycle issued by the system clock controller, the real values ​​of the phase margin and the gain margin calculated independently in the preceding sequence are extracted in parallel; the extracted real values ​​of the phase margin and the constant 45 contained in the safety margin threshold are fed in parallel into the digital comparator circuit unit to perform a size comparison logic branch decision operation; the extracted real values ​​of the gain margin and the constant 6 contained in the safety margin threshold are fed into another parallel digital comparator circuit unit to perform a size comparison logic branch decision operation. Finally, when the logic status flag bit output by any of the aforementioned digital comparator circuit units deflects, indicating that the phase margin is less than the constant 45 in arithmetic absolute value, or the gain margin is less than the constant 6 in arithmetic absolute value, it is determined that the underlying algorithm triggering constraint condition of the phase margin or the gain margin falling to the set safety margin threshold is met. When the underlying algorithm triggering constraint condition is met, the system central diagnostic kernel automatically suspends a memory alarm status indicator with the highest access priority in the global address space, and defines and determines the integrated physical quantity conduction interaction state maintained by the underlying hardware energy delivery topology network and the digital compensation control link in the current state as the closed-loop control loop entering the instability risk range.

[0096] S803, send a first execution instruction to update the feedback compensation coefficient or shrink the output power boundary of the DC-DC conversion circuit.

[0097] Specifically, when the upper-level control architecture determines that the system's underlying computing state has entered the instability risk range, it controls the central processing unit core to send a set of data encoding sequence packets with addressing operation targets and rewriting numerical action constraints to the system address bus channel. This data encoding sequence packet is then set as the first execution instruction at the code management level. In some optional implementations, this first execution instruction includes two parallel optional operation rewriting branches at the logical flow level. Furthermore, when executing the first optional operation to rewrite the branch, the three floating-point real number vectors of the constant within the feedback compensation coefficient that are currently in effect in the current cycle are retrieved and extracted from the working reservation area of ​​the system memory; a scaling constant with buffer shaving ratio characteristics is set and assigned a value of 0.8; the scaling constant with a value of 0.8 is used to perform scalar multiplication operation with the three floating-point real number vectors of the constant one by one to reduce the dimension; the new real number value combination sequence entity after the dimension reduction by the multiplication operator is forcibly overwritten back into the original independent high-speed static memory working address block, thereby weakening the amplification factor distribution of the high-frequency part in the closed-loop feedback path and completing the data manipulation process of updating the feedback compensation coefficient. Finally, when executing the second optional operation rewrite branch, the real number of the heavy-load current threshold used to constrain the theoretical upper limit of charge transfer in the main physical circuit is extracted; a power reduction fixed constant with a value set to 0.85 is configured; the power reduction fixed constant 0.85 and the real number of the heavy-load current threshold are sent to the arithmetic multiplication processor to perform scalar multiplication operator operation; the calculated new floating-point interception limit value is written into the extreme value judgment comparison benchmark register of the hardware overload protection logic execution module, directly reducing the ceiling of the limit energy distribution that the underlying power semiconductor device can conduct and transfer each time it is turned on on at the physical cutoff scale, thereby completing the shrinking of the output power boundary of the DC to DC conversion circuit; the system central control kernel automatically executes one dimension of the two optional operation rewrite branches or the dual-dimensional superposition intervention processing according to the configuration status selection flag bit pre-written in the hardware initialization document.

[0098] S804, send a second execution instruction to narrow the effective range of the warning threshold, and use the warning protection action to intervene in the system adjustment process to force the closed-loop control loop back to the safety margin threshold.

[0099] Specifically, immediately following the first execution instruction push and dispatch step, the control CPU core further sends another set of data encoding judgment sequence packets with the permission to modify the interrupt trigger scale to the independent memory addressing range of the underlying security monitoring network of the management system. This data encoding judgment sequence packet with interrupt modification permission is set and marked as the second execution instruction. In some optional embodiments, the flow process of the second execution instruction actively extracts the warning threshold originally statically residing in the random access protection memory. This warning threshold includes a first-level security judgment scale constant of 2.5 for the current dimension and a first-level security judgment scale constant of 13.5 for the voltage dimension. Furthermore, a desensitization multiplier coefficient for performing contraction suppression is set in the central processing unit core, and the value of the desensitization multiplier coefficient is set to 0.9. The desensitization multiplier coefficient of 0.9 is combined with the first-level security judgment scale constants containing constants of 2.5 and 13.5 respectively, and scalar multiplication and product operation is performed in the arithmetic logic unit. Thus, a new real value of the temporary security boundary current defense line with a reduced value of 2.25 and a new real value of the temporary security boundary voltage defense line with a reduced value of 12.15 are obtained. Finally, the reduced numerical array is used to replace the warning threshold originally residing in the protection memory address block, thereby reducing the effective range of the warning threshold in the underlying comparison calculation logic. By implementing this arithmetic processing method of the starting line reference height of the interrupt triggering logic, in the very early stage of runaway where the underlying physical inductor and capacitor components are subjected to multi-dimensional environmental parameter composite disturbances, resulting in weak high-frequency voltage ripples or high-frequency current oscillation waveforms but before global spread, the hardware defense judgment mechanism with a lower sensitive threshold measurement range after reduction and modification can more quickly and frequently match and satisfy the trigger activation boundary restriction conditions, thus achieving this at the nanosecond extremely short physical delay level. The system generates a physical hardware interruption pulse signal in advance. This pulse signal intensively activates the forced current peak clipping and flattening limiting strategy and the soft derating duty cycle suppression arithmetic logic branch within the protection unit. Through a dual-barrier action mode combining high-frequency low-level hardware action judgment and interception with algorithm-forced arithmetic value suppression, the system forcibly reduces and eliminates the real variables that cause the drift of the transfer function phase boundary frequency point before the system state parameters diffuse into the irreversible physical range. This gradually smooths out the physical transmission trend of oscillation and divergence. The system then implements the action cycle, thereby using the early warning protection action to intervene in the system adjustment process and force the closed-loop control loop back to the safety margin threshold.

[0100] This embodiment demonstrates the multi-level load step response of a Doppler log under typical underwater exploration mission timing. For example... Figure 1As shown, the load current experienced five abrupt changes within a 0.06-second time span: standby (0.55A), data processing (0.95A), high-power transmission (1.75A), idle (0.65A), and deep sleep (0.35A). Faced with this nonlinear operating condition, the intelligent control layer, by integrating an autoregressive moving average model (ARIMA), pre-determines the load current value and combines it with a feedforward duty cycle compensation command. This suppresses the output voltage fluctuations of the DC-to-DC conversion circuit at the moment of load transition, maintaining a smooth transition of the output voltage within the steady-state range of 12V.

[0101] This embodiment tests the system's frequency dynamic matching capability under a comprehensive disturbance environment. Figure 2 This demonstrates the switching frequency response of a Doppler odometer power supply system under load current fluctuations (1.0±0.6A, 5Hz) combined with input voltage disturbances (24±3.5V, 3Hz) and ambient temperature variations (25±12°C, 0.5Hz). The load adaptive adjustment module calculates the theoretical switching frequency in real time based on the predicted load current trend and performs a first-order low-pass filter to output the target switching frequency. As shown in the figure, this target switching frequency adaptively and smoothly adjusts within the 150kHz to 350kHz range, following the load fluctuation trend and optimizing switching losses in the light load range.

[0102] This embodiment demonstrates the parameter adaptive optimization process of the intelligent control layer when faced with external parameter perturbations. For example... Figure 3 As shown, during multi-parameter coupled disturbance testing involving load, input voltage, and temperature, the fuzzy proportional-integral-derivative (FIG) control module dynamically calculates and applies new compensation coefficients based on real-time operating conditions (target switching frequency, predicted load current value, and target operating mode). Specifically, the proportional gain parameter is adjusted within the range of 0.4 to 0.7 volts inverse, the integral gain parameter varies within the range of 8 to 15 volts inverse per second, and the derivative gain parameter is fine-tuned within the range of 0.01 to 0.03 volts per second. This online tuning of the control parameters ensures the adaptability of the control loop to complex disturbance environments.

[0103] This embodiment verifies the attenuation capability of the proposed method against periodic interference through frequency domain analysis. The system is subjected to a composite disturbance simulating the periodic characteristics of sound wave emission (80Hz sinusoidal fluctuation of load current superimposed with 120Hz sinusoidal fluctuation of input voltage). For example... Figure 4 The spectrum analysis results show that at the critical interference frequency of 80Hz, the system disturbance rejection ratio (DRR) of the feedforward compensation and adaptive parameter tuning method based on the hierarchical control architecture of this invention is 26.2dB; as a control, the system disturbance rejection ratio of the traditional fixed-parameter PID control method is 18.5dB. This comparative data demonstrates that the present invention has a superior suppression effect on complex disturbances within the operating frequency band.

[0104] This embodiment uses radar charts to quantitatively evaluate the system's global operating performance under long-term multivariate coupled disturbances. For the severe operating conditions involving load jumps, input voltage fluctuations, and temperature drift, evaluation indicators are extracted from three dimensions: dynamic response time, steady-state voltage accuracy, and light-load conversion efficiency. For example... Figure 5 As shown, under the same hardware and testing conditions, compared with the traditional fixed parameter control scheme, the present invention achieved improvements of 6.41%, 6.98% and 12.2 percentage points in the above three comprehensive performance evaluation indicators, respectively, verifying the engineering advantages of the closed-loop hierarchical control architecture and multi-dimensional prediction compensation mechanism in complex application scenarios.

[0105] Example 2: A Doppler odometer power supply control system based on hierarchical intelligent control, executing any one of the hierarchical intelligent control-based Doppler odometer power supply control methods described above, applied to a Doppler odometer power supply. The Doppler odometer power supply includes a power supply hardware module, an intelligent control layer, and a stability verification layer. The power supply hardware module includes an input filter circuit, a DC-DC conversion circuit, a feedback control circuit, and a protection circuit. The DC-DC conversion circuit includes a switching transistor, a freewheeling diode, and an energy storage inductor. The intelligent control layer includes a multi-parameter dynamic detection module, a load adaptive adjustment module, and a fuzzy proportional-integral-derivative control module. The system includes:

[0106] The sensor data is filtered using the multi-parameter dynamic detection module to obtain real-time electrical parameters and real-time environmental parameters. The real-time electrical parameters include load current sampling data and feedback voltage sampling data, and the real-time environmental parameters include ambient temperature parameters.

[0107] The load adaptive adjustment module performs identification calculations based on the load current sampling data to obtain the predicted load current value and the prediction error amplitude.

[0108] The fuzzy proportional-integral-derivative control module calculates the difference between the feedback voltage sampling data and the set output voltage reference value to generate an error signal, and the feedback duty cycle is obtained based on the error signal.

[0109] The load adaptive adjustment module generates a feedforward compensation command based on the predicted load current value, which is then fused with the feedback duty cycle to control the target switching frequency, target duty cycle, and target operating mode of the DC-DC converter circuit, forming a closed-loop control circuit.

[0110] The stability verification layer calculates the stability index of the closed-loop control loop. When the stability index reaches the set instability critical threshold, a correction command containing changes to control parameters or warning thresholds is sent to the intelligent control layer and the protection circuit.

[0111] The embodiments of this example have been described above. However, this example is not limited to the specific implementation methods described above. The specific implementation methods described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms based on the guidance of this example, and all of them are within the protection scope of this example.

Claims

1. A power supply control method for a Doppler odometer based on hierarchical intelligent control, applied to a Doppler odometer power supply, wherein the Doppler odometer power supply includes a power supply hardware module, an intelligent control layer, and a stability verification layer; the power supply hardware module includes an input filter circuit, a DC-DC conversion circuit, a feedback control circuit, and a protection circuit; the DC-DC conversion circuit includes a switching transistor, a freewheeling diode, and an energy storage inductor; the intelligent control layer includes a multi-parameter dynamic detection module, a load adaptive adjustment module, and a fuzzy proportional-integral-derivative control module; characterized in that, include: The sensor data is filtered using the multi-parameter dynamic detection module to obtain real-time electrical parameters and real-time environmental parameters. The real-time electrical parameters include load current sampling data and feedback voltage sampling data, and the real-time environmental parameters include ambient temperature parameters. The load adaptive adjustment module performs identification calculations based on the load current sampling data to obtain the predicted load current value and the prediction error amplitude. The fuzzy proportional-integral-derivative control module calculates the difference between the feedback voltage sampling data and the set output voltage reference value to generate an error signal, and the feedback duty cycle is obtained based on the error signal. The load adaptive adjustment module generates a feedforward compensation command based on the predicted load current value, which is then fused with the feedback duty cycle to control the target switching frequency, target duty cycle, and target operating mode of the DC-DC converter circuit, forming a closed-loop control circuit. The stability verification layer calculates the stability index of the closed-loop control loop. When the stability index reaches the set instability critical threshold, a correction command containing changes to control parameters or warning thresholds is sent to the intelligent control layer and the protection circuit.

2. The power supply control method for a Doppler log based on hierarchical intelligent control according to claim 1, characterized in that, The process of obtaining real-time electrical parameters and real-time environmental parameters includes: Simultaneously acquire raw electrical signals and raw environmental signals; Obtain the signal change rate of the original electrical signal; Based on the comparison result between the signal rate of change and the set signal rate of change threshold, select the corresponding dynamic filtering coefficient; When the rate of change of the signal is greater than or equal to the threshold of the rate of change of the signal, the first filter coefficient is selected and the first time constant of the first-order exponential weighted moving average filter is set. When the rate of change of the signal is less than the threshold of the rate of change of the signal, a second filter coefficient is selected, and a second time constant of the first-order exponentially weighted moving average filter is set; the second filter coefficient is less than the first filter coefficient, and the second time constant is greater than the first time constant. The original electrical signal is processed by the dynamic filtering coefficients and passed through the first-order exponentially weighted moving average filter to output the real-time electrical parameters.

3. The power supply control method for a Doppler log based on hierarchical intelligent control according to claim 1, characterized in that, The process of obtaining the predicted load current value and the prediction error magnitude includes: The load current sampling data is subjected to first-order differential processing to eliminate the data trend term from satisfying the sequence stationarity condition; Extract the load current values ​​of a set number of historical periods as an autoregressive term, extract the prediction error of a set number of historical periods as a moving average term, and establish an integrated autoregressive moving average prediction model. Using the data observation vector and gain matrix, the autoregressive coefficients and moving average coefficients of the integrated autoregressive moving average prediction model are updated by recursive least squares with a forgetting factor. The updated autoregressive coefficients and moving average coefficients are input into the integrated autoregressive moving average prediction model, which outputs the predicted load current value for the target period and calculates the prediction error magnitude. When the magnitude of the prediction error continuously exceeds the set error threshold, the identification calculation of the autoregressive coefficient and the moving average coefficient is re-executed.

4. The power supply control method for a Doppler log based on hierarchical intelligent control according to claim 1, characterized in that, The control of the target switching frequency, target duty cycle, and target operating mode of the DC-to-DC conversion circuit includes: Based on the predicted load current value, the set heavy load current threshold, and the light load current threshold, the corresponding theoretical switching frequency is extracted. The target switching frequency is obtained by performing a first-order low-pass filter on the theoretical switching frequency. The critical current characterizing the switching boundary of the operating mode is determined by combining the inductance parameters of the energy storage inductor and the target switching frequency. When the predicted load current value changes from the light load current range to the heavy load current range and crosses the set first hysteresis switching threshold, the target operating mode is controlled to switch to continuous conduction mode. When the predicted load current value changes from the heavy load current range to the light load current range and crosses the set second hysteresis switching threshold, the target operating mode is controlled to switch to the discontinuous conduction mode. The first hysteresis switching threshold is greater than the second hysteresis switching threshold.

5. The power supply control method for a Doppler log based on hierarchical intelligent control according to claim 4, characterized in that, The control of the DC-to-DC conversion circuit by integrating the control action with the feedback duty cycle includes: By combining the predicted load current value, the output voltage reference value, the detected input voltage, the forward voltage drop of the freewheeling diode, and the on-state voltage drop of the switching transistor, a feedforward duty cycle is generated to maintain the output voltage in the steady-state range. Obtain the feedback duty cycle obtained by the fuzzy proportional-integral-derivative control module; The feedforward duty cycle is weighted and adjusted using a set feedforward gain. The feedforward duty cycle with the adjusted weight is added and combined to output the target duty cycle applied to the DC-DC conversion circuit. The output voltage fluctuation in the steady-state range is compensated by introducing a parameter with predictive properties.

6. The power supply control method for a Doppler log based on hierarchical intelligent control according to claim 5, characterized in that, The step of deriving the feedback duty cycle based on the error signal processing includes: By utilizing the dual sampling branches set in the feedback control circuit, the control feedback current signal for closed-loop control and the overcurrent protection current signal for triggering hardware protection are respectively acquired. The control feedback current signal and the error signal are input into a digital compensator with coefficient update function; Based on the state machine information of the target switching frequency, the predicted load current value, and the target operating mode combination, the feedforward compensation coefficient and the feedback compensation coefficient are extracted from the coefficient lookup table. The filtering parameters of the digital compensator are reconstructed using the feedforward compensation coefficient and the feedback compensation coefficient, and the digital compensator is adjusted to generate the feedback duty cycle.

7. The power supply control method for a Doppler log based on hierarchical intelligent control according to claim 6, characterized in that, Before sending a correction command containing the changed warning threshold to the protection circuit, the process also includes hardware protection steps performed by the protection circuit: The protection circuit is used to compare the device's operating status parameters with the set warning threshold and hardware limit threshold. When the operating status parameter reaches the warning threshold, an interrupt signal is sent to the intelligent control layer; The trigger source of the interrupt signal is identified by combining the predicted load current value; If the trigger source corresponds to a load step condition within a set rate of change range, then the judgment range of the warning threshold is expanded. If the trigger source corresponds to an overcurrent fault condition that exceeds the set rate of change range, then derating is performed to limit the output power boundary of the DC-to-DC conversion circuit. The predicted temperature rise of the switching transistor and the freewheeling diode is obtained by combining the equipment thermal model, the detected real-time power consumption and the ambient temperature parameters. When the predicted temperature rise exceeds the set over-temperature protection threshold, the derating adjustment is executed. When the operating status parameter reaches the hardware limit threshold, the output of the DC-DC conversion circuit is turned off.

8. The power supply control method for a Doppler log based on hierarchical intelligent control according to claim 7, characterized in that, Sending correction instructions that include changes to control parameters or warning thresholds includes: The closed-loop control loop is analyzed by using the linear periodic time-varying Nyquist stability criterion to obtain the phase margin and gain margin, which are the stability indicators. When the phase margin or the gain margin falls to the set safety margin threshold, the closed-loop control loop is determined to have entered the instability risk range. Send a first execution instruction to update the feedback compensation coefficient or shrink the output power boundary of the DC-to-DC conversion circuit; Send a second execution command to narrow the effective range of the warning threshold, and use the warning protection action to intervene in the system adjustment process to force the closed-loop control loop back to the safety margin threshold.

9. A power control system for a Doppler log based on hierarchical intelligent control, wherein the system executes the power control method for a Doppler log based on hierarchical intelligent control as described in any one of claims 1-8.

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