A rail-to-rail input-output reference voltage buffer circuit for a SAR ADC
By integrating a double-folded cascode input stage, a gain bootstrap structure, a transconducting linear loop, and a Class AB output stage, the problems of narrow input/output swing, low gain, high noise, and slow speed of the SAR ADC reference voltage buffer under low voltage were solved, achieving high-precision and high-speed signal processing.
Patent Information
- Application Number
- CN202610784167.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-06-02
- Publication Date
- 2026-08-25
AI Technical Summary
Traditional SAR ADC reference voltage buffers suffer from limited input common-mode range, insufficient output swing, transconductance ripple, conflict between drive capability and stability, and noise issues at low voltages, making it difficult to meet the requirements of low-voltage, low-noise, and high-speed applications.
The design incorporates a rail-to-rail input stage with a double-folded cascode structure, a gain bootstrap structure, a transconducting linear loop, and a Class AB output stage to achieve rail-to-rail input/output swing, improve open-loop gain and stability, reduce noise, and enhance drive capability.
It achieves a wide input/output swing, high open-loop gain, low noise, and high speed operational amplifier, suitable for low-voltage applications, and meets the high-precision and high-speed signal processing requirements of SAR ADCs.
Smart Images
Figure CN122639876A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of analog integrated circuit design technology, specifically relating to a rail-to-rail input / output operational amplifier circuit for SAR ADC, and particularly a rail-to-rail reference voltage buffer circuit suitable for successive approximation analog-to-digital converters (SAR ADC). Background Technology
[0002] Successive approximation analog-to-digital converters (SAR ADCs) are widely used in portable devices, sensor interfaces, medical electronics, and industrial control due to their low power consumption, moderate accuracy, and moderate conversion speed. As process dimensions continue to shrink and supply voltages continue to decrease (e.g., to 1.2V or even 0.8V), SAR ADCs often require rail-to-rail input signals (from ground GND to supply voltage VDD) to maximize input dynamic range and accommodate multiple signal levels. Therefore, their internal reference voltage buffers also need to have rail-to-rail input / output capabilities.
[0003] However, traditional reference voltage buffers (such as source followers, two-stage operational amplifiers, etc.) have the following prominent problems in practical applications:
[0004] Limited input common-mode range: Traditional differential pair (such as NMOS or PMOS pair) input stages cannot operate normally across the entire power supply voltage range. When the input approaches VDD or GND, the input transistor enters the linear region or even turns off, resulting in a significant drop in transconductance (gm) and a reduction in loop gain, thereby affecting the setup accuracy and speed of the buffer.
[0005] Insufficient output swing: Amplifiers using a common-source output structure often fail to achieve true output voltage reach of the power rail due to the minimum voltage drop across the output transistor (VDSAT). At low supply voltages, this limited output swing compresses the reference voltage range of the SARADC, reducing the quantization signal-to-noise ratio (SNR).
[0006] Transconductance ripple: To enable the input stage to operate across the entire common-mode range, a common practice is to use complementary differential pairs (PMOS and NMOS pairs in parallel). However, in the switching region (near the midpoint of the common-mode level), the total transconductance changes significantly (e.g., a "transconductance dip" or "transconductance bulge"), causing loop gain ripple, which in turn leads to inconsistent settling times and even stability issues.
[0007] The conflict between driving capability and stability: The reference voltage buffer needs to provide a large instantaneous current to the capacitor array inside the SAR ADC. Traditional amplifiers are prone to insufficient slew rate under heavy load transient response, and large compensation capacitors are often required for stability, which further reduces the response speed.
[0008] Reference voltage spikes and noise: During successive comparisons in a SAR ADC, capacitor array switching generates charge injection and current spikes, causing reference voltage fluctuations. If the buffer output impedance is not low enough or the recovery speed is slow, setup error will be introduced, directly affecting the ADC's linearity and spurious-free dynamic range (SFDR).
[0009] Traditional operational amplifiers suffer from narrow input / output swing, high noise, and slow speed, making them unsuitable for low-voltage, low-noise, and high-speed applications. Rail-to-rail input / output op-amps, capable of operating across the entire input / output voltage range from the negative to the positive rail of the power supply, have become a key technology for low-voltage analog circuits.
[0010] In existing rail-to-rail operational amplifier designs, the input stage often employs a complementary differential pair structure, while the output stage uses a Class AB or common-source stage structure. However, achieving high open-loop gain, low noise, high switching speed, and output short-circuit protection while ensuring rail-to-rail swing remains a design challenge. Summary of the Invention
[0011] This invention aims to address the problems of narrow input / output swing, low gain, high noise, slow speed, and lack of output protection in existing operational amplifiers. To this end, this invention provides a rail-to-rail input / output reference voltage buffer circuit for SAR ADCs.
[0012] A rail-to-rail input / output reference voltage buffer circuit for a SAR ADC, characterized in that it comprises:
[0013] The rail-to-rail input stage circuit adopts a double-folded cascode structure to receive differential input signals and realize the input swing from the negative rail to the positive rail.
[0014] A gain bootstrap structure is connected to the double-folded cascode structure to improve output impedance and open-loop gain.
[0015] A transconducting linear loop structure is used to stabilize the quiescent operating point of the Class AB output stage and shield AC interference.
[0016] The AB class output stage circuit uses a common-source transistor structure to achieve rail-to-rail output swing.
[0017] Furthermore, the rail-to-rail input stage circuit includes parallel N-channel differential pairs (M1, M2) and P-channel differential pairs (M3, M4). The N-channel differential pairs are active when the input voltage is close to the positive rail; the P-channel differential pairs are active when the input voltage is close to the negative rail; in the intermediate voltage region, both differential pairs conduct simultaneously, thereby achieving an input swing from 100mV below the negative rail to 100mV above the positive rail.
[0018] Furthermore, the double-folded cascode structure is composed of M1 to M14, and its output impedance under typical conditions can be expressed as: .
[0019] Furthermore, the gain bootstrap structure is an auxiliary operational amplifier, employing a single-folded cascode structure. When the gain bootstrap structure is added, the output impedance is amplified by A1 times: .
[0020] Furthermore, the transconducting linear ring structure includes two sets of transconducting linear rings: one set consists of M2a / M2b and M10 / M3a, and the other set consists of M1a / M1b and M11 / M3b. The transconducting linear rings satisfy the following relationship: .
[0021] This allows us to derive a current expression related to transistor size, making the output stage current independent of the power supply voltage, preventing the output transistor from turning off under high current, and reducing crossover distortion.
[0022] Furthermore, the Class AB output stage circuit is composed of common-source transistors M3a and M3b. Under light resistive loads (>10kΩ), the output voltage swing is within 50mV of the power rail; under loads from 600Ω to 10kΩ, the output swing is within 100mV of the power rail, while maintaining an open-loop gain of over 100dB.
[0023] Beneficial effects:
[0024] Wide input / output swing: Through complementary differential pair input stage and class AB common source output stage, rail-to-rail input / output swing from negative rail to positive rail is achieved, suitable for low voltage applications.
[0025] High open-loop gain: By introducing a gain bootstrap structure, the output impedance and open-loop gain are increased by about 4000 times, with an actual open-loop gain greater than 110dB, meeting the requirements for high precision.
[0026] Low noise and high speed: Input voltage noise density as low as 3.9nV / Hz, suitable for high-speed signal processing.
[0027] High stability and low distortion: The transconducting linear loop structure stabilizes the static operating point of the output stage, reduces crossover distortion, and improves linearity. Attached Figure Description
[0028] Figure 1 This is an overall architecture diagram of the rail-to-rail input / output reference voltage buffer circuit for SAR ADC of the present invention.
[0029] Figure 2 This is a diagram of the auxiliary operational amplifier.
[0030] Figure 3This is a graph showing the transient simulation results of the buffer.
[0031] Figure 4 This is a diagram showing the AC simulation results of the buffer.
[0032] Figure 5 This is a simulation result of the noise from the buffer. Detailed Implementation
[0033] The technical solutions of the embodiments of the present invention will be clearly and thoroughly described below with reference to the accompanying drawings. The described embodiments are merely some embodiments of the present invention.
[0034] like Figure 1 As shown, the rail-to-rail input / output reference voltage buffer circuit for SAR ADC provided by the present invention includes: a rail-to-rail input stage (double-folded cascode structure), a gain bootstrap structure, a transconducting linear loop structure, and a Class AB output stage.
[0035] Input-level design: such as Figure 1 As shown, the rail-to-rail input circuit consists of N-channel differential pairs (M1, M2) and P-channel differential pairs (M3, M4) connected in parallel. When the input voltage is close to the positive rail, the N-channel differential pairs are active; when it is close to the negative rail, the P-channel differential pairs are active; in the intermediate region, both are active simultaneously, realizing rail-to-rail input. M1~M14 constitute a double-folded common-source common-gate circuit.
[0036] Gain Bootstrap: The gain bootstrap structure is a single-folded cascode auxiliary operational amplifier structure, such as... Figure 2 As shown, the open-loop gain is 72dB, which is connected to the key node of the main op-amp to amplify the output impedance and open-loop gain.
[0037] Transconducting linear loops: Transconducting linear loops include a first group of loops consisting of M2a / M2b and M10 / M3a, and a second group of loops consisting of M1a / M1b and M11 / M3b.
[0038] Output stage: The Class AB output stage consists of common-source transistors M3a and M3b, enabling rail-to-rail output. Under light load, the output swing distance from the power rail is less than 50mV, and under a load of 600Ω~10kΩ, it is less than 100mV, while maintaining an open-loop gain of over 100dB.
[0039] Circuit simulation: 180nm CMOS process, Spectre software simulation. Input noise density 3.93nV / Hz.
[0040] In summary, this invention proposes a rail-to-rail input / output operational amplifier circuit suitable for SAR ADCs. Through the integrated design of a double-folded cascode input stage, gain bootstrapping, transconductance linear loop, Class AB output stage, and output short-circuit protection, a good balance is achieved between wide input / output swing, high gain, low noise, high speed, and high reliability.
[0041] Simulation results
[0042] 1. When the transient simulation of the buffer is as follows Figure 3 If the output can follow the input and maintain 2.5V when the voltage input is 2.5V, it means that the function is normal.
[0043] 2. Buffer AC simulation as follows Figure 4 Its closed-loop gain is 110dB and its phase margin is 72°, which meets the high precision requirements.
[0044] Noise simulation of 3 buffers is as follows Figure 5 Its noise level is 3.93V / Hz, which meets the requirements for high speed.
Claims
1. A rail-to-rail input / output reference voltage buffer circuit for a SAR ADC, characterized in that, include: The rail-to-rail input stage circuit adopts a double-folded cascode structure to receive differential input signals and realize the input swing from the negative rail to the positive rail. A gain bootstrap structure, connected to the double-folded cascode structure, is used to improve output impedance and open-loop gain; a transconducting linear loop structure and a floating current source structure are used to stabilize the static operating point of the Class AB output stage and shield AC interference; the Class AB output stage circuit adopts a cascode structure to achieve rail-to-rail output swing.
2. The rail-to-rail input / output reference voltage buffer circuit for a SAR ADC according to claim 1, characterized in that, M1 and M2 form an input differential pair, with their sources connected to the drain of M3. The source of M3 is grounded and its gate is connected to Vbias1. The drain of M1 is connected to the drain of M5 and VO1. The drain of M2 is connected to the drain of M6 and VO2. The sources of M5 and M6 are connected to V+, and their gates are interconnected and connected to the drain of M5 to form a diode-connected active load. The gate of M8 is connected to VO1, and the gate of M9 is connected to VO2. The sources of M8 and M9 are connected to the drain of M7. The source of M7 is grounded and its gate is connected to Vbias2. The drain of M8 is connected to the drain of M10, and the drain of M9 is connected to... The drain of M11, the sources of M10 and M11 are connected to V+, the gate of M10 is connected to Vbias3, the gate of M11 is connected to the drain of M11, the gate of M12 is connected to node A, the drain of M9 is connected to the drain of M11, the source is grounded, and the drain is connected to the output or M13, the gate of M13 is connected to node B, the source is grounded, and the drain is connected to the output, and the gate of M14 is connected to the bias or node B, the source is grounded, and the drain is connected to the output. This forms a complete fully differential operational amplifier structure with differential input, two-stage amplification, active load, and output stage drive capability. Through the above connection method, the input can be amplified.
3. The rail-to-rail input / output reference voltage buffer circuit for a SAR ADC according to claim 1, characterized in that, The gain bootstrap structure is an auxiliary operational amplifier, which adopts a single-folded common-source common-gate structure to amplify the output impedance and open-loop gain of the main operational amplifier.
4. A rail-to-rail input / output reference voltage buffer circuit for a SAR ADC according to claim 1, characterized in that, The transconducting linear loop structure includes at least two sets of transconducting linear loops composed of MOS transistors, which are used to make the current of the output stage transistor independent of the power supply voltage and to prevent the output transistor from being completely turned off when the current is too large, thereby reducing crossover distortion and improving speed.
5. A rail-to-rail input / output reference voltage buffer circuit for a SAR ADC according to claim 1, characterized in that, The AB class output stage circuit is composed of common source transistors M3a and M3b. When the light resistive load is greater than 10kΩ, the output voltage swing is within 50mV of the power rail; when the load is between 600Ω and 10kΩ, the output voltage swing is within 100mV of the power rail.
6. A rail-to-rail input / output reference voltage buffer circuit for a SAR ADC according to claim 1, characterized in that, The circuit is implemented using a 180nm CMOS process, with an open-loop gain greater than 110dB and an input voltage noise density of 3.93nV / Hz.