A signal processing device for an accelerometer

Abstract

The application provides a signal processing device for an accelerometer, which comprises an analog signal conditioning unit, an analog-digital conversion unit and a programmable logic gate array unit; the analog signal conditioning unit is configured to perform bias voltage adjustment processing, anti-aliasing low-pass filtering processing and proportional amplification processing on original signals output by an accelerometer sensor; the programmable logic gate array unit is configured to load a digital filter with configurable coefficients, perform difference equation recursion operation on digital sequences output by the analog-digital conversion unit, and output filtered digital sequences; the coefficients of the digital filter are converted by a bilinear transformation method from an analog prototype filter, and the coefficients are reconfigured in response to online configuration instructions to adjust the cutoff frequency of the digital filter. Through the application, the adjustment of the filtering cutoff frequency no longer depends on the physical replacement of hardware elements, and the software real-time adjustment of the accelerometer signal filtering parameters is realized.

Description

Technical Field

[0001] This application relates to the field of precision measurement technology, and more specifically, to a signal processing device for an accelerometer. Background Technology

[0002] Traditional piezoelectric accelerometers are high-impedance, charge-output sensors. The raw output signal is extremely weak, usually superimposed with a large DC bias voltage, and is easily mixed with high-frequency noise interference. When acquiring and processing accelerometer signals, bias voltage adjustment, anti-aliasing low-pass filtering, and proportional amplification must be performed on the signal before analog-to-digital conversion to match the input range of the subsequent circuit and prevent spectral aliasing.

[0003] After analog signal conditioning, the signal still needs to be filtered to extract vibration information within the effective frequency band. In existing technologies, this filtering stage is usually implemented using analog filters with fixed parameters, and the filter's cutoff frequency is determined by the parameters of hardware components such as resistors and capacitors. Once the circuit is soldered, the filtering characteristics are fixed. When the measurement scenario changes and the filter cutoff frequency needs to be adjusted, this can only be achieved by desoldering and replacing resistors, which is cumbersome, cannot be adjusted online, and is difficult to adapt to precision measurement tasks that require flexible switching of filter bandwidth. Summary of the Invention

[0004] In view of this, the purpose of this application is to provide a signal processing device for an accelerometer, which aims to overcome at least one of the above-mentioned defects.

[0005] In a first aspect, this application provides a signal processing device for an accelerometer, including an analog signal conditioning unit, an analog-to-digital converter unit, and a programmable gate array unit; The input terminal of the analog signal conditioning unit is used to connect to the accelerometer sensor, the output terminal of the analog signal conditioning unit is connected to the input terminal of the analog-to-digital converter, and the output terminal of the analog-to-digital converter is connected to the data input terminal of the programmable gate array unit. The analog signal conditioning unit is configured to perform bias voltage adjustment, anti-aliasing low-pass filtering, and proportional amplification on the raw signal output by the accelerometer sensor. The programmable gate array unit is configured to load a digital filter with configurable coefficients, perform a difference equation recursive operation on the digital sequence output by the analog-to-digital converter unit to output a filtered digital sequence. The coefficients of the digital filter are obtained by converting the analog prototype filter through the bilinear transform method, and the coefficients are reconfigured in response to an online configuration command to adjust the cutoff frequency of the digital filter.

[0006] In one possible implementation, it also includes: A constant current source circuit is provided, the output terminal of which is connected to the power supply terminal of the accelerometer sensor. The constant current source circuit is configured to set the output current value by adjusting the resistance value of resistor Rset.

[0007] In one possible implementation, the analog signal conditioning unit includes an active low-pass filter circuit, a high-pass filter circuit, and a proportional amplifier circuit. The input terminal of the active low-pass filter circuit is used to receive the raw signal output by the accelerometer sensor. The output terminal of the active low-pass filter circuit is connected to the input terminal of the high-pass filter circuit. The output terminal of the high-pass filter circuit is connected to the input terminal of the proportional amplifier circuit. The output terminal of the proportional amplifier circuit is connected to the input terminal of the analog-to-digital converter unit.

[0008] In one possible implementation, it also includes: A network interface unit is connected to the data output terminal of the programmable gate array unit. The network interface unit is configured to encapsulate the filtered digital sequence output by the programmable gate array unit into a data packet and send the data packet to the data acquisition device through an Ethernet interface or an optical fiber interface.

[0009] In one possible implementation, the network interface unit includes a PHY chip and an RJ45 network port. The input terminal of the PHY chip is connected to the data output terminal of the programmable gate array unit, and the output terminal of the PHY chip is connected to the RJ45 network port. The PHY chip is configured to encapsulate the filtered digital sequence into data packets and transmit them through the RJ45 network port.

[0010] In one possible implementation, the network interface unit includes an optical port circuit, the input of which is connected to the data output of the programmable gate array unit, and the optical port circuit is configured to encapsulate the filtered digital sequence into a data packet and transmit it through the optical fiber interface.

[0011] In one possible implementation, the analog-to-digital conversion unit includes: An ADC chip acquisition circuit is provided, wherein the input terminal of the ADC chip acquisition circuit is connected to the output terminal of the analog signal conditioning unit, and the output terminal of the ADC chip acquisition circuit is connected to the data input terminal of the programmable gate array unit.

[0012] In one possible implementation, the programmable gate array unit is configured such that the difference equation recursive operation is performed by executing an equation that defines the input-output relationship of the digital filter, the coefficients of which are obtained by the analog prototype filter through a bilinear transform method.

[0013] In one possible implementation, the programmable gate array unit is further configured to adjust the cutoff frequency of the digital filter by modifying the coefficients of the digital filter.

[0014] In one possible implementation, the analog-to-digital conversion unit, the programmable gate array unit, and the network interface unit are integrated on the same board, and the board is connected to the data acquisition device through the Ethernet interface or the fiber optic interface.

[0015] This application provides a signal processing device for an accelerometer, comprising an analog signal conditioning unit, an analog-to-digital converter (ADC), and a programmable gate array (PGA) unit. The analog signal conditioning unit is configured to perform bias voltage adjustment, anti-aliasing low-pass filtering, and proportional amplification on the raw signal output from the accelerometer sensor. The PGA unit is configured to load a digital filter with configurable coefficients, perform a difference equation recursive operation on the digital sequence output from the ADC unit, and output a filtered digital sequence. The coefficients of the digital filter are obtained by converting the analog prototype filter using a bilinear transform method, and the coefficients are reconfigured in response to online configuration commands to adjust the cutoff frequency of the digital filter. This application eliminates the need for physical replacement of hardware components to adjust the filter cutoff frequency, enabling real-time software-based adjustment of the accelerometer signal filtering parameters.

[0016] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is one of the structural schematic diagrams of a signal processing device for an accelerometer provided in an embodiment of this application; Figure 2 This is a second schematic diagram of the signal processing device for an accelerometer provided in an embodiment of this application. Figure 3 This is a schematic diagram illustrating the relationship between Rset and current provided in an embodiment of this application. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely represents selected embodiments of this application. Based on the embodiments of this application, every other embodiment obtained by those skilled in the art without inventive effort falls within the scope of protection of this application.

[0020] First, the applicable application scenarios of this application are introduced. This application can be applied to the technical field of accelerometer signal acquisition and processing, specifically involving vibration signal front-end processing in precision motion control scenarios.

[0021] Research has revealed that traditional piezoelectric accelerometers are high-impedance, charge-output sensors, producing very weak signals that are highly susceptible to cable movement, electromagnetic interference, and humid environments. Using these sensors requires expensive specialized charge amplifiers, resulting in complex system setups and poor interference immunity. IEPE technology solves these problems by integrating a miniature charge amplifier within the sensor. The IEPE accelerometer works by generating a charge when the internal piezoelectric crystal is subjected to acceleration. This charge is immediately amplified by the built-in micro-integrated circuit and converted into a low-impedance voltage signal. This voltage signal is output via a coaxial cable, providing extremely strong interference immunity. The accelerometer sensor is powered by a constant current source, typically 2-20mA, which is used for both power supply and signal transmission via a signal cable. The constant current source provides DC power from a remote location, such as the data acquisition terminal, and the built-in IC operates using this DC power. The accelerometer signal is superimposed on a DC bias voltage in the form of an AC voltage. The acquisition terminal uses a capacitor to perform preliminary filtering of the accelerometer signal.

[0022] Based on the accelerometer level of the sensor frame, XY lens acceleration feedforward is necessary. By applying lens feedforward, the impact of lens motion on the servo control system error can be reduced. For this purpose, lens acceleration needs to be measured and used as feedforward for the short-stroke motor. The signals in the X and Y directions are measured from two dual-axis accelerometers, amplified to an appropriate level, and filtered to limit their bandwidth.

[0023] The existing technology has the following objective drawbacks. First, the existing solution cannot adjust the frequency range in real time; it can only adjust the frequency range by desoldering and resoldering resistors. When it is necessary to change the filter cutoff frequency, the resistors on the circuit board must be replaced, which is cumbersome and cannot be adjusted online, making it difficult to adapt to application scenarios that require flexible switching of filter parameters. Second, the existing solution transmits data by connecting the chassis with cables. The resistance in long cables can cause analog signal attenuation and distortion, and the signal is also susceptible to electromagnetic interference along the transmission path, affecting the authenticity and accuracy of the acquired data.

[0024] Based on this, this application provides a signal processing device for an accelerometer to solve the problems of real-time filtering and signal transmission fidelity in accelerometer signal acquisition. This application uses an FPGA software algorithm to filter the acquired accelerometer signal using a Bessel filtering method, and adjusts the frequency range in real time by adjusting the FPGA algorithm parameters. Analog-to-digital conversion (ADC) is performed on the board, and data transmission is achieved through an optical module and chassis. This solution has extremely strong anti-interference capabilities. Digital signal conversion is completed on the board, and digital signals have inherent robustness, preserving the original signal fidelity. The FPGA is no longer a simple processor, but a highly customizable hardware circuit. Processing the acquired accelerometer signal using the FPGA software algorithm is equivalent to calculating difference equations, achieved by executing an equation defining the input-output relationship of a digital filter. Then, high-speed, highly anti-interference signal transmission is achieved through the ADC analog-to-digital conversion circuit, PHY chip circuit, and network port circuit or optical port circuit.

[0025] The specific implementation methods of the embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0026] Please see Figure 1 , Figure 1 This is one of the structural schematic diagrams of a signal processing device for an accelerometer according to an embodiment of this application. The device includes: an analog signal conditioning unit 100, an analog-to-digital converter 200, and a programmable gate array unit 300.

[0027] The input terminal of the analog signal conditioning unit 100 is used to connect to the accelerometer sensor, the output terminal of the analog signal conditioning unit 100 is connected to the input terminal of the analog-to-digital converter unit 200, and the output terminal of the analog-to-digital converter unit 200 is connected to the data input terminal of the programmable logic gate array unit 300.

[0028] The analog signal conditioning unit 100 is configured to perform bias voltage adjustment, anti-aliasing low-pass filtering, and proportional amplification on the raw signal output from the accelerometer sensor. The programmable gate array unit 300 is configured to load a digital filter with configurable coefficients, perform a difference equation recursive operation on the digital sequence output from the analog-to-digital converter unit 200, and output a filtered digital sequence. The coefficients of the digital filter are obtained by converting the analog prototype filter through a bilinear transform method, and the coefficients are reconfigured in response to online configuration commands to adjust the cutoff frequency of the digital filter.

[0029] Specifically, the raw signal output by the accelerometer sensor is superimposed on a DC bias voltage in the form of an AC voltage. The bias voltage adjustment process adjusts the DC bias component of the signal to a level suitable for subsequent circuit processing. The anti-aliasing low-pass filter removes signal components with frequencies higher than the Nyquist frequency to prevent spectral aliasing during analog-to-digital conversion. The proportional amplification process amplifies the weak signal to an amplitude matching the input range of the analog-to-digital converter 200. The programmable gate array (FPGA) 300 internally performs a point-by-point differential equation recursive operation on the digital sequence using its loaded digital filter. The output at each moment is determined by the current input and the input / output values ​​from several previous moments. When the filter cutoff frequency needs to be changed, the coefficients of the digital filter can be reset by sending an online configuration command without replacing or soldering any hardware components. This achieves real-time online adjustment of the filter parameters compared to existing technologies that require desoldering resistors to change the frequency range.

[0030] In some embodiments of this application, the analog signal conditioning unit 100 includes an active low-pass filter circuit, a high-pass filter circuit, and a proportional amplifier circuit.

[0031] Specifically, the input of the active low-pass filter circuit is used to receive the raw signal output from the accelerometer sensor. The output of the active low-pass filter circuit is connected to the input of the high-pass filter circuit, the output of the high-pass filter circuit is connected to the input of the proportional amplifier circuit, and the output of the proportional amplifier circuit is connected to the input of the analog-to-digital converter unit 200. The acquired accelerometer sensor signal contains noise, which is filtered out by the active low-pass and high-pass filter circuits within a specific frequency range, such as 70Hz to 400Hz. Since the acquired signal is weak, it is amplified by a certain factor on the board using a proportional amplifier circuit.

[0032] Please see Figure 2 , Figure 2This is a second schematic diagram of the signal processing device for an accelerometer according to an embodiment of this application. The device also includes: a constant current source circuit 400 and a network interface unit 500.

[0033] Specifically, the output of the constant current source circuit 400 is connected to the power supply of the accelerometer sensor. The constant current source circuit 400 is configured to set the output current value by adjusting the resistance value of the resistor Rset. The constant current source circuit 400 uses an active bias controller circuit to provide a stable current. The constant current source provides DC power from a remote end. The IC built into the accelerometer sensor operates using DC power. Power supply and signal transmission share the same signal cable.

[0034] In one specific implementation, the resistance value of Rset is preferably 560Ω. The correspondence between the resistance value of Rset and the output current value of the constant current source is as follows: Figure 3 As shown, Figure 3 This is a schematic diagram showing the relationship between Rset and current.

[0035] Specifically, the network interface unit 500 is connected to the data output terminal of the programmable gate array unit 300. The network interface unit 500 is configured to encapsulate the filtered digital sequence output by the programmable gate array unit 300 into data packets and send the data packets to the data acquisition device via an Ethernet interface or a fiber optic interface. Transmission via a fiber optic interface offers strong anti-interference capabilities, and the inherent robustness of digital signals preserves the original signal fidelity, avoiding signal attenuation and distortion problems caused by long-distance analog cable transmission.

[0036] In one implementation, the network interface unit 500 includes a PHY chip and an RJ45 network port. The input of the PHY chip is connected to the data output of the programmable gate array unit 300, and the output of the PHY chip is connected to the RJ45 network port. The PHY chip is configured to encapsulate the filtered digital sequence into data packets and send them through the RJ45 network port.

[0037] In one specific implementation, the PHY chip model is 88E1518, the ADC chip model is LTC2328IMS-18#PBF, and the optical module model is AXS85-192-M3.

[0038] In another implementation, the network interface unit 500 includes an optical port circuit. The input of the optical port circuit is connected to the data output of the programmable gate array unit 300. The optical port circuit is configured to encapsulate the filtered digital sequence into data packets and transmit them through the fiber optic interface. The optical port circuit converts electrical signals into optical signals for transmission through a photoelectric conversion module. The optical signals are not affected by electromagnetic interference on the transmission path and there are no grounding or potential difference issues.

[0039] In some embodiments of this application, the analog-to-digital conversion unit 200 includes an ADC chip acquisition circuit, the input terminal of which is connected to the output terminal of the analog signal conditioning unit 100, and the output terminal of which is connected to the data input terminal of the programmable logic gate array unit 300.

[0040] In some embodiments of this application, the analog-to-digital conversion unit 200, the programmable gate array unit 300, and the network interface unit 500 are integrated on the same board, which is connected to the data acquisition device via an Ethernet interface or a fiber optic interface. An ADC chip acquisition circuit, a PHY chip circuit, and a network port circuit or an optical port circuit are added to the board to complete the ADC analog-to-digital conversion on the board and transmit data through the optical module or network port, achieving fully digital processing of the front-end signal.

[0041] In some embodiments of this application, the programmable gate array (FPGA) unit 300 is configured such that the differential equation recursive operation is implemented by executing an equation defining the input-output relationship of a digital filter. The coefficients of the equation are obtained from the analog prototype filter through a bilinear transform method. The input to the FPGA algorithm module is the accelerometer signal acquired along the X-axis or Y-axis, and the output after processing by the FPGA algorithm is a voltage signal. The digital filter can be a Bessel filter, a Butterworth filter, or a Chebyshev filter. The cutoff frequency of the digital filter can be adjusted by modifying its coefficients, completely replacing the existing method of adjusting the frequency range by desoldering resistors. Regardless of whether the digital filter is a Bessel filter, a Butterworth filter, or a Chebyshev filter, its coefficients are all obtained from the corresponding analog prototype filter through a bilinear transform method.

[0042] The following section details the acquisition and filtering process of digital filter coefficients. This process is executed within a programmable gate array (PGA) unit, and the specific steps are as follows.

[0043] In one implementation, the digital filter is a Bessel filter, and the transfer function of the Bessel filter is:

[0044] Where n is the order of the filter, Let be the transfer function of an nth-order Bessel filter, and s be the complex frequency variable. Let be the value of the nth-order inverse Bessel polynomial at s. Let be the value of the nth-order inverse Bessel polynomial at s = zero. The amplitude characteristic function of the Bessel analog low-pass filter is:

[0045] in, Let be the magnitude of the amplitude characteristic function, representing the relationship between the filter's output signal amplitude and the input signal amplitude as a function of the angular frequency ω. Here, j is the imaginary unit, ω is the angular frequency, and jω is the expression after replacing the complex frequency variable s in the transfer function with purely imaginary numbers. Let ω be the value of the inverse Bessel polynomial of order n at jω.

[0046] The first step is to determine the filter order based on its technical specifications. These specifications include the passband cutoff frequency, stopband cutoff frequency, maximum passband attenuation, and minimum stopband attenuation. The required filter order is then calculated based on these specifications. The filter order determines its complexity; a higher order results in a steeper transition band, but also increases the computational load.

[0047] The second step is to look up the coefficients of the analog prototype filter in a table. The analog prototype filter is a normalized low-pass filter whose coefficients have been pre-calculated and stored in a table. Based on the determined order and the selected filter type, the corresponding analog prototype filter coefficients are retrieved from the table. The filter type can be a Bessel filter, Butterworth filter, or Chebyshev filter; different types of analog prototype filters have different amplitude-frequency and phase characteristics.

[0048] The third step is to perform S-domain frequency transformation. S-domain frequency transformation, also known as frequency pre-distortion, maps the cutoff frequency of the digital filter to the analog domain using a pre-defined frequency pre-distortion formula, yielding the actual cutoff frequency of the analog filter. This step is crucial because the bilinear transform method introduces nonlinear compression on the frequency axis. If the digital domain cutoff frequency is directly used to design the analog filter, the cutoff frequency will shift after conversion back to the digital domain. Frequency pre-distortion compensates for this nonlinear distortion in advance, ensuring that the final digital filter cutoff frequency matches the original design specifications.

[0049] The fourth step involves using the bilinear transform method to convert the analog filter coefficients into digital filter coefficients. The bilinear transform method is a mathematical approach that maps an analog system to a digital system. Its core principle is to represent the complex frequency variables in the analog domain transfer function using digital domain variables. Through algebraic substitution, the transfer function of the analog filter is converted into the transfer function of the digital filter, thus obtaining the coefficients of the digital filter.

[0050] The fifth step is to derive the difference equation based on the digital coefficients. The transfer function of the digital filter is expressed as a rational fraction representing the ratio of the output sequence to the input sequence. After cross-multiplying this rational fraction and rearranging, we obtain an expression that represents the current output value in terms of the current input value, the input values ​​from several previous times, and the output values ​​from several previous times. This expression is the difference equation. The difference equation directly provides the iterative relationship for the recursive calculation.

[0051] The sixth step involves recursively calculating the filtering result using the actual collected data. The digital sequence output from the analog-to-digital converter is used as the input sequence, and each point is substituted into the difference equation. For each new data point, the corresponding filtered output value is calculated. During the recursive calculation, the input and output values ​​from the previous few time steps are stored in a register for use in calculating the current output value. After the calculation is complete, the values ​​in the register are shifted and updated sequentially to prepare for the calculation of the next data point.

[0052] Step 7: Save the calculation results and end the algorithm flow. The filtered digital sequence obtained by recursive calculation is stored in the output buffer for subsequent network interface units to read and send.

[0053] The signal processing device for an accelerometer provided in this application processes the accelerometer signal through active low-pass and high-pass filtering, a proportional amplifier circuit, and FPGA software algorithms. Finally, the data is transmitted via an optical port or an RJ45 network port, improving data transmission rate and signal stability. The FPGA software filtering method allows for real-time adjustment of the filtering frequency range, and the use of optical ports or RJ45 network ports improves signal transmission efficiency and anti-interference capabilities. Compared with existing technologies, this device offers stronger anti-interference capabilities, higher bandwidth and speed, longer transmission distances, and eliminates grounding and potential difference issues. The FPGA software algorithm filtering provides deterministic low latency, extremely high processing speed, and real-time performance, resulting in more accurate accelerometer signal acquisition.

[0054] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0055] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. Furthermore, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Additionally, the shown or discussed mutual couplings, direct couplings, or communication connections may be through some communication interfaces; indirect couplings or communication connections between devices or units may be electrical, mechanical, or other forms.

[0056] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0057] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0058] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a processor-executable, non-volatile, computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0059] Finally, it should be noted that the above-described embodiments are merely specific implementations of this application, used to illustrate the technical solutions of this application, and not to limit them. The scope of protection of this application is not limited thereto. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can still modify or easily conceive of changes to the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features, within the scope of the technology disclosed in this application. Such modifications, changes, or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be covered within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A signal processing device for an accelerometer, characterized in that, It includes analog signal conditioning units, analog-to-digital converters, and programmable gate arrays; The input terminal of the analog signal conditioning unit is used to connect to the accelerometer sensor, the output terminal of the analog signal conditioning unit is connected to the input terminal of the analog-to-digital converter, and the output terminal of the analog-to-digital converter is connected to the data input terminal of the programmable gate array unit. The analog signal conditioning unit is configured to perform bias voltage adjustment, anti-aliasing low-pass filtering, and proportional amplification on the raw signal output by the accelerometer sensor. The programmable gate array unit is configured to load a digital filter with configurable coefficients, perform a difference equation recursive operation on the digital sequence output by the analog-to-digital converter unit to output a filtered digital sequence. The coefficients of the digital filter are obtained by converting the analog prototype filter through the bilinear transform method, and the coefficients are reconfigured in response to an online configuration command to adjust the cutoff frequency of the digital filter.

2. The apparatus according to claim 1, characterized in that, Also includes: A constant current source circuit is provided, the output terminal of which is connected to the power supply terminal of the accelerometer sensor. The constant current source circuit is configured to set the output current value by adjusting the resistance value of resistor Rset.

3. The apparatus according to claim 1, characterized in that, The analog signal conditioning unit includes an active low-pass filter circuit, a high-pass filter circuit, and a proportional amplifier circuit. The input terminal of the active low-pass filter circuit is used to receive the raw signal output by the accelerometer sensor. The output terminal of the active low-pass filter circuit is connected to the input terminal of the high-pass filter circuit. The output terminal of the high-pass filter circuit is connected to the input terminal of the proportional amplifier circuit. The output terminal of the proportional amplifier circuit is connected to the input terminal of the analog-to-digital converter unit.

4. The apparatus according to claim 1, characterized in that, Also includes: A network interface unit is connected to the data output terminal of the programmable gate array unit. The network interface unit is configured to encapsulate the filtered digital sequence output by the programmable gate array unit into a data packet and send the data packet to the data acquisition device through an Ethernet interface or an optical fiber interface.

5. The apparatus according to claim 4, characterized in that, The network interface unit includes a PHY chip and an RJ45 network port. The input terminal of the PHY chip is connected to the data output terminal of the programmable gate array unit, and the output terminal of the PHY chip is connected to the RJ45 network port. The PHY chip is configured to encapsulate the filtered digital sequence into a data packet and send it through the RJ45 network port.

6. The apparatus according to claim 4, characterized in that, The network interface unit includes an optical port circuit. The input terminal of the optical port circuit is connected to the data output terminal of the programmable gate array unit. The optical port circuit is configured to encapsulate the filtered digital sequence into a data packet and send it through the optical fiber interface.

7. The apparatus according to claim 1, characterized in that, The analog-to-digital conversion unit includes: An ADC chip acquisition circuit is provided, wherein the input terminal of the ADC chip acquisition circuit is connected to the output terminal of the analog signal conditioning unit, and the output terminal of the ADC chip acquisition circuit is connected to the data input terminal of the programmable gate array unit.

8. The apparatus according to claim 1, characterized in that, The programmable gate array unit is configured such that the differential equation recursive operation is implemented by executing an equation that defines the input-output relationship of the digital filter, the coefficients of which are obtained by the analog prototype filter through a bilinear transform method.

9. The apparatus according to claim 1, characterized in that, The programmable gate array unit is also configured to adjust the cutoff frequency of the digital filter by modifying the coefficients of the digital filter.

10. The apparatus according to claim 4, characterized in that, The analog-to-digital conversion unit, the programmable gate array unit, and the network interface unit are integrated on the same board, and the board is connected to the data acquisition device through the Ethernet interface or the fiber optic interface.

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