Memory module
By adding two main control chips and two DIMMs to the memory module and connecting them with DDR and CXL interfaces, the problem of insufficient memory capacity expansion of existing memory modules is solved, and higher memory capacity and computing performance are achieved.
Patent Information
- Application Number
- CN202420700551.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-04-07
- Publication Date
- 2025-03-18
- Estimated Expiration
- 2034-04-07
AI Technical Summary
The memory capacity of existing memory modules is not very expanded, making it difficult to meet the growing demand for computer memory.
Design a memory module, including two main control chips and two DIMMs, connect the DIMMs through the DDR controller interface, and connect it to external devices through the CXL interface and PCIE interface to achieve expansion of memory capacity.
By increasing the number of DIMMs and using high bandwidth DDR and CXL interfaces, the memory capacity of the memory module is significantly improved, meeting higher computing needs.
Smart Images
Figure CN222636632U_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of memory chips, and in particular to a memory module. Background Art
[0002] With the continuous development of computer technology, the demand for memory capacity is increasing. Compute Express Link (CXL) is currently supported as a cache coherent interconnect protocol for memory expansion. CXL technology maintains consistency between the CPU memory space and the memory on the attached device, and allows resource sharing for higher performance. For example, a CXL Accelerator Card (CXL AIC) typically includes a high-speed interface that supports the CXL protocol, which can be integrated into a server or computing platform that supports CXL to enhance performance in computing, storage, or networking, and is used to expand memory, accelerate GPUs, or accelerate other types of hardware. However, the memory capacity expansion of existing memory modules, such as CXL AIC memory modules, is not high. Utility Model Content
[0003] In view of this, it is necessary to provide a memory module to solve the technical problem of insufficient memory capacity expansion of the memory module.
[0004] An embodiment of the present application provides a memory module, which includes: a first main control chip, a second main control chip, a first DIMM and a second DIMM, wherein the first main control chip is connected to the first DIMM through a first DDR controller interface, and a CXL interface of the first main control chip is connected to an external device through a first PCIE interface; the second main control chip is connected to the second DIMM through a second DDR controller interface, and a CXL interface of the second main control chip is connected to the external device through a second PCIE interface, the CXL interface of the first main control chip is a CEM interface, and the CXL interface of the second main control chip is an MCIO interface.
[0005] The technical effects of the embodiments of the present application include: the first master control chip is connected to the first DIMM through the first DDR controller interface, the second master control chip is connected to the second DIMM through the second DDR controller interface, and at the same time, the CEM interface of the first master control chip is connected to the server mainboard through the first PCIE connection and the MCIO interface of the second master control chip is connected to the server mainboard through the second PCIE interface, thereby realizing the expansion connection of the first master control chip and the second master chip to the DIMM, thereby improving the memory capacity of the memory module.
[0006] In some embodiments of the present application, the first DDR controller interface includes a first preset number of fourth-generation double data rate unbuffered dual in-line memory modules DDR4 UDIMM, fourth-generation double data rate registered dual in-line memory modules DDR4 RDIMM, fifth-generation double data rate unbuffered dual in-line memory modules DDR5 UDIMM, and / or, fifth-generation double data rate registered dual in-line memory modules DDR5 RDIMM; the second DDR controller interface includes a second preset number of fourth-generation double data rate unbuffered dual in-line memory modules DDR4 UDIMM, fourth-generation double data rate registered dual in-line memory modules DDR4 RDIMM, fifth-generation double data rate unbuffered dual in-line memory modules DDR5 UDIMM, and / or, fifth-generation double data rate registered dual in-line memory modules DDR5 RDIMM.
[0007] In some embodiments of the present application, the bandwidth bit number of the first master control chip includes 8 bits and / or 16 bits, and the bandwidth bit number of the second master control chip includes 8 bits and / or 16 bits.
[0008] In some embodiments of the present application, the first master control chip is connected to a third preset number of first DIMMs through the first DDR controller interface, and / or the second master control chip is connected to a fourth preset number of second DIMMs through the second DDR controller interface.
[0009] In some embodiments of the present application, the first PCIE interface includes an interface that supports the PCIE protocol and has an X8 or X16 channel interface, and the second PCIE interface includes an interface that supports the PCIE protocol and has an X8 or X16 channel interface.
[0010] In some embodiments of the present application, the first master control chip is connected to the first Nor flash through a first SPI interface, and the first non-volatile flash memory Nor flash is used to store the firmware of the first master control chip; the second master control chip is connected to the second Nor flash through a second SPI interface, and the second Nor flash is used to store the firmware of the second master control chip.
[0011] In some embodiments of the present application, the memory module further includes a CEM gold finger, the CEM gold finger is plugged into the CEM interface, and the CEM interface is connected to the external device through the CEM gold finger.
[0012] In some embodiments of the present application, the CEM gold finger includes a CEM X16 gold finger.
[0013] In some embodiments of the present application, the memory module further includes a MCIO connector, the MCIO connector is plugged into the MCIO interface, and the second main control chip is connected to the external device via the MCIO connector.
[0014] In some embodiments of the present application, the MCIO connector includes a MCIO X8 connector or a MCIO X16 connector. BRIEF DESCRIPTION OF THE DRAWINGS
[0015] Figure 1 A schematic diagram of the structure of a memory module in an embodiment is shown.
[0016] Main component symbols
[0017] 10-memory module; 101-first main control chip; 102-second main control chip; 103-first DIMM; 104-second DIMM; 105-first Nor flash; 106-second Nor flash; 107-CEM interface; 108-MCIO connector; 109-first Power connector; 20-external device; 201-external CEM interface; 202-external MCIO connector; 203-second Power connector.
[0018] The following specific embodiments will further illustrate the present application in conjunction with the above-mentioned drawings. DETAILED DESCRIPTION
[0019] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments.
[0020] It should be noted that when a component is referred to as being "mounted on" another component, it may be directly on the other component or there may be a central component. When a component is considered to be "set on" another component, it may be directly set on the other component or there may be a central component at the same time.
[0021] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application. The term "or / and" used herein includes any and all combinations of one or more related listed items.
[0022] Some embodiments of the present application will be described in detail below with reference to the accompanying drawings.
[0023] Compute Express Link (CXL) is the currently supported cache coherent interconnect protocol for memory expansion. There are three types of existing CXL protocols: Type 1, Type 2, and Type 3. Type 1 is commonly used in cache devices such as network cards, and usually only supports io and cache protocols. Type 2 is a memory accelerator commonly used in applications such as GPUs and AI, and usually supports io, cache, and memory protocols. Type 3 is commonly used in memory buffers and is used to expand memory bandwidth or memory capacity. Type 3 supports both io and memory protocols. This application involves how to increase the memory capacity of a type 3 memory expansion controller chip.
[0024] The appearance of the memory module 10 involved in the present application is a preset appearance, and the preset appearance dimensions are based on the appearance dimensions of a standard accelerator card (AIC). For example, the preset appearance dimensions can be set to 3 / 4 of the length, the same height, and double the width of an AIC card. The memory module 10 can be inserted into a PCIE slot that supports a CXL protocol platform for application.
[0025] See also Figure 1 , an embodiment of the present application provides a memory module 10, the memory module 10 includes: a first main control chip 101, a second main control chip 102, a first DIMM 103 and a second DIMM 104, wherein DIMM stands for Dual inline memory module, and its Chinese name is dual inline memory module. The first main control chip 101 is connected to the first DIMM 103 through a first DDR controller interface, and the Compute Express Link (CXL) interface of the first main control chip 101 is connected to an external device 20 through a first PCIE interface, wherein DDR stands for Double Data Rate, and its Chinese name is double data rate. The second main control chip 102 is connected to the second DIMM 104 through a second DDR controller interface, and the Compute Express Link (CXL) interface of the second main control chip 102 is connected to the external device 20 through a second PCIE interface. The CXL interface of the first master control chip 101 is a CEM interface 107, and the CXL interface of the second master control chip 102 is an MCIO interface, wherein PCIE stands for Peripheral Component Interconnect Express, and its Chinese name is External Device Interconnect Bus.
[0026] In some embodiments of the present application, the first main control chip 101 and the second main control chip 102 are memory expansion controller (Memory Expander Controller, MXC) chips, and the external device 20 may be a server motherboard, which is not limited in this embodiment.
[0027] In some embodiments of the present application, the first master control chip 101 is connected to the first DIMM 103 through the first DDR controller interface, and the second master control chip 102 is connected to the second DIMM 104 through the second DDR controller interface. At the same time, the CEM interface 107 of the first master control chip 101 is connected to the server motherboard through the first PCIE connection and the MCIO interface of the second master control chip 102 is connected to the server motherboard through the second PCIE interface, thereby realizing the expansion connection of the DIMM between the first master control chip 101 and the second master control chip 102, thereby increasing the memory capacity of the memory module 10.
[0028] In some embodiments of the present application, the first DDR controller interface includes a first preset number of fourth-generation double data rate unbuffered dual in-line memory modules DDR4 UDIMM, fourth-generation double data rate registered dual in-line memory modules DDR4 RDIMM, fifth-generation double data rate unbuffered dual in-line memory modules DDR5 UDIMM, and / or, fifth-generation double data rate registered dual in-line memory modules DDR5 RDIMM; the second DDR controller interface includes a second preset number of fourth-generation double data rate unbuffered dual in-line memory modules DDR4 UDIMM, fourth-generation double data rate registered dual in-line memory modules DDR4 RDIMM, fifth-generation double data rate unbuffered dual in-line memory modules DDR5 UDIMM, and / or, fifth-generation double data rate registered dual in-line memory modules DDR5 RDIMM.
[0029] In some embodiments of the present application, the first preset number of the first DDR controller interface can be pre-set according to the memory expansion requirement, and the second preset number of the second DDR controller interface can also be pre-set according to the memory expansion requirement, which is not limited in this embodiment. For example, the first preset number and the second preset number can be set to one or more of the following combinations: 1, 2, 4.
[0030] In some embodiments of the present application, the memory module 10 has two main control chips, both of which support DDR4 and DDR5 protocols, and the CXL signals of the two main control chips are connected to the server motherboard through the CEM interface 107 and the MCIO interface respectively, thereby improving the adaptability of the memory module 10.
[0031] In some embodiments of the present application, the bandwidth bit number of the first master control chip 101 includes 8 bits and / or 16 bits, and the bandwidth bit number of the second master control chip 102 includes 8 bits and / or 16 bits.
[0032] In some embodiments of the present application, the number of bandwidth bits of the first master control chip 101 is 8, indicating an 8-bit CXL signal, and the number of bandwidth bits of the first master control chip 101 is 16, indicating a 16-bit CXL signal. This embodiment does not limit the number of bandwidth bits. For example, the number of bandwidth bits of the first master control chip 101 and the second master control chip 102 can be set according to memory expansion requirements.
[0033] In some embodiments of the present application, the first master control chip 101 is connected to a third preset number of first DIMMs 103 through the first DDR controller interface, and / or the second master control chip 102 is connected to a fourth preset number of second DIMMs 104 through the second DDR controller interface.
[0034] In some embodiments of the present application, this embodiment does not limit the third preset number and the fourth preset number. For example, the third preset number and the fourth preset number can be set to one of 1, 2 or 4.
[0035] In some embodiments of the present application, the first PCIE interface includes an interface that supports the PCIE protocol and has an X8 or X16 channel, and the second PCIE interface includes an interface that supports the PCIE protocol and has an X8 or X16 channel. The PCIE interface includes a first PCIE interface and a second PCIE interface. Since the data transmission efficiency of the PCIE interface is high, the performance of the memory module 10 can be better improved through the PCIE interface.
[0036] In some embodiments of the present application, the first main control chip 101 is connected to the first Nor flash 105 through a first SPI interface, and the first Nor flash 105 is used to store the firmware of the first main control chip 101; the second main control chip 102 is connected to the second Nor flash 106 through a second SPI interface, and the second Nor flash 106 is used to store the firmware of the second main control chip 102.
[0037] In some embodiments of the present application, the memory module 10 further includes a CEM gold finger, which is plugged into the CEM interface 107 and is used to provide a reset signal for the first main control chip 101 .
[0038] In some embodiments of the present application, the first main control chip 101 is connected to the external CEM interface 201 of the external device 20 through the CEM gold finger, and the CEM gold finger includes a CEM X16 gold finger.
[0039] In some embodiments of the present application, the memory module 10 further includes a MCIO connector 108 , which is plugged into the MCIO interface and is used to provide a reset signal for the second main control chip 102 .
[0040] In some embodiments of the present application, the second master control chip 102 is connected to the external MCIO connector 202 of the external device 20 through the MCIO connector 108 , and the MCIO connector 108 includes a MCIO X8 connector or a MCIO X16 connector.
[0041] In some embodiments of the present application, for example, the memory module 10 may use a first main control chip 101 with a 16-bit bandwidth and a second main control chip 102 with a 16-bit bandwidth. The first main control chip 101 corresponds to a first DDR4 controller interface, and the second main control chip 102 corresponds to a second DDR5 controller interface. The first DDR4 controller interface can support external expansion of four first DIMMs 103, and the second DDR5 controller interface can support external expansion of four second DIMMs 104, so as to increase the memory capacity of the memory module 10.
[0042] In some embodiments of the present application, the memory module 10 further includes a first power connector 109 , and the first Power connector 109 is connected to a second Power connector 203 of the external device 20 for providing power input to the memory module 10 .
[0043] Those skilled in the art should recognize that the above embodiments are only used to illustrate the present application, and are not used as limitations on the present application. As long as they are within the spirit of the present application, appropriate changes and modifications to the above embodiments are within the scope of the present application.
Claims
1. A memory module, characterized in that: The memory module includes: a first main control chip, a second main control chip, a first DIMM and a second DIMM, the first main control chip is connected to the first DIMM through a first DDR controller interface, and the CXL interface of the first main control chip is connected to an external device through a first PCIE interface; the second main control chip is connected to the second DIMM through a second DDR controller interface, and the CXL interface of the second main control chip is connected to the external device through a second PCIE interface, the CXL interface of the first main control chip is a CEM interface, and the CXL interface of the second main control chip is an MCIO interface.
2. The memory module according to claim 1, wherein: The first DDR controller interface includes a first preset number of fourth-generation double data rate unbuffered dual in-line memory modules DDR4 UDIMM, fourth-generation double data rate registered dual in-line memory modules DDR4 RDIMM, fifth-generation double data rate unbuffered dual in-line memory modules DDR5 UDIMM, and / or, fifth-generation double data rate registered dual in-line memory modules DDR5 RDIMM; the second DDR controller interface includes a second preset number of fourth-generation double data rate unbuffered dual in-line memory modules DDR4 UDIMM, fourth-generation double data rate registered dual in-line memory modules DDR4 RDIMM, fifth-generation double data rate unbuffered dual in-line memory modules DDR5 UDIMM, and / or, fifth-generation double data rate registered dual in-line memory modules DDR5 RDIMM.
3. The memory module according to claim 1, wherein: The number of bits of the bandwidth of the first master control chip includes 8 bits and / or 16 bits, and the number of bits of the bandwidth of the second master control chip includes 8 bits and / or 16 bits.
4. The memory module according to claim 1, wherein: The first master control chip is connected to a third preset number of first DIMMs via the first DDR controller interface, and / or the second master control chip is connected to a fourth preset number of second DIMMs via the second DDR controller interface.
5. The memory module according to claim 1, wherein: The first PCIE interface includes an interface supporting the PCIE protocol and having an X8 or X16 channel interface, and the second PCIE interface includes an interface supporting the PCIE protocol and having an X8 or X16 channel interface.
6. The memory module according to claim 1, wherein: The first master control chip is connected to a first Nor flash via a first SPI interface, and the first Nor flash is used to store the firmware of the first master control chip; the second master control chip is connected to a second Nor flash via a second SPI interface, and the second Nor flash is used to store the firmware of the second master control chip.
7. The memory module according to claim 1, wherein: The memory module further comprises a CEM gold finger, the CEM gold finger is plugged into the CEM interface, and the CEM interface is connected to the external device via the CEM gold finger.
8. The memory module according to claim 7, wherein: The CEM gold finger includes a CEM X16 gold finger.
9. The memory module according to claim 1, wherein: The memory module further comprises a MCIO connector, the MCIO connector is plugged into the MCIO interface, and the second main control chip is connected to the external device via the MCIO connector.
10. The memory module according to claim 9, wherein: The MCIO connector includes a MCIO X8 connector or a MCIO X16 connector.