Data transmission methods, network interface cards (NICs) at the data receiving end, electronic devices, and storage media.

Abstract

This application provides a data transmission method, a network interface card (NIC) for a data receiving end, an electronic device, and a storage medium. The data transmission method is applied to the NIC of the data receiving end. The NIC writes data to the host memory of the data receiving end via a bus. The data transmission method includes: if the bus bandwidth resources required for the NIC to write the target data to the host memory exceed the bus bandwidth resources available to the NIC, then writing a portion of the target data to the NIC's NIC buffer; the NIC buffer includes a first memory buffer configured for the NIC based on its on-chip memory and a second memory buffer configured for the NIC based on its onboard memory; the data sending end sends the target data to the data receiving end via remote direct memory access; and a portion of the data is written from the NIC buffer to the host memory. The solution of this application can better avoid data packet loss problems when facing sudden traffic surges.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to data transmission methods, network interface cards (NICs) for data receiving ends, electronic devices, and storage media. Background Technology

[0002] When using RDMA (Remote Direct Memory Access) technology for data transmission, the communication latency and CPU (Central Processing Unit) resources consumed during the data transmission process are relatively low because the operating systems of both the sending and receiving ends are involved relatively little.

[0003] However, during data transmission from the sending end to the receiving end via RDMA, in the event of a sudden surge in traffic—that is, the sending end sending a large amount of target data to the receiving end in a short period of time—the bus bandwidth resources required by the receiving end's Network Interface Card (NIC) to write the target data to the host memory often exceed the available bus bandwidth resources of the NIC. When the required bus bandwidth resources exceed the available bus bandwidth resources, the NIC cannot write part of the target data to the receiving end's host memory via the bus, often resulting in data packet loss. Data packet loss often affects communication latency and data transmission rate. Therefore, how to minimize data packet loss has become a pressing technical problem for relevant engineers. Summary of the Invention

[0004] This application provides a data transmission method, a network card for a data receiving end, an electronic device, and a storage medium to solve one or more of the above-mentioned technical problems.

[0005] In a first aspect, embodiments of this application provide a data transmission method applied to a network interface card (NIC) at a data receiving end. The NIC writes data to the host memory of the data receiving end via a bus. The method includes:

[0006] During the process of receiving target data sent by the data sender at the data receiver, if the bus bandwidth resources required for the network card to write the target data into the host memory exceed the bus bandwidth resources available to the network card, then a portion of the target data is written into the network card buffer. The network card buffer includes a first memory buffer configured for the network card based on its on-chip memory and a second memory buffer configured for the network card based on its onboard memory. The data sender sends the target data to the data receiver via remote direct memory access.

[0007] Write some data from the network card buffer to the host memory.

[0008] Secondly, embodiments of this application provide a network interface card (NIC) for a data receiver, which writes data to the host memory of the data receiver via a bus. The NIC includes:

[0009] The first data writing module is used to write a portion of the target data to the network card buffer if, during the process of receiving target data sent by the data sender at the data receiver, the bus bandwidth resources required by the network card to write the target data to the host memory exceed the bus bandwidth resources available to the network card. The network card buffer includes a first memory buffer configured for the network card based on its on-chip memory and a second memory buffer configured for the network card based on its onboard memory. The data sender sends the target data to the data receiver via remote direct memory access.

[0010] The second data writing module is used to write a portion of the data from the network card buffer to the host memory.

[0011] Thirdly, embodiments of this application provide an electronic device, including a memory, a processor, and a computer program stored in the memory, wherein the processor implements the method provided in any embodiment of this application when executing the computer program.

[0012] Fourthly, embodiments of this application provide a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the method provided in any embodiment of this application.

[0013] Compared with the prior art, this application has the following advantages:

[0014] The technical solution of this application, because the network interface card (NIC) buffer includes both a first memory buffer configured based on the NIC's on-chip memory and a second memory buffer configured based on the NIC's onboard memory, has a higher memory capacity than the first memory buffer configured based on the NIC's on-chip memory. In other words, the NIC buffer can store more data than the first memory buffer configured based on the NIC's on-chip memory. Because the NIC buffer can store more data, when the bus bandwidth required for the NIC to write target data to host memory exceeds the available bus bandwidth, writing a portion of the target data to the NIC buffer first, and then writing the remaining data from the NIC buffer to host memory, can better avoid data packet loss when the required bus bandwidth exceeds the available bus bandwidth. In other words, when the required bus bandwidth resources exceed the available bus bandwidth resources due to sudden traffic surges, it can better avoid data packet loss, thereby reducing the impact of data packet loss on communication latency and data transmission rate.

[0015] In addition, since the onboard memory of the network card is configured inside the network card and its cost is relatively low, configuring the onboard memory of the network card as the second memory buffer of the network card can reduce the configuration cost and configuration complexity of the network card buffer.

[0016] The above overview is for illustrative purposes only and is not intended to be limiting in any way. In addition to the illustrative aspects, embodiments, and features described above, further aspects, embodiments, and features of this application will become readily apparent from the accompanying drawings and the following detailed description. Attached Figure Description

[0017] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the various drawings denote the same or similar parts or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings depict only some embodiments disclosed in this application and should not be construed as limiting the scope of this application.

[0018] Figure 1 A schematic diagram of a data transmission process provided in an embodiment of this application is shown;

[0019] Figure 2 A flowchart of a data transmission method provided in an embodiment of this application is shown;

[0020] Figure 3 A schematic diagram of a second data transmission process provided in an embodiment of this application is shown;

[0021] Figure 4 A schematic diagram of the third data transmission process provided in the embodiments of this application is shown;

[0022] Figure 5 A structural block diagram of a data transmission apparatus according to an embodiment of this application is shown; and

[0023] Figure 6 A block diagram of an electronic device used to implement embodiments of this application is shown. Detailed Implementation

[0024] In the following description, only certain exemplary embodiments are briefly described. As those skilled in the art will recognize, the described embodiments can be modified in various ways without departing from the concept or scope of this application. Therefore, the drawings and description are considered to be exemplary in nature and not restrictive.

[0025] To facilitate understanding of the technical solutions of the embodiments of this application, the relevant technologies of the embodiments of this application are described below. The following relevant technologies are optional solutions and can be combined with the technical solutions of the embodiments of this application in any way, and all of them fall within the protection scope of the embodiments of this application.

[0026] This application embodiment relates to a data transmission scheme applied to the network interface card (NIC) of the data receiving end. The NIC is a hardware device in the data receiving end responsible for network communication. The NIC is connected to the host of the data receiving end via a bus, and also to other hardware devices on the data receiving end via the bus. If the data sending end transmits data to the data receiving end via Remote Direct Memory Access (RDM), that is, sends target data to the data receiving end via RDM, the NIC of the data receiving end, upon receiving the target data transmitted by the data sending end, will write the data (target data) into the host memory via the bus.

[0027] In this embodiment, the bus type is generally a PCIe (PCI Express, high-speed serial computer expansion bus standard) bus, but other types of buses are also possible. The network card type is generally a Smart NIC (Smart Network Interface Card), but other types of network cards are also possible. Furthermore, it should be noted that the number of data transmitters sending data to the data receiver via remote direct memory access is generally multiple, but can also be only one. The following description uses a PCIe bus, a Smart NIC network card, and multiple data transmitters as examples to illustrate the data transmission method provided in this embodiment.

[0028] In the data transmission scheme involved in this application embodiment, if the bus bandwidth resources required by the network card to write the target data to the host memory exceed the bus bandwidth resources that the network card can obtain, then a portion of the target data is first written to the network card buffer of the network card, and then a portion of the data is written from the network card buffer to the host memory.

[0029] Specifically, when a network interface card (NIC) writes data to the host memory of the receiving end via the bus, it must first acquire flow control credits. However, in situations where a sudden surge in traffic causes the flow control credits required for the NIC to write the target data to host memory to exceed the NIC's available flow control credits, the NIC will be unable to acquire enough flow control credits to write a portion of the target data to host memory. This results in a situation where the bus bandwidth resources required for the NIC to write the target data to host memory exceed the NIC's available bus bandwidth resources. When this situation occurs, some of the data can be temporarily written to the NIC's buffer. Then, once the NIC can acquire enough flow control credits to support the transmission of some data, the remaining data can be written from the NIC buffer to host memory.

[0030] In this embodiment, the network interface card (NIC) buffer includes a first memory buffer and a second memory buffer. The first memory buffer is a default memory buffer configured for the NIC based on its on-chip memory, such as a shared memory buffer configured based on the NIC's on-chip memory. The second memory buffer is an extended memory buffer configured for the NIC using its onboard memory.

[0031] Because the network interface card (NIC) buffer includes both a first memory buffer configured based on the NIC's on-chip memory and a second memory buffer configured based on the NIC's onboard memory, the NIC buffer has a larger memory capacity than the first memory buffer configured based on the NIC's on-chip memory. In other words, the NIC buffer can store more data than the first memory buffer configured based on the NIC's on-chip memory. Since the NIC buffer can store more data, when the bus bandwidth required for the NIC to write target data to host memory exceeds the NIC's available bus bandwidth, writing a portion of the target data to the NIC buffer first, and then writing the remaining data from the NIC buffer to host memory, can better prevent data loss when the required bus bandwidth exceeds the available bus bandwidth. In other words, when the required bus bandwidth resources exceed the available bus bandwidth resources due to sudden traffic surges, it can better avoid data packet loss, thereby reducing the impact of data packet loss on communication latency and data transmission rate.

[0032] In addition, since the onboard memory of the network card is configured inside the network card and its cost is relatively low, configuring the onboard memory of the network card as the second memory buffer of the network card can reduce the configuration cost and configuration complexity of the network card buffer.

[0033] To more clearly illustrate the data transmission method provided in the embodiments of this application, an application example of the data transmission method provided in the embodiments of this application is first introduced. This data transmission method is applied to the network card of the data receiving end, and the network card writes data to the host memory of the data receiving end through the bus. The specific implementation process of this application example can be found in [reference needed]. Figure 1 The data transmission process is shown below:

[0034] In most cases, when multiple data senders send a large amount of target data to the network interface card (NIC) within a short period, the flow control credits required for the NIC to write the target data to host memory exceed the NIC's available flow control credits. When the required flow control credits exceed the NIC's available credits, the NIC cannot obtain enough credits to write a portion of the target data to host memory. This results in the bus bandwidth resources consumed by the NIC to write the target data to host memory exceeding its available bus bandwidth resources. In this situation, a portion of the target data is first written to the NIC's buffer. Then, when the NIC can obtain enough flow control credits to support the transmission of some data, the remaining data is written from the NIC buffer to host memory. Specifically, when the NIC can obtain enough flow control credits to support the transmission of some data, it reads some data from the NIC buffer and writes the remaining data to host memory.

[0035] Because the network interface card (NIC) buffer includes both a first memory buffer configured based on the NIC's on-chip memory and a second memory buffer configured based on the NIC's onboard memory, the NIC buffer has a larger memory capacity than the first memory buffer configured based on the NIC's on-chip memory. In other words, the NIC buffer can store more data than the first memory buffer configured based on the NIC's on-chip memory. Therefore, even if the data sender abnormally sends a large amount of target data to the NIC in a short period, causing the required bus bandwidth resources to exceed the available bus bandwidth resources, data packet loss can be better avoided by first writing a portion of the target data to the NIC buffer and then writing a portion of the data from the NIC buffer to the host memory. Because it can better avoid data packet loss, the data transmission method provided in this embodiment can also reduce the impact of data packet loss on communication latency and data transmission rate.

[0036] It should be noted that the above application examples of the data transmission method provided in the embodiments of this application are for ease of understanding and are not intended to limit the data transmission method provided in the embodiments of this application. Specifically, the application scenarios of the data transmission method provided in the embodiments of this application are not specifically limited.

[0037] In addition, the data receiving end and the data sending end can be hardware devices with data transmission capabilities, such as servers and terminal devices.

[0038] The technical solutions of this application and how they solve the aforementioned technical problems are described in detail below with specific embodiments. The following related technologies are optional solutions and can be arbitrarily combined with the technical solutions of the embodiments of this application, all of which fall within the protection scope of the embodiments of this application. Identical or similar concepts or processes may not be described again in some embodiments.

[0039] Figure 2 A flowchart of a data transmission method 200 provided in an embodiment of this application is shown. Figure 2 The data transmission method shown is applied to the network card of the data receiving end. The network card writes data to the host memory of the data receiving end through the bus. The method may include steps S201-S202.

[0040] In step S201, during the process of the data receiving end receiving the target data sent by the data sending end, if the bus bandwidth resources required for the network card to write the target data to the host memory exceed the bus bandwidth resources that the network card can obtain, then a portion of the target data is written to the network card buffer of the network card; the network card buffer includes a first memory buffer configured for the network card based on the on-chip memory of the network card and a second memory buffer configured for the network card based on the onboard memory of the network card; the data sending end sends the target data to the data receiving end through remote direct memory access.

[0041] The situation where the bus bandwidth resources required for the network interface card (NIC) to write target data to host memory exceed the NIC's available bus bandwidth resources generally occurs when a data sending end sends a large amount of target data to the NIC in a short period of time. For example, this can happen when multiple data sending ends simultaneously send large amounts of target data to the NIC within a short timeframe. Specifically, when the flow control credits required for the NIC to write target data to host memory exceed its available flow control credits, the NIC will be unable to obtain sufficient flow control credits to write a portion of the target data to host memory. This results in the situation where the bus bandwidth resources required for the NIC to write target data to host memory exceed its available bus bandwidth resources.

[0042] Writing a portion of the target data to the network card's buffer can mean first obtaining a segment of available memory space from the network card buffer as the target available memory space, and then writing a portion of the data into the target available memory space.

[0043] In one possible implementation, to facilitate the management of the network interface card (NIC) buffer's memory space, improve its utilization, and increase the efficiency of writing partial data from the target data into the NIC buffer, when writing partial data from the target data into the NIC buffer, if there are remaining buffer queue elements in the pre-configured buffer queue (BQ), the target buffer queue element is read from the remaining buffer queue elements. Then, the partial data is written to the target available memory space identified by the target buffer queue element. Here, the buffer queue is used to store multiple buffer queue elements configured according to the available memory space corresponding to the NIC buffer; the buffer queue element is used to identify a segment of available memory space in the NIC buffer.

[0044] The buffer queue is created by the application running on the data receiving end and its corresponding driver. Generally, before data transmission, the application and its driver pre-create the buffer queue in a second memory buffer. For example... Figure 3 As shown, after the application and its corresponding driver pre-create buffer queues in the second memory buffer, the host at the data receiving end (specifically, the application running on the host) first configures multiple buffer queue elements (BQEs) based on the available memory space corresponding to the network card buffer, and then writes these multiple buffer queue elements into the buffer queue. Configuring multiple buffer queue elements based on the available memory space corresponding to the network card buffer can mean first dividing the available memory space corresponding to the second memory buffer in the network card buffer into multiple segments, and then generating corresponding buffer queue elements for each segment. Each segment of available memory space corresponds to a contiguous physical address, and each buffer queue element is used to identify a segment of available memory space in the network card buffer; that is, each buffer queue element is used to identify a contiguous physical address segment in the network card buffer. Specifically, each buffer queue element is used to identify a contiguous physical address segment in the second memory buffer.

[0045] In one example, the available memory space corresponding to the second memory buffer is 50MB (Mega Byte). At this time, 40MB of available memory space can be selected from the available memory space corresponding to the second memory buffer, and this 40MB of available memory space can be divided into 20 segments of available memory space. Then, corresponding buffer queue elements are generated for each of these 20 segments of available memory space, that is, 20 buffer queue elements are generated. Each buffer queue element is used to identify a 2MB segment of available memory space in the second memory buffer.

[0046] After writing multiple buffer queue elements to the buffer queue, since the buffer queue elements are used to identify a segment of available memory space in the network interface card (NIC) buffer, the presence of remaining buffer queue elements in the buffer queue proves that at least one segment of available memory space exists in the NIC buffer. Please refer to [further details]. Figure 3 When there are remaining buffer queue elements in the network card's buffer queue, the network card can further read the target buffer queue element from the remaining buffer queue elements, obtain the target available memory space identified by the target buffer queue element, and write some data to the target available memory space, so as to realize writing some data to the network card's buffer.

[0047] In one possible implementation, in order to ensure that the remaining buffer queue elements can accurately identify the remaining available memory space in the network card buffer, after writing some data to the target available memory space identified by the target buffer queue element, the target buffer queue element should be further deleted from the remaining buffer queue elements.

[0048] In one example, the remaining buffer queue elements include buffer queue element 1, buffer queue element 2, and buffer queue element 3. After buffer queue element 1 is the target buffer queue element and the network card has written some data to the target available memory space identified by buffer queue element 1, buffer queue element 1 can be deleted from the remaining buffer queue elements to update the remaining buffer queue elements and obtain the updated remaining buffer queue elements. At this time, the updated remaining buffer queue elements include buffer queue element 2 and buffer queue element 3.

[0049] Additionally, to ensure the receiving host can promptly understand the data storage status of partial data (at least including whether the data is stored in the network interface card (NIC) buffer and its location within the buffer), and to write some data from the NIC buffer to the host memory when the required bus bandwidth exceeds the available bus bandwidth, such as... Figure 3As shown, after writing partial data to the target available memory space identified by the target buffer queue element, the network card can further write a first completion queue element (CQE) to the pre-configured completion queue (CQ) and send the first completion queue element to the host of the data receiving end. To better identify the completed IO (Input / Output) task, while sending the first completion queue element to the host of the data receiving end, the IO task identifier corresponding to the IO task that wrote partial data to the target available memory space can also be sent to the host of the data receiving end. The completion queue is created by the application running on the data receiving end and the corresponding driver. Generally, the application and the corresponding driver will create the completion queue in advance before data transmission. The first completion queue element is used to identify that the IO task of writing partial data to the target available memory space has been completed.

[0050] The data transmission method provided in this application embodiment, after writing some data to the network card buffer of the network card, further executes step S202, in which some data is written from the network card buffer to the host memory.

[0051] Writing partial data from the network interface card (NIC) buffer to host memory can mean reading some data from the NIC buffer and writing some of that data to the host memory. Specifically, when the NIC has sufficient flow control credits to support the transmission of some data, it can read some data from the NIC buffer and write some of that data to the host memory.

[0052] In one possible implementation, in order to accurately write a portion of the data from the network interface card (NIC) buffer to the host memory, when writing the data from the NIC buffer to the host memory, the physical address corresponding to the data in the NIC buffer and the physical address to be written in the host memory can be obtained first. Then, the data is read from the memory corresponding to the physical address and written to the memory corresponding to the physical address to be written.

[0053] Obtaining the physical address of a portion of the data stored in the network interface card (NIC) buffer can refer to reading the target send queue element (Send Queue Entry, SQE) for that portion of the data from a pre-created send queue (SQ) and retrieving its physical address. The target send queue element is generated based on the data transmission request provided by the data receiving host (specifically, an application running on the host) for that portion of the data. The send queue is created by the application running on the data receiving end and its corresponding driver; typically, the application and driver will pre-create the send queue before data transmission.

[0054] Obtaining the physical address to be written to a portion of the data in the host memory can refer to reading the target receive queue element (RQE) for that portion of the data from the network interface card's receive queue (RQ) to obtain the physical address to be written. The target receive queue element is generated based on the data receiving host's (specifically, the application running on the host) data receiving request for that portion of the data. The receive queue is created by the application running on the data receiving end and its corresponding driver. Generally, the application and its driver will create the receive queue beforehand before data transmission.

[0055] In one example, the process of writing partial data from the network card buffer to the host memory is as follows: Figure 4As shown, the process is as follows: After the network interface card (NIC) writes some data into its NIC buffer, when the NIC reads the target transmit queue element indicating that some data should be sent from the NIC buffer to the host memory, the NIC obtains the physical address of the corresponding data in the NIC buffer. When the NIC reads the target receive queue element indicating that some data should be received from the NIC buffer to the host memory, the NIC obtains the physical address of the corresponding data to be written in the host memory. After obtaining the physical address and the physical address to be written, the NIC further reads some data from the memory corresponding to the physical address and writes some data to the memory corresponding to the physical address to be written. Specifically, the target transmit queue element is written to the transmit queue by the host at the data receiving end (specifically, an application running on the host), and the target receive queue element is written to the receive queue by the host at the data receiving end (specifically, an application running on the host). In addition, to ensure the receiving host can promptly understand the data storage status of partial data (at least including whether the data is stored in the host memory and its location within that memory), after reading partial data from the memory corresponding to the storage physical address and writing it to the memory corresponding to the write physical address, the network interface card (NIC) can further write a second completion queue element to the completion queue and send this element to the receiving host. The second completion queue element identifies the completion of the I / O task of writing partial data from the NIC buffer to the host memory. Specifically, it identifies the completion of both the I / O tasks of reading partial data from the storage physical address and writing it to the write physical address. To better identify the completed I / O tasks, the receiving host can also receive an I / O task identifier corresponding to the task of writing partial data from the NIC buffer to the host memory simultaneously with the second completion queue element.

[0056] In one example, to ensure that the remaining buffer queue elements accurately identify the remaining available memory space in the network interface card (NIC) buffer, and to accurately determine the labeling probability based on the number of elements corresponding to the remaining buffer queue elements, after reading some data from the storage physical address and writing some data to the write physical address, it is necessary to further configure a target buffer queue element in the NIC's buffer queue for the storage physical address, and add the target buffer queue element to the buffer queue to update the remaining buffer queue elements. The buffer queue stores multiple buffer queue elements configured according to the available memory space corresponding to the NIC buffer; the buffer queue element identifies a segment of available memory space in the NIC buffer. In other words, after writing some data from the NIC buffer to host memory, the target buffer queue element needs to be replenished in the buffer queue in a timely manner.

[0057] In one possible implementation, to accurately and promptly control the data transmission rate reduction at the data sender to avoid packet loss, after writing a portion of the target data into the network card's buffer, the explicit congestion notification labeling probability can be determined for the data already written to the host memory. Then, based on the labeling probability, explicit congestion notification labels are applied to the data receipt packets corresponding to the written data, resulting in data receipt packets to be sent. These packets are then sent to the data sender. The labeling probability indicates the degree of rate reduction at the data receiver; generally, a higher labeling probability results in a greater rate reduction. Specifically, a higher labeling probability means more data receipt packets with explicit congestion notification labels will be received by the data receiver. The more data reception messages marked with explicit congestion notifications the data receiver receives, the less available memory space remains in the network card buffer. In this case, the data sender should reduce the data transmission rate to a greater extent.

[0058] For data already written to the host memory, the receiving end needs to send a data receipt message via the network card to the sending end to inform the receiving end that the written data has been successfully received. In one example, the data receipt message is sent in the form of an ACK (Acknowledgement) message. Additionally, the labeling probability of Explicit Congestion Notification (ECN) represents the probability of explicitly labeling the data receipt messages corresponding to the written data with congestion notification.

[0059] In one possible implementation, when determining the labeling probability of explicit congestion notification for the written data that has been written to the host memory in the target data, the remaining buffer queue elements existing in the network card's buffer queue can be obtained first, and then the labeling probability can be determined based on the number of elements corresponding to the remaining buffer queue elements.

[0060] Buffer queue elements are used to identify a segment of available memory space in the network interface card (NIC) buffer. Remaining buffer queue elements accurately identify the remaining available memory space in the NIC buffer. When the bus bandwidth required for the NIC to write target data to host memory exceeds the NIC's available bus bandwidth, the bus is already at full load. In this case, fewer remaining buffer queue elements indicate less remaining available memory space in the NIC buffer. To avoid data loss, the less available memory space in the NIC buffer, the greater the reduction in data transmission rate required by the data sender. Therefore, determining the labeling probability based on the number of elements corresponding to the remaining buffer queue elements allows the labeling probability to accurately reflect the degree of reduction in data transmission rate required by the data sender. Specifically, when the bus bandwidth required for the NIC to write target data to host memory exceeds the NIC's available bus bandwidth, the less available memory space in the NIC buffer, the higher the labeling probability, and the greater the reduction in data transmission rate required by the data sender.

[0061] In one example, when determining the labeling probability based on the number of elements corresponding to the remaining buffer queue elements, one can first determine the numerical range corresponding to the number of elements within multiple numerical ranges configured for multiple buffer queue elements. Then, within the labeling probability calculation models corresponding to each of the multiple numerical ranges, a labeling probability calculation model corresponding to the number of elements is determined based on the numerical range corresponding to the number of elements. Finally, the labeling probability is calculated using the number of elements and the labeling probability calculation model. For example, three numerical ranges are configured for multiple buffer queue elements (the number of multiple buffer queue elements is N, where N is a positive integer), denoted as numerical range 1, numerical range 2, and numerical range 3, respectively. Numerical range 1 is greater than P (P is a positive integer less than N) and less than or equal to N; numerical range 2 is less than or equal to P and greater than or equal to Q (Q is a positive integer less than P); and numerical range 3 is greater than or equal to 0 and less than Q. Furthermore, the annotation probability calculation models configured for multiple numerical ranges are as follows: numerical range 1 corresponds to annotation probability calculation model 1, numerical range 2 corresponds to annotation probability calculation model 2, and numerical range 3 corresponds to annotation probability calculation model 3. The calculation formula for annotation probability calculation model 1 can be Y = 0, (P < M ≤ N); the calculation formula for annotation probability calculation model 2 can be Y = (PM) / (PQ), (Q ≤ M ≤ P); and the calculation formula for annotation probability calculation model 3 can be Y = 1, (0 ≤ M < Q). Here, M represents the number of elements corresponding to the remaining buffer queue elements, and Y represents the annotation probability.

[0062] The data transmission method provided in this application embodiment has a higher memory capacity than the first memory buffer configured based on the on-chip memory of the network card (NIC). This means the NIC buffer can store more data than the first memory buffer configured based on the on-chip memory. Since the NIC buffer can store more data, when the bus bandwidth required to write target data to host memory exceeds the available bus bandwidth, writing a portion of the target data to the NIC buffer first, and then writing the remaining data from the NIC buffer to host memory, better avoids data packet loss when the required bus bandwidth exceeds the available bus bandwidth. In other words, when the required bus bandwidth resources exceed the available bus bandwidth resources due to sudden traffic surges, it can better avoid data packet loss, thereby reducing the impact of data packet loss on communication latency and data transmission rate.

[0063] In addition, since the onboard memory of the network card is configured inside the network card and its cost is relatively low, configuring the onboard memory of the network card as the second memory buffer of the network card can reduce the configuration cost and configuration complexity of the network card buffer.

[0064] Corresponding to the application examples and methods provided in the embodiments of this application, the embodiments of this application also provide a network interface card (NIC) applied to a data receiving end, such as... Figure 5 As shown. Figure 5 This illustration shows a structural block diagram of a network interface card (NIC) 500 applied to a data receiving end according to an embodiment of this application. The NIC 500 writes data to the host memory of the data receiving end via a bus and may include:

[0065] The first data writing module 501 is used to write a portion of the target data to the network card buffer if, during the process of receiving target data sent by the data sender at the data receiver, the bus bandwidth resources required by the network card to write the target data to the host memory exceed the bus bandwidth resources available to the network card. The network card buffer includes a first memory buffer configured for the network card based on its on-chip memory and a second memory buffer configured for the network card based on its onboard memory. The data sender sends the target data to the data receiver via remote direct memory access.

[0066] The second data writing module 502 is used to write a portion of the data from the network card buffer to the host memory.

[0067] In one possible implementation, the bus bandwidth resources required for the network interface card (NIC) to write target data to host memory exceed the bus bandwidth resources available to the NIC, including: the flow control credits required for the NIC to write target data to host memory exceed the flow control credits available to the NIC.

[0068] In one possible implementation, the first data writing module 501 includes:

[0069] The target buffer queue element reading submodule is used to read the target buffer queue element from the remaining buffer queue elements when there are remaining buffer queue elements in the pre-configured buffer queue. The buffer queue is used to store multiple buffer queue elements configured according to the available memory space corresponding to the network card buffer. The buffer queue element is used to identify a segment of available memory space in the network card buffer.

[0070] The first data writing submodule is used to write a portion of the data to the target available memory space identified by the target buffer queue element.

[0071] In one possible implementation, the network interface card (NIC) used at the data receiving end also includes:

[0072] The target buffer queue element deletion module is used to delete the target buffer queue element from the remaining buffer queue elements after writing part of the data to the target available memory space identified by the target buffer queue element.

[0073] And / or, the first completion queue element writing module is used to write a first completion queue element into a pre-configured completion queue; the first completion queue element is used to identify that the IO task of writing part of the data to the target available memory space has been completed;

[0074] The first completion queue element sending module is used to send the first completion queue element to the host of the data receiving end.

[0075] In one possible implementation, the second data writing module 502 includes:

[0076] The physical address acquisition submodule is used to acquire the physical address of some data stored in the network card buffer, and the physical address of some data to be written in the host memory.

[0077] The second data writing submodule is used to read part of the data from the memory corresponding to the physical address and write part of the data to the memory corresponding to the physical address to be written.

[0078] In one possible implementation, the physical address acquisition submodule includes:

[0079] The physical address acquisition submodule is used to read the target sending queue element for a portion of the data from the pre-configured sending queue and obtain the physical address for storage. The target sending queue element is generated based on the data sending request provided by the host of the data receiving end for a portion of the data.

[0080] In one possible implementation, the network interface card (NIC) used at the data receiving end also includes:

[0081] The second completion queue element writing module is used to write a second completion queue element into the network card's completion queue after reading part of the data from the memory corresponding to the storage physical address and writing part of the data to the memory corresponding to the physical address to be written; the second completion queue element is used to indicate that the IO task of writing part of the data from the network card buffer to the host memory has been completed.

[0082] The second completion queue element sending module is used to send the second completion queue element to the host of the data receiving end.

[0083] In one possible implementation, the network interface card (NIC) used at the data receiving end also includes:

[0084] The target buffer queue element configuration module is used to configure a target buffer queue element in a pre-configured buffer queue for the storage physical address after reading part of the data from the memory corresponding to the storage physical address and writing part of the data to the memory corresponding to the physical address to be written. The buffer queue is used to store multiple buffer queue elements configured according to the available memory space corresponding to the network card buffer. The buffer queue element is used to identify a segment of available memory space in the network card buffer.

[0085] The target buffer queue element writing module is used to add target buffer queue elements to the buffer queue.

[0086] In one possible implementation, the network interface card (NIC) used at the data receiving end also includes:

[0087] The labeling probability determination module is used to determine the labeling probability of explicit congestion notification for the data already written to host memory after writing a portion of the target data to the network card buffer. The labeling probability is used to identify the degree of reduction in the data transmission rate at the data receiving end.

[0088] The annotation module is used to explicitly annotate the data receipt messages corresponding to the written data based on the annotation probability, so as to obtain the data receipt messages to be sent.

[0089] The message sending module is used to send the data receipt message to the data sending end.

[0090] In one possible implementation, the annotation probability determination module includes:

[0091] The Remaining Buffer Queue Element Acquisition Submodule is used to retrieve the remaining buffer queue elements existing in the network interface card's buffer queue. The buffer queue is used to store multiple buffer queue elements configured according to the available memory space corresponding to the network interface card's buffer. The buffer queue element is used to identify a segment of available memory space in the network interface card's buffer.

[0092] The labeling probability determination submodule is used to determine the labeling probability based on the number of elements corresponding to the elements in the remaining buffer queue.

[0093] In one possible implementation, the annotation probability determination submodule includes:

[0094] The numerical range determination submodule is used to determine the numerical range corresponding to the number of elements among multiple numerical ranges configured for multiple buffer queue elements.

[0095] The annotation probability calculation model determination submodule is used to determine the corresponding annotation probability calculation model based on the numerical range corresponding to the number of elements among the annotation probability calculation models corresponding to multiple numerical ranges.

[0096] The annotation probability calculation submodule is used to calculate the annotation probability using the number of elements and the annotation probability calculation model.

[0097] The functions of each module in each device in the embodiments of this application can be found in the corresponding description in the above method, and they have corresponding beneficial effects, which will not be repeated here.

[0098] Figure 6 This is a block diagram of an electronic device used to implement embodiments of this application. For example... Figure 6 As shown, the electronic device includes a memory 601 and a processor 602. The memory 601 stores a computer program that can run on the processor 602. When the processor 602 executes the computer program, it implements the methods described in the above embodiments. The number of memories 601 and processors 602 can be one or more.

[0099] The electronic device also includes:

[0100] The communication interface 603 is used to communicate with external devices and perform data exchange and transmission.

[0101] If the memory 601, processor 602, and communication interface 603 are implemented independently, they can be interconnected via a bus to communicate with each other. This bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. This bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 6 The bus is represented by a single thick line, but this does not mean that there is only one bus or one type of bus.

[0102] Optionally, in a specific implementation, if the memory 601, processor 602, and communication interface 603 are integrated on a single chip, then the memory 601, processor 602, and communication interface 603 can communicate with each other through an internal interface.

[0103] This application provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the method provided in this application.

[0104] This application also provides a chip, which includes a processor for calling and executing instructions stored in a memory, causing a communication device on which the chip is installed to perform the method provided in this application.

[0105] This application also provides a chip, including: an input interface, an output interface, a processor, and a memory. The input interface, output interface, processor, and memory are connected through an internal connection path. The processor is used to execute code in the memory. When the code is executed, the processor is used to execute the method provided in the application embodiment.

[0106] It should be understood that the aforementioned processor can be a Central Processing Unit (CPU), or other general-purpose processors, Digital Signal Processors (DSPs), Application Specific Integrated Circuits (ASICs), Field-Programmable Gate Arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. General-purpose processors can be microprocessors or any conventional processor. It is worth noting that the processor can be a processor supporting Advanced Reduced Instruction Set Machines (ARM) architecture.

[0107] Further, optionally, the aforementioned memory may include read-only memory and random access memory, and may also include non-volatile random access memory. The memory may be volatile or non-volatile, or may include both. Non-volatile memory may include read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. Volatile memory may include random access memory (RAM), which serves as an external cache. Many forms of RAM are available by way of example, but not limitation. Examples include Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), Synchronous DRAM (SDRAM), Double Data Rate SDRAM (DDR SDRAM), Enhanced Synchronous DRAM (ESDRAM), Synchlink DRAM (SLDRAM), and Direct Rambus RAM (DR RAM).

[0108] In the above embodiments, implementation can be achieved, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented in software, it can be implemented, in whole or in part, as a computer program product. A computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the flow or function according to this application is generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transferred from one computer-readable storage medium to another.

[0109] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of those different embodiments or examples.

[0110] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified.

[0111] Any process or method description in the flowchart or otherwise herein can be understood as representing a module, segment, or portion of code comprising one or more executable instructions for implementing a particular logical function or process. Furthermore, the scope of the preferred embodiments of this application includes additional implementations in which functions may be performed not in the order shown or discussed, including substantially simultaneously or in reverse order depending on the functionality involved.

[0112] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus or device (such as a computer-based system, a processor-included system or other system that can fetch and execute instructions from, an instruction execution system, apparatus or device).

Claims

1. A data transmission method applied to a network interface card (NIC) at a data receiving end, wherein the NIC writes data to the host memory of the data receiving end via a bus, the method comprising: During the process of the data receiving end receiving target data sent by the data sending end, if the bus bandwidth resources required by the network card to write the target data into the host memory exceed the bus bandwidth resources available to the network card, then a portion of the target data to be written into the host memory is written into the network card buffer of the network card; the network card buffer is used as a buffer pool for burst traffic, including a first memory buffer configured for the network card based on the on-chip memory of the network card and a second memory buffer configured for the network card based on the onboard memory of the network card; the data sending end sends the target data to the data receiving end via remote direct memory access; The data is written from the network card buffer to the host memory.

2. The method according to claim 1, wherein, The fact that the bus bandwidth resources required for the network card to write the target data to the host memory exceed the bus bandwidth resources available to the network card includes: the traffic control credit required for the network card to write the target data to the host memory exceeds the traffic control credit limit available to the network card.

3. The method according to claim 1, wherein, The step of writing a portion of the target data into the network interface card (NIC) buffer includes: When there are remaining buffer queue elements in the pre-configured buffer queue, the target buffer queue element in the remaining buffer queue elements is read; the buffer queue is used to store multiple buffer queue elements configured according to the available memory space corresponding to the network card buffer; the buffer queue element is used to identify a segment of available memory space in the network card buffer; The data is written to the target available memory space identified by the target buffer queue element.

4. The method according to claim 3, wherein, After writing the partial data to the target available memory space identified by the target buffer queue element, the method further includes: Delete the target buffer queue element from the remaining buffer queue elements; After writing the partial data to the target available memory space identified by the target buffer queue element, the method further includes: Write a first completion queue element into a pre-configured completion queue; the first completion queue element is used to identify that the IO task of writing the partial data to the target available memory space has been completed. The first completed queue element is sent to the host of the data receiving end.

5. The method according to claim 1, wherein, The step of writing the partial data from the network interface card buffer to the host memory includes: Obtain the physical address of the data in the network interface card buffer and the physical address of the data to be written in the host memory; Read the partial data from the memory corresponding to the physical address and write the partial data to the memory corresponding to the physical address to be written.

6. The method according to claim 5, wherein, The step of obtaining the physical address of the corresponding storage in the network interface card buffer for the partial data includes: The target sending queue element for the portion of data is read from the pre-configured sending queue to obtain the storage physical address; the target sending queue element is generated based on the data sending request provided by the host of the data receiving end for the portion of data.

7. The method according to claim 5, wherein, After reading the partial data from the memory corresponding to the storage physical address and writing the partial data to the memory corresponding to the physical address to be written, the method further includes: Write a second completion queue element into a pre-configured completion queue; the second completion queue element is used to identify that the IO task of writing the partial data from the network card buffer to the host memory has been completed; The second completed queue element is sent to the host of the data receiving end.

8. The method according to claim 5, wherein, After reading the partial data from the memory corresponding to the storage physical address and writing the partial data to the memory corresponding to the physical address to be written, the method further includes: For the stored physical address, a target buffer queue element is configured in a pre-configured buffer queue; the buffer queue is used to store multiple buffer queue elements configured according to the available memory space corresponding to the network card buffer; the buffer queue element is used to identify a segment of available memory space in the network card buffer; Add the target buffer queue element to the buffer queue.

9. The method according to claim 1, wherein, After writing a portion of the target data into the network interface card (NIC) buffer, the method further includes: For the written data already written to the host memory in the target data, determine the labeling probability of explicit congestion notification; the labeling probability is used to identify the degree of reduction in the data transmission rate by the data receiving end; Based on the labeled probability, explicit congestion notification labels are applied to the data receipt messages corresponding to the written data to obtain the data receipt messages to be sent. The data receipt confirmation message to be sent is sent to the data sending end.

10. The method according to claim 9, wherein, The determination of the labeling probability of explicit congestion notification for the written data already written to the host memory in the target data includes: Retrieve the remaining buffer queue elements existing in the pre-configured buffer queue; the buffer queue is used to store multiple buffer queue elements configured according to the available memory space corresponding to the network card buffer; the buffer queue element is used to identify a segment of available memory space in the network card buffer; The labeling probability is determined based on the number of elements corresponding to the remaining buffer queue elements.

11. The method according to claim 10, wherein, Determining the labeling probability based on the number of elements corresponding to the remaining buffer queue elements includes: Among the multiple numerical ranges configured for the multiple buffer queue elements, determine the numerical range corresponding to the number of elements; In the annotation probability calculation models corresponding to the multiple numerical ranges, the corresponding annotation probability calculation model is determined based on the numerical range corresponding to the number of elements. The labeling probability is calculated using the number of elements and the labeling probability calculation model.

12. A network interface card (NIC) for a data receiver, the NIC writing data to the host memory of the data receiver via a bus, the NIC comprising: The first data writing module is configured to, during the process of the data receiving end receiving target data sent by the data sending end, if the bus bandwidth resources required by the network card to write the target data to the host memory exceed the bus bandwidth resources available to the network card, write a portion of the target data to be written to the host memory into the network card buffer of the network card; the network card buffer is used as a buffer pool for burst traffic, including a first memory buffer configured for the network card based on the on-chip memory of the network card and a second memory buffer configured for the network card based on the onboard memory of the network card; the data sending end sends the target data to the data receiving end via remote direct memory access; The second data writing module is used to write the partial data from the network card buffer to the host memory.

13. An electronic device comprising a memory, a processor, and a computer program stored in the memory, wherein the processor, when executing the computer program, implements the method of any one of claims 1-11.

14. A computer-readable storage medium storing a computer program that, when executed by a processor, implements the method of any one of claims 1-11.

Images