Stacked interposer semiconductor package structure

Abstract

This application relates to a stacked interlocking semiconductor packaging structure, comprising: a substrate, a base plate, two chips, a packaging layer, and a protective shell; the substrate is disposed on the top surface of the base plate, and two chips are disposed on the substrate, with the packaging layer encapsulating the chips and the substrate; the protective shell is disposed on the top surface of the base plate and surrounds the sidewalls of the packaging layer; the protective shell includes: two or more stacked rings, each ring having a limiting groove on its inner sidewall, and the packaging layer having multiple limiting protrusions on its sidewalls, the limiting protrusions matching the limiting grooves for embedding within the limiting grooves. The protective shell surrounding the packaging layer effectively isolates and protects the packaging layer, preventing damage caused by direct exposure of the packaging layer's sidewalls to the outside. This application utilizes a stacked, interlocking ring structure to reliably complete the packaging process of microelectronic components or semiconductor devices; the overall structure is simple and easy to manufacture; it has significant advantages in terms of process speed and cost.

Description

Technical Field

[0001] This application relates to the field of chip packaging technology, and in particular to a stacked interlocking semiconductor packaging structure. Background Technology

[0002] Packaging refers to the process of using a series of technologies to lay out, attach, fix and connect chips on a frame, bring out terminals and fix them through a plastic insulating medium to form an overall three-dimensional structure. It has the functions of placing, fixing, sealing and protecting chips.

[0003] At present, epoxy resin is often used to encapsulate chips, as can be seen in the semiconductor package with publication number CN205319149U. After encapsulation, the encapsulation layer is directly exposed to the external environment. If no protective measures are taken for the encapsulation layer, it is easy to be damaged or cracked over time. Summary of the Invention

[0004] In view of this, this application proposes a stacked inter-embedded semiconductor packaging structure.

[0005] According to one aspect of this application, a stacked interlocking semiconductor packaging structure is provided, characterized in that it includes: a substrate, a base plate, two chips, a packaging layer, and a protective shell;

[0006] The substrate is set on the top surface of the base plate, and two chips are set on the substrate. The encapsulation layer wraps the chips and the substrate. The protective shell is set on the top surface of the base plate and surrounds the sidewalls of the encapsulation layer.

[0007] The protective shell includes two or more stacked ring pieces, and each ring piece has a limiting groove on its inner sidewall. The sidewall of the encapsulation layer is provided with multiple limiting protrusions, which are matched with the limiting grooves to be embedded in the limiting grooves.

[0008] In one possible implementation, a connecting groove is provided on the top surface of the base plate, and a connecting protrusion for embedding into the connecting groove is provided on the side of the encapsulation layer that connects to the base plate.

[0009] In one possible implementation, the main body of the connecting groove is annular, and the connecting groove surrounds the outside of the substrate.

[0010] In one possible implementation, the protective casing has two or more through holes for external leads to pass through.

[0011] In one possible implementation, the encapsulation layer is made of epoxy resin.

[0012] In one possible implementation, the ring is made of ceramic.

[0013] In one possible implementation, the base plate is made of metal.

[0014] Beneficial effects: The base plate is suitable for supporting the substrate and the chip on it. The substrate is suitable for mounting the chip, providing physical support and electrical connection for the chip. The encapsulation layer wraps around the outside of the chip and the substrate and provides all-round protection for the wires between the two chips. It is suitable for isolating the chip from the outside world to prevent impurities in the air from corroding the chip and circuit and causing a decline in electrical performance. The protective shell surrounding the encapsulation layer effectively isolates and protects it, preventing damage caused by direct exposure of the encapsulation layer's sidewalls to the outside. Since each ring of the protective shell has a limiting groove, the limiting protrusions of the encapsulation layer embedding into the limiting grooves of the rings improve the connection between each ring and the encapsulation layer, preventing the rings from detaching and causing protection failure. Furthermore, the combined limiting effect of multiple rings on the encapsulation layer ensures that the encapsulation layer can be gripped and fixed at various heights, improving its shape stability and preventing internal cracking due to thermal expansion and contraction. This application also utilizes a stacked, interlocking ring structure to reliably complete the packaging of microelectronic components or semiconductor devices; the overall structure is simple and easy to manufacture; and it offers significant advantages in terms of process speed and cost.

[0015] Other features and aspects of this application will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0016] The accompanying drawings, which are included in and form part of this specification, illustrate exemplary embodiments, features, and aspects of this application together with the specification and serve to explain the principles of this application.

[0017] Figure 1 A cross-sectional view of a stacked interlocking semiconductor package structure according to an embodiment of this application is shown;

[0018] Figure 2 This is a front view of a stacked interlocking semiconductor package structure according to an embodiment of this application;

[0019] Figure 3 A side view of a stacked interlocking semiconductor package structure according to an embodiment of this application is shown;

[0020] Figure 4 A top view of a stacked interlocking semiconductor package structure according to an embodiment of this application is shown;

[0021] Figure 5 This diagram illustrates the main structural structure of the annular piece according to an embodiment of this application.

[0022] Figure 6 This diagram shows the main structure of the sealing layer according to an embodiment of this application.

[0023] Substrate 200, base plate 100, chip 300, encapsulation layer 400, ring 500, limiting protrusion 410, connecting protrusion 420, sealing layer 600. Detailed Implementation

[0024] Various exemplary embodiments, features, and aspects of the present invention will now be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings denote elements that have the same or similar functions. Although various aspects of the embodiments are shown in the drawings, they are not necessarily drawn to scale unless specifically indicated otherwise.

[0025] It should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this utility model or simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this utility model.

[0026] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this utility model, "a plurality of" means two or more, unless otherwise explicitly specified.

[0027] The term “exemplary” as used herein means “serving as an example, embodiment, or illustration.” Any embodiment illustrated herein as “exemplary” is not necessarily to be construed as superior to or better than other embodiments.

[0028] Furthermore, to better illustrate this utility model, numerous specific details are provided in the following detailed embodiments. Those skilled in the art should understand that this utility model can be implemented even without certain specific details. In some instances, methods, means, components, and circuits well-known to those skilled in the art have not been described in detail, in order to highlight the main points of this utility model.

[0029] Figure 1 A cross-sectional view of a stacked interlocking semiconductor package structure according to an embodiment of this application is shown; Figure 2 This is a front view of a stacked interlocking semiconductor package structure according to an embodiment of this application; Figure 3 A side view of a stacked interlocking semiconductor package structure according to an embodiment of this application is shown; Figure 4This is a top view showing a stacked interlocking semiconductor package structure according to an embodiment of this application. Figure 1 As shown, this stacked interlocking semiconductor packaging structure includes: a substrate 200, a base plate 100, two chips 300, a packaging layer 400, and a protective shell; the substrate 200 is disposed on the top surface of the base plate 100, the two chips 300 are arranged adjacently on the top surface of the substrate 200, and the packaging layer 400 encapsulates the chips 300 and the substrate 200; the protective shell is disposed above the base plate 100 and surrounds the sidewalls of the packaging layer 400; the protective shell includes: two or more stacked ring plates 500, and each ring plate 500 has a limiting groove 510 formed on its inner sidewall, and the packaging layer 400 has a limiting protrusion 410 on its sidewall, the limiting protrusion 410 matching the limiting groove 510 to be embedded in the limiting groove 510.

[0030] It should be noted that the base plate 100 is used to support the substrate 200 and the chip 300 on it. The substrate 200 is used to mount the chip 300, providing physical support and electrical connection for the chip 300. The encapsulation layer 400 wraps around the chip 300 and the substrate 200 and provides all-round protection for the wires 310 between the two chips 300 and the wires 330 between the chip 300 and the external lead 320. It is used to isolate the chip 300 from the outside world to prevent impurities in the air from corroding the chip 300 and the circuit and causing a decline in electrical performance. The encapsulated chip 300 is also easier to transport. The protective shell surrounding the encapsulation layer 400 effectively isolates and protects the encapsulation layer 400, preventing damage caused by direct exposure of the sidewalls of the encapsulation layer 400 to the outside. The protective shell is composed of multiple stacked rings 500, so the height of the encapsulation cavity can be changed by altering the number of stacked rings 500 to meet the different thickness requirements of different chips 300 for the encapsulation layer 400. Since each ring 500 has a limiting groove 510, the limiting protrusion 410 of the encapsulation layer 400, embedded in the limiting groove 510 of the ring, improves the connection strength between each ring 500 and the encapsulation layer 400, preventing damage. The protection is not compromised by the ring 500 detaching from the encapsulation layer 400. Furthermore, the combined restraining effect of multiple rings 500 on the encapsulation layer 400 ensures that the encapsulation layer 400 can be firmly held and fixed at various heights, improving its shape stability and preventing internal cracking due to thermal expansion and contraction. This application employs multiple encapsulation structures and utilizes the stacked and interlocking structure of the rings 500 to reliably complete the encapsulation process of microelectronic components or semiconductor devices. The overall structure is simple and easy to manufacture, offering significant advantages in terms of process speed and cost.

[0031] In one possible implementation, a connecting groove is formed on the top surface of the base plate 100, and a connecting protrusion 420 for embedding into the connecting groove is provided on the side of the encapsulation layer 400 that connects to the base plate 100. It should be noted that the encapsulation layer 400 and the base plate 100 are connected to each other by an interlocking method, which can improve the connection stability between the base plate 100 and the encapsulation layer 400, ensuring that the encapsulation layer 400 is firmly set on the base plate 100, preventing gaps between them or the entire encapsulation layer 400 from detaching from the base plate 100; thus ensuring the stability of the electrical operation.

[0032] Furthermore, the main body of the connecting groove is annular, and the connecting groove surrounds the outer side of the substrate 200. The cross-section of the connecting groove is convex; correspondingly, the connecting protrusion 420 at the bottom of the encapsulation layer 400 is also annular, and its cross-section is convex; to ensure that the encapsulation layer 400 can firmly grip the base plate 100.

[0033] In one possible implementation, the main body of the base plate 100 is a rectangular plate-like structure to fit the shape of the substrate 200, which is disposed in the middle of the top surface of the base plate 100, and two chips 300 are arranged adjacent to each other on the substrate 200. Figure 5 As shown, the main body of the ring piece 500 is a rectangular ring structure, and the limiting groove 510 on the inner side of the ring piece 500 is formed in a circle along the circumference of the ring piece 500.

[0034] Preferably, the bottom surface of the substrate 200 and the top surface of the base plate 100 are fixed by means of bonding, brazing or sintering.

[0035] Preferably, the thickness of a single ring piece 500 is in the range of 0.8-1.2 mm.

[0036] In one possible implementation, the protective casing has two or more through holes 610 for the external leads 320 to pass through. It should be noted that in order to realize the electrical connection between the chip 300 and various external devices, external leads 320 are required to connect the chip 300 to the devices outside the protective casing. Therefore, the protective casing needs to have through holes 610 to make way for the external leads 320.

[0037] In one possible implementation, the protective shell further includes a sealing layer 600 disposed between two annular plates 500. Two or more through-holes for external leads 320 to pass through are formed in the sealing layer 600, and the external leads 320 are adapted to pass through the through-holes 610 of the sealing layer 600 and extend outwards. It should be noted that the sealing layer 600 is fixed to the upper and lower annular plates 500 by sintering.

[0038] In one possible implementation, there are four ring plates 500, which are stacked sequentially along a direction perpendicular to the base plate 100. It should be noted that the number of ring plates 500 can be determined according to the thickness of the encapsulation layer 400.

[0039] Furthermore, such as Figure 6 As shown, the sealing layer 600 is located between the two annular pieces 500 in the middle, and a total of 12 wire passage holes 610 are provided. Six wire passage holes 610 are provided on each of the opposite sides of the sealing layer 600.

[0040] In one possible implementation, the encapsulation layer 400 is made of epoxy resin. Epoxy resin has the characteristics of low shrinkage, high heat resistance, and excellent sealing and electrical insulation properties. Therefore, using epoxy resin as the encapsulation layer 400 can effectively ensure the reliability of the encapsulation.

[0041] In one possible implementation, the ring 500 is made of ceramic; ceramic has stable performance at high temperatures and is suitable for high-frequency and high-temperature scenarios; it also has good moisture resistance and corrosion resistance.

[0042] In one possible implementation, the sealing layer 600 is made of glass.

[0043] In one possible implementation, the base plate 100 is made of metal; furthermore, the base plate 100 can be made of metal materials such as copper or aluminum, which have advantages such as high thermal conductivity, and can quickly transfer the temperature of the chip 300 to the outside, thereby improving the heat dissipation efficiency of the chip 300.

[0044] The construction process of this application is described as follows: First, two chips 300 are mounted on the substrate 200, and the wires 310 between the two chips 300 are connected to ensure that the circuit connection is complete. Then, the substrate 200 is placed on the base plate 100 and its position is adjusted. The number of rings 500 is determined according to the required encapsulation thickness, and multiple rings 500 and sealing layers 600 are stacked sequentially on the base plate 100 to form a protective shell. Then, one end of each external lead 320 is connected to the chip 300 through the wire 330, and the other end passes through the wire hole 610 of the sealing layer 600 to the outside. Finally, epoxy resin is injected into the protective shell to fill the protective shell and allow it to cure and form a solid shape.

[0045] The various embodiments of the present invention have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or improvement of the technology in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A stacked interlocking semiconductor packaging structure, characterized in that, include: Substrate, base plate, two chips, encapsulation layer and protective shell; The substrate is disposed on the top surface of the base plate, and two chips are disposed on the substrate. The encapsulation layer encapsulates the chips and the substrate. The protective shell is disposed on the top surface of the base plate and surrounds the sidewalls of the encapsulation layer; The protective shell includes two or more stacked ring pieces, and each ring piece has a limiting groove on its inner sidewall. The sidewall of the encapsulation layer is provided with multiple limiting protrusions, which are matched with the limiting grooves and are suitable for embedding into the limiting grooves.

2. The stacked interlocking semiconductor packaging structure according to claim 1, characterized in that, The top surface of the base plate is provided with a connecting groove, and the side of the encapsulation layer that connects to the base plate is provided with a connecting protrusion for embedding into the connecting groove.

3. The stacked interlocking semiconductor packaging structure according to claim 2, characterized in that, The main body of the connecting groove is annular, and the connecting groove surrounds the outside of the substrate.

4. The stacked interlocking semiconductor packaging structure according to claim 1, characterized in that, The protective shell has two or more through holes for external leads to pass through.

5. The stacked interlocking semiconductor packaging structure according to claim 4, characterized in that, The protective shell further includes a sealing layer disposed between the two of the ring pieces, and the wire hole is formed on the sealing layer.

6. The stacked interlocking semiconductor packaging structure according to claim 5, characterized in that, There are four ring pieces in total, and the four ring pieces are stacked in sequence along a direction perpendicular to the base plate. The sealing layer is located between the two middle ring pieces.

7. The stacked interlocking semiconductor packaging structure according to claim 1, characterized in that, The encapsulation layer is made of epoxy resin.

8. The stacked interlocking semiconductor packaging structure according to claim 1, characterized in that, The ring plate is made of ceramic.

9. The stacked interlocking semiconductor packaging structure according to claim 1, characterized in that, The base plate is made of copper.

10. The stacked interlocking semiconductor packaging structure according to claim 5, characterized in that, The sealing layer is made of glass.

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