Display panel and display device

Abstract

The present disclosure relates to the technical field of display, and discloses a display panel and a display device. The display panel comprises a display area and a fan-out area. The display area comprises a plurality of gate lines extending along a first direction and arranged along a second direction. The fan-out area is located on at least one side of the plurality of gate lines in the first direction. The fan-out area comprises a gate drive circuit connected with the plurality of gate lines. Compared with the scheme of arranging the gate drive circuit on the left and right sides of the display panel, the scheme of arranging the gate drive circuit on the fan-out area on at least one side in the first direction can realize seamless splicing of the display panel. Especially when the resolution of the display panel is high, the gate drive circuit cannot be placed in the display area due to space limitations. The arrangement of the gate drive circuit in the fan-out area enables seamless splicing of the high-resolution display panel.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and provides a display panel and a display device. Background Technology

[0002] In related technologies, Mini / Micro LED display technology does not require edge packaging, and multiple display panels can be seamlessly spliced. However, the gate driving circuit is placed on the left and right sides of the display panel, which limits the splicing methods. Furthermore, when the pixel density (Pixels Per Inch, PPI) is high enough, the gate driving circuit cannot be placed in the display area of ​​the display panel due to space constraints, making it impossible to splice the display panels side by side. Utility Model Content

[0003] This disclosure provides a display panel and display device to solve the problem that display panels cannot be seamlessly spliced ​​under high PPI.

[0004] The specific technical solution provided in this disclosure is as follows:

[0005] In a first aspect, embodiments of this disclosure provide a display panel, including: a display area and a fan-out area;

[0006] The display area includes: multiple gate lines extending along a first direction and arranged along a second direction; a fan-out area located on at least one side of the multiple gate lines in the first direction;

[0007] The fan-out region includes a gate drive circuit, which is connected to multiple gate lines.

[0008] In some possible implementations, the fan-out area may further include: multiple scan fan-out lines;

[0009] The scanning fan-out line is electrically connected between the gate drive circuit and the gate line;

[0010] Multiple scanning fan-out lines extend along the second direction and are arranged along the first direction.

[0011] In some possible implementations, the display area further includes: multiple scan signal lines;

[0012] The scan signal line is electrically connected between the scan fan-out line and the grid line, with each scan signal line corresponding to a scan fan-out line.

[0013] In some possible implementations, multiple scan signal lines extend along a second direction and are arranged along a first direction.

[0014] In some possible implementations, the fan-out area may also include: multiple signal adapter cables;

[0015] The signal adapter cable is electrically connected between the scan fan-out line and the scan signal line, wherein the signal adapter cable, the scan signal line and the scan fan-out line are connected in a one-to-one correspondence.

[0016] In some possible implementations, each scan signal line includes a first scan signal sub-line and a second scan signal sub-line that are connected to each other;

[0017] The first scan signal sub-line is connected to the scan fan-out line, and the first scan signal sub-line extends along the second direction and is arranged along the first direction;

[0018] The second scan signal sub-line is connected to the gate line, and the second scan signal sub-line extends along the first direction and is arranged along the second direction.

[0019] In some possible implementations, the scan fan-out line includes a first scan fan-out sub-line and a second scan fan-out sub-line connected together;

[0020] The first scan fan-out sub-line is connected to the drive output terminal of the gate drive circuit. Each first scan fan-out sub-line is arranged along the first direction. The length of each first scan fan-out sub-line gradually increases from the drive output terminal to both ends of the fan-out area.

[0021] The second scan fan-out sub-line is connected to the scan signal line, and each second scan fan-out sub-line extends along the second direction and is arranged along the first direction.

[0022] In some possible implementations, the fan-out region further includes: a plurality of compensation resistors, each compensation resistor being electrically connected between the drive output terminal and the first scan fan-out sub-line;

[0023] The resistance value of each compensation resistor gradually decreases from the drive output terminal to the two ends of the fan-out region.

[0024] In some possible implementations, the gate drive circuit includes: a first gate drive circuit and a second gate drive circuit.

[0025] The first row scan signal generated by the first gate drive circuit is provided to the scan signal line located in the odd row of the display area via the scan fan-out line;

[0026] The second row scan signal generated by the second gate drive circuit is provided to the scan signal line located in the even-numbered rows of the display area via the scan fan-out line.

[0027] In some possible implementations, the gate drive circuit includes: a third gate drive circuit and a fourth gate drive circuit;

[0028] The third row scan signal generated by the third gate drive circuit is provided to some pixel units located in any row of the display area via the scan fan-out line.

[0029] The fourth row scan signal generated by the fourth gate drive circuit is provided to the pixel units located in the remaining part of any row of the display area via the scan fan-out line.

[0030] In some possible implementations, the display area may also include: multiple data lines;

[0031] Multiple data lines and multiple scan signal lines are arranged alternately along the first direction.

[0032] In some possible implementations, it also includes:

[0033] A first conductive layer is located on a substrate, and the first conductive layer includes multiple second scan fan-out sub-lines and multiple second scan signal sub-lines;

[0034] The first insulating layer is located on the side of the first conductive layer that is away from the substrate.

[0035] The second conductive layer is located on the side of the first insulating layer away from the substrate. The second conductive layer includes multiple first scan fan-out sub-lines and multiple signal conversion lines.

[0036] In some possible implementations, it also includes:

[0037] The second insulating layer is located on the side of the second conductive layer that is away from the substrate.

[0038] The third conductive layer is located on the side of the second insulating layer away from the substrate, and the third conductive layer includes multiple first scan signal sub-lines;

[0039] The third insulating layer is located on the side of the third conductive layer that is away from the substrate.

[0040] The fourth conductive layer, located on the side of the third insulating layer away from the substrate, includes multiple power lines.

[0041] In some possible implementations, the first scan signal sub-line includes: a first type of first scan signal sub-line and a second type of first scan signal sub-line;

[0042] The third conductive layer includes multiple first-type first scan signal sub-lines;

[0043] The second conductive layer includes multiple second-type first scan signal sub-lines.

[0044] In some possible implementations, the first end of the first scanning fan-out sub-line is connected to the first end of the second scanning fan-out sub-line through a first via penetrating the first insulating layer;

[0045] The second end of the second scanning fan-out sub-line is connected to the first end of the first scanning signal sub-line or the first end of the first type of first scanning signal sub-line through a second via penetrating the first and second insulating layers.

[0046] In some possible implementations, the second end of the first scan signal sub-line is connected to the first end of the second scan signal sub-line through a third via penetrating the first and second insulating layers.

[0047] In some possible implementations, the second end of the first type of first scan signal sub-line is connected to the first end of the second type of first scan signal sub-line through a fourth via penetrating the second insulating layer;

[0048] The second end of the second type of first scan signal sub-line passes through the fifth via of the first insulating layer and is connected to the first end of the second scan signal sub-line.

[0049] In some possible implementations, the second end of the second scan fan-out sub-line is connected to the first end of the signal adapter line through a sixth via penetrating the first insulating layer, and the second end of the signal adapter line is connected to the first end of the first scan signal sub-line through a seventh via penetrating the second insulating layer; or

[0050] The second end of the second scan fan-out sub-line is connected to the first end of the signal adapter line through the eighth via penetrating the first insulating layer, and the second end of the signal adapter line is connected to the first end of the first type of first scan signal sub-line through the ninth via penetrating the second insulating layer.

[0051] In some possible implementations, the thickness of the second insulating layer is between 2.5 micrometers and 4 micrometers, and the thickness of the third insulating layer is between 3 micrometers and 4 micrometers.

[0052] Secondly, embodiments of this disclosure also provide a display device, including the display panel of any of the above.

[0053] In some possible implementations, it includes: multiple display panels;

[0054] Multiple display panels are sequentially spliced ​​along a first direction; and / or

[0055] The two rows of display panels are symmetrically spliced ​​along the axis of symmetry in the second direction, wherein the axis of symmetry extends along the opposite side of the fan-out area away from the edge of the display area.

[0056] The beneficial effects of this disclosure are as follows:

[0057] In summary, this disclosure provides a display panel and a display device. The display panel includes a display area and a fan-out area. The display area includes multiple gate lines extending along a first direction and arranged along a second direction. The fan-out area is located on at least one side of the multiple gate lines in the first direction. The fan-out area includes a gate driving circuit connected to the multiple gate lines. Compared with the scheme of placing the gate driving circuit on the left and right sides of the display panel, the scheme of placing the gate driving circuit in the fan-out area located on at least one side in the first direction allows the display panel to achieve seamless splicing. Especially when the resolution of the display panel is high, the gate driving circuit cannot be placed in the display area due to space limitations. The method of placing the gate driving circuit in the fan-out area enables high-resolution display panels to achieve seamless splicing.

[0058] Other features and advantages of this disclosure will be set forth in the following description and will be apparent in part from the description or may be learned by practicing the disclosure. The objects and other advantages of this disclosure may be realized and obtained by means of the structures particularly pointed out in the written description, claims, and drawings. Attached Figure Description

[0059] The accompanying drawings, which are included to provide a further understanding of this disclosure and form part of this disclosure, illustrate exemplary embodiments of the present disclosure and are used to explain the disclosure, but do not constitute an undue limitation of the disclosure. In the drawings:

[0060] Figure 1 This is a schematic diagram of the connection of a display panel in related technologies;

[0061] Figure 2 This is a schematic diagram showing the connection of the first type of display panel in an embodiment of this disclosure;

[0062] Figure 3 This is a schematic diagram showing the connection of the second type of display panel in an embodiment of this disclosure;

[0063] Figure 4 This is a schematic diagram showing the connection of the third type of display panel in this embodiment of the present disclosure;

[0064] Figure 5 This is a connection diagram of the fourth type of display panel in this embodiment of the present disclosure;

[0065] Figure 6 This is a connection diagram of the fifth type of display panel in the embodiments of this disclosure;

[0066] Figure 7 This is a connection diagram of the sixth type of display panel in the embodiments of this disclosure;

[0067] Figure 8This is a schematic diagram showing the connection between the first scanning fan-out sub-line and the second scanning fan-out sub-line in the display panel of this embodiment.

[0068] Figure 9 This is a schematic diagram of the connection of the compensation resistor in an embodiment of this disclosure;

[0069] Figure 10 This is a schematic diagram of the connection of a scanning signal line in the first case of the embodiments of this disclosure;

[0070] Figure 11 This is a schematic diagram showing the connection of another scanning signal line in the first case of the embodiments of this disclosure;

[0071] Figure 12 This is a schematic diagram of the connection of a scanning signal line in the second case of the embodiments of this disclosure;

[0072] Figure 13 This is a schematic diagram showing the connection of another scanning signal line in the second case of an embodiment of this disclosure;

[0073] Figure 14 This is a schematic diagram of the signal adapter cable connection in an embodiment of this disclosure;

[0074] Figure 15 This is a schematic diagram showing the connection between the first gate driving circuit and the second gate driving circuit in an embodiment of this disclosure.

[0075] Figure 16 This is a schematic diagram showing the connection between the third gate driving circuit and the fourth gate driving circuit in an embodiment of this disclosure;

[0076] Figure 17 This is a schematic diagram showing the alternating arrangement of data lines and scan signal lines in an embodiment of this disclosure;

[0077] Figure 18 This is a schematic diagram of the first membrane structure in the embodiments of this disclosure;

[0078] Figure 19 This is a schematic diagram of the second membrane structure in the embodiments of this disclosure;

[0079] Figure 20 This is a schematic diagram of the third membrane structure in the embodiments of this disclosure;

[0080] Figure 21 This is a schematic diagram of the film layers of each connecting line in the first embodiment of this disclosure;

[0081] Figure 22 This is a schematic diagram of the membrane layers of each connecting line in the second type of embodiment of this disclosure;

[0082] Figure 23 This is a schematic diagram of the fourth and fifth vias in an embodiment of this disclosure;

[0083] Figure 24 This is a schematic diagram of the membrane layers of each connecting line in the third type of embodiment of this disclosure;

[0084] Figure 25 This is a schematic diagram of the membrane layers of each connecting line in the fourth type of embodiment of this disclosure;

[0085] Figure 26 This is a schematic diagram of the signal adapter cable connection in an embodiment of this disclosure;

[0086] Figure 27 This is a schematic diagram illustrating the first type of splicing of multiple display panels;

[0087] Figure 28 This is a schematic diagram illustrating the second type of splicing of multiple display panels. Detailed Implementation

[0088] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the technical solutions of this disclosure, and not all embodiments. Based on the embodiments recorded in this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the technical solutions of this disclosure.

[0089] The terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this utility model are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such use of data can be interchanged where appropriate so that embodiments of the utility model described herein can be implemented in sequences other than those illustrated or described herein.

[0090] In related technologies, the gate driving circuits used to drive the display panel for horizontal scanning during the display process are typically located on the left and right sides of the display panel (including Mini LED, Micro LED, LCD, and OLED). (See also...) Figure 1 As shown, for example, the display panel includes a display area and a fan-out area. The gate driving circuit 1 is disposed on the left side of the display area, and the gate driving circuit 2 is disposed on the right side of the display area. Furthermore, the row scanning signal generated by the gate driving circuit is provided to each gate line in the display panel line by line.

[0091] However, with advancements in technology, display panels composed of Mini LEDs and Micro LEDs no longer require edge packaging, theoretically enabling seamless splicing of such panels. However, the aforementioned... Figure 1The way the gate driving circuit is set up makes it impossible to splice Mini LED and Micro LED display panels side by side. Furthermore, when the PPI is high enough, the gate driving circuit cannot be placed in the display area of ​​the display panel due to space limitations. Therefore, the splicing problem of display panels cannot be solved.

[0092] The preferred embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0093] A display panel proposed in this application embodiment includes a display area and a fan-out area.

[0094] The display area includes: multiple gate lines extending along a first direction and arranged along a second direction. A fan-out region is located on at least one side of the multiple gate lines in the first direction.

[0095] The fan-out region includes a gate drive circuit, which is connected to multiple gate lines.

[0096] In this embodiment of the application, the display area includes multiple grid lines arranged parallel to each other. The multiple grid lines extend in the display panel along a first direction (exemplarily, horizontal direction). For example, each grid line extends from the left edge of the display area of ​​the display panel to the right edge of the display area. Furthermore, the multiple grid lines are arranged along a second direction (exemplarily, vertical direction). For example, the multiple grid lines are arranged in parallel from the upper edge of the display area to the lower edge of the display area.

[0097] It should be noted that the above-mentioned gate line can be an luminescence control signal line (i.e., EM line), a reset control signal line (i.e., Reset line), a scan signal line (i.e., Gate line), or other signal control lines in the pixel driving circuit to which the gate line is connected, without any specific limitation here.

[0098] In this embodiment of the application, the fan-out region is located on at least one side of the multiple gates in the first direction. For example, the fan-out region is located on one side of the gate line in the first direction, that is, the fan-out region is located above the display area, or the fan-out region is located below the display area, or, for example, the fan-out region is located on both sides of the gate line in the first direction, that is, the fan-out region is located above and below the display area respectively.

[0099] It should be noted that the above-mentioned gate driving circuit setting in the fan-out area is suitable for high PPI scenarios, for example, PPI below 0.3 mm. Furthermore, when display panels with the above-mentioned PPI need to be spliced, the gate driving circuits set on the left and right sides will cause splicing to fail.

[0100] See Figure 2As shown, in the first embodiment, the display panel includes a display area and a fan-out area. The fan-out area is located above the display area. Typically, in order to save space and facilitate wiring, the two corners of the fan-out area away from the display area are designed in an arc shape, and the two arcs protrude in the direction away from the display area.

[0101] In this embodiment, the gate driving circuit is disposed in the aforementioned fan-out region, see reference. Figure 2 As shown, to facilitate wiring for the entire display panel, the gate driving circuit is positioned in the middle of the fan-out area. To avoid overlapping with power lines in the fan-out area, the gate driving circuit can also be positioned on either side of the fan-out area. For example, see [reference needed]. Figure 3 As shown, the gate drive circuit is located on the left side of the fan-out region. For example, see [reference needed]. Figure 4 As shown, the gate drive circuit is located on the right side of the fan-out region, etc.

[0102] In some implementations, for example, when the display panel is dual-sided driven, the display panel includes two gate driving circuits, which may be respectively disposed on both sides of the fan-out region. See also... Figure 5 As shown, when the display panel includes a gate driving circuit 11 and a gate driving circuit 12, the gate driving circuit 11 is located on the left side of the fan-out area, and the gate driving circuit 12 is located on the right side of the fan-out area.

[0103] In the second embodiment, see Figure 6 As shown, the display panel includes a display area and a fan-out area, which can also be located below the display area. Similarly, the two corners of the fan-out area away from the display area are arc-shaped, and these two arcs bulge outwards in the direction away from the display area. When the fan-out area is located below the display area, the gate drive circuit can also be located in the middle or on both sides of the fan-out area, which will not be elaborated here.

[0104] In the third embodiment, see Figure 7 As shown, the display panel includes a display area and two fan-out areas, one of which is located above the display area and the other below it. In this embodiment, the gate driving circuit 1 of the display panel can be placed in the fan-out area 1 located above the display area, and the gate driving circuit 2 of the display panel can be placed in the fan-out area 2 located below the display area. The arrangement of the two fan-out areas allows the wiring harness of the display panel to be connected to the peripheral source driving circuit, etc., through both fan-out areas simultaneously, thereby making the wiring more flexible.

[0105] During implementation, the row scanning signals generated by the gate driving circuit are provided to each gate line located in the display area after passing through the fan-out area, so that the gate lines can perform row scanning display, thereby enabling the display panel to complete the display process.

[0106] After introducing the configuration of the gate drive circuit in the fan-out region, the following section describes the signal line connection between the gate drive circuit and the gate line.

[0107] In this embodiment, the fan-out area further includes multiple scanning fan-out lines.

[0108] The scanning fan-out line is electrically connected between the gate drive circuit and the gate line.

[0109] Multiple scanning fan-out lines extend along the second direction and are arranged along the first direction.

[0110] The following describes the wiring using an example of a display panel comprising a fan-out area and a display area, with the gate driving circuit positioned in the middle of the fan-out area. To ensure that the horizontal scanning signal generated by the gate driving circuit can be provided to each gate line of the display area, in this embodiment, multiple scanning fan-out lines are connected to the drive output terminal of the gate driving circuit. These multiple scanning fan-out lines are positioned within the fan-out area, with one end connected to the drive output terminal of the gate driving circuit and the other end connected to a gate line. Thus, after the gate driving circuit generates the horizontal scanning signal, the signal is transmitted through the scanning fan-out lines of the fan-out area before being provided to the gate lines of the display area.

[0111] To facilitate connection with the gate lines of the display area, the aforementioned multiple scanning fan-out lines extend along a second direction (exemplarily, vertical direction). For example, each scanning fan-out line extends from the edge where the drive output terminal of the gate drive circuit in the fan-out area is located to the lower edge of the fan-out area, and is arranged along a first direction (exemplarily, horizontal direction). For example, the multiple scanning fan-out lines are arranged sequentially from the left edge of the fan-out area to the right edge of the fan-out area.

[0112] It should be further explained that since there is only one drive output terminal of the gate drive circuit, when each scan fan-out line is connected to the gate line from the drive output terminal, the extension of each scan fan-out line along the second direction can be understood as extending approximately along the second direction. That is, the second direction approximately satisfies the vertical direction, which is within the protection scope of this utility model, that is, it can be the vertical direction allowed within the allowable error range.

[0113] See Figure 8 As shown, the scanning fan-out line includes a first scanning fan-out sub-line and a second scanning fan-out sub-line that are connected to each other.

[0114] The first scan fan-out sub-line is connected to the drive output terminal of the gate drive circuit. Each first scan fan-out sub-line is arranged along the first direction, and the length of each first scan fan-out sub-line gradually increases from the drive output terminal to both ends of the fan-out area.

[0115] The second scan fan-out sub-line is connected to the scan signal line, and each second scan fan-out sub-line extends along the second direction and is arranged along the first direction.

[0116] To ensure consistent capacitance and resistance characteristics among the scanning fan-out lines, each scanning fan-out line in this embodiment includes two connecting segments in the fan-out area: a first scanning fan-out sub-line and a second scanning fan-out sub-line. One end of the first scanning fan-out sub-line is connected to the drive output terminal of the gate driving circuit, and the other end is connected to one end of the second scanning fan-out sub-line. The other end of the second scanning fan-out sub-line is connected to the scan signal line of the display area. Thus, the row scanning signal generated by the gate driving circuit, after being transmitted through the first and second scanning fan-out sub-lines in the fan-out area, is provided to the scan signal line of the display area.

[0117] See Figure 8 As shown, each first scan fan-out sub-line is arranged along a first direction (exemplarily, horizontally), that is, each first scan fan-out sub-line is arranged in a fan shape with the aforementioned drive output terminal as the center. In this embodiment, the length of each first scan fan-out sub-line gradually increases from the drive output terminal to both ends of the fan-out area. Since the resistance value of a signal line is proportional to its length, correspondingly, the resistance value of each first scan fan-out sub-line also gradually increases from the drive output terminal to both ends of the fan-out area. For example, see [reference needed]. Figure 8 As shown, when the gate drive circuit is set in the middle of the fan-out region, the resistance value of the first scan fan-out sub-line located on both sides is larger, and the resistance value of the first scan fan-out sub-line near the middle position is smaller.

[0118] See Figure 8 As shown, each second scan fan-out sub-line extends along a second direction (exemplarily, vertical direction), that is, each second scan fan-out sub-line extends from the lower edge of the first scan fan-out sub-line in the fan-out area to the lower edge of the fan-out area, and is arranged along a first direction (exemplarily, horizontal direction). For example, multiple second scan fan-out sub-lines are arranged sequentially from the left edge of the fan-out area to the right edge of the fan-out area.

[0119] See Figure 9 As shown, the fan-out area also includes multiple compensation resistors, each of which is electrically connected between the drive output terminal and the first scan fan-out sub-line.

[0120] The resistance value of each compensation resistor gradually decreases from the drive output terminal to the two ends of the fan-out region.

[0121] Since the resistance value affects the time delay, in order to compensate for the influence of the different resistance values ​​of the different first scan fan-out sub-lines on the transmitted signal, compensation resistors with different resistance values ​​are used to compensate the resistance values ​​of each first scan fan-out sub-line, so that the resistance values ​​of each first scan fan-out sub-line are equal after compensation. In this way, the attenuation of the row scan signal after transmission through each first scan fan-out sub-line and the corresponding compensation resistor is the same.

[0122] See Figure 9 As shown, the multiple compensation resistors included in the fan-out area have different resistance values. Each resistor is positioned between the drive output terminal of the gate drive circuit and the first scan fan-out sub-line; that is, the horizontal scan signal is provided to the second scan fan-out sub-line after transmission through the first scan fan-out sub-line and the compensation resistors. See details... Figure 9 As shown, compensation resistor R1 is connected to the first scan fan-out sub-line 1, and the first scan fan-out sub-line 1 is connected to the second scan fan-out sub-line 1. Compensation resistor R2 is connected to the first scan fan-out sub-line 2, and the first scan fan-out sub-line 2 is connected to the second scan fan-out sub-line 2. Compensation resistor R3 is connected to the first scan fan-out sub-line 3, and the first scan fan-out sub-line 3 is connected to the second scan fan-out sub-line 3. Compensation resistor R4 is connected to the first scan fan-out sub-line 4, and the first scan fan-out sub-line 4 is connected to the second scan fan-out sub-line 4. Compensation resistor R2' is connected to the first scan fan-out sub-line 2', and the first scan fan-out sub-line 2' is connected to the second scan fan-out sub-line 2'. Compensation resistor R3' is connected to the first scan fan-out sub-line 3', and the first scan fan-out sub-line 3' is connected to the second scan fan-out sub-line 3'. Compensation resistor R4' is connected to the first scan fan-out sub-line 4', and the first scan fan-out sub-line 4' is connected to the second scan fan-out sub-line 4'.

[0123] It should also be noted that the first scanning fan-out sub-line 1 is the shortest and has the lowest resistance; correspondingly, the compensation resistor connected to it has the highest resistance. The first scanning fan-out sub-lines 4 and 4' are the longest and have the highest resistance; correspondingly, the compensation resistor connected to them has the lowest resistance. The first scanning fan-out sub-lines 2, 3, 2', and 3' are of medium length and have medium resistance; correspondingly, the compensation resistor connected to them also has a medium resistance.

[0124] In this embodiment, the display area also includes multiple scan signal lines. It should be noted that, regarding the arrangement of the scan signal lines in the display area, there are two scenarios in this embodiment: First scenario: the scan signal lines extend only along the second direction. (See [reference]). Figure 10 and Figure 11 As shown; the second case: the scan signal line extends first along the second direction and then along the first direction, see reference. Figure 12 As shown.

[0125] In the first and second cases described above, the scan signal line is electrically connected between the scan fan-out line and the grid line, wherein the scan signal line and the scan fan-out line are connected in a one-to-one correspondence.

[0126] To facilitate connection with the grid lines of the display area, in this embodiment of the application, the display area also includes multiple scan signal lines. The number of scan signal lines is the same as the number of scan fan-out lines, thereby realizing a one-to-one correspondence between the scan fan-out lines and the scan signal lines.

[0127] One end of the aforementioned scanning signal line is connected to the scanning fan-out line of the fan-out area, and the other end of the aforementioned scanning signal line is connected to the gate line of the display area. From the perspective of the direction of the horizontal scanning signal, the horizontal scanning signal output by the drive output terminal of the gate drive circuit is first provided to the scanning fan-out line of the fan-out area (or the first scanning fan-out sub-line and the second scanning fan-out sub-line), and after being transmitted through the scanning fan-out line (or the first scanning fan-out sub-line and the second scanning fan-out sub-line), the aforementioned horizontal scanning signal is further provided to the gate line of the display area.

[0128] In the first case mentioned above, see [link / reference] Figure 10 As shown, multiple scanning signal lines extend along the second direction and are arranged along the first direction.

[0129] In this embodiment of the application, the above-mentioned multiple scanning signal lines extend along the second direction (exemplarily, the vertical direction). Exemplarily, each scanning signal line extends from the upper edge of the display area to the lower edge of the display area and is arranged along the first direction (exemplarily, the horizontal direction). Exemplarily, the multiple scanning signal lines are arranged sequentially from the left edge of the display area to the right edge of the signal area.

[0130] It should be noted that, see reference Figure 11 As shown, in order to ensure that the capacitance-resistance characteristics (i.e., RC characteristics) of each scan signal line are the same, the lengths of the scan signal lines are equal, that is, the lengths of each scan signal line are as follows: Figure 11 As shown in H, the lengths of each scan signal line in the second direction are equal. For example, each scan signal line extends from the position of the first gate line in the display area to the position of the last gate line, so that the capacitance characteristics of each scan signal line are consistent.

[0131] In the second scenario described above, see [reference] Figure 12 As shown, each scan signal line includes a first scan signal sub-line and a second scan signal sub-line that are connected to each other.

[0132] The first scan signal sub-line is connected to the scan fan-out line, and the first scan signal sub-line extends along the second direction and is arranged along the first direction.

[0133] The second scan signal sub-line is connected to the gate line, and the second scan signal sub-line extends along the first direction and is arranged along the second direction.

[0134] See Figure 12 As shown, taking a display panel that includes a fan-out area and a display area, with the gate driving circuit located on the left side of the fan-out area as an example, the wiring is explained. In order to facilitate the connection with the gate line of the display area, each scan signal line in this embodiment includes two connected segments, that is, the scan signal line includes a first scan signal sub-line and a second scan signal sub-line connected together.

[0135] One end of the first scan signal sub-line is connected to the scan fan-out line (or the second scan fan-out sub-line) of the fan-out area, and the other end of the first scan signal sub-line is connected to one end of the second scan signal sub-line. The other end of the second scan signal sub-line is connected to the gate line of the display area. In this way, the row scan signal generated by the gate drive circuit is provided to the first scan signal sub-line and the second scan signal sub-line of the display area after being transmitted through the fan-out area.

[0136] See Figure 12 As shown, each first scan signal sub-line extends along a second direction (exemplarily, vertically), that is, each first scan signal sub-line extends from the upper edge of the display area to the lower edge of the display area, and is arranged along a first direction (exemplarily, horizontally). For example, see [reference needed]. Figure 12 As shown, when the gate drive circuit is set to the left side of the fan-out area, the multiple first scan signal sub-lines located on the left side extend from the position of the first gate line in the display area to the position of the last gate line.

[0137] See Figure 12 As shown, each second scan signal sub-line extends along a first direction (exemplarily, horizontal direction), that is, each second scan signal sub-line extends from the left border of the display area to the left end of the grid line in the display area, and is arranged along a second direction (exemplarily, vertical direction). For example, multiple second scan signal sub-lines are arranged sequentially from the upper edge of the display area to the lower edge of the display area.

[0138] It should be noted that, in order to improve the consistency of capacitance characteristics among the first scan signal sub-lines, the lengths of the first scan signal sub-lines are equal. Preferably, see [reference needed]. Figure 13 As shown, in the display area, each first scan signal sub-line extends from the position of the first gate line to the position of the last gate line in the display area, that is, the length of each first scan signal sub-line is as follows: Figure 13 As shown in L, the starting point of each first scan signal sub-line is the upper edge of the display area, and the ending point of each first scan signal sub-line is the lower edge of the display area (or the aforementioned ending point coincides with the left end point of the last gate line in the display area), thereby effectively ensuring that the capacitance characteristics of each first scan signal sub-line are the same.

[0139] It should be further explained that, although the row scan signal is transferred from the corresponding gate line position in the first scan signal sub-line to the second scan signal sub-line for different first scan signal sub-lines, meaning that the transmission length of each row scan signal in each first scan signal sub-line is not equal, the resistance value of the signal line of the same material is proportional to the length of the transmission line (in this embodiment, it is assumed that the resistivity, i.e., the material, of each first scan signal sub-line is the same, and the cross-sectional area of ​​each first scan signal sub-line is also the same), and therefore the resistance values ​​of each first scan signal sub-line are different. However, since the length between the start and end points of each first scan signal sub-line is equal, in this embodiment, it is assumed that the facing areas of different first scan signal sub-lines in different film layers are the same. Thus, the facing areas of the capacitor plates of the coupling capacitor formed by different first scan signal sub-lines are the same, and therefore the capacitance value of each first scan signal sub-line is the same.

[0140] In addition, the above Figure 12 and Figure 13 This is merely a schematic diagram of the first and second scan signal sub-lines; the actual arrangement and length of the first and second scan signal sub-lines are not specifically defined. Compared to the method where the gate drive circuit is located on both sides of the display area, the above-mentioned row scan signal... Figure 13 The way the first and second scan signal sub-lines are transmitted to the gate lines will inevitably occupy some space on both sides of the display area, but the space occupied is still within the scope of the borderless display panel.

[0141] It should be further explained that, in order to facilitate the connection between the second scan signal sub-line and the gate line, the second scan signal sub-line and the gate line are usually disposed in the same film layer (exemplarily, Gate1 layer). Considering the RC characteristics between the second scan signal sub-line and the gate line, the second scan signal sub-line can also be first disposed in a metal layer SD1 adjacent to Gate1 before providing the row scan signal to the gate line. For example, the second scan signal sub-line is transferred through the SD1 layer before entering the film layer Gate1 where the gate line is located; no specific limitation is made here.

[0142] It should also be noted that in some application scenarios, please refer to... Figure 14 As shown, the fan-out area also includes multiple signal adapter cables.

[0143] The signal adapter cable is electrically connected between the scan fan-out line and the scan signal line, wherein the signal adapter cable, the scan signal line and the scan fan-out line are connected in a one-to-one correspondence.

[0144] During implementation, the scan fan-out lines and scan signal lines can be connected via signal adapter cables. These signal adapter cables are typically located in the fan-out area, with each scan fan-out line connecting to its corresponding scan signal line via a specific signal adapter cable. This arrangement of signal adapter cables allows for more flexible connection methods between the scan fan-out lines and scan signal lines.

[0145] Additionally, see Figure 15 As shown, the gate driving circuit includes: a first gate driving circuit and a second gate driving circuit.

[0146] The first row scan signal generated by the first gate drive circuit is provided to the scan signal lines located in the odd-numbered rows of the display area via the scan fan-out line.

[0147] The second row scan signal generated by the second gate drive circuit is provided to the scan signal line located in the even-numbered rows of the display area via the scan fan-out line.

[0148] First, it should be noted that the gate driving circuit mentioned in the embodiments of this application can be any one of the following: a gate driving circuit for controlling light emission (i.e., EM GOA), a gate driving circuit for controlling the reset of a certain port (e.g., the anode of the light-emitting device, the control terminal of the driving transistor, etc.) (i.e., Reset GOA), a gate driving circuit for controlling the writing of data voltage (i.e., Gate GOA), or a gate driving circuit for other purposes in related pixel driving circuits.

[0149] See Figure 15 As shown, in one embodiment, the gate driving circuit in this application includes a first gate driving circuit and a second gate driving circuit. For example, the first gate driving circuit can be a Gate GOA for controlling data voltage writing, and correspondingly, the second gate driving circuit is also a Gate GOA for controlling data voltage writing. Furthermore, the first gate driving circuit (or the second gate driving circuit) can also be an EMGOA for controlling light emission, and the first gate driving circuit (or the second gate driving circuit) can also be a Reset GOA for controlling reset; no specific limitations are made here.

[0150] It should be noted that the gate driving circuit including the first gate driving circuit and the second gate driving circuit is only for illustrative purposes. In actual use cases, the specific number and function of the gate driving circuits are not limited. For example, the gate driving circuit may also include Gate GOA for controlling data writing, EMGOA for controlling light emission, and Reset GOA for controlling reset, etc.

[0151] During implementation, when multiple gate drive circuits are included, individual control of the gate lines in odd-numbered and even-numbered rows can be achieved accordingly.

[0152] For example, the first row scan signal generated by the first gate driving circuit is provided to the gate lines of the odd-numbered rows in the display area. That is, the first row scan signal is provided to the scan signal lines of the odd-numbered rows in the display area via the scan fan-out lines of the fan-out area, and then provided to the gate lines of the odd-numbered rows by the scan signal lines. Similarly, the second row scan signal generated by the second gate driving circuit is provided to the gate lines of the even-numbered rows in the display area. That is, the second row scan signal is provided to the scan signal lines of the even-numbered rows in the display area via the scan fan-out lines of the fan-out area, and then provided to the gate lines of the even-numbered rows by the scan signal lines.

[0153] See Figure 16 As shown, the gate driving circuit includes a third gate driving circuit and a fourth gate driving circuit.

[0154] The third row scan signal generated by the third gate drive circuit is provided to some pixel units located in any row of the display area via the scan fan-out line.

[0155] The fourth row scan signal generated by the fourth gate drive circuit is provided to the pixel units located in the remaining part of any row of the display area via the scan fan-out line.

[0156] See Figure 16 As shown, in another embodiment, the gate driving circuit in this application includes a third gate driving circuit and a fourth gate driving circuit. The row scanning signals generated by the third gate driving circuit and the fourth gate driving circuit are provided to each gate line in the display area. However, the difference is that the third row scanning signal generated by the third gate driving circuit is only provided to a portion of the pixel units connected to each row of gate lines in the display area. The remaining pixel units connected to the row of gate lines are driven by the fourth row scanning signal generated by the fourth gate driving circuit.

[0157] That is, the third row of scanning signals generated by the third gate driving circuit is provided to some pixel units located in any row of the display area. After passing through the scanning fan-out line of the fan-out area, the third row of scanning signals is further provided to the scanning signal line in the display area that is connected to the scanning fan-out line. Then, the scanning signal line provides the third row of scanning signals to the gate line of any row, and then to some pixel units.

[0158] For example, considering the low distortion of the row scan signal at the beginning of the gate driving circuit, the pixel units on the left side of any row in the display area can be connected to a gate line. The pixel units connected to this gate line are driven by the third row scan signal provided by the third gate driving circuit. The pixel units on the right side of any row in the display area can be connected to another gate line. The pixel units connected to this gate line are driven by the fourth row scan signal provided by the fourth gate driving circuit. Alternatively, in a Dual Gate pixel architecture, pixel units in the same row are connected by different gate lines. In this way, a portion of the pixel units are driven by the third row scan signal provided by the third gate driving circuit, while the remaining pixel units are driven by the fourth row scan signal provided by the fourth gate driving circuit.

[0159] See Figure 17 As shown, the display area also includes multiple data lines.

[0160] Multiple data lines and multiple scan signal lines are arranged alternately along the first direction.

[0161] It should be noted that, in order to ensure that the multiple scanning signal lines in the display area are evenly arranged, in this embodiment of the application, the multiple data lines and multiple scanning signal lines are arranged alternately along the first direction. The specific number of the multiple data lines and multiple scanning signal lines is not limited.

[0162] See Figure 17 As shown, in the display area, every six data lines and one scan signal line are arranged alternately in a first direction (exemplarily, the horizontal direction). Figure 17 In the display area, data lines 1, 2, 3, 4, 5, and 6 are arranged sequentially from left to right. To the right of data line 6, there is a scan signal line 1 parallel to data line 6. In the vertical direction, the scan fan-out line 1 of the fan-out area is connected to the scan signal line 1. And so on. After every 6 data lines are arranged horizontally, there is a scan signal line. There are a total of seven scan signal lines, from the left edge to the right edge of the display area, from scan signal line 1 to scan signal line 7. Correspondingly, there are a total of seven scan fan-out lines, from the left edge to the right edge of the fan-out area, from scan fan-out line 1 to scan fan-out line 7.

[0163] The alternating arrangement of multiple data lines and multiple scan signal lines makes the distribution of data lines and scan signal lines in the entire display area more uniform.

[0164] After introducing the related connecting lines such as the scanning fan-out lines and scanning signal lines, the following section will explain the connection relationship of the scanning fan-out lines and scanning signal lines in the various film layers of the display panel, in conjunction with the film layer diagram.

[0165] first, Figure 18 , Figure 19 and Figure 20 Some schematic diagrams of film layers provided for embodiments of this disclosure, wherein, Figure 18 The semiconductor material layer in the film is the Poly layer, the Gate1 layer, SD1 layer, SD2 layer and Cu layer are the conductive layers, and the remaining film layers are insulating layers. Figure 19 The semiconductor material layer in the film is the Poly layer, and the Gate1 layer, Gate2 layer, SD1 layer, SD2 layer and Cu layer are the conductive layers, while the remaining film layers are insulating layers. Figure 20 The semiconductor material layer in the film is the Poly layer, and the Gate1 layer, Gate2 layer, SD1 layer, SD2 layer, SD3 layer and Cu layer are the conductive layers, while the remaining film layers are insulating layers.

[0166] In the embodiments of this application, the membrane structure can also be Figure 18 , Figure 19 and Figure 20 Other structures besides the membrane shown in the schematic diagram will not be described in detail here. The following description will focus on... Figure 18 , Figure 19 and Figure 20 The following is a detailed explanation using a schematic diagram of the membrane layer shown as an example.

[0167] See Figure 18 As shown, the display panel also includes:

[0168] The first conductive layer is located on the substrate and includes multiple second scan fan-out sub-lines and multiple second scan signal sub-lines.

[0169] It should be noted that, based on the connection relationship between each scanning fan-out line and each scanning signal line in different film layers, the aforementioned multiple scanning fan-out lines include connected first scanning fan-out sub-lines and second scanning fan-out sub-lines, and the aforementioned multiple scanning signal lines include connected first scanning signal sub-lines and second scanning signal sub-lines. Furthermore, in order to ensure the consistency of the RC electrical characteristics of each scanning fan-out line and each scanning signal line in the fan-out area and the display area, that is, to ensure that the time delay caused by the resistance and capacitance values ​​are equal, the aforementioned first scanning signal sub-lines also include first type first scanning signal sub-lines and second type first scanning signal sub-lines.

[0170] For example, a first conductive layer is disposed on a substrate, see reference. Figure 18 , Figure 19 and Figure 20 As shown, the first conductive layer is the Gate 1 layer. Considering that a power signal bus (VDD line and VSS line) is also provided in the fan-out region, which is usually located in the SD2 layer or Cu layer, in order to minimize the coupling effect with the power signal bus, the multiple second scan fan-out sub-lines are located on the first conductive layer. Thus, from the film layer diagram, the distance between the first conductive layer where the second scan fan-out sub-lines are located and the film layer where the power signal bus is located is the farthest, and the coupling effect of resistors, capacitors, etc. is minimized.

[0171] Considering that the gates of the transistors in the pixel driving circuit included in the pixel unit are disposed in the first conductive layer, in order to facilitate the transmission of the row scanning signal, the multiple second scanning signal sub-lines are also disposed in the first conductive layer. It should be noted that, in order to facilitate signal transmission and minimize the coupling effect between the connecting lines, the length of the second scanning signal sub-lines in the first conductive layer is relatively short. For example, one second scanning signal sub-line is disposed in the first conductive layer between every two adjacent gate lines.

[0172] The first insulating layer is located on the side of the first conductive layer that is away from the substrate.

[0173] In this embodiment, a first insulating layer is provided on the side of the first conductive layer that is away from the substrate, thereby insulating it from the first conductive layer.

[0174] See Figure 18 As shown, the first insulating layer is a GI layer. (See reference...) Figure 19 As shown, the first insulating layer is the GI1 layer. (See reference...) Figure 20 As shown, the first insulating layer is the GI1 layer.

[0175] The second conductive layer is located on the side of the first insulating layer away from the substrate. The second conductive layer includes multiple first scan fan-out sub-lines and multiple signal conversion lines.

[0176] In this embodiment, a second conductive layer is provided on the side of the first insulating layer that faces away from the substrate. (See reference...) Figure 18 , Figure 19 and Figure 20 As shown, the second conductive layer is the SD1 layer.

[0177] In this embodiment, the row scan signal is transmitted through the first scan fan-out sub-line located in the SD1 layer after being output from the drive output terminal of the gate drive circuit. Since no power signal bus is provided in the first conductive layer corresponding to the first scan fan-out sub-line in the SD1 layer, in the implementation process, only the resistance value of the first scan fan-out sub-line needs to be considered for this connection.

[0178] Additionally, see Figure 19 and 19 As shown, the first conductive layer can also be Figure 19 and 19 The Gate2 layer, the second conductive layer can also be Figure 19 and 19 The SD2 or SD3 layer. In specific implementation, the film layer containing the gate of the relevant transistor in the pixel driving circuit that provides the row scan signal by the gate driving circuit can be determined first. For example, when the gate is located in the Gate2 layer, the first conductive layer is the Gate2 layer.

[0179] In addition, the display panel also includes a second insulating layer located on the side of the second conductive layer away from the substrate.

[0180] In this embodiment, a second insulating layer is provided on the side of the second conductive layer that faces away from the substrate, thereby insulating it from the second conductive layer.

[0181] See Figure 18 As shown, the second insulating layer is an ILD layer. (See reference...) Figure 19 As shown, the second insulating layer is an ILD layer. (See reference...) Figure 20 As shown, the second insulating layer is an ILD layer.

[0182] The third conductive layer is located on the side of the second insulating layer away from the substrate, and the third conductive layer includes multiple first scan signal sub-lines.

[0183] In this embodiment, a third conductive layer is provided on the side of the second insulating layer that faces away from the substrate. (See reference...) Figure 18 , Figure 19 and Figure 20 As shown, the third conductive layer is the SD2 layer.

[0184] Considering that the power lines in the display area (i.e., the arrangement of power lines connected to the aforementioned power signal bus in the display area) are usually disposed in the Cu layer, in the first embodiment, the multiple first scan signal sub-lines in this application embodiment are disposed in the third conductive layer, that is, the SD2 layer as the film layer for the vertical scan signal lines. This avoids the vertical gate lines from opening, i.e., avoids signal abnormalities in other rows of gate lines that may be caused by signal coupling. It should be noted that the first scan signal sub-lines in the aforementioned third conductive layer are usually vertically extending scan signal lines.

[0185] The third insulating layer is located on the side of the third conductive layer that faces away from the substrate.

[0186] In this embodiment, a third insulating layer is provided on the side of the third conductive layer that faces away from the substrate, thereby insulating it from the aforementioned third conductive layer.

[0187] See Figure 18 As shown, the third insulating layer consists of a PLN1 layer and a PVX1 layer. (See reference...) Figure 19 As shown, the third insulating layer consists of a PLN1 layer and a PVX1 layer. (See reference...) Figure 20 As shown, the third insulating layer consists of PLN1 and PVX1 layers.

[0188] The fourth conductive layer, located on the side of the third insulating layer away from the substrate, includes multiple power lines.

[0189] In this embodiment, a fourth conductive layer is provided on the side of the third insulating layer that faces away from the substrate. (See reference...) Figure 18 , Figure 19 and Figure 20 As shown, the fourth conductive layer is a Cu layer.

[0190] For example, see Figure 21 As shown, the first insulating layer is represented by insulating layer 1, the second insulating layer is represented by insulating layer 2, and the third insulating layer is represented by insulating layer 3.

[0191] Multiple power lines disposed in the fourth conductive layer extend vertically in the display area. In order to make the power lines in the display area intersect into a mesh, the power lines can also be transferred to the first conductive layer and arranged as connecting lines extending horizontally.

[0192] In the second embodiment, see Figure 22 As shown, the first scan signal sub-line includes: a first type of first scan signal sub-line and a second type of first scan signal sub-line.

[0193] The third conductive layer includes multiple first-type first scan signal sub-lines.

[0194] The second conductive layer includes multiple second-type first scan signal sub-lines.

[0195] Considering that the first scan signal sub-line extends a relatively long length in the vertical direction, in order to reduce the coupling effect between different connecting lines in this embodiment, the above-mentioned multiple first-type first scan signal sub-lines are disposed in the third conductive layer. From the perspective of film structure, the third conductive layer is farther from the first conductive layer than the second conductive layer, so the coupling capacitance value between the second scan fan-out sub-line, the second scan signal sub-line and the first-type first scan signal sub-line is smaller.

[0196] However, for ease of wiring, the second type of first scan signal sub-line connected to the first type of first scan signal sub-line is transferred to the second conductive layer, thereby facilitating signal transmission with the gate line located in the first conductive layer. Typically, the second type of first scan signal sub-line is positioned at a shorter distance in the second conductive layer.

[0197] See Figure 21 As shown, the first end of the first scanning fan-out sub-line is connected to the first end of the second scanning fan-out sub-line through a first through-hole penetrating the first insulating layer.

[0198] The second end of the second scanning fan-out sub-line is connected to the first end of the first scanning signal sub-line or the first end of the first type of first scanning signal sub-line through a second via penetrating the first and second insulating layers.

[0199] In order to make the second scanning fan-out sub-line electrically connected to the first scanning fan-out sub-line, that is, to make the line scanning signal smoothly transmitted from the first scanning fan-out sub-line to the second scanning fan-out sub-line, in this embodiment of the application, a first via is provided in the first insulating layer, that is, the insulating layer between the second conductive layer and the first conductive layer is etched away, so that the first end of the first scanning fan-out sub-line is connected to the first end of the second scanning fan-out sub-line.

[0200] Similarly, a through-hole is provided in the first and second insulating layers, that is, the insulating layer between the third conductive layer and the first conductive layer is etched away. In this way, the second end of the second scanning fan-out sub-line can be connected to the first end of the first scanning signal sub-line or the first end of the first type of first scanning signal sub-line through the second through-hole.

[0201] From the perspective of the horizontal scanning signal's trajectory, after passing through the first scan fan-out sub-line, the horizontal scanning signal is provided to the second scan fan-out sub-line via the first via. (See reference...) Figure 21 and 21 As shown, the aforementioned row scan signal is further provided to the first scan signal sub-line through the second via, or the aforementioned row scan signal is further provided to the first type of first scan signal sub-line through the second via.

[0202] See Figure 21As shown, the second end of the first scan signal sub-line is connected to the first end of the second scan signal sub-line through a third via penetrating the first and second insulating layers.

[0203] In order to make the first scan signal sub-line and the second scan signal sub-line electrically connected, that is, to make the row scan signal smoothly transmitted from the first scan signal sub-line to the second scan signal sub-line, in this embodiment of the application, a through third via is provided in the first insulating layer and the second insulating layer, that is, the insulating layer between the third conductive layer and the first conductive layer is etched away, so that the second end of the first scan signal sub-line is connected to the first end of the second scan signal sub-line.

[0204] From the perspective of the direction of the row scan signal, the row scan signal is provided to the second scan signal sub-line after passing through the first scan signal sub-line.

[0205] See Figure 22 and Figure 23 As shown, the second end of the first scan signal sub-line of the first type is connected to the first end of the first scan signal sub-line of the second type through a fourth via penetrating the second insulating layer.

[0206] The second end of the second type of first scan signal sub-line passes through the fifth via of the first insulating layer and is connected to the first end of the second scan signal sub-line.

[0207] In order to make the first type of first scan signal sub-line electrically connected to the second type of first scan signal sub-line, that is, to make the row scan signal smoothly transmitted from the first type of first scan signal sub-line to the second type of first scan signal sub-line, in this embodiment of the application, a through fourth via is provided in the second insulating layer, that is, the insulating layer between the third conductive layer and the second conductive layer is etched away, so that the second end of the first type of first scan signal sub-line is connected to the first end of the second type of first scan signal sub-line.

[0208] Similarly, in this embodiment, a through-hole is provided in the first insulating layer, that is, the insulating layer between the second conductive layer and the first conductive layer is etched away, so that the second end of the second type of first scan signal sub-line is connected to the first end of the second scan signal sub-line.

[0209] From the perspective of the direction of the row scanning signal, the row scanning signal is provided to the second type of first scanning signal sub-line after passing through the first type of first scanning signal sub-line, and then further provided to the second scanning signal sub-line.

[0210] It should be noted that, see reference Figure 24 , Figure 25 and Figure 26As shown, in another embodiment, the second end of the second scanning fan-out sub-line is connected to the first end of the signal adapter line through a sixth via penetrating the first insulating layer, and the second end of the signal adapter line is connected to the first end of the first scanning signal sub-line through a seventh via penetrating the second insulating layer; or

[0211] See Figure 24 As shown, in order to enable the second scanning fan-out sub-line to be electrically connected to the first scanning signal sub-line without passing through the aforementioned second via, that is, to enable the row scanning signal to be smoothly transmitted from the second scanning fan-out sub-line to the first scanning signal sub-line, in this embodiment of the application, a signal adapter cable is also provided, and a sixth through-hole is provided in the aforementioned first insulating layer and a seventh through-hole is provided in the aforementioned second insulating layer. That is, the first insulating layer between the second conductive layer and the first conductive layer and the second insulating layer between the third conductive layer and the second conductive layer are etched away, so that the second end of the second scanning fan-out sub-line is connected to the first end of the first scanning signal sub-line through the signal adapter cable.

[0212] From the perspective of the direction of the horizontal scanning signal, the horizontal scanning signal is provided to the signal adapter after passing through the second scanning fan-out sub-line, and then to the first scanning signal sub-line.

[0213] The second end of the second scan fan-out sub-line is connected to the first end of the signal adapter line through the eighth via penetrating the first insulating layer, and the second end of the signal adapter line is connected to the first end of the first type of first scan signal sub-line through the ninth via penetrating the second insulating layer.

[0214] See Figure 25 As shown, in order to enable the second scanning fan-out sub-line to be electrically connected to the first type of first scanning signal sub-line without passing through the aforementioned second via, that is, to enable the row scanning signal to be smoothly transmitted from the second scanning fan-out sub-line to the first type of first scanning signal sub-line, in this embodiment of the application, a signal adapter is also provided, and an eighth through-hole is provided in the aforementioned first insulating layer and a ninth through-hole is provided in the aforementioned second insulating layer. That is, the first insulating layer between the second conductive layer and the first conductive layer and the second insulating layer between the third conductive layer and the second conductive layer are etched away, so that the second end of the second scanning fan-out sub-line is connected to the first end of the first type of first scanning signal sub-line through the signal adapter.

[0215] From the perspective of the direction of the horizontal scanning signal, the horizontal scanning signal is provided to the signal adapter after passing through the second scanning fan-out sub-line, and then provided to the first type of first scanning signal sub-line.

[0216] In addition, the thickness of the second insulating layer is between 2.5 micrometers and 4 micrometers, and the thickness of the third insulating layer is between 3 micrometers and 4 micrometers.

[0217] In this embodiment, the capacitive coupling effect between the connecting lines is reduced by increasing the thickness of the insulation layer. In practice, the thickness of the second insulation layer (exemplarily, PLN1) is between 2.5 micrometers and 4 micrometers, and the thickness of the third insulation layer (exemplarily, PLN2) is between 3 micrometers and 4 micrometers.

[0218] It should also be noted that, during implementation, in addition to increasing the thickness of the second and third insulating layers, the thickness of the first insulating layer and other insulating layers in the film structure can be increased according to the actual application scenario, thereby reducing the capacitive coupling effect between adjacent conductive layers. This will not be elaborated on here.

[0219] Based on the same inventive concept, this disclosure provides a display device including the display panel of any of the above.

[0220] The aforementioned display device includes: multiple display panels;

[0221] Multiple display panels are sequentially spliced ​​along a first direction; and / or

[0222] The two rows of display panels are symmetrically spliced ​​along the axis of symmetry in the second direction, wherein the axis of symmetry extends along the opposite side of the fan-out area away from the edge of the display area.

[0223] See Figure 27 As shown, in one splicing method, the aforementioned display panels can be sequentially spliced ​​along a first direction (exemplarily, the horizontal direction), that is, multiple Mini / Micro LED display panels are spliced ​​together horizontally to form a larger display panel. In this splicing method, it can be understood that the number of rows of display panels in the horizontal direction is one row.

[0224] See Figure 28 As shown, in another splicing method, the display panel has two rows in the horizontal direction. It should be noted that the display panel here only includes one fan-out area. For example, see [link to relevant documentation]. Figure 28 As shown, the display panel in the first row includes a fan-out area 1 and a display area 1. The fan-out area 1 is located above the display panel, that is, the gate driving circuit is located above the display panel. The display panel in the second row includes a fan-out area 2 and a display area 2. The fan-out area 2 is located below the display panel, that is, the gate driving circuit is located below the display panel.

[0225] During the splicing process, the two rows of display panels are symmetrically spliced ​​along the axis of symmetry in the second direction (exemplarily, the vertical direction). It should be noted that the axis of symmetry extends along the edge of the opposite side of the fan-out area, away from the edge of the display area. The opposite side of the fan-out area is... Figure 28The lower half of the first row of the display panel, or the area opposite the aforementioned fan-out area, is... Figure 28 The upper half of the second row of the display panel, and the edge of the opposite area furthest from the display area, is the lower edge of the display panel, i.e., the axis of symmetry is... Figure 28 The ray with the arrow in the middle is shown.

[0226] In this embodiment of the invention, the display device can be any product or component with a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. Other essential components of the display device are understood by those skilled in the art and will not be described in detail here, nor should they be construed as limiting the invention.

[0227] In summary, the present disclosure provides a display panel and display device. The display panel includes a display area and a fan-out area. The display area includes multiple gate lines extending along a first direction and arranged along a second direction. The fan-out area is located on at least one side of the multiple gate lines in the first direction. The fan-out area includes a gate driving circuit connected to the multiple gate lines. Compared with the scheme of placing the gate driving circuit on the left and right sides of the display panel, the above-mentioned scheme of placing the gate driving circuit in the fan-out area located on at least one side in the first direction allows the display panel to achieve seamless splicing. Especially when the resolution of the display panel is high, the gate driving circuit cannot be placed in the display area due to space limitations. The above-mentioned method of placing the gate driving circuit in the fan-out area enables high-resolution display panels to achieve seamless splicing.

[0228] Those skilled in the art will understand that embodiments of this disclosure can be provided as methods, systems, or computer program product systems. Therefore, this disclosure can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this disclosure can take the form of a computer program product system implemented on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0229] This disclosure is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program product systems according to this disclosure. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations. Figure 1One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0230] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0231] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0232] Obviously, those skilled in the art can make various modifications and variations to this disclosure without departing from its spirit and scope. Therefore, if such modifications and variations fall within the scope of the claims of this disclosure and their equivalents, this disclosure is also intended to include such modifications and variations.

Claims

1. A display panel, wherein, include: Display area and fan-out area; The display area includes: a plurality of grid lines extending along a first direction and arranged along a second direction; the fan-out area is located on at least one side of the plurality of grid lines in the first direction; The fan-out region includes a gate driving circuit, which is connected to the plurality of gate lines.

2. The display panel as claimed in claim 1, wherein, The fan-out area also includes: multiple scanning fan-out lines; The scanning fan-out line is electrically connected between the gate driving circuit and the gate line; Multiple scanning fan-out lines extend along the second direction and are arranged along the first direction.

3. The display panel as described in claim 2, wherein, The display area also includes: multiple scanning signal lines; The scanning signal line is electrically connected between the scanning fan-out line and the gate line, wherein the scanning signal line and the scanning fan-out line are connected in a one-to-one correspondence.

4. The display panel as claimed in claim 3, wherein, Multiple scan signal lines extend along the second direction and are arranged along the first direction.

5. The display panel as claimed in claim 3, wherein, The fan-out area also includes: multiple signal adapter cables; The signal adapter cable is electrically connected between the scanning fan-out line and the scanning signal line, wherein the signal adapter cable, the scanning signal line, and the scanning fan-out line are connected in a one-to-one correspondence.

6. The display panel as claimed in claim 3, wherein, Each of the aforementioned scan signal lines includes a first scan signal sub-line and a second scan signal sub-line that are connected to each other; The first scan signal sub-line is connected to the scan fan-out line, and the first scan signal sub-line extends along the second direction and is arranged along the first direction; The second scan signal sub-line is connected to the gate line, and the second scan signal sub-line extends along the first direction and is arranged along the second direction.

7. The display panel as claimed in claim 6, wherein, The scanning fan-out line includes a first scanning fan-out sub-line and a second scanning fan-out sub-line that are connected to each other; The first scan fan-out sub-line is connected to the drive output terminal of the gate drive circuit. Each of the first scan fan-out sub-lines is arranged along the first direction, and the length of each of the first scan fan-out sub-lines gradually increases from the drive output terminal to both ends of the fan-out area. The second scanning fan-out sub-line is connected to the scanning signal line, and each of the second scanning fan-out sub-lines extends along the second direction and is arranged along the first direction.

8. The display panel as claimed in claim 7, wherein, The fan-out area further includes: a plurality of compensation resistors, each of the compensation resistors being electrically connected between the drive output terminal and the first scanning fan-out sub-line; The resistance value of each of the compensation resistors gradually decreases from the drive output terminal to the two ends of the fan-out region.

9. The display panel as claimed in claim 3, wherein, The gate driving circuit includes: a first gate driving circuit and a second gate driving circuit. The first row scan signal generated by the first gate driving circuit is provided to the scan signal line located in the odd-numbered rows of the display area via the scan fan-out line; The second row scan signal generated by the second gate driving circuit is provided to the scan signal line located in the even-numbered rows of the display area via the scan fan-out line.

10. The display panel as claimed in claim 2, wherein, The gate driving circuit includes: a third gate driving circuit and a fourth gate driving circuit; The third row scanning signal generated by the third gate driving circuit is provided to a portion of the pixel units located in any row of the display area via the scanning fan-out line. The fourth row scan signal generated by the fourth gate driving circuit is provided to the pixel units located in the remaining part of any row of the display area via the scan fan-out line.

11. The display panel as claimed in claim 3, wherein, The display area also includes: multiple data cables; The multiple data lines and the multiple scan signal lines are arranged alternately along the first direction.

12. The display panel as claimed in claim 7, wherein, Also includes: A first conductive layer is located on a substrate, and the first conductive layer includes multiple second scan fan-out sub-lines and multiple second scan signal sub-lines; The first insulating layer is located on the side of the first conductive layer that is away from the substrate. The second conductive layer is located on the side of the first insulating layer away from the substrate. The second conductive layer includes multiple first scan fan-out sub-lines and multiple signal conversion lines.

13. The display panel as claimed in claim 12, wherein, Also includes: The second insulating layer is located on the side of the second conductive layer that is away from the substrate. The third conductive layer is located on the side of the second insulating layer away from the substrate, and the third conductive layer includes multiple first scan signal sub-lines; The third insulating layer is located on the side of the third conductive layer that is away from the substrate. The fourth conductive layer, located on the side of the third insulating layer opposite to the substrate, includes multiple power lines.

14. The display panel as claimed in claim 13, wherein, The first scan signal sub-line includes: a first type of first scan signal sub-line and a second type of first scan signal sub-line; The third conductive layer includes multiple first-type first scan signal sub-lines; The second conductive layer includes multiple second-type first scan signal sub-lines.

15. The display panel as claimed in claim 14, wherein, The first end of the first scanning fan-out sub-line is connected to the first end of the second scanning fan-out sub-line through a first through-hole penetrating the first insulating layer; The second end of the second scanning fan-out sub-line is connected to the first end of the first scanning signal sub-line or the first end of the first type of first scanning signal sub-line through a second via penetrating the first and second insulating layers.

16. The display panel as claimed in claim 14, wherein, The second end of the first scan signal sub-line is connected to the first end of the second scan signal sub-line through a third via penetrating the first and second insulating layers.

17. The display panel as claimed in claim 14, wherein, The second end of the first type of first scan signal sub-line is connected to the first end of the second type of first scan signal sub-line through a fourth via penetrating the second insulating layer; The second end of the second type of first scan signal sub-line passes through the fifth via of the first insulating layer and is connected to the first end of the second scan signal sub-line.

18. The display panel as claimed in claim 14, wherein, The second end of the second scanning fan-out sub-line is connected to the first end of the signal adapter cable through a sixth via penetrating the first insulating layer, and the second end of the signal adapter cable is connected to the first end of the first scanning signal sub-line through a seventh via penetrating the second insulating layer; or The second end of the second scanning fan-out sub-line is connected to the first end of the signal adapter line through an eighth via penetrating the first insulating layer, and the second end of the signal adapter line is connected to the first end of the first type of first scanning signal sub-line through a ninth via penetrating the second insulating layer.

19. The display panel as claimed in claim 13, wherein, The thickness of the second insulating layer is between 2.5 micrometers and 4 micrometers, and the thickness of the third insulating layer is between 3 micrometers and 4 micrometers.

20. A display device, wherein, include: The display panel as described in any one of claims 1 to 19.

21. The display device as claimed in claim 20, wherein, include: Multiple display panels; Multiple display panels are sequentially spliced ​​together along the first direction; and / or The two rows of display panels are symmetrically spliced ​​along an axis of symmetry in the second direction, wherein the axis of symmetry extends along the edge of the opposite region of the fan-out area away from the display area.

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