A multi-device timing distributor

Abstract

The utility model discloses a time sequence distributor of many equipment time sequence technical field, including FPGA module: FPGA module is built -in with ARM, MMCM, IDELAY / ODELAY and IO BAK output module, and MMCM and IDELAY / ODELAY electricity are connected. The utility model discloses through external clock input module receives trigger signal source, and trigger signal source connects IDELAY / ODELAY through the FPGA module inside multiple copies, and IDELAY / ODELAY fine adjustment each channel's delay, ensures that trigger signal reaches time consistent when each channel output, realizes reference clock common source to reach the clock of many instruments of phase -locking or synchronization, and the clock signal and trigger signal of multichannel satisfy the working mode of many equipment synchronization / trigger, and do not depend on the interface number that instrument itself provides, and the use effect is good.

Description

Technical Field

[0001] This utility model relates to the field of timing allocation technology, specifically a multi-device timing distributor. Background Technology

[0002] With the widespread application of high-speed data acquisition and testing equipment, synchronous acquisition between multiple devices has become crucial for ensuring data consistency and analytical accuracy. Signal generators, oscilloscopes, high-speed acquisition cards, and other devices require synchronization when working collaboratively with multiple instruments and channels. For example, in stimulus-response testing, signal generators and oscilloscopes need to operate simultaneously, with a large number of channels synchronously acquiring / transmitting signals. High-end instruments and acquisition cards have Reference In / Out and Trig In / Out interfaces, allowing for easy connection between two devices working collaboratively to form a test system that starts simultaneously and is clock-coordinated.

[0003] The existing multiple devices require a synchronized / triggered working mode, which cannot be achieved by simply providing the interface, sharing the clock, and wiring for triggering on the instrument itself, resulting in poor performance. Utility Model Content

[0004] The purpose of this invention is to provide a multi-device timing distributor to solve the problem that the above-mentioned multiple devices need to work in a synchronized / triggered mode, which cannot be achieved by simply providing an interface, sharing a clock, and wiring for triggering.

[0005] To achieve the above objectives, this utility model provides the following technical solution:

[0006] A multi-device timing distributor includes an FPGA module: the FPGA module has a built-in ARM, MMCM, IDELAY / ODELAY, and IO BAK output module; the MMCM and IDELAY / ODELAY are electrically connected; the IDELAY / ODELAY is electrically connected to the IO BAK output module; the MMCM is electrically connected to a crystal oscillator and an external clock input module; the IDELAY / ODELAY is electrically connected to an external trigger module; the crystal oscillator provides a master reference clock; the external clock input module is used for external clock input; the external trigger module is used for external trigger signal input; the MMCM and IDELAY / ODELAY are electrically connected to a signal buffer drive circuit; the signal buffer drive circuit is used for signal amplification transmission; the ARM is used for system operation; the MMCM generates multiple phase-adjustable clock outputs; the IDELAY / ODELAY controls the phase delay of the clock signal; and the IO BAK output module is used for multi-level output.

[0007] As a further aspect of this invention: the MMCM has a built-in phase-locked loop, and the crystal oscillator generates a sampling clock based on the phase-locked loop.

[0008] As a further aspect of this invention: the crystal oscillator and external clock input module provide a 10MHz reference clock.

[0009] As a further aspect of this invention: the MMCM receives a reference clock from a crystal oscillator or an external clock input module, and the MMCM generates output clocks with different phases.

[0010] As a further aspect of this invention: the MMCM divides one oscillation cycle into 56 phase steps.

[0011] As a further aspect of this utility model: the IO BAK output module outputs several level standards, and these several level standards are used to support different voltage outputs.

[0012] As a further embodiment of this invention, the IO BAK output module further includes a dynamic switching module, which is used for programmable level switching.

[0013] As a further embodiment of this utility model, it also includes a display and input module, which is electrically connected to the ARM and includes a display interface, a touch screen, and / or buttons.

[0014] As a further aspect of this invention: the MMCM and IDELAY / ODELAY are electrically connected to the digital output channel, the digital output channel being used to output an additional clock signal, which serves as an auxiliary signal.

[0015] Compared with the prior art, the beneficial effects of this utility model are:

[0016] 1. In this invention, the clock signal is processed jointly by the MMCM and IDELAY / ODELAY within the FPGA module. The clock signal input is provided by an external clock input module or crystal oscillator. The MMCM generates multiple phase-adjustable MHz clocks to ensure that the multiple output clock signals remain synchronized when received by the receiving device. The trigger signal source is received through the external clock input module. The trigger signal source is replicated multiple times within the FPGA module and then connected to IDELAY / ODELAY. IDELAY / ODELAY finely adjusts the delay of each channel to ensure that the trigger signal is output in the same time on each channel, achieving a common reference clock source. Thus, multiple instruments achieve coherent or synchronous clocks. The multiple clock signals and trigger signals meet the synchronous / triggering working mode of multiple devices, without relying on the number of interfaces provided by the instrument itself, resulting in good performance.

[0017] 2. In this utility model, the modulated clock signal and trigger signal are matched with the receiving device through the IO BAK output module to different level standards, which facilitates integration into different types of test platforms. Then, the clock signal and trigger signal are amplified through the external clock input module to improve the driving capability and ensure stable long-distance transmission. MMCM +IDELAY / ODELAY achieves sub-nanosecond phase adjustment. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the structure of this utility model.

[0019] In the diagram: 1. FPGA module; 2. Crystal oscillator; 3. External clock input module; 4. External trigger module; 5. Signal buffer drive circuit; 6. Display and input module; 7. Digital output channel. Detailed Implementation

[0020] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.

[0021] Example:

[0022] The FPGA module is based on a Zynq XC7Z100 FPGA, employing an architecture that combines its on-chip ARM processor with programmable logic resources. The ARM core controls the programmable logic resources, enabling timing allocation for multiple external devices. The ARM core acts as the main controller, executing parameter configuration, interface control, and human-machine interaction logic. The Zynq chip integrates an ARM Cortex-A9 processor, which can be used to run embedded software. We developed Linux-based control software that can communicate with a Windows-based host computer. The host computer software includes a setup program and a human-machine interface for setting various parameters, including the selection of internal / external clocks / trigger sources, phase delay values, and channel enable states. This user-friendly graphical interface facilitates on-site debugging and maintenance.

[0023] Please see Figure 1In this embodiment of the present invention, a multi-device timing distributor includes an FPGA module 1: the FPGA module 1 has a built-in ARM, MMCM, IDELAY / ODELAY, and IO BAK output module. The MMCM and IDELAY / ODELAY are electrically connected, and IDELAY / ODELAY is electrically connected to the IO BAK output module. The MMCM is electrically connected to a crystal oscillator 2 and an external clock input module 3. IDELAY / ODELAY is electrically connected to an external clock input module 4. The crystal oscillator 2 is used to provide the master reference clock. The external clock input module 3 is used for external clock input. The external clock input module 4 is used for external trigger signal input. The MMCM and IDELAY / ODELAY are electrically connected to an external clock input module 5. The external clock input module 5 is used for signal enhancement transmission. The ARM is used for system operation. The MMCM is used to generate multiple phase-adjustable clock outputs. IDELAY / ODELAY is used to control the phase delay of the clock signal. The IO BAK output module is used for multi-level output.

[0024] Specifically, MMCM (Mixed-Mode Clock Manager) is used to generate multiple phase-adjustable clock outputs, supporting frequency multiplication, frequency division, and phase adjustment;

[0025] Input: External or internal 10MHz reference clock;

[0026] Output: Up to 7 output clocks with different phases can be generated, and each phase is independently adjustable; Adjustment accuracy: In the Zynq 7 series, the MMCM supports dividing a VCO (voltage-controlled oscillator) cycle into up to 56 phase steps. With a VCO frequency of 1GHz, the single step is about 17.8 ps, which is much less than 1ns, and can meet nanosecond-level phase compensation.

[0027] Output capability: If more channels are needed, multiple MMCMs can be cascaded or combined with a BUFG multi-output distributed structure to achieve clock replication.

[0028] IDELAY / ODELAY refers to input delay / output delay. IDELAY / ODELAY precisely controls the phase delay of each trigger / clock signal to achieve compensation.

[0029] Specifically, the MMCM and IDELAY / ODELAY within FPGA module 1 jointly process the clock signal. The external clock input module 3 or crystal oscillator 2 provides the clock signal input. The MMCM generates multiple 10MHz clocks with adjustable phases. This compensates for delays caused by transmission lines and actively adds phase delays to ensure synchronization of the multiple output clock signals when received by the receiving device. For more channels, multiple MMCMs can be cascaded or a BUFG multi-output distributed structure can be used to achieve clock replication. The external clock input module 4 receives the trigger signal source. The trigger signal source is replicated multiple times within FPGA module 1 and then connected to IDELAY / ODELAY. IDELAY / ODELAY finely adjusts the delay of each channel to ensure that the trigger signal is time-consistent when outputting from each channel, achieving a common reference clock source. This allows multiple instruments to achieve coherent or synchronous clocks. Programmable delay compensation is performed on each trigger signal, with an accuracy of tens of picoseconds. The modulated clock signal and trigger signal are then processed through I / O. The BAK output module is matched with the receiving device for different level standards, which facilitates integration into different types of test platforms. Then, the clock signal and trigger signal are amplified by the external clock input module 5 to improve the driving capability and ensure stable long-distance transmission. The multiple clock signals and trigger signals meet the synchronous / triggering working mode of multiple devices, without relying on the number of interfaces provided by the instrument itself, and the effect is good.

[0030] Furthermore, MMCM + IDELAY / ODELAY achieves sub-nanosecond phase adjustment, meeting synchronization requirements of 1GS / s and above;

[0031] Furthermore, crystal oscillator 2 is a high-precision crystal oscillator with high frequency stability and minimal error, ensuring the accuracy and reliability of the clock signal. In the FPGA system, high-precision crystal oscillator 2 serves as the clock source, providing a stable time reference for the entire system. By processing the clock signal output from crystal oscillator 2 through the MMCM, multiple phase-adjustable clocks that meet various requirements can be generated, further improving the system's performance and flexibility.

[0032] Furthermore, the trigger signal source can be an external input or a device trigger. The single-step delay is approximately 78 ps (typical value for the 7 series), supporting up to 32 steps, with a maximum delay of approximately 2.5 ns. The trigger signal can be input from within or outside the FPGA module 1. After being internally copied, it is connected to multiple ODELAY units. The delay tap number for each channel is set through the configuration register. By finely adjusting the delay of each channel, the timing of the trigger signal output on each channel is ensured to be consistent.

[0033] Preferred, such as Figure 1 As shown, the MMCM has a built-in phase-locked loop, and the crystal oscillator 2 generates a sampling clock based on the phase-locked loop.

[0034] Specifically, the internal crystal oscillator 2 generates a sampling clock via a phase-locked loop or an external input sampling clock (suitable for low-speed acquisition scenarios). When there is no external clock input or it is used as a backup, the high-precision crystal oscillator 2 on the FPGA board generates the required sampling clock through the internal PLL (phase-locked loop) of the FPGA. Similar to the 10MHz clock processing process, multi-channel phase adjustment is implemented by the MMCM.

[0035] Preferred, such as Figure 1 As shown, crystal oscillator 2 and external clock input module 3 provide a 10MHz reference clock.

[0036] Specifically, the device can flexibly choose whether to use the clock generated by the internal crystal oscillator 2 or the external input clock, which improves the adaptability and flexibility of the system. The 10MHz reference clock, after precise PLL processing, can meet the high requirements of high-speed data acquisition for clock stability and accuracy.

[0037] Preferred, such as Figure 1 As shown, the MMCM receives the reference clock from the crystal oscillator 2 or the external clock input module 3, and generates output clocks with different phases, each of which is independently adjustable.

[0038] Preferred, such as Figure 1 As shown, MMCM divides an oscillation period into several phase steps.

[0039] Specifically, MMCM supports dividing a VCO (voltage-controlled oscillator) cycle into up to 56 phase steps. With a VCO frequency of 1 GHz, a single step is approximately 17.8 ps, which is much smaller than 1 ns, thus meeting nanosecond-level phase compensation requirements.

[0040] Preferred, such as Figure 1 As shown, the IO BAK output module outputs several voltage levels, which are used to support different voltage outputs.

[0041] Specifically, the IO BAK output module supports multiple voltage levels (1.8V, 2.5V, 3.3V, 5.0V, etc.) to achieve direct voltage level matching. However, in some cases, to ensure signal power and quality, an external clock input module 5 is connected to the output of FPGA module 1 to improve signal driving capability, integrity, and anti-interference capability.

[0042] Preferred, such as Figure 1 As shown, the IO BAK output module also includes a dynamic switching module, which is used for programmable level switching. If dynamic switching is required, it needs to be combined with an external level converter (such as a programmable level conversion chip or a multi-input MUX solution).

[0043] Specifically, through the dynamic switching module, the system can flexibly adjust the output level according to different application requirements or working scenarios without manually replacing hardware or redesigning circuits, greatly improving the system's flexibility and adaptability. The introduction of external level converters, such as programmable level conversion chips or multi-input MUX solutions, further enhances the diversity and accuracy of level switching, enabling the IO BAK output module to meet more complex and varied signal transmission requirements.

[0044] Preferred, such as Figure 1 As shown, it also includes an external clock input module 6, which is electrically connected to the ARM. The external clock input module 6 includes a display interface, a touch screen, and / or buttons.

[0045] Specifically, the design of the external clock input module 6 allows users to intuitively monitor and operate the system status. The display interface provides a clear information display, enabling users to quickly understand the current working status of the system. The addition of a touch screen not only improves the convenience of user interaction but also makes the operation more intuitive and flexible. The presence of buttons provides users with another operation option. The electrical connection between the external clock input module 6 and the ARM ensures efficient data transmission and processing, providing users with a stable and reliable monitoring and operation platform.

[0046] Preferred, such as Figure 1 As shown, MMCM and IDELAY / ODELAY are electrically connected to the external clock input module 7, which is used to output an additional clock signal as an auxiliary signal.

[0047] Specifically, MMCM and IDELAY / ODELAY output additional clock signals through external clock input module 7, which are used as auxiliary signals in multi-instrument synchronous operation.

[0048] The above description is only a preferred embodiment of the present utility model, but the protection scope of the present utility model is not limited thereto. Any equivalent substitutions or changes made by those skilled in the art within the technical scope disclosed in the present utility model, based on the technical solution and the inventive concept of the present utility model, should be included within the protection scope of the present utility model.

Claims

1. A multi-device timing distributor, characterized in that, The system includes an FPGA module: the FPGA module has a built-in ARM, MMCM, IDELAY / ODELAY, and IO BAK output module. The MMCM and IDELAY / ODELAY are electrically connected, and the IDELAY / ODELAY is electrically connected to the IO BAK output module. The MMCM is electrically connected to a crystal oscillator and an external clock input module. The IDELAY / ODELAY is electrically connected to an external trigger module. The crystal oscillator is used to provide the master reference clock. The external clock input module is used for external clock input. The external trigger module is used for external trigger signal input. The MMCM and IDELAY / ODELAY are electrically connected to a signal buffer drive circuit. The signal buffer drive circuit is used for signal amplification transmission. The ARM is used for system operation. The MMCM is used to generate multiple phase-adjustable clock outputs. The IDELAY / ODELAY is used to control the phase delay of the clock signal. The IO BAK output module is used for multi-level output.

2. The multi-device timing distributor according to claim 1, characterized in that: The MMCM has a built-in phase-locked loop, and the crystal oscillator generates a sampling clock based on the phase-locked loop.

3. The multi-device timing distributor according to claim 2, characterized in that: The crystal oscillator and external clock input module provide a 10MHz reference clock.

4. The multi-device timing distributor according to claim 3, characterized in that: The MMCM receives a reference clock from a crystal oscillator or an external clock input module, and generates output clocks with different phases.

5. The multi-device timing distributor according to claim 4, characterized in that: The MMCM divides one oscillation cycle into 56 phase steps.

6. The multi-device timing distributor according to claim 5, characterized in that: The IO BAK output module outputs several voltage levels, which are used to support different voltage outputs.

7. The multi-device timing distributor according to claim 6, characterized in that: The IO BAK output module also includes a dynamic switching module, which is used for programmable level switching.

8. The multi-device timing distributor according to claim 1, characterized in that: It also includes a display and input module, which is electrically connected to the ARM and includes a display interface, a touch screen and / or buttons.

9. A multi-device timing distributor according to claim 1, characterized in that: The MMCM and IDELAY / ODELAY are electrically connected to the digital output channel, which is used to output an additional clock signal, which serves as an auxiliary signal.

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