Tri-state inverter circuit and bus system

Abstract

The application provides a tri-state inverter circuit and a bus system, and belongs to the technical field of electronic circuits. The first control end of a transmission gate and the first end of a logic module are used for connecting a power supply voltage, the input end of the transmission gate and the second end of the logic module are used for connecting a control signal, and the output end of the transmission gate is connected with the third end of the logic module. The fourth end of the logic module is used for connecting an input logic level. The transmission gate is used for being turned on when the control signal is a high level, and inputting a high level to the logic module. The logic module outputs a target level under the action of the high level, the control signal and the input logic level, and the target level is opposite to the input logic level. The transmission gate is also used for being turned off when the control signal is a low level, and the logic module is suspended under the action of the control signal and the input logic level. The application can reduce the dynamic power consumption of the tri-state logic gate, and further improve the circuit performance of the tri-state logic gate.

Description

Technical Field

[0001] This application relates to the field of electronic circuit technology, and more specifically, to a three-state inverter circuit and a bus system. Background Technology

[0002] A tri-state logic gate is a digital logic gate with three output states. Due to its flexibility, resource sharing, and reduced signal interference, tri-state logic gates are widely used in bus systems, multiplexers, and digital circuit design. A tri-state logic gate only requires one logic gate to drive a node to a strong logic state; other logic gates associated with it will not cause the node to become floating, and the level toggling of other logic gates will not affect the logic output of the tri-state logic gate. However, the level toggling of other logic gates generates dynamic power consumption, which will seriously affect the reliability and stability of the tri-state logic gate circuit characteristics. Therefore, there is an urgent need for a tri-state logic gate with reduced power consumption.

[0003] In related technologies, tri-state logic gates are often implemented by combining logic gates and transmission gates. By connecting a transmission gate to the output of the logic gate, the transmission gate is turned on by a control signal applied to the control terminal of the transmission gate, and then the non-tri-state output of the logic gate is transmitted to the tri-state output node.

[0004] However, in tri-state logic gates based on related technologies, when the transmission gate is turned off under the action of a low-level control signal, the circuit is in tri-state mode. The switching of the input and output levels of the logic gate generates dynamic power consumption, which in turn leads to a decrease in the stability and reliability of the circuit. Therefore, the related technology solutions suffer from poor stability and reliability. Utility Model Content

[0005] The purpose of this application is to provide a tri-state inverter circuit and a bus system that can reduce the dynamic power consumption of tri-state logic gates and thus improve the circuit performance of tri-state logic gates.

[0006] The embodiments of this application are implemented as follows:

[0007] A first aspect of this application provides a tri-state inverter circuit, which includes: a transmission gate and a logic module;

[0008] The first control terminal of the transmission gate and the first terminal of the logic module are both used to connect to the power supply voltage. The input terminal of the transmission gate and the second terminal of the logic module are both used to connect to the control signal. The output terminal of the transmission gate is connected to the third terminal of the logic module.

[0009] The fourth terminal of the logic module is used to input the logic level. The fifth terminal of the logic module and the second control terminal of the transmission gate are both grounded. The sixth terminal of the logic module serves as the output terminal of the tri-state inverter circuit.

[0010] The transmission gate is used to turn on when the control signal is high and input a high level to the logic module. Under the action of the high level, the control signal and the input logic level, the logic module outputs the target level, which is out of phase with the input logic level.

[0011] The transmission gate is also used to cut off when the control signal is low, and the logic module is left floating under the influence of the control signal and the input logic level.

[0012] As one possible implementation, the logic module includes: a first logic gate and a second logic gate;

[0013] Both the first control terminal and the second control terminal of the first logic gate are used to connect to the input logic level. The first input terminal of the first logic gate is used to connect to the power supply voltage. The first output terminal of the first logic gate is connected to the first input terminal of the second logic gate. The second output terminal of the first logic gate is connected to the second input terminal of the second logic gate. The second input terminal of the first logic gate is grounded.

[0014] The first control terminal of the second logic gate is used to receive the control signal, the second control terminal of the second logic gate is connected to the output terminal of the transmission gate, and the output terminal of the second logic gate serves as the output terminal of the tri-state inverter circuit.

[0015] As one possible implementation, the first logic gate includes: a first conducting component and a second conducting component;

[0016] The control terminals of both the first and second conduction components are used to connect to the input logic level. The input terminal of the first conduction component is used to connect to the power supply voltage, and the output terminal of the first conduction component is connected to the first input terminal of the second logic gate.

[0017] The output of the second conducting component is connected to the second input of the second logic gate, and the input of the second conducting component is grounded.

[0018] As one possible implementation, the first conducting component includes: a first P-type metal-oxide-semiconductor transistor;

[0019] The gate of the first P-type metal-oxide-semiconductor transistor is used to connect to the input logic level, the source of the first P-type metal-oxide-semiconductor transistor is used to connect to the power supply voltage, and the drain of the first P-type metal-oxide-semiconductor transistor is connected to the first input terminal of the second logic gate.

[0020] As one possible implementation, the second conducting component includes: a first N-type metal-oxide-semiconductor transistor;

[0021] The gate of the first N-type metal-oxide-semiconductor transistor is used to input logic level, the drain of the first N-type metal-oxide-semiconductor transistor is connected to the second input terminal of the second logic gate, and the source of the first N-type metal-oxide-semiconductor transistor is grounded.

[0022] As one possible implementation, the second logic gate includes: a third conducting component and a fourth conducting component;

[0023] The control terminal of the third conducting component is connected to the output terminal of the transmission gate, the input terminal of the third conducting component is connected to the output terminal of the first conducting component, and the output terminal of the third conducting component is connected to the output terminal of the fourth conducting component, and serves as the output terminal of the three-state inverter circuit.

[0024] The control terminal of the fourth conduction component is used to receive control signals, and the input terminal of the fourth conduction component is connected to the output terminal of the second conduction component.

[0025] As one possible implementation, the third conducting component includes: a second P-type metal-oxide-semiconductor transistor;

[0026] The gate of the second P-type metal-oxide-semiconductor transistor is connected to the output terminal of the transmission gate, the source of the second P-type metal-oxide-semiconductor transistor is connected to the output terminal of the first conduction component, and the drain of the second P-type metal-oxide-semiconductor transistor is connected to the output terminal of the fourth conduction component.

[0027] As one possible implementation, the fourth conducting component includes: a second N-type metal-oxide-semiconductor transistor;

[0028] The gate of the second N-type metal-oxide-semiconductor transistor is used to receive the control signal. The drain of the second N-type metal-oxide-semiconductor transistor is connected to the drain of the second P-type metal-oxide-semiconductor transistor. The source of the second N-type metal-oxide-semiconductor transistor is connected to the output terminal of the second conduction component.

[0029] As one possible implementation, the transmission gate includes: a third P-type metal-oxide-semiconductor transistor and a third N-type metal-oxide-semiconductor transistor;

[0030] The source of the third P-type metal-oxide-semiconductor transistor is connected to the source of the third N-type metal-oxide-semiconductor transistor. Both the source of the third P-type metal-oxide-semiconductor transistor and the source of the third N-type metal-oxide-semiconductor transistor are used to receive control signals. The gate of the third P-type metal-oxide-semiconductor transistor is used to receive the power supply voltage. The gate of the third N-type metal-oxide-semiconductor transistor is grounded. Both the drain of the third P-type metal-oxide-semiconductor transistor and the drain of the third N-type metal-oxide-semiconductor transistor are connected to the second control terminal of the second logic gate.

[0031] A second aspect of this application provides a bus system that includes the tri-state inverter circuit described in the first aspect above.

[0032] The beneficial effects of the embodiments of this application include:

[0033] This application provides a three-state inverter circuit, which is constructed using a transmission gate and a logic module to enable the inverter to operate in three states. The first control terminal of the transmission gate and the first terminal of the logic module are both connected to a power supply voltage. The input terminal of the transmission gate and the second terminal of the logic module are both connected to a control signal. The output terminal of the transmission gate is connected to the third terminal of the logic module. The fourth terminal of the logic module is connected to an input logic level. The fifth terminal of the logic module and the second control terminal of the transmission gate are both grounded. The sixth terminal of the logic module serves as the output terminal of the three-state inverter circuit. When the control signal received by the transmission gate is high, the transmission gate conducts and sends a high-level signal to the third terminal of the logic module. Under the combined action of the output signal of the transmission gate, the control signal, and the input logic level, the logic module outputs a target level that is opposite in phase to the input logic level to the subsequent circuit. When the control signal received by the transmission gate is low, the transmission gate is cut off, and the logic module is left floating under the combined action of the control signal and the input logic level, thus the three-state inverter circuit enters three-state mode. Specifically, the transmission gate operates and the tri-state inverter circuit undergoes level switching only when the control signal is high. When the control signal is low, the transmission gate is cut off, and the tri-state inverter circuit no longer performs meaningless level switching, generating unnecessary power consumption. In this way, the dynamic power consumption of the tri-state logic gate can be reduced, thereby improving the circuit performance of the tri-state logic gate. Attached Figure Description

[0034] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0035] Figure 1 This is a schematic diagram of an existing three-state logic gate;

[0036] Figure 2 This is a schematic diagram of the structure of a first type of three-state inverter circuit provided in an embodiment of this application;

[0037] Figure 3 This is a schematic diagram of the structure of a second type of three-state inverter circuit provided in an embodiment of this application;

[0038] Figure 4This is a schematic diagram of the structure of a third type of three-state inverter circuit provided in the embodiments of this application;

[0039] Figure 5 This is a schematic diagram of the structure of the fourth type of three-state inverter circuit provided in the embodiments of this application;

[0040] Figure 6 This is a schematic diagram of the fifth type of three-state inverter circuit provided in the embodiments of this application;

[0041] Figure 7 This is a schematic diagram of a bus system provided in an embodiment of this application.

[0042] Figure descriptions: 10: Tri-state inverter circuit; 101: Transmission gate; 1011: Third P-type metal-oxide-semiconductor transistor; 1012: Third N-type metal-oxide-semiconductor transistor; 102: Logic module; 1021: First logic gate; 211: First conducting component; 2111: First P-type metal-oxide-semiconductor transistor; 212: Second conducting component; 2121: First N-type metal-oxide-semiconductor transistor; 1022: Second logic gate; 221: Third conducting component; 2211: Second P-type metal-oxide-semiconductor transistor; 222: Fourth conducting component; 2221: Second N-type metal-oxide-semiconductor transistor; 20: Bus system. Detailed Implementation

[0043] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0044] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0045] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0046] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the product of the invention is in use. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. In addition, the terms "first," "second," and "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0047] In the description of this application, it should also be noted that, unless otherwise expressly specified and limited, the terms "set up," "install," "connect," and "link" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0048] Currently, tri-state logic gates are often implemented by combining logic gates and transmission gates. A transmission gate is connected to the output of the logic gate, and its on / off state is controlled by a control signal applied to its control terminal. When the transmission gate is on, the non-tri-state output of the logic gate is transmitted to the tri-state output node. However, in this type of tri-state logic gate, when the transmission gate is cut off under a low-level control signal, the circuit is in tri-state mode. The switching between the input and output levels of the logic gate generates dynamic power consumption, which reduces the stability and reliability of the circuit.

[0049] To address this, this application provides a tri-state inverter circuit. The circuit comprises a transmission gate and a logic module, forming a tri-state inverter. The first control terminal of the transmission gate and the first terminal of the logic module are both connected to a power supply voltage. The input terminal of the transmission gate and the first terminal of the logic module are both connected to a control signal. The output terminal of the transmission gate is connected to the third terminal of the logic module. The fourth terminal of the logic module is connected to an input logic level. The fifth terminal of the logic module and the second control terminal of the transmission gate are both grounded. The sixth terminal of the logic module serves as the output terminal of the tri-state inverter circuit. The transmission gate is turned on when the control signal is high, outputting a high-level signal to the logic module. Under the combined action of this high-level signal, the control signal, and the input logic level, the logic module outputs a target level that is inversely phase to the input logic level. The transmission gate is also turned off when the control signal is low, leaving the logic module floating under the influence of the control signal and the input logic level, thus placing the tri-state inverter circuit in a high-impedance state. This reduces the dynamic power consumption of the tri-state logic gate, thereby improving its circuit performance.

[0050] Figure 1 Here is a schematic diagram of an existing three-state logic gate. (See attached diagram) Figure 1 Existing tri-state logic gates consist of logic gates and transmission gates. The logic gates function as inverters, with their control terminals receiving the input logic level and their input terminals receiving the power supply voltage. The output of the logic gate is connected to a transmission gate, whose two control terminals are inverted. When the transmission gate is turned on by the control signal, it can transmit the non-tri-state output of the logic gate to the tri-state transmission node. Conversely, when the transmission gate is turned off by the control signal, the circuit is in tri-state mode. The level switching between the input and output logic levels generates dynamic power consumption. However, changes in the input logic level do not affect the circuit's logical result. Therefore, this dynamic power consumption is not beneficial to the circuit and can even degrade its stability.

[0051] The following description, in conjunction with the accompanying drawings, provides a detailed explanation of the tri-state inverter circuit and bus system provided in the embodiments of this application.

[0052] Figure 2 A schematic diagram of a three-state inverter circuit provided in this application is shown below. Figure 2 This application provides a three-state inverter circuit 10, which includes a transmission gate 101 and a logic module 102.

[0053] Optionally, the transmission gate 101 is a logic gate composed of N-type metal-oxide-semiconductor transistors and P-type metal-oxide-semiconductor transistors connected in parallel. The source of the N-type metal-oxide-semiconductor transistor in the transmission gate 101 is connected to the source of the P-type metal-oxide-semiconductor transistor, and the drain of the N-type metal-oxide-semiconductor transistor in the transmission gate 101 is connected to the drain of the P-type metal-oxide-semiconductor transistor. Based on the complementary characteristics of the N-type metal-oxide-semiconductor transistor and the P-type metal-oxide-semiconductor transistor, the transmission gate 101 can provide a low-impedance path across the entire signal voltage range, thereby reducing the power consumption of the tri-state inverter circuit 10.

[0054] The first control terminal of the transmission gate 101 and the first terminal of the logic module 102 are both used to connect to the power supply voltage. The input terminal of the transmission gate 101 and the second terminal of the logic module 102 are both used to connect to the control signal. The output terminal of the transmission gate 101 is connected to the third terminal of the logic module 102.

[0055] Optionally, the control signal is a high or low level signal. The control signal is used to control the on / off state of the transmission gate 101 and the on / off state of the second terminal of the logic module 102. For example, the control signal can be a high level 1 or a low level 0. The power supply voltage is provided by an external power supply. The power supply voltage can be 5V, 10V, etc., and this application does not make specific limitations on it.

[0056] Optionally, the tri-state inverter circuit 10 refers to the internal circuitry of a tri-state inverter. Essentially, the tri-state inverter circuit 10 is an inverter that can operate in three states: high level, low level, and high impedance. The transmission gate 101 is turned on or off by a control signal, which can be considered the enable signal for the tri-state inverter circuit 10. It's worth noting that when the output state of the tri-state inverter circuit 10 is high impedance, the output is effectively disconnected. In this state, the tri-state inverter circuit 10 outputs neither a high nor a low level signal, and the high impedance state has no effect on subsequent circuits.

[0057] Optionally, the input terminal of transmission gate 101 is used to receive control signals, the first control terminal of transmission gate 101 is used to receive power supply voltage, the second control terminal of transmission gate 101 is grounded, and the output terminal of transmission gate 101 is connected to the third terminal of logic module 102. Transmission gate 101 is considered to be embedded in the inverter, and transmission gate 101 can reduce the power consumption of the inverter.

[0058] The fourth terminal of logic module 102 is used to input the logic level. The fifth terminal of logic module 102 and the second control terminal of transmission gate 101 are both grounded. The sixth terminal of logic module 102 serves as the output terminal of tri-state inverter circuit 10.

[0059] Optionally, the input logic level refers to the input level signal of the tri-state inverter circuit 10. The input logic level can be a high level (1) or a low level (0). The input logic level is unrelated to the control signal. The input logic level can be the same as the control signal or the opposite of the control signal. This application does not make any specific limitations on this.

[0060] The transmission gate 101 is turned on when the control signal is high and inputs a high level to the logic module 102. Under the action of the high level, the control signal and the input logic level, the logic module 102 outputs a target level, which is inversely phase with the input logic level.

[0061] Optionally, when the control signal is high level 1, transmission gate 101 is turned on, and transmission gate 101 outputs a high-level signal to the third terminal of logic module 102. If the input logic level is also high level 1, the target level output by logic module 102 is low level 0; conversely, if the input logic level is low level 0, the target level output by logic module 102 is high level 1. It is worth noting that the target level refers to the actual output level signal of the tri-state inverter circuit 10. The target level is out of phase with the input logic level received at the input terminal of the tri-state inverter circuit 10, that is, the tri-state inverter circuit 10 can achieve phase flipping through transmission gate 101 and logic module 102.

[0062] The transmission gate 101 is also used to cut off when the control signal is low, and the logic module 102 is left floating under the influence of the control signal and the input logic level.

[0063] Optionally, when the control signal is low level 0, the transmission gate 101 is turned off. At this time, the output state of the transmission gate 101 is a high impedance state, that is, there is no signal transmission between the output terminal of the transmission gate 101 and the third terminal of the logic module 102. Regardless of whether the input logic level is high level 1 or low level 0, the source of the transistor in the tri-state inverter circuit 10 is floating, and the output state of the tri-state inverter circuit 10 is in a high impedance state, that is, the tri-state inverter circuit 10 neither outputs high level 1 nor low level 0.

[0064] In this embodiment, a tri-state inverter circuit is constructed using a transmission gate and a logic module to enable the inverter to operate in tri-state mode. The first control terminal of the transmission gate and the first terminal of the logic module are both connected to a power supply voltage. The input terminal of the transmission gate and the second terminal of the logic module are both connected to a control signal. The output terminal of the transmission gate is connected to the third terminal of the logic module. The fourth terminal of the logic module is connected to an input logic level. The fifth terminal of the logic module and the second control terminal of the transmission gate are both grounded. The sixth terminal of the logic module serves as the output terminal of the tri-state inverter circuit. When the control signal received by the transmission gate is high, the transmission gate conducts and sends a high-level signal to the third terminal of the logic module. Under the combined action of the output signal of the transmission gate, the control signal, and the input logic level, the logic module outputs a target level that is opposite in phase to the input logic level to the subsequent circuit. When the control signal received by the transmission gate is low, the transmission gate is turned off, and the logic module is left floating under the combined action of the control signal and the input logic level, thus the tri-state inverter circuit enters tri-state mode. Specifically, the transmission gate operates and the tri-state inverter circuit undergoes level switching only when the control signal is high. When the control signal is low, the transmission gate is cut off, and the tri-state inverter circuit no longer performs meaningless level switching, generating unnecessary power consumption. In this way, the dynamic power consumption of the tri-state logic gate can be reduced, thereby improving the circuit performance of the tri-state logic gate.

[0065] In one alternative implementation, see [link to implementation details]. Figure 3 The logic module 102 in the tri-state inverter circuit 10 provided in this application embodiment includes: a first logic gate 1021 and a second logic gate 1022.

[0066] Both the first control terminal and the second control terminal of the first logic gate 1021 are used to connect to the input logic level. The first input terminal of the first logic gate 1021 is used to connect to the power supply voltage. The first output terminal of the first logic gate 1021 is connected to the first input terminal of the second logic gate 1022. The second output terminal of the first logic gate 1021 is connected to the second input terminal of the second logic gate 1022. The second input terminal of the first logic gate 1021 is grounded.

[0067] The first control terminal of the second logic gate 1022 is used to receive control signals. The second control terminal of the second logic gate 1022 is connected to the output terminal of the transmission gate 101. The output terminal of the second logic gate 1022 serves as the output terminal of the tri-state inverter circuit 10.

[0068] Optionally, the first logic gate 1021 is used to turn on or off under the control of the input logic level, and the second logic gate 1022 is used to turn on or off under the combined action of the output signal of the transmission gate 101 and the control signal. The output signal of the second logic gate 1022 serves as the output signal of the entire tri-state inverter circuit 10.

[0069] In one alternative implementation, see [link to implementation details]. Figure 4 The first logic gate 1021 in the tri-state inverter circuit 10 provided in this application embodiment includes: a first conduction component 211 and a second conduction component 212.

[0070] The control terminals of the first conducting component 211 and the second conducting component 212 are both used to connect to the input logic level. The input terminal of the first conducting component 211 is used to connect to the power supply voltage. The output terminal of the first conducting component 211 is connected to the first input terminal of the second logic gate 1022.

[0071] The output terminal of the second conducting component 212 is connected to the second input terminal of the second logic gate 1022, and the input terminal of the second conducting component 212 is grounded.

[0072] Optionally, the first conducting component 211 and the second conducting component 212 are composed of conducting components with complementary characteristics. Both the first conducting component 211 and the second conducting component 212 are controlled by the input logic level. When the first conducting component 211 is turned on, the second conducting component 212 is turned off; conversely, when the first conducting component 211 is turned off, the second conducting component 212 is turned on.

[0073] In one alternative implementation, see [link to implementation details]. Figure 5 The first conducting component 211 in the tri-state inverter circuit 10 provided in this application embodiment includes: a first P-type metal-oxide-semiconductor transistor 2111.

[0074] The gate of the first P-type metal-oxide-semiconductor transistor 2111 is used to connect to the input logic level, the source of the first P-type metal-oxide-semiconductor transistor 2111 is used to connect to the power supply voltage, and the drain of the first P-type metal-oxide-semiconductor transistor 2111 is connected to the first input terminal of the second logic gate 1022.

[0075] In one alternative implementation, see [link to implementation details]. Figure 5 The second conducting component 212 in the tri-state inverter circuit 10 provided in this application embodiment includes: a first N-type metal-oxide-semiconductor transistor 2121.

[0076] The gate of the first N-type metal-oxide-semiconductor transistor 2121 is used to connect to the input logic level, the drain of the first N-type metal-oxide-semiconductor transistor 2121 is connected to the second input terminal of the second logic gate 1022, and the source of the first N-type metal-oxide-semiconductor transistor 2121 is grounded.

[0077] Optionally, the first conducting component 211 is implemented by a first P-type metal-oxide-semiconductor transistor 2111, and the second conducting component 212 is implemented by a first N-type metal-oxide-semiconductor transistor 2121. Both the first P-type metal-oxide-semiconductor transistor 2111 and the first N-type metal-oxide-semiconductor transistor 2121 are turned on and off under the action of the input logic level. When the input logic level is high, the first N-type metal-oxide-semiconductor transistor 2121 is turned on, the first P-type metal-oxide-semiconductor transistor 2111 is turned off, the first logic gate 1021 outputs a logic low level, and the logic low level output by the first logic gate 1021 is connected to the second logic gate 1022 via the second input terminal of the second logic gate 1022; conversely, when the input logic level is low, the first P-type metal-oxide-semiconductor transistor 2111 is turned on, the first N-type metal-oxide-semiconductor transistor 2121 is turned off, the first logic gate 1021 outputs a logic high level, and the logic high level output by the first logic gate 1021 is connected to the second logic gate 1022 via the first input terminal of the second logic gate 1022.

[0078] In one alternative implementation, see [link to implementation details]. Figure 4 The second logic gate 1022 in the tri-state inverter circuit 10 provided in this application embodiment includes: a third conduction component 221 and a fourth conduction component 222.

[0079] The control terminal of the third conduction component 221 is connected to the output terminal of the transmission gate 101, the input terminal of the third conduction component 221 is connected to the output terminal of the first conduction component 211, and the output terminal of the third conduction component 221 is connected to the output terminal of the fourth conduction component 222, and serves as the output terminal of the three-state inverter circuit 10.

[0080] The control terminal of the fourth conduction component 222 is used to receive control signals, and the input terminal of the fourth conduction component 222 is connected to the output terminal of the second conduction component 212.

[0081] Optionally, the third conducting component 221 and the fourth conducting component 222 are conducting components with complementary characteristics. The third conducting component 221 is controlled by the output signal of the transmission gate 101, and the fourth conducting component 222 is controlled by the control signal. When the third conducting component 221 is turned on, the fourth conducting component 222 is turned off; conversely, when the third conducting component 221 is turned off, the fourth conducting component 222 is turned on.

[0082] In one alternative implementation, see [link to implementation details]. Figure 5 The third conducting component 221 in the tri-state inverter circuit 10 provided in this application embodiment includes: a second P-type metal-oxide-semiconductor transistor 2211.

[0083] The gate of the second P-type metal-oxide-semiconductor transistor 2211 is connected to the output terminal of the transmission gate 101, the source of the second P-type metal-oxide-semiconductor transistor 2211 is connected to the output terminal of the first conduction component 211, and the drain of the second P-type metal-oxide-semiconductor transistor 2211 is connected to the output terminal of the fourth conduction component 222.

[0084] In one alternative implementation, see [link to implementation details]. Figure 5 The fourth conducting component 222 in the tri-state inverter circuit 10 provided in this application embodiment includes: a second N-type metal-oxide-semiconductor transistor 2221.

[0085] The gate of the second N-type metal-oxide-semiconductor transistor 2221 is used to receive a control signal. The drain of the second N-type metal-oxide-semiconductor transistor 2221 is connected to the drain of the second P-type metal-oxide-semiconductor transistor 2211. The source of the second N-type metal-oxide-semiconductor transistor 2221 is connected to the output terminal of the second conduction component 212.

[0086] Optionally, the third conducting component 221 is implemented by the second P-type metal-oxide-semiconductor transistor 2211, and the fourth conducting component 222 is implemented by the second N-type metal-oxide-semiconductor transistor 2221. The second P-type metal-oxide-semiconductor transistor 2211 is turned on or off under the action of the output signal of the transmission gate 101, and the second N-type metal-oxide-semiconductor transistor 2221 is turned on or off under the action of the control signal. When the control signal is high, transmission gate 101 is turned on, sending a high-level signal to the second P-type metal-oxide-semiconductor transistor 2211. The second P-type metal-oxide-semiconductor transistor 2211 is turned off under the action of the high-level signal output by transmission gate 101, and the second N-type metal-oxide-semiconductor transistor 2221 is turned on under the action of the control signal. If the level signal of the first logic gate 1021 input to the second logic gate 1022 is high, then the target level output by the second logic gate 1022 is a high-level signal; if the level signal of the first logic gate 1021 input to the second logic gate 1022 is low, then the target level output by the second logic gate 1022 is a low-level signal. When the control signal is low, transmission gate 101 is turned off, and the output of transmission gate 101 is in a high-impedance state. The second P-type metal-oxide-semiconductor transistor 2211 cannot receive the output signal of transmission gate 101. The second N-type metal-oxide-semiconductor transistor 2221 is turned off under the action of the control signal, and the second logic gate 1022 enters the high-impedance mode. Regardless of whether the level signal of the input of the first logic gate 1021 to the second logic gate 1022 is high or low, the output of the second logic gate 1022 is in a high-impedance state.

[0087] In one alternative implementation, see [link to implementation details]. Figure 6 The transmission gate 101 in the tri-state inverter circuit 10 provided in this application embodiment includes: a third P-type metal-oxide-semiconductor transistor 1011 and a third N-type metal-oxide-semiconductor transistor 1012.

[0088] The source of the third P-type metal-oxide-semiconductor transistor 1011 is connected to the source of the third N-type metal-oxide-semiconductor transistor 1012. Both the source of the third P-type metal-oxide-semiconductor transistor 1011 and the source of the third N-type metal-oxide-semiconductor transistor 1012 are used to receive control signals. The gate of the third P-type metal-oxide-semiconductor transistor 1011 is used to receive the power supply voltage. The gate of the third N-type metal-oxide-semiconductor transistor 1012 is grounded. Both the drain of the third P-type metal-oxide-semiconductor transistor 1011 and the drain of the third N-type metal-oxide-semiconductor transistor 1012 are connected to the second control terminal of the second logic gate 1022.

[0089] Optionally, the source of the third P-type metal-oxide-semiconductor transistor 1011 and the source of the third N-type metal-oxide-semiconductor transistor 1012 serve as the input terminal of the transmission gate 101, and the control signal enters the transmission gate 101 through the input terminal of the transmission gate 101; the drain of the third P-type metal-oxide-semiconductor transistor 1011 and the drain of the third N-type metal-oxide-semiconductor transistor 1012 serve as the output terminal of the transmission gate 101. When the control signal is high, both the third P-type metal-oxide-semiconductor transistor 1011 and the third N-type metal-oxide-semiconductor transistor 1012 are turned on, and the transmission gate 101 outputs a high level; conversely, when the control signal is low, both the third P-type metal-oxide-semiconductor transistor 1011 and the third N-type metal-oxide-semiconductor transistor 1012 are turned off, the transmission gate 101 is cut off, and the output terminal of the transmission gate 101 is in a high-impedance state, that is, the transmission gate 101 neither outputs a high level nor a low level.

[0090] Figure 7 A schematic diagram of a bus system provided in this application is shown below. Figure 7 The bus system 20 provided in this application embodiment includes the above-mentioned tri-state inverter circuit 10, and its specific implementation is the same as that of the above-mentioned tri-state inverter circuit 10, which will not be described in detail here.

[0091] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

[0092] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A three-state inverter circuit, characterized in that, include: Transmission gates and logic modules; The first control terminal of the transmission gate and the first terminal of the logic module are both used to connect to the power supply voltage. The input terminal of the transmission gate and the second terminal of the logic module are both used to connect to the control signal. The output terminal of the transmission gate is connected to the third terminal of the logic module. The fourth terminal of the logic module is used to input the logic level. The fifth terminal of the logic module and the second control terminal of the transmission gate are both grounded. The sixth terminal of the logic module serves as the output terminal of the tri-state inverter circuit. The transmission gate is used to turn on when the control signal is high and input a high level to the logic module. The logic module outputs a target level under the action of the high level, the control signal and the input logic level. The target level is out of phase with the input logic level. The transmission gate is also used to cut off when the control signal is low, and the logic module is left floating under the influence of the control signal and the input logic level.

2. The three-state inverter circuit according to claim 1, characterized in that, The logic module includes: a first logic gate and a second logic gate; Both the first control terminal and the second control terminal of the first logic gate are used to connect to the input logic level. The first input terminal of the first logic gate is used to connect to the power supply voltage. The first output terminal of the first logic gate is connected to the first input terminal of the second logic gate. The second output terminal of the first logic gate is connected to the second input terminal of the second logic gate. The second input terminal of the first logic gate is grounded. The first control terminal of the second logic gate is used to receive a control signal, the second control terminal of the second logic gate is connected to the output terminal of the transmission gate, and the output terminal of the second logic gate serves as the output terminal of the tri-state inverter circuit.

3. The three-state inverter circuit according to claim 2, characterized in that, The first logic gate includes: a first conducting component and a second conducting component; Both the control terminal of the first conducting component and the control terminal of the second conducting component are used to connect to the input logic level. The input terminal of the first conducting component is used to connect to the power supply voltage. The output terminal of the first conducting component is connected to the first input terminal of the second logic gate. The output terminal of the second conducting component is connected to the second input terminal of the second logic gate, and the input terminal of the second conducting component is grounded.

4. The three-state inverter circuit according to claim 3, characterized in that, The first conducting component includes: a first P-type metal-oxide-semiconductor transistor; The gate of the first P-type metal-oxide-semiconductor transistor is used to connect to the input logic level, the source of the first P-type metal-oxide-semiconductor transistor is used to connect to the power supply voltage, and the drain of the first P-type metal-oxide-semiconductor transistor is connected to the first input terminal of the second logic gate.

5. The three-state inverter circuit according to claim 3, characterized in that, The second conducting component includes: a first N-type metal-oxide-semiconductor transistor; The gate of the first N-type metal-oxide-semiconductor transistor is used to access the input logic level, the drain of the first N-type metal-oxide-semiconductor transistor is connected to the second input terminal of the second logic gate, and the source of the first N-type metal-oxide-semiconductor transistor is grounded.

6. The three-state inverter circuit according to claim 3, characterized in that, The second logic gate includes: a third conduction component and a fourth conduction component; The control terminal of the third conducting component is connected to the output terminal of the transmission gate, the input terminal of the third conducting component is connected to the output terminal of the first conducting component, and the output terminal of the third conducting component is connected to the output terminal of the fourth conducting component, and serves as the output terminal of the three-state inverter circuit. The control terminal of the fourth conducting component is used to receive control signals, and the input terminal of the fourth conducting component is connected to the output terminal of the second conducting component.

7. The three-state inverter circuit according to claim 6, characterized in that, The third conducting component includes: a second P-type metal-oxide-semiconductor transistor; The gate of the second P-type metal-oxide-semiconductor transistor is connected to the output terminal of the transmission gate, the source of the second P-type metal-oxide-semiconductor transistor is connected to the output terminal of the first conduction component, and the drain of the second P-type metal-oxide-semiconductor transistor is connected to the output terminal of the fourth conduction component.

8. The three-state inverter circuit according to claim 7, characterized in that, The fourth conducting component includes: a second N-type metal-oxide-semiconductor transistor; The gate of the second N-type metal-oxide-semiconductor transistor is used to receive a control signal, the drain of the second N-type metal-oxide-semiconductor transistor is connected to the drain of the second P-type metal-oxide-semiconductor transistor, and the source of the second N-type metal-oxide-semiconductor transistor is connected to the output terminal of the second conduction component.

9. The three-state inverter circuit according to claim 2, characterized in that, The transmission gate includes: a third P-type metal-oxide-semiconductor transistor and a third N-type metal-oxide-semiconductor transistor; The source of the third P-type metal-oxide-semiconductor transistor is connected to the source of the third N-type metal-oxide-semiconductor transistor. Both the source of the third P-type metal-oxide-semiconductor transistor and the source of the third N-type metal-oxide-semiconductor transistor are used to receive control signals. The gate of the third P-type metal-oxide-semiconductor transistor is used to receive power supply voltage. The gate of the third N-type metal-oxide-semiconductor transistor is grounded. Both the drain of the third P-type metal-oxide-semiconductor transistor and the drain of the third N-type metal-oxide-semiconductor transistor are connected to the second control terminal of the second logic gate.

10. A bus system, characterized in that, The bus system includes the tri-state inverter circuit as described in any one of claims 1-9.

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