Semiconductor Device and Method

Abstract

Device with: a first group of nanostructures (66) on a substrate (50), wherein the first group of nanostructures (66) has a first channel region; a second group of nanostructures (66) on the substrate (50), wherein the second group of nanostructures has a second channel region; a dielectric gate layer (112) enclosing each of the first and second groups of nanostructures (66); a first work function setting layer (114A) on the dielectric gate layer (112) of the first group of nanostructures (66), wherein the first work function setting layer (114A) surrounds each of the first group of nanostructures (66) and the first work function setting layer (114A) has an n work function metal; an adhesive layer (114B) on the first work function setting layer (114A), wherein the adhesive layer (114B) encloses each of the first group of nanostructures, and the adhesive layer (114B) comprises titanium aluminum carbide, tantalum aluminum carbide or silicon-doped tantalum aluminum carbide; a protective layer (114F) between the first work function setting layer (114A) and the adhesive layer (114B) on the first group of nanostructures (66), wherein the protective layer (114F) surrounds each of the first group of nanostructures (66) and comprises amorphous silicon; wherein the adhesive layer (114B) fills a region between respective parts of the protective layer (114F) on adjacent nanostructures of the first group of nanostructures (66) and thus separates the respective parts of the protective layer (114F) on adjacent nanostructures of the first group of nanostructures (66); a second work function setting layer (114C, 114D) on the adhesive layer (114B) of the first group of nanostructures (66) and on the dielectric gate layer (112) of the second group of nanostructures (66), wherein the second work function setting layer (114C, 114D) has a p-work function metal and the p-work function metal is different from the n-work function metal; and a fill layer (114E) on the second exit work adjustment layer (114C, 114D).

Description

BACKGROUND

[0001] Semiconductor devices are used in various electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by successively depositing insulating or dielectric material layers, conductive material layers, and semiconductor material layers onto a semiconductor substrate. The different material layers are then structured by lithography to create circuit components and elements on the substrate.

[0002] The semiconductor industry is constantly improving the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the smallest feature size, thus enabling the integration of more components in a given area. However, reducing the smallest feature size introduces further problems that need to be addressed.

[0003] US patent 2020 / 0 066 859 A1 discloses complementary transistors and their fabrication, whereby the transistors can also be gate-all-around (GAA) nanosheet or nanowire transistors. One gate comprises a dielectric gate layer, a first output function setting layer containing an n-type output metal on the dielectric gate layer, a TiN layer on the first output function layer, and a second output function layer containing a p-type output metal on the TiN layer. The other gate comprises the dielectric gate layer, the second output function setting layer on the dielectric gate layer, and a filler layer on the second output function setting layer. The n-type output metal is deposited first, followed by the p-type output metal.

[0004] US 2020 / 0 411 387 A1 describes a method for fabricating semiconductor devices in which multiple first and second semiconductor nanolayers are formed in p- and n-type regions, respectively. An n-type exit function layer is deposited around each of the first and second semiconductor nanolayers. Subsequently, a passivation layer is deposited on the n-type exit function layer, which also encloses the first and second semiconductor nanolayers. A structured mask is formed on the passivation layer in the n-type region. In the p-type region, the n-type exit function layer and the passivation layer are removed by an etching process using the structured mask. The structured mask is then removed, and a p-type exit function layer is deposited, which encloses the first semiconductor nanolayers and covers the passivation layer. The passivation layer may contain silicon.DE 10 2020 111 602 A1 is a subsequently published prior art and describes a method comprising providing a first and a second channel layer in a p-region or in an n-region, forming a gate dielectric layer around the first and the second channel layers, and forming a sacrificial layer around the gate dielectric layer. The sacrificial layer flows into the space between the first channel layers and between the second channel layers.The process further includes etching the sacrificial layer such that only sections of the sacrificial layer remain in the space between the first channel layers and between the second channel layers, forming a mask covering the p-region and leaving the n-region free, removing the sacrificial layer from the n-region, removing the mask, and forming an n-exit metal layer around the gate dielectric layer in the n-region and over the gate dielectric layer and the sacrificial layer in the p-region.

[0005] US Patent 2020 / 0328213 A1 describes a semiconductor device comprising first nanostructures stacked vertically over a first region of a substrate, a gate dielectric layer surrounding the first nanostructures, a first oxygen barrier surrounding the gate dielectric layer in the first region, a first work-function setting layer surrounding the first oxygen barrier in the first region, a second oxygen barrier surrounding the first work-function setting layer in the first region, and a second work-function setting layer surrounding the second oxygen barrier in the first region. The first work-function setting layer is n-type and the second is p-type.The semiconductor device further comprises second nanostructures stacked over a second region of the substrate and surrounded by the gate dielectric layer and the second work function layer on the gate dielectric layer. The second oxygen barrier layer can be silicon-based, produced by an impregnation process. The p-type work function layer, comprising, for example, TiN, also extends into the spaces between adjacent first nanostructures. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Aspects of this disclosure are best understood with reference to the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not shown to scale. In fact, the dimensions of the various features may have been arbitrarily enlarged or reduced for the sake of clarity. Fig. Figure 1 shows an example of a nanostructured field-effect transistor (nano-FET) in a three-dimensional representation according to some embodiments. The Fig. Figures 2 to 27B show views of intermediate stages in the fabrication of nano-FETs according to the present disclosure, wherein Fig. Sections 20A to 23B illustrate partial aspects of the invention with examples and Fig. 24A, Fig. 24B represent embodiments according to the invention. Fig. Figure 28 shows a flowchart of an exemplary method for manufacturing replacement gates for nano-FETs according to partial aspects of some embodiments. DETAILED DESCRIPTION

[0007] The following description provides many different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below. For example, the fabrication of a first element over or on top of a second element in the following description may include embodiments in which the first and second elements are fabricated in direct contact, and it may also include embodiments in which additional elements can be fabricated between the first and second elements, such that the first and second elements are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in the various examples in the present invention.This repetition serves the purpose of simplicity and clarity and does not in itself prescribe any relationship between the various designs and / or configurations discussed.

[0008] Furthermore, spatially relative terms, such as "located below," "under," "lower," "located above," "upper," and the like, can be used here to simply describe the relationship of an element or structure to one or more other elements or structures depicted in the figures. These spatially relative terms are intended to encompass orientations of the device in use or operation beyond the orientation shown in the figures. The device may be oriented differently (rotated by 90 degrees or in a different orientation), and the spatially relative descriptors used here can be interpreted accordingly.

[0009] According to various embodiments, replacement gate electrodes are fabricated for p-type and n-type devices. In some embodiments, the output work adjustment layers for the n-type devices are fabricated prior to the output work adjustment layers for the p-type devices to better control the threshold voltages of the resulting devices. The method for fabricating the output work adjustment layers for the n-type devices prior to the output work adjustment layers for the p-type devices involves fabricating and structuring sacrificial layers to prevent the output work adjustment layers for the n-type devices from being fabricated between the nanostructures of the p-type devices. This helps prevent the output work adjustment layers from remaining on the p-type devices, which could reduce the performance of the p-type devices.In the embodiments according to the invention, a protective layer is produced between the output work setting layer and an adhesive layer to block (e.g., substantially prevent or at least reduce) the diffusion of the output work setting layer, wherein the protective layer comprises amorphous silicon. The threshold voltages of the resulting devices can thus be more precisely tuned.

[0010] The embodiments are described in a specific context: a die with nano-FETs. However, various embodiments can be applied to dies that incorporate other types of transistors (e.g., fin field-effect transistors (FinFETs), planar transistors, or the like) instead of, or in combination with, the nano-FETs.

[0011] Fig. Figure 1 shows an example of nano-FETs (e.g., nanowire FETs, nanolayer FETs, or the like) according to some embodiments. Fig. Figure 1 is a three-dimensional representation in which some structural elements of the nano-FETs have been omitted for clarity. The nano-FETs can be nanolayer field-effect transistors (NSFETs), nanowire field-effect transistors (NWFETs), gate-all-around field-effect transistors (GAAFETs), or similar devices.

[0012] The nanoFETs comprise nanostructures 66 (e.g., nanolayers, nanowires, or the like) mounted over fins 62 on a substrate 50 (e.g., a semiconductor substrate), the nanostructures 66 acting as channel regions for the nanoFETs. The nanostructures 66 can be p-nanostructures, n-nanostructures, or a combination thereof. Isolation regions 70, such as shallow trench isolation (STI) regions, are arranged between adjacent fins 62, which may extend beyond and protrude between adjacent isolation regions 70. Although the isolation regions 70 are described / represented as regions separated from the substrate 50, the term "substrate" used here can refer to either the semiconductor substrate alone or a combination of the semiconductor substrate and the isolation regions.And although a lower part of the fins 62 is depicted as a single material connected to the substrate 50, the lower part of the fins 62 and / or the substrate 50 can consist of a single material or a plurality of materials. Here, the fins 62 denote the part that extends beyond and protrudes between the adjacent insulation areas 70.

[0013] Gate dielectrics 122 are arranged over the top surfaces of the fins 62 and along the top, side, and bottom surfaces of the nanostructures 66. Gate electrodes 124 are arranged over the gate dielectrics 122. Epitaxial source / drain regions 98 are arranged on the fins 62 on opposite sides of the gate dielectrics 122 and the gate electrodes 124. The epitaxial source / drain regions 98 can be shared by different fins 62. For example, adjacent epitaxial source / drain regions 98 can be electrically connected, such as by joining the epitaxial source / drain regions 98 through epitaxial growth or by coupling the epitaxial source / drain regions 98 with a common source / drain contact.

[0014] Fig. Figure 1 shows reference cross-sections that will be used in later figures. Cross-section AA' extends along a longitudinal axis of a gate electrode 124 and in a direction that is, for example, perpendicular to a direction of current flow between the epitaxial source / drain regions 98 of a nanoFET. Cross-section BB' extends along a longitudinal axis of a fin 62 and, for example, in a direction of current flow between the epitaxial source / drain regions 98 of the nanoFET. Cross-section CC' is parallel to cross-section AA' and extends through the epitaxial source / drain regions 98 of the nanoFETs. For clarity, later figures refer to these reference cross-sections.

[0015] Some embodiments discussed here relate to nanoFETs fabricated using a gate-last process. Other embodiments may employ a gate-first process. Furthermore, some embodiments consider aspects used in planar devices, such as planar FETs or fin field-effect transistors (FinFETs). For example, FinFETs may have fins on a substrate, with the fins acting as channel regions for the FinFETs. Similarly, planar FETs may have a substrate, with portions of the substrate acting as channel regions for the planar FETs.

[0016] The Fig. Figures 2 to 27B show views of intermediate stages in the fabrication of nano-FETs according to some embodiments. Fig. 2, Fig. 3, Fig. 4, Fig. 5 and Fig. 6 are three-dimensional representations that are similar to a three-dimensional representation of Fig. Show 1. The Fig. 7A, Fig. 8A, Fig. 9A, Fig. 10A, Fig. 11A, Fig. 12A, Fig. 13A, Fig. 14A, Fig. 14B, Fig. 15A, Fig. 15B, Fig. 16A, Fig. 16B, Fig. 17A, Fig. 17B, Fig. 18A, Fig. 18B, Fig. 19A, Fig. 19B, Fig. 20A, Fig. 20B, Fig. 21A, Fig. 21B, Fig. 22A, Fig. 22B, Fig. 23A, Fig. 23B, Fig. 24A, Fig. 24B, Fig. 25A, Fig. 26A and Fig. 27A shows the reference cross-section A-A', which is in Fig. 1 is shown, except that two Finns are shown. Fig. 7B, Fig. 8B, Fig. 9B, Fig. 10B, Fig. 11B, Fig. 12B, Fig. 13B, Fig. 25B, Fig. 26B, Fig. 27B shows the reference cross-section B-B', which is in Fig. 1 is shown. Fig. 9C and Fig. 9D shows the reference cross-section C-C', which is in Fig. 1 is shown, except that two Finns are shown.

[0017] In Fig. 2. A substrate 50 is provided for fabricating nanoFETs. The substrate 50 can be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with a p- or n-type dopant) or undoped. The substrate 50 can be a wafer, such as a silicon wafer. In general, an SOI substrate comprises a layer of semiconductor material that has been fabricated on an insulating layer. The insulating layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulating layer is fabricated on a substrate, usually a silicon or glass substrate. Other substrates, such as multilayer or gradient substrates, may also be used.In some embodiments, the semiconductor material of the substrate 50 may comprise silicon; germanium; a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; an alloy semiconductor, such as silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide and / or gallium indium arsenide phosphide; combinations thereof; or the like.

[0018] Substrate 50 has an n-region 50N and a p-region 50P. The n-region 50N can be used to fabricate n-type devices, such as NMOS transistors, e.g., n-nanoFETs, and the p-region 50P can be used to fabricate p-type devices, such as PMOS transistors, e.g., p-nanoFETs. The n-region 50N can be physically separated from the p-region 50P (not shown separately), and any number of device elements (e.g., other active devices, doped regions, insulating structures, etc.) can be placed between the n-region 50N and the p-region 50P. Although one n-region 50N and one p-region 50P are shown, any number of n-regions 50N and p-regions 50P can be provided.

[0019] The substrate 50 can be lightly doped with a p-type or an n-type dopant. Anti-punch-through (APT) implantation can be performed on an upper portion of the substrate 50 to create an APT region. During APT implantation, dopants can be implanted into the substrate 50. The dopants can have a conductivity type opposite to that of the source / drain regions subsequently created in the n-type region 50N and the p-type region 50P, respectively. The APT region can extend to the source / drain regions in the nanoFETs. The APT region can be used to reduce leakage losses from the source / drain regions into the substrate 50. In some embodiments, the doping concentration in the APT region can be within a range of 10 18 cm -3 up to 10 19 cm -3 lay.

[0020] A multilayer stack 52 is fabricated on the substrate 50. The multilayer stack 52 comprises alternating first semiconductor layers 54 and second semiconductor layers 56. The first semiconductor layers 54 are fabricated from a first semiconductor material, and the second semiconductor layers 56 are fabricated from a second semiconductor material. The semiconductor materials are selected from the candidate semiconductor materials of the substrate 50. In one illustrated embodiment, the multilayer stack 52 comprises three layers each of the first semiconductor layers 54 and the second semiconductor layers 56. It is understood that the multilayer stack 52 can comprise any number of first semiconductor layers 54 and second semiconductor layers 56.

[0021] In the illustrated embodiment, and as will be described in more detail later, the first semiconductor layers 54 are removed and the second semiconductor layers 56 are patterned to create channel regions for the nanoFETs in both the n-region 50N and the p-region 50P. The first semiconductor layers 54 are sacrificial (or dummy) layers that are removed during subsequent processing to expose the top and bottom surfaces of the second semiconductor layers 56. The first semiconductor material of the first semiconductor layers 54 is a material that exhibits high etch selectivity for the etching of the second semiconductor layers 56, such as silicon germanium. The second semiconductor material of the second semiconductor layers 56 is a material suitable for both n- and p-type devices, such as silicon.

[0022] In another embodiment (not shown separately), the first semiconductor layers 54 are structured to create channel regions for nanoFETs in one region (e.g., the p-region 50P), and the second semiconductor layers 56 are structured to create channel regions for nanoFETs in another region (e.g., the n-region 50N). The first semiconductor material of the first semiconductor layers 54 can be a material suitable for p-type devices, such as silicon germanium (e.g., Si3). x Ge 1-x, where x can be in the range from 0 to 1), pure germanium, a III-V compound semiconductor, a II-VI compound semiconductor, or the like. The second semiconductor material of the second semiconductor layers 56 can be a material suitable for n devices, such as silicon, silicon carbide, a III-V compound semiconductor, a II-VI compound semiconductor, or the like. The first semiconductor material and the second semiconductor material can have high etch selectivity with respect to each other, such that the first semiconductor layers 54 can be removed without removing the second semiconductor layers 56 in the n region 50N, and the second semiconductor layers 56 can be removed without removing the first semiconductor layers 54 in the p region 50P.

[0023] Each layer of the multilayer stack 52 can be grown by a process such as vapor phase epitaxy (VPE) or molecular beam epitaxy (MBE), or deposited by a process such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or the like. Each layer can have a small thickness, such as a thickness in the range of 5 nm to 30 nm. In some embodiments, some layers (e.g., the second semiconductor layers 56) are fabricated to be thinner than other layers (e.g., the first semiconductor layers 54).For example, in embodiments where the first semiconductor layers 54 are sacrificial (or dummy) layers and the second semiconductor layers 56 are structured to form channel regions for the nanoFETs in both the n-region 50N and the p-region 50P, the first semiconductor layers 54 can have a first thickness T1 and the second semiconductor layers 56 can have a second thickness T2, where the second thickness T2 is 30% to 60% less than the first thickness T1. By fabricating the second semiconductor layers 56 with a smaller thickness, channel regions with a higher density can be produced.

[0024] In Fig. 3. Trenches are structured in the substrate 50 and the multilayer stack 52 to fabricate fins 62, first nanostructures 64, and second nanostructures 66. The fins 62 are semiconductor strips structured in the substrate 50. The first nanostructures 64 and the second nanostructures 66 comprise the remaining portions of the first semiconductor layers 54 and the second semiconductor layers 56, respectively. The trenches can be structured using any suitable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), or a combination thereof. The etching process can be anisotropic.

[0025] The fins 62 and the nanostructures 64, 66 can be structured using any suitable method. For example, the fins 62 and the nanostructures 64, 66 can be structured using one or more photolithographic processes, such as dual-structure or multiple-structure processes. In general, dual-structure or multiple-structure processes combine photolithographic and self-aligning processes, enabling the creation of structures with, for example, grid spacings smaller than those achievable with a single direct photolithographic process. For example, in one embodiment, a sacrificial layer is produced over a substrate and structured using a photolithographic process. Spacers are produced along the structured sacrificial layer using a self-aligning process.The sacrificial layer is then removed, and the remaining spacers are used as masks for structuring the fins 62 and the nanostructures 64, 66. In some embodiments, the mask (or another layer) can remain on the nanostructures 64, 66.

[0026] The fins 62 and the nanostructures 64, 66 can each have widths in a range of 8 nm to 40 nm. In the illustrated embodiment, the fins 62 and the nanostructures 64, 66 have essentially the same widths in the n-region 50N and the p-region 50P. In another embodiment, the fins 62 and the nanostructures 64, 66 are wider or narrower in one region (e.g., the n-region 50N) than in another region (e.g., the p-region 50P).

[0027] In Fig. 4. STI regions 70 are produced above the substrate 50 and between adjacent fins 62. The STI regions 70 are arranged around at least a portion of the fins 62 such that at least a portion of the nanostructures 64, 66 protrude from adjacent STI regions 70. In the illustrated embodiment, the top surfaces of the STI regions 70 are coplanar (within the process variations) with the top surfaces of the fins 62. In some embodiments, the top surfaces of the STI regions 70 are located above or below the top surfaces of the fins 62. The STI regions 70 separate the structural elements of adjacent devices.

[0028] The STI areas 70 can be fabricated using any suitable method. For example, an insulating material can be fabricated over the substrate 50 and the nanostructures 64, 66, and between adjacent fins 62. The insulating material can be an oxide, such as silicon oxide, a nitride, such as silicon nitride, the like, or a combination thereof, which can be fabricated by a chemical vapor deposition (CVD) process, such as high-density plasma (HDP)-CVD, flowable CVD (FCVD), the like, or a combination thereof. Other insulating materials fabricated by a suitable process can be used. In some embodiments, the insulating material is silicon oxide fabricated by FCVD. An annealing process can be performed after the insulating material has been fabricated.In one embodiment, the insulating material is produced such that excess insulating material covers the nanostructures 64, 66. Although the STI regions 70 are each shown as a single layer, several layers can be used in some embodiments. For example, in some embodiments, a coating (not shown separately) can first be produced along the surfaces of the substrate 50, the fins 62, and the nanostructures 64, 66. A filler material, such as those described above, can then be produced over the coating.

[0029] A removal process is then applied to the insulating material to remove excess insulating material over the nanostructures 64, 66. In some embodiments, a planarization process, such as chemical mechanical polishing (CMP), a back-etching process, combinations thereof, or the like, can be used. The planarization process exposes the nanostructures 64, 66 so that the top surfaces of the nanostructures 64, 66 and the insulating material are coplanar (within the process fluctuations) after completion of the planarization process. In embodiments where a mask remains on the nanostructures 64, 66, the planarization process can expose or remove the mask so that the top surfaces of the mask or of the nanostructures 64, 66 and the insulating material are coplanar (within the process fluctuations) after completion of the planarization process.The insulating material is then recessed to create the STI regions 70. The recession is such that at least a portion of the nanostructures 64, 66 protrudes between adjacent portions of the insulating material. Furthermore, the top surfaces of the STI regions 70 can have a flat surface, as shown, a convex surface, a concave surface (such as "dishing"), or a combination thereof. The top surfaces of the STI regions 70 can be produced flat, convex, and / or concave by suitable etching. The insulating material can be recessed using a suitable etching process, such as one that is selective for the insulating material (e.g., etching the insulating material of the STI regions 70 at a higher rate than the materials of the fins 62 and the nanostructures 64, 66). For example, oxide removal can be performed using dilute hydrofluoric acid (dHF acid).

[0030] The process described above is merely one example of how the fins 62 and the nanostructures 64, 66 can be fabricated. In some embodiments, the fins 62 and / or the nanostructures 64, 66 can be fabricated using a mask and an epitaxial growth process. For example, a dielectric layer can be fabricated over a top surface of the substrate 50, and trenches can be etched through the dielectric layer to expose the underlying substrate 50. Epitaxial structures can be epitaxially grown in the trenches, and the dielectric layer can be recessed such that the epitaxial structures protrude from the dielectric layer to form the fins 62 and / or the nanostructures 64, 66.The epitaxial structures can feature the alternating semiconductor materials, such as the first semiconductor material and the second semiconductor material, as described above. In some embodiments where epitaxial structures are grown epitaxially, the epitaxially grown materials can be doped in situ during growth, thereby avoiding prior and / or subsequent implantation, although in-situ and implantation doping can also be used together.

[0031] Furthermore, suitable wells (not shown separately) can be fabricated in the substrate 50, the fins 62, and / or the nanostructures 64, 66. The conductivity type of the wells can be opposite to the conductivity type of source / drain regions, which are subsequently fabricated in the n-region 50N and the p-region 50P, respectively. In some embodiments, a p-well is fabricated in the n-region 50N, and an n-well is fabricated in the p-region 50P. In some embodiments, a p-well or an n-well is fabricated in both the n-region 50N and the p-region 50P.

[0032] In embodiments with different well types, different implantation steps for the n-region 50N and the p-region 50P can be achieved using a mask (not shown separately), such as a photoresist. For example, a photoresist can be fabricated over the fins 62, the nanostructures 64, 66, and the STI regions 70 in the n-region 50N. The photoresist is structured to expose the p-region 50P. The photoresist can be fabricated using a spin-deposition process and can be structured using suitable photolithography techniques. After the photoresist has been structured, implantation with an n-doping agent can be performed in the p-region 50P, and the photoresist can act as a mask to essentially prevent n-doping agents from being implanted into the n-region 50N.The n-doping agents can be phosphorus, arsenic, antimony, or the like, with a concentration in the range of 10. 13 cm -3 up to 10 14 cm -3 It is implanted into the area. After implantation, the photoresist can be removed, for example with a suitable detachment process.

[0033] Before or after implantation of the p-region 50P, a mask (not shown separately), such as a photoresist, is fabricated over the fins 62, the nanostructures 64 and 66, and the STI regions 70 within the p-region 50P. The photoresist is structured to expose the n-region 50N. The photoresist can be fabricated using a spin-coating process and can be structured using suitable photolithography techniques. After the photoresist has been structured, implantation with a p-doping agent can be performed within the n-region 50N, and the photoresist can act as a mask to essentially prevent p-doping agents from being implanted into the p-region 50P. The p-doping agents can be boron, boron fluoride, indium, or the like, with a concentration in the range of 10 13 cm -3 up to 10 14 cm -3It is implanted into the area. After implantation, the photoresist can be removed, for example with a suitable detachment process.

[0034] Following the implantation of the n-region 50N and the p-region 50P, a tempering process can be performed to repair implantation damage and activate the implanted p- and / or n-doping materials. In some embodiments where epitaxial structures for the fins 62 and / or the nanostructures 64, 66 are grown epitaxially, the grown materials can be doped in situ during growth, thus avoiding implantation, although in-situ and implantation doping can be used together.

[0035] In Fig. In step 5, a dielectric dummy layer 72 is fabricated on the fins 62 and the nanostructures 64, 66. The dielectric dummy layer 72 can be made from a dielectric material, such as silicon oxide, silicon nitride, a combination thereof, or the like, which can be deposited or thermally grown using suitable methods. A dummy gate layer 74 is fabricated over the dielectric dummy layer 72, and a mask layer 76 is fabricated over the dummy gate layer 74. The dummy gate layer 74 can be deposited over the dielectric dummy layer 72 and then planarized, for example, using CMP. The mask layer 76 can be deposited over the dummy gate layer 74.The dummy gate layer 74 can be made of a conductive or non-conductive material, such as amorphous silicon, polycrystalline silicon (polysilicon), polycrystalline silicon germanium (poly-SiGe), a metal, a metal nitride, a metal silicide, a metal oxide, or the like, which can be deposited by physical vapor deposition (PVD), CVD, or the like. The dummy gate layer 74 can be made of one or more materials that have high etch selectivity with respect to insulating materials, e.g., the STI regions 70 and / or the dielectric dummy layer 72. The mask layer 76 can be made of a dielectric material, such as silicon nitride, silicon oxide nitride, or the like. In this example, a single dummy gate layer 74 and a single mask layer 76 are produced across the n-region 50N and the p-region 50P.In the illustrated embodiment, the dielectric dummy layer 72 covers the fins 62, the nanostructures 64, 66, and the STI regions 70, such that the dielectric dummy layer 72 extends over the STI regions 70 and between the dummy gate layer 74 and the STI regions 70. In another embodiment, the dielectric dummy layer 72 covers only the fins 62 and the nanostructures 64, 66.

[0036] In Fig. In step 6, the mask layer 76 is structured using suitable photolithography and etching techniques to fabricate masks 86. The structure of the masks 86 is then transferred to the dummy gate layer 74 using a suitable etching technique to fabricate dummy gates 84. The structure of the masks 86 can optionally be further transferred to the dielectric dummy layer 72 using a suitable etching technique to fabricate dummy dielectrics 82. The dummy gates 84 cover portions of the nanostructures 64, 66 that are exposed during subsequent processing to form channel regions. In particular, the dummy gates 84 extend along the portions of the nanostructures 66 that are structured to form the channel regions 68. The structure of the masks 86 can be used to physically separate adjacent dummy gates 84.The dummy gates 84 can also have longitudinal directions that are essentially perpendicular (within the process variations) to the longitudinal directions of the fins 62. The masks 86 can optionally be removed after structuring, for example, by a suitable etching process.

[0037] The Fig. Figures 7A to 22B show several further steps in the manufacture of devices of the embodiments. Fig. 7A to 13B and the Fig. Figures 21A to 22B show structural elements in both domains, the n-domain 50N and the p-domain 50P. For example, the structures shown can be applicable to both the n-domain 50N and the p-domain 50P. Differences (if any) in the structures of the n-domain 50N and the p-domain 50P are described in the accompanying text for each figure. Fig. 14A, Fig. 15A, Fig. 16A, Fig. 17A, Fig. 18A, Fig. 19A and Fig. 20A show structural elements in the n-range 50N. Fig. 14B, Fig. 15B, Fig. 16B, Fig. 17B, Fig. 18B, Fig. 19B and Fig. 20B show structural elements in the p-region 50P.

[0038] In the Fig. 7A and Fig. 7B Gate spacers 90 are fabricated over the nanostructures 64, 66 on exposed sidewalls of the masks 86 (if present), the dummy gates 84, and the dummy dielectrics 82. The gate spacers 90 can be fabricated by conformal deposition of one or more dielectric materials and subsequent etching of the one or more dielectric materials. Suitable dielectric materials are oxides, such as silicon oxide or aluminum oxide; nitrides, such as silicon nitride; carbides, such as silicon carbide; the like; or combinations thereof, such as silicon oxide nitride, silicon oxide carbide, silicon carbonitride, silicon oxide carbonitride, or the like; multiple layers thereof; or the like.The dielectric materials can be fabricated using a conformal deposition process, such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), or the like. In the illustrated embodiment, the gate spacers 90 each have multiple layers, e.g., a first spacer layer 90A and a second spacer layer 90B. In some embodiments, the first spacer layers 90A and the second spacer layers 90B are made of silicon dioxide carbonitride (e.g., SiO₂). x N y C 1-x-ywhere x and y lie in the range from 0 to 1, the first spacer layers 90A can be fabricated with a similar or different composition of silicon dioxide carbonitride as the second spacer layers 90B. A suitable etching process, such as a dry etching process, a wet etching process, the like, or a combination thereof, can be performed to pattern the one or more dielectric materials. The etching process can be anisotropic. Portions of the one or more dielectric materials remain on the sidewalls of the dummy gates 84 after etching (thus forming the gate spacers 90). After etching, the gate spacers 90 can have straight sidewalls (as shown) or curved sidewalls (not shown).As will be described in more detail later, during etching, parts of one or more dielectric materials can remain on the side walls of the fins 62 and / or the nanostructures 64, 66 (thus forming fin spacers).

[0039] Furthermore, implantations can be performed to fabricate lightly doped source / drain regions (LDD regions) (not shown separately). In embodiments with different device types, similar to the implantations described above for the wells, a mask (not shown separately), such as a photoresist, can be fabricated over the n-region 50N while the p-region 50P is exposed, and dopants of the appropriate type (e.g., p-dopers) can be implanted into the fins 62 and / or the nanostructures 64, 66 exposed in the p-region 50P. The mask can then be removed. Subsequently, a mask (not shown separately), such as a photoresist, can be fabricated over the p-region 50P while the n-region 50N is exposed, and dopants of the appropriate type (e.g.,n-Dopants can be implanted into the fins 62 and / or the nanostructures 64, 66, which are exposed in the n-region 50N. The mask can then be removed. The n-dopants can be the previously described n-dopants, and the p-dopants can be the previously described p-dopants. During implantation, the channel regions 68 remain covered by the dummy gates 84, so that the channel regions 68 remain essentially free of implanted dopants to form the LDD regions. The LDD regions can have a doping concentration in the range of 10. 15 cm -3 up to 10 19 cm -3 exhibit. A tempering process can be used to repair implant damage and activate the implanted dopants.

[0040] It should be noted that the preceding disclosure generally describes a process for manufacturing spacers and LDD areas. Other processes and sequences can be used. For example, fewer or more spacers can be used, steps can be performed in different sequences, additional spacers can be manufactured and removed, and / or the like. Furthermore, the n-devices and the p-devices can be manufactured using different structures and steps.

[0041] In the Fig. 8A and Fig. In 8B, source / drain recesses 94 are produced in the nanostructures 64, 66. In the illustrated embodiment, the source / drain recesses 94 extend through the nanostructures 64, 66 and into the fins 62. The source / drain recesses 94 can also extend into the substrate 50. In various embodiments, the source / drain recesses 94 can extend to a top surface of the substrate 50 without etching the substrate 50; the fins 62 can be etched so that the bottom surfaces of the source / drain recesses 94 are located beneath the top surfaces of the STI areas 70; or the like. The source / drain recesses 94 can be produced by etching the nanostructures 64, 66 using an anisotropic etching process, such as a RIE process, an NBE process or the like.The gate spacers 90 and the dummy gates 84 together mask parts of the fins 62 and / or the nanostructures 64, 66 during the etching processes used to create the source / drain recesses 94. A single etching process can be used to etch the nanostructures 64, 66 individually, or multiple etching processes can be used to etch the nanostructures 64, 66. Timed etching processes can be used to stop the etching of the source / drain recesses 94 after they have reached a desired depth.

[0042] Optionally, internal spacers 96 are fabricated on the sidewalls of the remaining portions of the first nanostructures 64, e.g., the sidewalls exposed by the source / drain recesses 94. As will be described in more detail later, source / drain regions are subsequently fabricated in the source / drain recesses 94, and the first nanostructures 64 are subsequently replaced with corresponding gate structures. The internal spacers 96 act as insulating elements between the subsequently fabricated source / drain regions and the subsequently fabricated gate structures. Furthermore, the internal spacers 96 can be used to prevent subsequent damage to the subsequently fabricated source / drain regions by later etching processes, such as those used to remove the first nanostructures 64.

[0043] To fabricate the inner spacers 96, the source / drain recesses 94 can, for example, be laterally extended. In particular, portions of the sidewalls of the first nanostructures 64, which have been exposed by the source / drain recesses 94, can be recessed. Although the sidewalls of the first nanostructures 64 are shown as straight, they can be concave or convex. The sidewalls can be recessed using a suitable etching process, such as one that is selective for the material of the first nanostructures 64 (e.g., etching the material of the first nanostructures 64 selectively at a higher rate than the material of the second nanostructures 66). The etching process can be isotropic.For example, if the second nanostructures 66 are made of silicon and the first nanostructures 64 are made of silicon germanium, the etching process can be a wet etching process using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or the like. In another embodiment, the etching process can be a dry etching process using a fluorine-based gas, such as hydrogen fluoride gas (HF gas). In some embodiments, the same etching process can be performed continuously to produce both the source / drain recesses 94 and to recess the sidewalls of the first nanostructures 64. The internal spacers 96 can then be produced by conformal fabrication of an insulating material and subsequent etching of the insulating material.The insulating material can be silicon nitride or silicon oxide nitride, although any suitable material, such as materials with a low dielectric constant (low-k materials) having a k-value less than 3.5, can be used. The insulating material can be deposited using a conformal deposition process, such as ALD, CVD, or the like. The etching of the insulating material can be anisotropic. For example, the etching process can be a dry etching process, such as a RIE process, an NBE process, or the like. Although the outer sidewalls of the inner spacers 96 are shown as flush with the sidewalls of the gate spacers 90, the outer sidewalls of the inner spacers 96 can extend beyond the sidewalls of the gate spacers 90 or can be recessed with respect to the sidewalls of the gate spacers 90.In other words, the inner spacers 96 can partially, fully, or excessively fill the side wall recesses. Although the side walls of the inner spacers 96 are shown as straight, they can also be concave or convex.

[0044] In the Fig. 9A and Fig. In embodiment 9B, epitaxial source / drain regions 98 are fabricated in the source / drain recesses 94. The epitaxial source / drain regions 98 are fabricated in the source / drain recesses 94 such that each dummy gate 84 (and corresponding channel regions 68) is arranged between respective adjacent pairs of epitaxial source / drain regions 98. In some embodiments, the gate spacers 90 and the inner spacers 96 are used to separate the epitaxial source / drain regions 98 from the dummy gates 84 and the first nanostructures 64 by a suitable lateral distance, so that the epitaxial source / drain regions 98 are not short-circuited with subsequently fabricated gates of the resulting nano-FETs. A material of the epitaxial source / drain regions 98 can be selected such that a stress is applied in the respective channel regions 68, thereby improving performance.

[0045] The epitaxial source / drain regions 98 in the n-region 50N can be produced by masking the p-region 50P. The epitaxial source / drain regions 98 in the n-region 50N are then epitaxially grown in the source / drain recesses 94 in the n-region 50N. The epitaxial source / drain regions 98 can comprise any material suitable for n-type devices. For example, the epitaxial source / drain regions 98 in the n-region 50N can comprise materials that impart a tensile stress to the channel regions 68, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, or the like. The epitaxial source / drain regions 98 in the n-region 50N can have surfaces that are raised above the respective surfaces of the fins 62 and the nanostructures 64, 66, and they can have facets.

[0046] The epitaxial source / drain regions 98 in the p-region 50P can be fabricated by masking the n-region 50N. The epitaxial source / drain regions 98 in the p-region 50P are then epitaxially grown in the source / drain recesses 94 in the p-region 50P. The epitaxial source / drain regions 98 can comprise any material suitable for p-type devices. For example, the epitaxial source / drain regions 98 in the p-region 50P can comprise materials that exert a compressive stress on the channel regions 68, such as silicon germanium, boron-doped silicon germanium, germanium, germanium-tin, or the like. The epitaxial source / drain regions 98 in the p-region 50P may have surfaces that are raised above the respective surfaces of the fins 62 and the nanostructures 64, 66, and may have facets.

[0047] Dopants can be implanted into the epitaxial source / drain regions 98, the nanostructures 64, 66 and / or the fins 62 to fabricate source / drain regions using a process similar to that described above for the fabrication of the LDD regions, followed by an annealing process. The source / drain regions can have a doping concentration in the range of 10 19 cm -3 up to 10 21 cm -3 exhibit. The n- and / or p-doping agents for source / drain regions can be the doping agents already described. In some embodiments, the epitaxial source / drain regions 98 can be doped in situ during growth.

[0048] As a result of the epitaxial process used to create the epitaxial source / drain regions 98, the upper surfaces of the epitaxial source / drain regions have facets that extend laterally outwards beyond the sidewalls of the fins 62 and the nanostructures 64, 66. In some embodiments, these facets cause adjacent epitaxial source / drain regions 98 to merge, as shown in Fig. 9C is shown. In some embodiments, adjacent epitaxial source / drain regions 98 remain separated after the epitaxial process is complete, as shown in Fig. Figure 9D shows the following embodiments. In the illustrated embodiments, the spacer etching used to produce the gate spacers 90 is configured to also produce fin spacers 92 on the sidewalls of the fins 62 and / or the nanostructures 64, 66. The fin spacers 92 are produced to cover a portion of the sidewalls of the fins 62 and / or the nanostructures 64, 66 that extend over the STI regions 70, thereby blocking epitaxial growth. In another embodiment, the spacer etching used to produce the gate spacers 90 is configured so that no fin spacers are produced, allowing the epitaxial source / drain regions 98 to extend to the surface of the STI regions 70.

[0049] The epitaxial source / drain regions 98 can have one or more semiconductor material layers. For example, the epitaxial source / drain regions 98 can each have a coating layer 98A, a main layer 98B, and a cover layer 98C (or more generally, a first semiconductor material layer, a second semiconductor material layer, and a third semiconductor material layer). Any number of semiconductor material layers can be used for the epitaxial source / drain regions 98. The coating layer 98A, the main layer 98B, and the cover layer 98C can each be made of different semiconductor materials and doped with different doping concentrations.In some embodiments, the coating layer 98A can have a lower doping concentration than the main layer 98B, and the top layer 98C can have a higher doping concentration than the coating layer 98A and a lower doping concentration than the main layer 98B. In embodiments where the epitaxial source / drain regions 98 have three semiconductor material layers, the coating layers 98A can be grown in the source / drain recesses 94, the main layers 98B can be grown on the coating layers 98A, and the top layers 98C can be grown on the main layers 98B.

[0050] In the Fig. 10A and Fig. In 10B, a first interlayer dielectric (ILD) 104 is deposited over the epitaxial source / drain regions 98, the gate spacers 90, the masks 86 (if present), or the dummy gates 84. The first ILD 104 can be made from a dielectric material deposited by a suitable process such as CVD, plasma-enhanced chemical vapor deposition (PECVD), FCVD, or the like. Suitable dielectric materials include materials such as phosphor silicate glass (PSG), borosilicate glass (BSG), boron-doped phosphor silicate glass (BPSG), undoped silicate glass (USG), or the like. Other insulating materials produced by a suitable process can be used.

[0051] In some embodiments, a contact etch stop layer (CESL) 102 is produced between the first ILD 104 and the epitaxial source / drain regions 98, the gate spacers 90, and the masks 86 (if present) or the dummy gates 84. The CESL 102 can be made of a dielectric material, such as silicon nitride, silicon oxide, silicon oxide nitride, or the like, which exhibits high etch selectivity with respect to the etching of the first ILD 104. The CESL 102 can be produced by a suitable process, such as CVD, ALD, or the like.

[0052] In the Fig. 11A and Fig. In 11B, a removal process is performed to bring the top surfaces of the first ILD 104 to the same level as the top surfaces of the masks 86 (if present) or the dummy gates 84. In some embodiments, a planarization process, such as chemical mechanical polishing (CMP), a back-etching process, combinations thereof, or the like, may be used. The planarization process may also remove the masks 86 on the dummy gates 84 and portions of the gate spacers 90 along the sidewalls of the masks 86. After the planarization process, the top surfaces of the gate spacers 90, the first ILD 104, the CESL 102, and the masks 86 (if present) or the dummy gates 84 are coplanar (within the process variations). Accordingly, the top surfaces of the masks 86 (if present) or the dummy gates 84 are exposed by the first ILD 104.In the illustrated embodiment, the masks 86 remain, and the planarization process brings the top surfaces of the first ILD 104 to the same level as the top surfaces of the masks 86.

[0053] In the Fig. 12A and Fig. In 12B, the masks 86 (if present) and the dummy gates 84 are removed in an etching process, creating recesses 110. Portions of the dummy dielectrics 82 within the recesses 110 are also removed. In some embodiments, the dummy gates 84 are removed using an anisotropic dry etching process. For example, the etching process may involve a dry etching process using one or more reactive gases that selectively etches the dummy gates 84 at a higher rate than the first ILD 104 or the gate spacers 90. During removal, the dummy dielectrics 82 may be used as etch stop layers when the dummy gates 84 are etched. The dummy dielectrics 82 are then removed. Each recess 110 exposes portions of the channel regions 68 and / or is located above portions of the channel regions 68.Parts of the second nanostructures 66, which function as the channel regions 68, are arranged between adjacent pairs of the epitaxial source / drain regions 98.

[0054] The remaining portions of the first nanostructures 64 are then removed to enlarge the recesses 110. These remaining portions can then be removed using a suitable etching process that selectively etches the material of the first nanostructures 64 at a higher rate than the material of the second nanostructures 66. The etching process can be isotropic. For example, if the first nanostructures 64 are made of silicon germanium and the second nanostructures 66 are made of silicon, the etching process can be a wet etching process using tetramethylammonium hydroxide (TMAH), NH4OH, H2O2, H2O, HF, C3H8O2, C2H4C3, the like, or combinations thereof. In some embodiments, a trimming process (not shown separately) is performed to reduce the thickness of the exposed portions of the second nanostructures 66. As will be shown more clearly in the Fig. As shown in Figures 14A to 20B (which will be described in more detail later), the remaining parts of the second nanostructures can have 66 rounded corners.

[0055] In the Fig. 13A and Fig. In 13B, a dielectric gate layer 112 is fabricated in the recesses 110. A gate electrode layer 114 is fabricated on the dielectric gate layer 112. The dielectric gate layer 112 and the gate electrode layer 114 are replacement gate layers, and each encloses all (e.g., four) sides of the second nanostructures 66.

[0056] The dielectric gate layer 112 is arranged on the sidewalls and / or top surfaces of the fins 62; on the top surfaces, sidewalls, and bottom surfaces of the second nanostructures 66; and on the sidewalls of the gate spacers 90. The dielectric gate layer 112 can also be produced on the top surfaces of the first ILD 104 and the gate spacers 90. The dielectric gate layer 112 can comprise an oxide, such as silicon oxide or a metal oxide, a silicate, such as a metal silicate, combinations thereof, multiple layers thereof, or the like. The dielectric gate layer 112 can comprise a dielectric material whose k-value is greater than 7.0, such as a metal oxide or a silicate of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. Although a dielectric gate layer 112 with only a single layer in the Fig. 13A and Fig. As shown in Figure 13B, the dielectric gate layer 112 can have a boundary layer and a main layer, as will be described in more detail later.

[0057] The gate electrode layer 114 can comprise a metal-containing material, such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, multiple layers thereof, or the like. Although a gate electrode layer 114 with only a single layer in the Fig. 13A and Fig. As shown in Figure 13B, the gate electrode layer 114 can have any number of exit work setting layers, any number of barrier layers, any number of adhesive layers and a filler material, as will be described in more detail later.

[0058] The Fig. Figures 14A to 24B show a process in which layers for replacement gates are manufactured in the recesses 110. Structural elements in areas corresponding to area 50R in Fig. 13A are shown. Fig. Figure 28 shows a flowchart of an exemplary method 200 for producing the replacement gate layers according to some embodiments. Fig. 14A to 24B are related to Fig. 28 described.

[0059] In the Fig. 14A and Fig. 14B and in step 202 of process 200, the dielectric gate layer 112 is deposited in the recesses 110 in both the first region (e.g., the n-region 50N) and the second region (e.g., the p-region 50P). The dielectric gate layer 112 can also be deposited on the top surfaces of the first ILD 104 and the gate spacers 90 (see Figure 14B). Fig. 13B). In the illustrated embodiment, the dielectric gate layer 112 is multilayered, comprising an interface layer 112A (or more generally, a first dielectric gate layer) and an overlying dielectric high-k layer 112B (or more generally, a second dielectric gate layer). The interface layer 112A can be made of silicon oxide or the like, and the dielectric high-k layer 112B can be made of hafnium oxide, lanthanum oxide, or the like. The methods for producing the dielectric gate layer 112 can include molecular beam deposition (MBD), ALD, PECVD, and the like. The dielectric gate layer 112 encloses all (e.g., four) sides of the second nanostructures 66.

[0060] In some embodiments, the second nanostructures 66 have a width W1 in a range of 1 nm to 50 nm, such as 15 nm to 25 nm. In other embodiments, adjacent second nanostructures 66 are spaced apart by a distance S1 in a range of 0.1 nm to 40 nm, such as 3 nm to 8 nm. If the distance S1 is greater than 40 nm, a seam or cavity may form between adjacent second nanostructures 66 after the subsequent fabrication of the gate structures. If the distance S1 is less than 0.1 nm, short circuits between adjacent second nanostructures 66 may more easily occur.

[0061] In the Fig. 15A and Fig. In step 204 of process 200, a first sacrificial layer 116A is deposited on the dielectric gate layer 112 in the first region (e.g., the n-region 50N) and the second region (e.g., the p-region 50P). As will be described in more detail later, the first sacrificial layer 116A is structured to remove portions of the first sacrificial layer 116A in the first region (e.g., the n-region 50N) while leaving portions of the first sacrificial layer 116A in the second region (e.g., the p-region 50P). In particular, the first sacrificial layer 116A is used to facilitate the removal of exit work layers from the second region (e.g., the p-region 50P) by preventing these exit work layers from migrating between the second nanostructures 66.The first sacrificial layer 116A comprises a suitable material that can be produced on and removed from the second nanostructures 66 and deposited using a suitable deposition process. For example, the first sacrificial layer 116A is made of TiN, WCN, WCl5, TaCl5, SnCl4, combinations thereof, or the like, which can be deposited using ALD, CVD, PVD, or the like. Although the first sacrificial layer 116A is shown as a single layer, it can also be multilayered. The first sacrificial layer 116A can fill portions of the second recesses 110 that extend between vertically adjacent nanostructures 66 and between the nanostructures 66 and the fins 62.

[0062] In the Fig. 16A and Fig. In step 206 of procedure 200, portions of the first sacrificial layer 116A are removed from the first region (e.g., the n-region 50N) and the second region (e.g., the p-region 50P). Removing these portions of the first sacrificial layer 116A allows for the subsequent fabrication of a second sacrificial layer 116B to protect the dielectric gate layer 112, while potentially providing etch selectivity for the first sacrificial layer 116A. Removal can be performed using suitable photolithography and etching techniques. Etching can be carried out using any suitable technique, such as reactive ion etching (RIE), neutral beam etching (NBE), or a combination thereof. The etching process can be anisotropic. As described in the Fig. 16A and Fig. As shown in Figure 16B, by removing portions of the first sacrificial layer 116A, outer parts of the first sacrificial layer 116A are removed to expose the dielectric gate layer 112, but the first sacrificial layer 116A is left behind between vertically adjacent nanostructures 66 and between the nanostructures 66 and the fins 62 in both the first and second regions 50N and 50P. Removing the outer parts of the first sacrificial layer 116A while leaving inner parts behind can be described as a trimming process.

[0063] After the removal of parts of the first sacrificial layer 116A, the dielectric gate layer 112 remains above insulation areas 70 and covers the insulation areas 70 (see e.g. Fig. 13A). These parts of the dielectric gate layer 112 can help to protect the insulation regions 70 from damage caused by subsequent deposition and removal processes.

[0064] In some embodiments, a single etching process is performed to remove the portions of the first sacrificial layer 116A. This single etching process can be selective for materials of the first sacrificial layer 116A (e.g., selectively etching the material of the first sacrificial layer 116A at a higher rate than one or more materials of the dielectric gate layer 112). In other embodiments, multiple etching steps / processes are performed to remove the portions of the first sacrificial layer 116A.

[0065] In the Fig. 17A and Fig. In step 208 of process 200, a second sacrificial layer 116A is deposited on the dielectric gate layer 112 and the remaining first sacrificial layer 116A in the first region (e.g., the n-region 50N) and the second region (e.g., the p-region 50P). As will be described in more detail later, the second sacrificial layer 116B is structured to remove it and the first sacrificial layer 116A from the first region (e.g., the n-region 50N), while the second sacrificial layer 116B and the first sacrificial layer 116A are left in the second region (e.g., the p-region 50P). In particular, the second sacrificial layer 116B is used to protect the dielectric gate layer 112 from the first mask layer 118A, which is produced in the first and second regions, by preventing the first mask layer 118A from being produced directly on the dielectric gate layer 112.The second sacrificial layer 116B comprises a suitable material that can be deposited on and removed from the dielectric gate layer 112 without damaging it, and it can be deposited by any suitable deposition process. For example, the second sacrificial layer 116B is made of TiN, WCN, WCl5, TaCl5, SnCl4, combinations thereof, or the like, which can be deposited by ALD, CVD, PVD, or the like. In some embodiments, the second sacrificial layer 116B is made of a different material than the first sacrificial layer 116A. Although the second sacrificial layer 116B is shown as a single layer, it can be multilayered.

[0066] In some embodiments, the second sacrificial layer 116B is made of the same material as the first sacrificial layer 116A, and there is no visible interface between layers 116A and 116B. In some embodiments, the second sacrificial layer 116B is omitted, and the first sacrificial layer 116A is not structured, as shown in the Fig. 16A and Fig. 16B shows that the first sacrificial layer 116A protects the dielectric layer 112 from the first mask layer 118A.

[0067] In the Fig. 18A and Fig. In step 210 of process 200, the first mask layer 118A is produced in the second recesses 110 above the second sacrificial layer 116B in the first and second regions 50N and 50P. The first mask layer 118A can be deposited by spin deposition or the like. The first mask layer 118A can comprise a polymer material such as poly(methyl)acrylate, poly(maleimide), novolac, poly(ether), combinations thereof, or the like. In some embodiments, the first mask layer 118A can be a bottom antireflective coating (BARC).

[0068] As in the Fig. 18A and Fig. As shown in Figure 18B, the first mask layer 118A is patterned to remove the first mask layer 118A from the recesses 110 in the first region 50N. The first mask layer 118A can be removed by a plasma removal process, an etching process such as an isotropic or anisotropic etching process, or the like. After patterning the first mask layer 118A, the first and second sacrificial layers 116A and 116B are removed from the first region 50N, using the first mask layer 118A as a mask. Removal can be performed using suitable photolithography and etching techniques. The etching can involve a suitable etching process such as a RIE process, an NBE process, a wet etching process, or a combination thereof. The etching process can be anisotropic.

[0069] In some embodiments, a single etching process is performed to remove the portions of the first and second sacrificial layers 116A and 116B. This single etching process can be selective for the materials of the first and second sacrificial layers 116A and 116B (e.g., selectively etching the materials of the first and second sacrificial layers 116A and 116B at a higher rate than the one or more materials of the dielectric gate layer 112). For example, if the first and second sacrificial layers 116A and 116B are made of titanium nitride, they can be removed by an inductively coupled plasma etching process using Ar / CHF3, Ar / Cl2, Ar / BCl3, the like, or a combination thereof. In some embodiments, multiple etching steps / processes can be performed to remove the first and second sacrificial layers 116A and 116B.

[0070] In the Fig. 19A and Fig. In step 19B, the first mask layer 118A is structured to facilitate removal of the first mask layer 118A from the recesses 110 in the second region 50P. The first mask layer 118A can be removed by a plasma removal process, an etching process such as an isotropic or anisotropic etching process, or the like. After the first mask layer 118A has been removed from the recesses 110 in the second region 50P, the second sacrificial layer 116B is removed from the second region 50P. The removal can be performed using suitable photolithography and etching techniques. The etching can involve a suitable etching process such as a RIE process, an NBE process, the like, or a combination thereof. The etching process can be anisotropic.

[0071] In some embodiments, a single etching process is performed to remove the second sacrificial layer 116B. This single etching process can be selective for the materials of the second sacrificial layer 116B (e.g., selectively etching the materials of the second sacrificial layer 116B at a higher rate than one or more materials of the dielectric gate layer 112 and / or the first sacrificial layer 116A). In some embodiments, multiple etching steps / processes can be performed to remove the second sacrificial layer 116B.

[0072] As in the Fig. 19A and Fig. As shown in Figure 19B, when the second sacrificial layer 116B is removed, outer parts of the second sacrificial layer 116B are removed to expose parts of the dielectric gate layer 112, but the first sacrificial layer 116A is left behind between vertically adjacent nanostructures 66 and between the nanostructures 66 and the fins 62 in the second region 50P. This removal of the outer parts of the second sacrificial layer 116B, while leaving inner parts behind, can be described as a trimming process.

[0073] In the Fig. 20A and Fig. In step 214 of process 200, a first work function setting layer 114A is deposited on the dielectric gate layer 112 in the first region (e.g., the n-region 50N) and on the dielectric gate layer 112 and the first sacrificial layer 116A in the second region (e.g., the p-region 50P). As will be described in more detail later, the first work function setting layer 114A is structured to remove portions of it in the second region (e.g., the p-region 50P) while leaving portions of it in the first region (e.g., the n-region 50N). The first exit work adjustment shift 114A can be referred to as an “n exit work adjustment shift” if it is removed from the second area (e.g. the p area 50P).The first work function adjustment layer 114A comprises a material suitable for adjusting the work function of a device to a value desired for the application of the device being manufactured and can be deposited using a suitable deposition process. For example, if the first work function adjustment layer 114A is an n-type work function adjustment layer, it can be made from an n-type work function metal (NWFM), such as titanium aluminum (TiAl), titanium aluminum carbide (TiAlC), TiAlC:N, titanium aluminum nitride (TiAlN), tantalum silicon aluminum (TaSiAl), WCl5, SnCl4, NbCl5, MoCl4, combinations thereof, or the like, which can be deposited by ALD, CVD, PVD, or the like. Although the first exit work adjustment layer 114A is shown as single-layer, the first exit work adjustment layer 114A can be multi-layer.For example, the first exit work adjustment layer 114A can have a layer of TiAlN and a layer of TiAlC.

[0074] The first work function setting layer 114A is fabricated to a thickness that prevents the parts of the first work function setting layer 114A from fusing between the second nanostructures 66 in the first region (e.g., the n-region 50N). As will be described in more detail later, the ALD process used to fabricate the first work function setting layer 114A can produce a thinner first work function setting layer 114A (one that does not fusing between the second nanostructures 66 in the cross-section shown in the first region 50N) while still achieving the desired effective work function value. The first work function setting layer 114A cannot fuse between the second nanostructures 66 in the second region (e.g. the p-region 50P) in the cross-section shown due to the remaining parts of the first sacrificial layer 116A in the second region.By not depositing the first work function setting layer 114A between the second nanostructures 66 in the second region (e.g., the p-region 50P), the fabrication process can be simplified, particularly for advanced semiconductor nodes with small structural element sizes, since work function setting layer materials are difficult to remove from small spaces. In some embodiments, the first work function setting layer 114A is produced with a thickness in the range of 0.5 nm to 12 nm, such as a range of 2 nm to 8 nm.

[0075] In some embodiments, the first work function setting layer 114A is produced from titanium aluminum carbide deposited by an ALD process. Specifically, the first work function setting layer 114A can be produced by placing the substrate 50 in a deposition chamber and cyclically distributing several source precursors in the chamber. A first pulse of an ALD cycle is performed by distributing a titanium source precursor in the chamber. Suitable titanium source precursors include precursors such as titanium chloride (TiCl4) or the like. The first pulse can be performed at a temperature in the range of 100 °C to 600 °C and at a pressure in the range of 133 Pa to 133 hPa, for example, by maintaining these temperatures and pressures in the deposition chamber.The first pulse can be performed for a duration ranging from 0.5 seconds to 20 seconds, for example, by leaving the titanium source precursor in the deposition chamber for this duration. The titanium source precursor is then purged from the deposition chamber, for example, by a suitable extraction process and / or by introducing an inert gas (sometimes called a carrier gas) into the deposition chamber. A second pulse of the ALD cycle is performed by distributing an aluminum source precursor in the deposition chamber. Suitable aluminum source precursors include precursors such as triethylaluminum (TEA)(Al₂(C₂H₅)₆ and the like. The second pulse can be performed at a temperature ranging from 100 °C to 600 °C and at a pressure ranging from 133 Pa to 133 hPa, for example, by maintaining these temperatures and pressures in the deposition chamber.The second pulse can be performed for a duration ranging from 0.5 seconds to 20 seconds, for example, by leaving the aluminum source precursor in the deposition chamber for this duration. The aluminum source precursor is then purged from the deposition chamber, for example, by a suitable extraction process and / or by introducing an inert gas into the deposition chamber. Performing either ALD pulse at a temperature above 600 °C can negatively affect the uniformity of the deposition and may result in uneven material concentrations in the deposited layer. Performing either ALD pulse at a temperature below 100 °C can negatively affect the throughput and / or productivity of the manufacturing process and may lead to higher manufacturing costs.Each ALD cycle results in the deposition of an atomic layer (sometimes referred to as a monomolecular layer) of titanium aluminum carbide. The ALD cycles are repeated until the first work function setting layer 114A reaches a desired thickness (described above). The ALD cycles can be repeated from 1 to 10 times. If the ALD process is performed with parameters within this range, the first work function setting layer 114A can be produced with the desired thickness (described above), quality, and composition. If the ALD process is performed with parameters outside this range, the first work function setting layer 114A may not be produced with the desired thickness, quality, and composition.

[0076] The ALD process described above for producing the first work function setting layer 114A has an equal number of titanium pulses and aluminum pulses in each ALD cycle. In some embodiments, there are more aluminum pulses than titanium pulses per ALD cycle. For example, each ALD cycle might have one titanium pulse and two aluminum pulses. In another example, each ALD cycle might have two titanium pulses and three aluminum pulses. By ensuring that each ALD cycle has at least as many aluminum pulses as titanium pulses, the first work function setting layer has a higher aluminum concentration. In some embodiments, the atomic percentage (at%) of aluminum in the first work function setting layer 114A is in a range of 3% to 80%, such as 20% to 40%.In some embodiments, the first work function setting layer 114A has a metal concentration gradient with a higher concentration of aluminum at an inner part near the second nanostructures 66 and a lower concentration at an outer part away from the second nanostructures 66. In some embodiments, the disclosed method for producing the first work function setting layer 114A has improved the effective work function by 10% to 15%.

[0077] In some embodiments, the ALD process for producing the first work-of-efficiency setting layer 114A includes introducing a carrier gas from an opening on the bottom of the deposition chamber (e.g., below or on the back side of the substrate 50), while the titanium and aluminum precursors described above enter from one or more openings on the top of the deposition chamber (e.g., above or on the front side of the substrate 50). In some embodiments, the carrier gas entering at the bottom of the deposition chamber is N2 or the like and has a volumetric flow rate in the range of 2 sccm to 100 sccm. In some embodiments, the carrier gas flow is a pulse performed at the end of each ALD cycle. In some embodiments, the carrier gas flow is a pulse performed after each titanium or aluminum precursor pulse in each ALD cycle.Because the ALD process has this backside carrier gas flow, the uniformity of the deposition thickness of the first exit work setting layer 114A is improved by 23% compared to processes without backside carrier gas flow.

[0078] Furthermore, in the Fig. 20A and Fig. 20B and in step 214 of process 200, an adhesive layer 114B is produced on the first exit work setting layer 114A in the first region (e.g., the n region 50N) and the second region (e.g., the p region 50P). As in Fig. As shown in Figure 20A, the adhesive layer 114B fuses between adjacent second nanostructures 66 in the first region 50N in the cross-section shown. In some embodiments, the adhesive layer 114B is produced to a thickness in the range of 10 nm to 50 nm. The adhesive layer 114B can comprise a material suitable for promoting adhesion and preventing diffusion. The adhesive layer 114B is produced from titanium aluminum carbide, tantalum aluminum carbide, or silicon-doped tantalum aluminum carbide, which can be deposited by ALD, CVD, PVD, or the like.

[0079] In some embodiments, the adhesive layer 114B is formed using a similar ALD process with titanium precursors, such as TiCl4 or the like, tantalum precursors, such as pentakis(dimethylamino)tantal(V) (PDMAT) (C 10 H 30Titanium dioxide (N5Ta), tantalum chloride (TaCl5) or the like, and / or nitrogen precursors, such as NH3, or the like, are used. The inflow of titanium or tantalum precursors into the deposition chamber can be in the range of 50 sccm to 100 sccm. The inflow of nitrogen precursors into the deposition chamber can be in the range of 50 sccm to 50,000 sccm. Performing the ALD process with a volumetric flow rate above these ranges can negatively affect the uniformity of the deposition and may result in precursor waste. Performing the ALD process with a volumetric flow rate below these ranges can negatively affect the throughput and / or productivity of the manufacturing process and may result in a lower material concentration in the deposited layer.In some embodiments, the ALD process can be performed at a temperature ranging from 100 °C to 600 °C and at a pressure ranging from 13.3 mPa to 133 Pa. Performing the ALD process at temperatures above 600 °C can negatively affect the uniformity of the deposition and may result in inconsistent material concentrations in the deposited layer. Performing the ALD process at temperatures below 100 °C can negatively impact the throughput and / or productivity of the manufacturing process and may lead to higher manufacturing costs.

[0080] In the Fig. 21A and Fig. 21B and in step 216 of process 200, a second mask layer 118B is produced in the second recesses 110 above the adhesive layer 114B in the first and second areas 50N and 50P. The second mask layer 118B can be similar to the first mask layer 118A described above, and the description is not repeated here.

[0081] As in the Fig. 21A and Fig. As shown in Figure 21B, the second mask layer 118B is patterned to remove the second mask layer 118B from the recesses 110 in the second region 50P. The second mask layer 118B can be removed by a plasma removal process, an etching process such as an isotropic or anisotropic etching process, or the like. After patterning the second mask layer 118B, the first exit work setting layer 114A, the adhesive layer 114B, and any remaining parts of the first sacrificial layer 116A are removed from the second region 50P, using the second mask layer 118B as a mask. By removing the first exit work setting layer 114A, the adhesive layer 114B and remaining parts of the first sacrificial layer 116A from the second region (e.g. the p-region 50P), the recesses 110 in the second region are enlarged to accommodate the dielectric gate layer 112 in the second region (e.g.to expose the p-region (50p). Removal can be carried out using suitable photolithography and etching techniques. The etching process can be any suitable process, such as a RIE process, an NBE process, the like, a wet etching process using, for example, ammonium hydroxide (NH4OH), dilute hydrofluoric acid (dHF acid), the like, or a combination thereof. The etching process can be isotropic.

[0082] In some embodiments, a single etching process is performed to remove the first exit-work setting layer 114A, the adhesive layer 114B, and any remaining portions of the first sacrificial layer 116A. This single etching process can be selective for the materials of the first exit-work setting layer 114A, the adhesive layer 114B, and the remaining portions of the first sacrificial layer 116A (e.g., selectively etching the materials of the first exit-work setting layer 114A, the adhesive layer 114B, and the remaining portions of the first sacrificial layer 116A at a higher rate than one or more materials of the dielectric gate layer 112). In some embodiments, multiple etching steps / processes are performed to remove the first exit-work setting layer 114A, the adhesive layer 114B, and any remaining portions of the first sacrificial layer 116A.As discussed above, the remaining parts of the first sacrificial layer 116A can be removed more easily between the second nanostructures 66 than the work function adjustment layers, and consequently the disclosed method allows for better control of the threshold voltage of the devices.

[0083] In the Fig. 22A and Fig. In step 22B, the second mask layer 118B is structured to allow removal of the second mask layer 118B from the recesses 110 in the first region 50N. The second mask layer 118B can be removed by a plasma removal process, an etching process such as an isotropic or anisotropic etching process, or the like.

[0084] After removing the second mask layer 118B from the recesses 110 in the second area 50N, the following are inserted into the Fig. 22A and Fig. 22B and in step 218 of the process, 200 second output work setting layers 114C and 114D are deposited on the adhesive layer 114B in the first region (e.g., the n-region 50N) and on the dielectric gate layer 112 in the second region (e.g., the p-region 50P). As will be described in more detail later, p-devices are fabricated that have the second output work setting layers 114C and 114D in the second region (e.g., the p-region 50P), and n-devices are fabricated that have the first output work setting layer 114A, the adhesive layer 114B, and the second output work setting layers 114C and 114D in the first region (e.g., the n-region 50N). The second exit work adjustment shifts 114C and 114D can be referred to as a “p exit work adjustment shift” if it is the only exit work adjustment shift in the second area (e.g., the p area 50P).The second work function adjustment layers 114C and 114D comprise a material suitable for adjusting the work function of a device to a value desired for the application of the device being manufactured, and this material can be deposited using a suitable deposition process. For example, if the second work function adjustment layers 114C and 114D are p-type work function adjustment layers, they can be made from p-type work function metals (PWFM), such as titanium nitride (TiN), tantalum nitride (TaN), combinations thereof, or the like, which can be deposited by ALD, CVD, PVD, or the like. Although the second work function adjustment layers 114C and 114D are shown as two layers, the second work function adjustment layer can be a single layer or can have more than two layers.In some embodiments, the second exit work adjustment layers 114C and 114D have a layer of titanium nitride (TiN) and a layer of tantalum nitride (TaN).

[0085] The second work function setting layers 114C and 114D are fabricated to a thickness sufficient to cause the fusion of the portions of the second work function setting layer 114C or 114D between the second nanostructures 66 in the second region (e.g., the p-region 50P). In some embodiments, the second work function setting layers 114C and 114D are fabricated to a thickness in the range of 1 nm to 20 nm, such as in the range of 2 nm to 2.5 nm. Fabricating the second work function setting layer 114C to a thickness of less than 2 nm may result in portions of the second work function setting layers 114C and 114D not fusion. The production of the second exit work setting layer 114C and 114D to a thickness of more than 2.5 nm can have a negative impact on the threshold stresses of the resulting devices.

[0086] The first exit work adjustment layer 114A has a different material than the second exit work adjustment layers 114C and 114D. As stated above, the first exit work adjustment layer 114A can be made from an n-type exit work metal (NWFM), and the second exit work adjustment layers 114C and 114D can be made from a p-type exit work metal (PWFM). The NWFM is different from the PWFM.

[0087] In the Fig. 23A and Fig. In step 220 of process 200, a filler layer 114E is deposited on the second output work setting layer 114D. After the fabrication is complete, the gate electrode layer 114 comprises the first output work setting layer 114A, the adhesive layer 114B, the second output work setting layers 114C and 114D, and the filler layer 114E.

[0088] The filler layer 114E comprises a suitable material with low resistance. For example, the filler layer 114E can be made of a metal such as tungsten, aluminum, cobalt, ruthenium, combinations thereof, or the like, which can be deposited by ALD, CVD, PVD, or the like. The filler layer 114E fills the remaining portions of the recesses 110. As shown in the cross-sections in the Fig. 23A and Fig. As shown in Figure 23B, the filling layer 114E does not extend between adjacent second nanostructures 66 in the first region 50N or in the second region 50P, because the area between adjacent nanostructures 66 in both regions 50N and 50P has already been filled with other layers.

[0089] Although the adhesive layer 114B is used to promote the adhesion of the first output work setting layer 114A during machining and to prevent the diffusion of the first output work setting layer 114A, it does not significantly affect the electrical properties of the resulting devices and can be left in the portions of the gate electrode layer 114 in the first region (e.g., the n-region 50N). The adhesive layer 114B is positioned between the portions of the first output work setting layer 114A and the second output work setting layer 114C in the first region (e.g., the n-region 50N) and physically separates them. Conversely, the second region (e.g., the p-region 50P) is free of the first output work setting layer 114A and the adhesive layer 114B, so that the second output work setting layer 114C and the dielectric gate layer 112 in the second region (e.g.,(in the p-range 50P) cannot be separated by an adhesive layer and can be in physical contact.

[0090] The Fig. 24A and Fig. Figure 24B shows an embodiment of the invention comprising a protective layer 114F between the first output work setting layer 114A and the adhesive layer 114B. The protective layer 114F is made of a material that is resistant to oxidation and prevents the diffusion of the first output work setting layer 114A, thereby preventing modification of the first output work setting layer 114A by subsequent processing.

[0091] In some examples, the protective layer 114F is made of amorphous silicon, tantalum nitride, titanium nitride, the like, or a combination thereof, which can be deposited by CVD, ALD, or the like. According to the invention, a protective layer comprising amorphous silicon is used. Although the protective layer 114F is shown as a single layer, it can be multilayered. For example, the protective layer 114F can have a layer of amorphous silicon and a layer of titanium nitride. In some embodiments, the protective layer 114F is produced to a thickness in the range of 0.1 nm to 10 nm.

[0092] In the Fig. 25A and Fig. In 25B, a removal process is performed to remove the excess parts of the materials of the dielectric gate layer 112 and the gate electrode layer 114, wherein these excess parts are located above the top surfaces of the first ILD 104 and the gate spacers 90, thereby producing gate dielectrics 122 and gate electrodes 124. In some embodiments, a planarization process, such as chemical-mechanical polishing (CMP), a back-etching process, combinations thereof, or the like, may be used. During planarization, parts of the dielectric gate layer 112 remain in the recesses 110 (thus forming the gate dielectrics 122). During planarization, parts of the gate electrode layer 114 remain in the recesses 110 (thus forming the gate electrodes 124). The top surfaces of the gate spacers 90; the CESL 102; the first ILD 104; the gate dielectric 122 (e.g.the boundary layers 112A and the dielectric high-k layers 112B, see the . Fig. 23A-24B); and the gate electrodes 124 (e.g., the first output work setting layer 114A, the adhesive layer 114B, the second output work setting layers 114C and 114D, the protective layer 114F, and the filler layer 114E, see the Fig. 23A-24B) are coplanar (within the process fluctuations). The gate dielectrics 122 and the gate electrodes 124 form substitute gates of the resulting nanoFETs. Each pair of a gate dielectric 122 and a gate electrode 124 can be collectively referred to as a “gate structure.” The gate structures extend along the top, side, and bottom surfaces of a channel region 68 of the second nanostructures 66.

[0093] In the Fig. 26A and Fig. In 26B, a second ILD 134 is deposited over the gate spacers 90, the CESL 102, the first ILD 104, the gate dielectrics 122, and the gate electrodes 124. In some embodiments, the second ILD 134 is a flowable layer produced by a flowable CVD process. In other embodiments, the second ILD 134 is produced from a dielectric material, such as PSG, BSG, BPSG, USG, or the like, which can be deposited by a suitable process, such as CVD, PECVD, or the like.

[0094] In some embodiments, an etch stop layer (ESL) 132 is produced between the second ILD 134 and the gate spacers 90, the CESL 102, the first ILD 104, the gate dielectrics 122, and the gate electrodes 124. The ESL 132 can comprise a dielectric material, such as silicon nitride, silicon oxide, silicon oxide nitride, or the like, which has high etch selectivity with respect to the etching of the second ILD 134.

[0095] In the Fig. 27A and Fig. In step 27B, gate contacts 142 and source / drain contacts 144 are fabricated to contact the gate electrodes 124 and the epitaxial source / drain regions 98, respectively. The gate contacts 142 are physically and electrically coupled to the gate electrodes 124. The source / drain contacts 144 are physically and electrically coupled to the epitaxial source / drain regions 98.

[0096] As an example of how to fabricate the gate contacts 142 and the source / drain contacts 144, openings for the gate contacts 142 are produced by the second ILD 134 and the ESL 132, and openings for the source / drain contacts 144 are produced by the second ILD 134, the ESL 132, the first ILD 104, and the CESL 102. The openings can be produced using suitable photolithography and etching techniques. A coating (not shown separately), such as a diffusion barrier, an adhesive layer, or the like, and a conductive material are produced in the openings. The coating can be titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material can be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. To remove excess material from a surface of the second ILD 134, a planarization process, such as CMP, can be performed.The remaining coating and conductive material form the gate contacts 142 and the source / drain contacts 144 in the openings. The gate contacts 142 and the source / drain contacts 144 can be manufactured using different processes, or they can be manufactured using the same process. Although the gate contacts 142 and the source / drain contacts 144 are shown as having the same cross-sections, it should be understood that they can each be manufactured with different cross-sections to prevent short-circuiting.

[0097] Optionally, metal-semiconductor alloy regions 146 are fabricated at the interfaces between the epitaxial source / drain regions 98 and the source / drain contacts 144. The metal-semiconductor alloy regions 146 can be silicide regions fabricated from a metal silicide (e.g., titanium silicide, cobalt silicide, nickel silicide, etc.), germanide regions fabricated from a metal germanide (e.g., titanium germanide, cobalt germanide, nickel germanide, etc.), silicon germanide regions fabricated from both a metal silicide and a metal germanide, or the like. The metal-semiconductor alloy regions 146 can be fabricated upstream of one or more of the source / drain contact materials 144 by depositing a metal in the openings for the source / drain contacts 144 and then performing a thermal annealing process. The metal can be any metal that is compatible with semiconductor materials (e.g.Silicon, silicon-germanium, germanium, etc.) of the epitaxial source / drain regions 98 can react to produce a low-resistance metal-semiconductor alloy, such as nickel, cobalt, titanium, tantalum, platinum, tungsten, other precious metals, other refractory metals, rare earth metals, or their alloys. The metal can be deposited by a deposition process such as ALD, CVD, PVD, or the like. After the thermal annealing process, a cleaning process, such as wet cleaning, can be performed to remove residual metal from the openings for the source / drain contacts 144, such as from the surfaces of the metal-semiconductor alloy regions 146. The one or more materials of the source / drain contacts 144 can be produced on the metal-semiconductor alloy regions 146.

[0098] Embodiments can offer advantages. In some embodiments, the output work adjustment layers for the n-devices are fabricated prior to the output work adjustment layers for the p-devices to better control the threshold stresses of the resulting devices. The method for fabricating the output work adjustment layers for the n-devices prior to the output work adjustment layers for the p-devices involves fabricating and structuring sacrificial layers to prevent the output work adjustment layers for the n-devices from being fabricated between the nanostructures of the p-devices. This prevents the output work adjustment layers from remaining on the p-devices, which could reduce the performance of the p-devices.In some embodiments, a protective layer is created between the output work setting layer and an adhesive layer to block (e.g., substantially prevent or at least reduce) the diffusion of the output work setting layer. This allows for more precise tuning of the threshold stresses of the resulting devices.

[0099] The invention is defined by the main claim and the dependent claims. The subclaims describe further embodiments of the invention.

Claims

[1] Device with: a first group of nanostructures (66) on a substrate (50), wherein the first group of nanostructures (66) has a first channel region; a second group of nanostructures (66) on the substrate (50), wherein the second group of nanostructures has a second channel region; a dielectric gate layer (112) enclosing each of the first and second groups of nanostructures (66); a first work function setting layer (114A) on the dielectric gate layer (112) of the first group of nanostructures (66), wherein the first work function setting layer (114A) surrounds each of the first group of nanostructures (66) and the first work function setting layer (114A) has an n work function metal; an adhesive layer (114B) on the first work function setting layer (114A), wherein the adhesive layer (114B) encloses each of the first group of nanostructures, and the adhesive layer (114B) comprises titanium aluminum carbide, tantalum aluminum carbide or silicon-doped tantalum aluminum carbide; a protective layer (114F) between the first work function setting layer (114A) and the adhesive layer (114B) on the first group of nanostructures (66), wherein the protective layer (114F) surrounds each of the first group of nanostructures (66) and comprises amorphous silicon; wherein the adhesive layer (114B) fills a region between respective parts of the protective layer (114F) on adjacent nanostructures of the first group of nanostructures (66) and thus separates the respective parts of the protective layer (114F) on adjacent nanostructures of the first group of nanostructures (66); a second work function setting layer (114C, 114D) on the adhesive layer (114B) of the first group of nanostructures (66) and on the dielectric gate layer (112) of the second group of nanostructures (66), wherein the second work function setting layer (114C, 114D) has a p-work function metal and the p-work function metal is different from the n-work function metal; and a fill layer (114E) on the second exit work adjustment layer (114C, 114D). [2] Device according to claim 1, wherein the second output work adjustment layer (114C, 114D) fills a region between respective parts of the dielectric gate layer (112) on adjacent nanostructures of the second group of nanostructures (66) and thus separates the respective parts of the dielectric gate layer (112) on adjacent nanostructures of the second group of nanostructures (66). [3] Device according to claim 1 or 2, wherein the filler layer (114E) does not extend between adjacent nanostructures (66) of the second group of nanostructures (66). [4] Procedure with the following steps: Fabricating a first group of nanostructures (66) and a second group of nanostructures (66) on a substrate (50), wherein the first group of nanostructures (66) has a first channel region and the second group of nanostructures (66) has a second channel region; Fabricating a dielectric gate layer (112) comprising a first part and a second part, wherein the first part is deposited on the first channel region and the second part is deposited on the second channel region; Establishing a first work function setting layer (114A) on the first part of the dielectric gate layer (112) and the second part of the dielectric gate layer (112); Producing a protective layer (114F) on the first work function setting layer (114A) on the first group of nanostructures (66), wherein the protective layer comprises amorphous silicon; Forming an adhesive layer (114B) on the protective layer (114F) on the first group of nanostructures (66) and on the first work function setting layer (114A), wherein the adhesive layer (114B) comprises titanium aluminum carbide, tantalum aluminum carbide or silicon-doped tantalum aluminum carbide; Removal of the adhesive layer (114B) and the first exit work setting layer (114A) from the second part of the dielectric gate layer (112); Forming a second output work setting layer (114C, 114D) on the remaining adhesive layer (114B) and the second part of the dielectric gate layer (112); and Establish a fill layer (114E) on the second exit work adjustment layer (114C, 114D). [5] Method according to claim 4, wherein the first exit work setting layer (114A) comprises an n exit work metal and wherein the second exit work setting layer (114C, 114D) comprises a p exit work metal. [6] The method of claim 4 or 5, further comprising: Prior to fabricating the first output work setting layer (114A), a sacrificial layer (116A) is fabricated on the second part of the dielectric gate layer (112) between adjacent nanostructures (66) of the second group of nanostructures (66), wherein the first output work layer (114A) is fabricated on the sacrificial layer (116A) and the second part of the dielectric gate layer (112). [7] Method according to claim 6, wherein the production of the sacrificial layer (116A) on the second part of the dielectric gate layer (112) between adjacent nanostructures (66) of the second group of nanostructures (66) further comprises: Producing a first sacrificial layer (116A) on the first part and the second part of the dielectric gate layer (112); Trimming the first sacrificial layer (116A) to expose parts of the first part and the second part of the dielectric gate layer (112), leaving parts of the first sacrificial layer (116A) between adjacent nanostructures (66) of both the first and second group of nanostructures (66) after trimming; Producing a second sacrificial layer (116B) on the exposed parts of the first part and the second part of the dielectric gate layer (112) and the remaining parts of the first sacrificial layer (116A); Removal of the first and second sacrificial layers (116A, 116B) from the first group of nanostructures (66) to expose the first part of the dielectric gate layer (112); and Trimming the second sacrificial layer (116B) to expose parts of the second part of the dielectric gate layer (112), leaving parts of the first sacrificial layer (116A) between adjacent nanostructures (66) of the second group of nanostructures (66) after trimming. [8] Method according to any one of claims 4 to 7, wherein the production of the first work function setting layer (114A) comprises the deposition of titanium aluminum carbide by an ALD process, the ALD process being carried out with titanium chloride and with triethylaluminium, the ALD process being carried out at a temperature in a range of 100 °C to 600 °C, and the ALD process being carried out at a pressure in a range of 133 Pa to 133 hPa. [9] Method according to claim 8, wherein the ALD process has the same number of pulses with titanium chloride and with triethylaluminium in each ALD cycle. [10] Method according to claim 8, wherein the ALD process has more pulses with triethylaluminium than with titanium chloride in each ALD cycle. [11] Procedure with the following steps: Fabricating a first group of nanostructures (66) and a second group of nanostructures (66) on a substrate (50), wherein the first group of nanostructures (66) has a first channel region and the second group of nanostructures (66) has a second channel region; Producing (202) a dielectric gate layer (112) on the first channel region and on the second channel region; Fabrication (204, 206, 208, 210, 212) of a sacrificial layer (116A) between the second group of nanostructures (66); Fabricating (214) an n-work function setting layer (114A) on the dielectric gate layer (112) and the sacrificial layer (116A), wherein the n-work function setting layer (114A) encloses each of the first group of nanostructures (66); Producing a protective layer (114F) on the n-work function setting layer (114A) on the first group of nanostructures (66), wherein the protective layer comprises amorphous silicon; Producing an adhesive layer (114B) on the protective layer (114F) on the first group of nanostructures (66) and on the n-work function setting layer (114A), wherein the adhesive layer (114B) surrounds each of the first group of nanostructures (66), and the adhesive layer (114B) comprises titanium aluminum carbide, tantalum aluminum carbide or silicon-doped tantalum aluminum carbide; Removal (216) of the adhesive layer (114B), the n-output work setting layer (114A) and the sacrificial layer (116A) from the dielectric gate layer (112) on the second channel region; Fabricating (218) a p-work function setting layer (114C, 114D) on the adhesive layer (114B) on the first group of nanostructures (66) and the dielectric gate layer (112) on the second channel region; and Producing (220) a fill layer (114E) on the p-output work setting layer (114C, 114D). [12] Method according to claim 11, wherein the production of a sacrificial layer (116A) between the second group of nanostructures (66) further comprises: Creating a first sacrificial layer (116A) on the dielectric gate layer (112); Trimming the first sacrificial layer (116A) to expose parts of the dielectric gate layer (112), leaving parts of the first sacrificial layer (116A) between adjacent nanostructures (66) of both the first and second group of nanostructures (66) after trimming; Producing a second sacrificial layer (116B) on the exposed parts of the dielectric gate layer (112) and the remaining parts of the first sacrificial layer (116A); Removal of the first and second sacrificial layers (116A, 116B) from the first group of nanostructures (66) to expose the dielectric gate layer (112) on the first channel region; and Trimming the second sacrificial layer (116B) to expose parts of the dielectric gate layer (112) on the second channel region, leaving parts of the first sacrificial layer (116A) between adjacent nanostructures (66) of the second group of nanostructures (66) after trimming. [13] Method according to claim 11 or 12, wherein producing the n-work function setting layer (114A) comprises depositing titanium aluminum carbide using an ALD process, the ALD process comprising performing multiple ALD cycles, each ALD cycle comprising pulses with titanium chloride and with triethylaluminium, the ALD process being performed at a temperature in a range of 100 °C to 600 °C, the ALD process being performed at a pressure in a range of 133 Pa to 133 hPa, the ALD process having more pulses with triethylaluminium than with titanium chloride in each ALD cycle.

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