PHOTODETECTOR WITH DOUBLE-DOTED SEMICONDUCTOR MATERIAL

Abstract

Comprehensive structure: a photodetector (14) in a semiconductor substrate (12); and a semiconductor material (24) on the photodetector (14), wherein the semiconductor material (24) comprises a semiconductor material of a first dopant type contacting an upper surface of the photodetector (14), a semiconductor material of a second dopant type contacting the upper surface of the photodetector (14), and intrinsic semiconductor material (24c) contacting the upper surface of the photodetector (14) and separating the semiconductor material of the first dopant type from the semiconductor material of the second dopant type.

Description

BACKGROUND

[0001] The present disclosure relates to semiconductor structures and in particular a photodetector and manufacturing process.

[0002] Photodetectors are sensors for light or other electromagnetic radiation. Semiconductor-based photodetectors typically feature a PN junction that converts light photons into an electric current. The absorbed photons create electron-hole pairs in the depletion region. The PN junction of a photodetector is reverse-biased, so that without an optical input signal, only a very small reverse saturation current flows through the photodetector.

[0003] Photodetectors have a number of performance metrics, also called figures of merit, by which they can be characterized and compared. One such metric is dark current. Dark current is the current that flows through a photodetector even in the absence of light. Photodetectors can also generate noise during this process, which is detrimental to performance. This type of noise is dark current noise, which can be reduced by lowering the reverse saturation current through material improvements and transition structure optimization.

[0004] In the publication “64Gb / s PAM4 and 160Gb / s 16QAM modulation reception using a low-voltage Si-Ge waveguide-integrated APD” by Jin Zhang et al. (Optics Express, Vol. 28, 2020, No. 16, pp. 23266-23273), an avalanche photodiode is taught, comprising a Ge absorption layer arranged over a pin structure formed in a Si substrate. Such a structure is also known from US 2022 / 0069153 A1.

[0005] From US patent 2018 / 0061883A1, an optical sensor is also known, comprising a first sensor formed in a Si substrate for measuring visible light and a second sensor arranged vertically above it for measuring light in the near-infrared range. Furthermore, from US patent 5994724A, a photodetector is known, comprising a plurality of Si and SiGe layers grown alternately on top of each other and epitaxially. BRIEF SUMMARY

[0006] In one aspect of the disclosure, a structure comprises: a photodetector in a semiconductor substrate; and a semiconductor material on the photodetector, wherein the semiconductor material comprises a semiconductor material of a first dopant type contacting an upper surface of the photodetector, a semiconductor material of a second dopant type contacting the upper surface of the photodetector, and intrinsic semiconductor material contacting the upper surface of the photodetector and separating the semiconductor material of the first dopant type from the semiconductor material of the second dopant type.

[0007] In one aspect of the disclosure, a structure comprises: a semiconductor substrate; an insulator material above the semiconductor substrate; a photodetector within a trench of the semiconductor substrate; a semiconductor material of a first dopant type on a first section of the photodetector; a semiconductor material of a second dopant type on a second section of the photodetector; and an intrinsic semiconductor material that contacts a third section of the photodetector between the semiconductor material of the first dopant type and the semiconductor material of the second dopant type.

[0008] In one aspect of the disclosure, a method comprises: forming a photodetector in a semiconductor substrate; and forming a semiconductor material on the photodetector, wherein the semiconductor material comprises a semiconductor material of a first dopant type contacting an upper surface of the photodetector, a semiconductor material of a second dopant type contacting the upper surface of the photodetector, and intrinsic semiconductor material contacting the upper surface of the photodetector and separating the semiconductor material of the first dopant type from the semiconductor material of the second dopant type. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The present disclosure is described in detail below with reference to the aforementioned multitude of drawings, using non-limiting examples of exemplary embodiments of the present disclosure. Fig. Figure 1 shows a photodetector with doped sidewalls according to aspects of the present disclosure. Fig. Figure 2 shows a photodetector with doped sidewalls according to additional aspects of the present disclosure. Fig. Figure 3 shows a photodetector without doped sidewalls according to aspects of the present disclosure. Fig. Figure 4 shows a photodetector without doped sidewalls according to additional aspects of the present disclosure. Fig. 5A-5C show processing steps for manufacturing the structure of Fig. 1 according to aspects of the present revelation. DETAILED DESCRIPTION

[0010] The present disclosure relates to semiconductor structures and, in particular, a photodetector and fabrication method. Specifically, the photodetector can be a Ge photodetector with a doubly doped polysilicon or silicon material separated by an intrinsic region on one top side of the Ge material. Advantageously, the photodetector provides improved DC (dark current) and AC (frequency vs. QE) performance.

[0011] The photodetector of this disclosure can be fabricated in several ways using several different tools. Generally, however, the methodologies and tools used are those for forming structures with dimensions on the micrometer and nanometer scale. The methodologies, i.e., technologies, employed to fabricate the photodetector of this disclosure were adopted from integrated circuit (IC) technology. For example, the structures are fabricated on wafers and realized in material films that are structured on the top side of a wafer by photolithographic processes. In particular, the fabrication of the photodetector uses three basic building blocks: (i) deposition of thin material films on a substrate, (ii) application of a structured mask to the top side of the films by photolithographic imaging, and (iii) selective etching of the films with respect to the mask.Additionally, as is known in the art, pre-cleaning processes can be used to remove any contaminants from etched surfaces. Furthermore, if necessary, rapid thermal annealing processes can be used to drive in dopants or material layers, as is known in the art.

[0012] Fig. Figure 1 shows a photodetector according to aspects of the present disclosure. In particular, the structure comprises 10 of Fig. 1. A semiconductor substrate 12 comprising a photodetector 14. In embodiments, the semiconductor substrate 12 may be composed of any suitable material comprising, but not limited to, Si. In further embodiments, the semiconductor substrate 12 may comprise any suitable crystallographic orientation (e.g., a crystallographic (100), (110), (111), or (001) orientation).

[0013] The photodetector 14 can, for example, be composed of Ge material. In embodiments, the Ge material 12 can be intrinsic Ge material provided within a trench of the semiconductor substrate 12. A collar 16 can surround the photodetector 14, i.e., line the trench of the semiconductor substrate 12. In this way, the collar 16 can abut the photodetector and can be provided between the photodetector 14 and the semiconductor substrate 12. In embodiments, the collar 16 can be an insulator material, e.g., oxide.

[0014] Still referring to Fig. 1. Flat trench insulation structures 18 can be provided within the semiconductor substrate 12 on sides of the photodetector 14. An insulator material 20 can be provided above the semiconductor substrate 12. In embodiments, the insulator material 20 can be an oxide material. Optional doped regions 22 can be provided in the semiconductor substrate 12 below the insulator material 20. The optional doped regions 22 can be p-doped or n-doped regions that are isolated from the photodetector 14 by the collar 16. The optional doped regions 22 can be isolated from other structures by the flat trench insulation structures 18. The optional n-doped regions 22 can be biased to provide the lowest dark current.

[0015] A semiconductor material 24 is provided above the photodetector 14 and the insulator material 20. In embodiments, the semiconductor material 24 can be epitaxially grown semiconductor material in direct contact with the photodetector 14 and the insulator material 20. As should be clear to those skilled in the art, the semiconductor material 24 can be polysilicon above the insulator material 20 and epitaxial silicon and polysilicon above the photodetector 14.

[0016] The semiconductor material 24 comprises a first doped region 24a, a second doped region 24b, and an intrinsic region 24c between the first doped region 24a and the second doped region 24b. This provides a doubly doped polysilicon / silicon region, separated by an intrinsic region, on the top surface of the photodetector 14. In embodiments, the first doped region 24a can be a P+ doped region (e.g., boron or gallium), and the second doped region 24b can be an N+ doped region (e.g., arsenic or phosphorus). Thus, the semiconductor material 24 above the photodetector 14 can form a PiN photodiode (e.g., P+ polysilicon, intrinsic Si, and N+ polysilicon).

[0017] Fig. Figure 2 shows a photodetector with doped sidewalls according to additional aspects of the present disclosure. In structure 10a of Fig. 2. The flat trench insulation structures 18 can abut the collar 16. In addition, in this embodiment, the doped regions 22 can extend below the flat trench insulation structures 18 within the semiconductor substrate 12. The remaining features are similar to structure 10 of Fig. 1.

[0018] Fig. Figure 3 shows a photodetector without doped sidewalls according to aspects of the present disclosure. In particular, it comprises, as in Fig. Figure 3 shows structure 10b comprising the photodetector 14 and the collar 16 surrounding the photodetector 14; however, in this embodiment, there is no dopant in contact with the collar 16 or the photodetector 14. The remaining features are similar to structure 10 of Figure 3. Fig. 1.

[0019] Fig. Figure 4 shows a photodetector without doped sidewalls according to additional aspects of the present disclosure. In particular, as shown in Fig. Figure 4 shows structure 10c, the photodetector 14, the bund 16 surrounding the photodetector 14, and the insulation structures 18 adjacent to the bund 16. However, similar to the one in Fig. In the structure shown in Figure 3, in this embodiment, there is no dopant material in contact with the collar 16 or the photodetector 14. The remaining features are similar to structure 10a of Figure 3. Fig. 2.

[0020] Fig. 5A-5C show processing steps for manufacturing structure 10 of Fig. 1. In particular, it shows Fig. 5A Flat trench insulation structures 18 formed in the semiconductor substrate 12 and the insulator material 20. The insulator material 20 can be formed by a conventional CVD process. In embodiments, the flat trench insulation structures 18 can be formed by conventional lithography, etching, and deposition processes known to those skilled in the art. For example, a resist formed over the semiconductor layer 12 is exposed to energy (light) and developed to form a structure (opening). An etching process with a selective chemistry, e.g., reactive ion etching (RIE), is used to transfer the structure from the structured photoresist to the semiconductor substrate 12 to form one or more trenches in the semiconductor substrate 12.Following resist removal by a conventional oxygen ashing process or other known stripping agents, the insulator material (e.g., SiO2) can be deposited by any conventional deposition process, e.g., chemical vapor deposition (CVD) processes. Any remaining material on the surface of the semiconductor substrate 12 can be removed by conventional chemical mechanical polishing (CMP) processes. It should be clear to those skilled in the art that the shallow trench insulation structures 18 can be larger by extending further inward, e.g., in . Fig. 2 and Fig. 4 shown, by providing a larger trench during the structuring step.

[0021] In Fig. 5B can form a trench 25 in the semiconductor substrate 12 and insulator material 20 using conventional lithography and etching processes as described above. An insulator material 16 can be deposited on the structure, e.g., within the trench 25 and the insulator material 20, using a conventional deposition process followed by an anisotropic etching process that includes a lateral etching component which etches the insulator material 16 at the bottom of the trench 25 and at the top surface of the insulator material 20. In this way, the insulator material 16 forms a ridge on the sidewalls of the trench 25. It should be clear to those skilled in the art that if the shallow trench insulation structures 18 are larger, they can extend up to the ridge on the sidewalls of the trench 25.

[0022] In an optional embodiment, doped regions 22 can be formed in the semiconductor substrate 12. In embodiments, the doped regions 22 can be formed by conventional ion implantation processes as described in more detail below. The doped regions 22 can be formed before or after the formation of the trench 25 and / or the shallow trench isolation structures 18, and can be composed of p or n dopants. In the Fig. 3 and Fig. In the embodiments shown in 4, doping is excluded.

[0023] In Fig. In 5C, a semiconductor material is epitaxially grown within the trench 25 to form the photodetector 14. In embodiments, the semiconductor material can be Ge material. In embodiments, the Ge material is grown upwards from the bottom of the trench 25. This results in the photodetector 14 having a collar 16 that isolates the photodetector 14 from the doped regions 22.

[0024] Following the formation of the photodetector 14, a semiconductor material 24 can be epitaxially grown on the photodetector 14 and the insulator material 20. The epitaxial growth process starts as a selective process on the photodetector 14 and continues as a non-selective process over the insulator material 20. As should be clear to those skilled in the art, the selective and non-selective processes result in a polysilicon material on the insulator material 20 and single-crystal (intrinsic) silicon material on the photodetector 14. In embodiments, due to the proximity of the insulator material 20, polysilicon can also be present at the edges of the photodetector 14.

[0025] Referring again to Fig.1. The semiconductor material 24 can be subjected to ion implantation processes to form the doped regions 24a, 24b. During these ion implantation processes, the semiconductor material 24 is masked and protected over a section of the photodetector 14 to maintain its intrinsic properties, e.g., intrinsic region 24c between the doubly doped regions 24a, 24b.

[0026] In embodiments, the ion implantation processes introduce a concentration of different dopants of opposite conductivity type into the semiconductor material 24. In embodiments, respective structured implantation masks can be used to define the selected regions 24a, 24b that are exposed for implantation. The implantation mask used to select the exposed region for forming the P+ region 24a is stripped after implantation and in front of the implantation mask used to form the N+ region 24b. Similarly, the implantation mask used to select the exposed region for forming the N+ region 24b is stripped after implantation has been performed. It should be clear that both masks can be used to overlap at the intrinsic region 24c such that this region is not subjected to any implantation processes.As is known in engineering, implantation masks can comprise a layer of a photosensitive material, such as an organic photoresist, applied by a spin-coating process, pre-baked, exposed to light projected through a photomask, baked after exposure, and developed with a chemical developer. The implantation masks possess a thickness and stopping power sufficient to block masked areas from receiving a dose of the implanted ions.

[0027] The P+ region 24a is doped with p-type dopants, e.g., boron (B), gallium, etc., and the N+ region 24b is doped with n-type dopants, e.g., arsenic (As), phosphorus (P), and antimony (Sb), among other suitable examples. In embodiments, the intrinsic region 24c is located between the P+ region 24a and the N+ region 24b, each of which is positioned above the photodetector 14. In this way, the P+ and N+ regions are separated by intrinsic silicon above the photodetector 14.

[0028] The photodetector can be used in a system-on-a-chip (SoC) technology. An SoC is an integrated circuit (also known as a "chip") that integrates all the components of an electronic system onto a single chip or substrate. Because the components are integrated onto a single substrate, SoCs consume far less power and occupy much less space than multi-chip designs with equivalent functionality. For this reason, SoCs are becoming the dominant technology in mobile computing (such as in smartphones) and edge computing markets. SoCs are also used in embedded systems and the Internet of Things (IoT).

[0029] The process(s) described above is / are used in the fabrication of integrated circuit chips. The resulting integrated circuit chips may be distributed by the manufacturer in raw wafer form (that is, as a single wafer containing multiple unpackaged chips), as bare dies, or in packaged form. In the latter case, the chip is mounted in a single-chip package (such as a plastic substrate with conductors attached to a motherboard or other higher-level support) or in a multi-chip package (such as a ceramic substrate having one or both surface interconnects or buried interconnects). In each case, the chip is then integrated with other chips, discrete switching elements, and / or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) a final product.The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products that feature a display, a keyboard or other input device, and a central processor.

Claims

[1] Structure encompassing: a photodetector (14) in a semiconductor substrate (12); and a semiconductor material (24) on the photodetector (14), wherein the semiconductor material (24) comprises a semiconductor material of a first dopant type contacting an upper surface of the photodetector (14), a semiconductor material of a second dopant type contacting the upper surface of the photodetector (14), and intrinsic semiconductor material (24c) contacting the upper surface of the photodetector (14) and separating the semiconductor material of the first dopant type from the semiconductor material of the second dopant type. [2] Structure according to claim 1, wherein the first dopant type comprises a P+ dopant type and the second dopant type comprises an N+ dopant type. [3] Structure according to claim 2, wherein the intrinsic semiconductor material (24c) comprises Si material. [4] Structure according to claim 3, wherein the N+ dopant type and the P+ dopant type comprise polysilicon / silicon material above the photodetector (14). [5] Structure according to claim 3, wherein the photodetector (14) comprises Ge material. [6] Structure according to any one of claims 1 to 5, wherein the semiconductor material (24) directly contacts the upper surface of the photodetector (14). [7] Structure according to claim 6, wherein the semiconductor material (24) comprises epitaxial semiconductor material that directly contacts the upper surface of the photodetector (14). [8] Structure according to claim 7, further comprising an insulator material (20) beneath the epitaxial semiconductor material (24c). [9] Structure according to claim 8, wherein the photodetector (14) is within a trench (25) of a semiconductor substrate (12), an insulator bundle (16) is on side walls of the trench (25) and the insulator material (20) is above the semiconductor substrate (12). [10] Structure according to one of claims 1 to 8, further comprising an insulator bundle (16) which abuts side walls of the photodetector (14). [11] Structure according to claim 10, further comprising dopant regions (22) on sides of the insulator bundle (16) which isolates the dopant regions (22) from the photodetector (14). [12] Structure encompassing: a semiconductor substrate (12); an insulating material (20) over the semiconductor substrate (12); a photodetector (14) within a trench (25) of the semiconductor substrate; a semiconductor material (24a) of a first dopant type on a first section of the photodetector (14); a semiconductor material (24b) of a second dopant type on a second section of the photodetector (14); and an intrinsic semiconductor material (24c) that contacts a third section of the photodetector (14) between the semiconductor material (24a) of the first dopant type and the semiconductor material (24b) of the second dopant type. [13] Structure according to claim 12, wherein the first dopant type comprises a P+ dopant type, the second dopant type comprises an N+ dopant type and the intrinsic semiconductor material (24c) is between the semiconductor material (24a) of the first dopant type and the semiconductor material (24b) of the second dopant type. [14] Structure according to claim 12 or 13, further comprising an insulator bundle (16) lining the trench (25). [15] Structure according to claim 14, further comprising dopant regions (22) within the semiconductor substrate (12) which are isolated from the photodetector (14) by the insulator bundle (16) lining the trench (25). [16] Structure according to one of claims 12 to 15, wherein the third section of the photodetector (14) is between the first section of the photodetector (14) and the second section of the photodetector (14). [17] Structure according to any one of claims 12 to 16, wherein the semiconductor material (24a) of the first dopant type and the semiconductor material (24b) of the second dopant type extend over the insulator material (20). [18] Structure according to any one of claims 12 to 17, wherein the photodetector (14) comprises Ge material and the intrinsic semiconductor material (24c) comprises Si material. [19] Structure according to claim 18, wherein the semiconductor material (24a) of the first dopant type, the semiconductor material (24b) of the second dopant type and the intrinsic semiconductor material (24c) comprise a PIN diode. [20] Procedure encompassing: Formation of a photodetector (14) in a semiconductor substrate (12); and Forming a semiconductor material (24) on the photodetector (14), wherein the semiconductor material (24) is a semiconductor material of a first dopant type contacting an upper surface of the photodetector (14), a semiconductor material of a second dopant type contacting the upper surface of the photodetector (14), and intrinsic semiconductor material (24c) which contacts the upper surface of the photodetector (14) and separates the semiconductor material (24a) of the first dopant type from the semiconductor material (24b) of the second dopant type.

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