DISPLAY DEVICE

Abstract

A display device (100, 500, 700) comprising a substrate (110); a control transistor (DT) on the substrate (110); an adhesive layer (AD) on the substrate (110); a light-emitting diode (LED) on the adhesive layer (AD) overlapping the control transistor (DT) and comprising a first semiconductor layer (121) on the adhesive layer (AD), an emission layer (122) on the first semiconductor layer, a second semiconductor layer (123) on the emission layer (122), a first electrode (124) on the first semiconductor layer (121) and a second electrode (125) on the second semiconductor layer (123), wherein the first electrode (124) is located closer to the substrate than the emission layer (122) and the second electrode (125) is located higher than the first electrode (124);a reflective connecting electrode (CE1) covering a lower lateral surface of the light-emitting diode (LED) and the first electrode (124), and electrically connecting the first electrode (124) to the drive transistor (DT); and a transparent connecting electrode (CE2) that overlaps the reflective connecting electrode (CE1), contacts an upper surface of the light-emitting diode (LED), and electrically connects the second electrode (125) to a current conductor (VDD) on the substrate (110).

Description

Background AREA

[0001] The present disclosure relates to a display device, in particular a display device that improves the front luminance. DISCUSSION OF THE STATE OF THE TECHNOLOGY

[0002] Display devices are used in various applications, such as computer monitors, televisions, and mobile phones. Among these display devices, some use an organic light-emitting diode (OLED) display, which is a self-illuminating device, while others use a liquid crystal display (LCD), which utilizes a separate light source. The range of display device applications being researched is diverse, extending from personal digital assistants and computer and television monitors to large-area displays with reduced size and weight, which are currently under investigation.

[0003] Furthermore, light-emitting diode (LED) displays are gaining increasing attention as the next generation of display technology. Because LEDs contain inorganic rather than organic materials, they offer superior reliability, resulting in a longer lifespan than liquid crystal displays or organic light-emitting diode displays. In addition, inorganic LEDs are characterized by a fast light-emitting amplitude, excellent luminous efficacy, and high impact resistance, enabling them to exhibit excellent stability and display images with high luminance. SUMMARY

[0004] Accordingly, one objective of the present disclosure is to provide a display device with improved front luminance. Another objective of the present disclosure is to provide a display device with improved light emission efficiency from the LEDs. A further objective of the present disclosure is to provide a display device in which process costs and time are saved by reducing the number of masks used in the manufacturing process. The objectives of the present disclosure are not limited to those mentioned above, and other objectives not mentioned above can be clearly understood by those skilled in the art from the following descriptions. According to one aspect of the present disclosure, a display device according to claim 1 is provided. Exemplary embodiments of the display device are described in the dependent claims.

[0005] According to one aspect of the present disclosure, a display device comprises a substrate in which a plurality of subpixels are defined; a plurality of drive transistors in each of the plurality of subpixels; a plurality of light-emitting diodes in each of the plurality of subpixels; a first connecting electrode covering part of a lower lateral surface of the plurality of light-emitting diodes and formed of a reflective conductive material; and a second connecting electrode in contact with the upper surfaces of the plurality of light-emitting diodes and formed of a transparent conductive material.

[0006] According to another aspect of the present disclosure, a display device comprises a substrate in which a plurality of sub-pixels are defined; a plurality of drive transistors in each of the plurality of sub-pixels; a first planarization layer on the plurality of drive transistors; a plurality of light-emitting diodes on the first planarization layer in each of the plurality of sub-pixels; a first connecting electrode electrically connected to the plurality of light-emitting diodes and formed from a reflective conductive material; a second connecting electrode electrically connected to the plurality of light-emitting diodes and formed from a transparent conductive material; and a second planarization layer between the first connecting electrode and the second connecting electrode, the second planarization layer comprising a black material.Further details of the embodiments are contained in the detailed description and the drawings.

[0007] According to at least one embodiment of the present disclosure, the number of manufacturing processes for a planarization layer is reduced to decrease the number of masks used for the manufacturing processes, thereby saving process costs and time while simultaneously achieving process optimization. Furthermore, the number of manufacturing processes is reduced by using the planarization layer as a mask to achieve process optimization. In addition, laterally traveling light is reflected forward to improve the front luminance, thus enabling the LED to be driven with low power.

[0008] Therefore, the amount of light contained in the LED is reduced to improve the luminous efficacy, allowing the LED to be driven with lower power. The effects described herein are not limited to the examples given above, and the present description includes various other effects. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above-mentioned and other objectives, features and other advantages of the present disclosure will be more readily understood by the person skilled in the art with reference to the following detailed description in conjunction with the accompanying drawings, in which Fig. 1 a schematic diagram of a display device according to an embodiment of the present disclosure; Fig. 2 an enlarged cross-sectional view of a display device according to an embodiment of the present disclosure; Fig. 3A to 3E are views to explain a manufacturing process of a display device according to an embodiment of the present disclosure; Fig. 4 is a diagram illustrating a luminance corresponding to a viewing angle of a display device according to an embodiment of the present disclosure; Fig. 5 is an enlarged cross-sectional view of a display device according to a further embodiment of the present disclosure; Fig. Figures 6A to 6D are views illustrating a manufacturing process for a display device according to a further embodiment of the present disclosure; and Fig. 7 is an enlarged cross-sectional view of a display device according to a further embodiment of the present disclosure. DETAILED DESCRIPTION OF THE EXECUTION FORM

[0010] The advantages and characteristics of the present disclosure and a method for achieving these advantages and characteristics will become clear with reference to the embodiments described in detail below in conjunction with the accompanying drawings. However, the present disclosure is not limited to the embodiments disclosed herein, but can be implemented in various forms. The embodiments serve only as examples to enable those skilled in the art to fully understand the disclosures and the scope of the present disclosure. The features of different embodiments of the present disclosure can be partially or completely coupled or combined with one another and can be interlocked and operated in technically different ways, and the embodiments can be implemented independently or in association with one another.Furthermore, the term "can" used here contains all meanings and definitions of the term "may".

[0011] The shapes, sizes, ratios, angles, numbers, and the like illustrated in the accompanying drawings to describe embodiments of the present disclosure are merely examples, and the present disclosure is not limited to them. The same reference numerals generally denote the same elements throughout the description. Furthermore, a detailed explanation of known related technologies may be omitted from the following description of the present disclosure in order not to obscure the subject matter of the present disclosure unnecessarily. Terms used herein, such as "including," "with," and "featuring," are generally intended to permit the addition of other components unless the terms are used with the term "only." Any reference to the singular form may also include the plural form unless expressly stated otherwise.

[0012] Components are interpreted as containing a normal error range, even if this is not explicitly stated. When the positional relationship between two parts is described using terms such as "on," "above," "below," and "next to," one or more parts may be positioned between the two parts unless the terms are used with "immediately" or "directly." If one element or layer is positioned "on" another element or layer, that other layer or element may be positioned directly on top of or between the other element.

[0013] Although the terms "first," "second," and the like are used to describe different components, these components are not limited to these terms. These terms are used merely to distinguish one component from the others. Therefore, a first component mentioned below may be a second component in a technical concept of the present disclosure. The same reference numerals generally denote identical elements throughout the entire description.

[0014] The size and thickness of each component illustrated in the drawing are shown for the sake of simplicity, and the present disclosure is not limited to the size and thickness of the illustrated component. The features of different embodiments of the present disclosure may be partially or completely incorporated or combined, and may be meshed and operated in technically different ways, and the embodiments may be carried out independently or in association with another embodiment.

[0015] The present disclosure is described in detail below with reference to the accompanying drawings. In particular, Fig. 1 a schematic diagram of a display device according to an embodiment of the present disclosure. Fig. Figure 1 illustrates the display device 100, including a display panel PN, a gate driver GD, a data driver DD, a plurality of sub-pixels SP and a timing control device TC.

[0016] With reference to Fig. The display device 100 includes the display panel PN, which contains the majority of the sub-pixels SP, the gate driver GD, and the data driver DD, which supply various signals to the display panel PN. Furthermore, the timing device TC controls the gate driver GD and the data driver DD.

[0017] A driver, such as a gate driver GD, a data driver DD, and a timing device TC, can be connected to the display panel PN in various ways. For example, the gate driver GD can be placed in a non-active area NA in a gate-in-panel (GIP) manner, or between the majority of sub-pixels SP in an active area AA in a gate-in-active-area (GIA) manner.

[0018] Furthermore, the display panel PN shows images to the user and contains intersecting sub-pixels (SP), scan lines (SL), and data lines (DL). As shown, each sub-pixel SP is connected to both the scan lines (SL) and the data lines (DL). Additionally, each sub-pixel SP can be connected to a high-potential current line, a low-potential current line, and a reference line.

[0019] As in Fig. As shown in Figure 1, the display panel PN contains an active area AA and an inactive area NA surrounding the active area AA. The active area AA displays images in the display device 100 and contains subpixels SP, which can be configured to form a plurality of pixels, as well as a circuit for driving the subpixels SP. Furthermore, the subpixel SP is a minimal unit that forms the active area AA, and n subpixels SP can form a pixel. Each subpixel SP contains a light-emitting diode (LED) and a thin-film transistor for driving the LED. In addition, the LEDs can be defined in different ways depending on the type of display panel PN. For example, if the display panel PN is an inorganic light-emitting display panel, the LED can be a standard light-emitting diode (LED) or a micro-LED.

[0020] The active area AA also contains a plurality of signal lines that supply various signals to the sub-pixels SP. For example, the signal lines can include a plurality of data lines DL, which supply a data voltage to each sub-pixel SP, and a plurality of scan lines SL, which supply a gate voltage to each sub-pixel SP. As shown in Fig. As shown in Figure 1, the scan lines SL extend in one direction within the active area AA and are connected to the subpixels SP, while the data lines DL extend in a different direction within the active area AA and are also connected to the subpixels SP. Furthermore, the active area AA contains a low-potential current line, a high-potential current line, and various other signal lines, which may be additionally arranged but are not limited to these.

[0021] Furthermore, no images are displayed in the inactive area NA, and a connecting line may be provided that transmits a signal to the subpixel SP of the active area AA, a pad electrode, or a driver IC, such as a gate driver IC or a data driver IC. The display panel PN also contains a plurality of pixels, each of which is composed of a plurality of subpixels SP. Each subpixel SP contains a light-emitting diode (LED) and pixel circuitry, allowing each subpixel SP to emit light independently. A pixel can also contain a first subpixel, a second subpixel, and a third subpixel. For example, a pixel can be configured by a pair of first subpixels, a pair of second subpixels, and a pair of third subpixels.Furthermore, every first subpixel is a red subpixel, every second subpixel is a green subpixel, and every third subpixel is a blue subpixel, but this is not limited to these configurations. In other examples, a pixel can be configured by a pair of first subpixels, a pair of second subpixels, a pair of third subpixels, and a pair of fourth subpixels, where every fourth subpixel is a white subpixel, a yellow subpixel, a magenta subpixel, or a pair of differently shaded / lighter blue pixels.

[0022] Furthermore, multiple LEDs can be arranged within the sub-pixels SP. For example, the LEDs can contain a first LED, a second LED, and a third LED. The first sub-pixel can contain the first light-emitting element, the second sub-pixel can contain the second light-emitting element, and the third sub-pixel can contain the third light-emitting element. Additionally, the first LED can be red, the second LED can be green, and the third LED can be blue.

[0023] Next up is in Fig. Figure 2 shows an enlarged cross-sectional view of a subpixel SP of a display device 100 according to an embodiment of the present disclosure. As shown in Fig. As shown in Figure 2, the sub-pixel SP of the display device 100 contains a substrate 110, a buffer layer 111, a gate insulating layer 112, a first insulating intermediate layer 113a, a second insulating intermediate layer 113b, a passivation layer 114, a first planarization layer 115, an adhesive layer AD, a second planarization layer 116, a third planarization layer 117, a fourth planarization layer 118, a control transistor DT, a light-emitting diode LED, a reflective electrode RE, a light-shielding layer LS, an auxiliary electrode LE, a first connecting electrode CE1, a second connecting electrode CE2, a capacitor Cst and an intermediate electrode TM.

[0024] First, the substrate 110 is a component for supporting various components contained in the display device 100 and can be made of an insulating material. For example, the substrate 110 can be made of glass or resin. Furthermore, the substrate 110 can contain a polymer or plastic or be made of a flexible material.

[0025] Furthermore, as shown, the light-shielding layer LS can be arranged in each sub-pixel SP on the substrate 110. The light-shielding layer LS blocks light that falls from a lower part of the substrate 110 onto an active layer ACT of the drive transistor DT described below. Light falling on the active layer ACT of the drive transistor DT is blocked by the light-shielding layer LS to minimize leakage current. The light-shielding layer LS can contain, but is not limited to, a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0026] Furthermore, the buffer layer 111 can be arranged on the substrate 110 and the light-shielding layer LS. In particular, the buffer layer 111 can reduce the penetration of moisture or contaminants through the substrate 110. For example, the buffer layer 111 can be a single layer or a double layer of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited to this. However, the buffer layer 111 can be omitted depending on the type of substrate 110 or the type of transistor, but is not limited to this.

[0027] Furthermore, the driver transistor DT can be arranged on the buffer layer 111 and, as shown, contains an active layer ACT, a gate electrode GE, a source electrode SE, and a drain electrode DE. The active layer ACT can also be arranged on the buffer layer 111 and be made of a semiconductor material, such as an oxide semiconductor, amorphous silicon, or polysilicon, but is not limited to this.

[0028] Furthermore, the gate insulating layer 112 can be arranged on the active layer ACT, insulating the active layer ACT from the gate electrode GE, and can be a single layer or a double layer of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited to this. The gate electrode GE can be arranged on the gate insulating layer 112 and can contain, but is not limited to, a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof. The gate electrode GE can also consist of multiple layers. For example, the gate electrode GE can consist of a bottom layer of molybdenum (Mo), a middle layer of copper (Cu) or aluminum (Al), and a top layer of titanium (Ti).

[0029] Furthermore, the first insulating layer 113a and the second insulating layer 113b can be arranged on the gate electrode GE and contain contact holes through which the source electrode SE and the drain electrode DE are connected to the active layer ACT. Specifically, the first insulating layer 113a and the second insulating layer 113b are insulating layers for protecting a component located below the first insulating layer 113a and the second insulating layer 113b, and can be, but are not limited to, a single layer or a double layer of silicon oxide (SiOx) or silicon nitride (SiNx).

[0030] Furthermore, the source electrode SE and the drain electrode DE, which are electrically connected to the active layer ACT, can be arranged on the second insulating layer 113b. The source electrode SE and the drain electrode DE can contain, but are not limited to, a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), an alloy thereof, or several layers of different conductive materials.

[0031] Furthermore, the present description details the first insulating layer 113a and the second insulating layer 113b. In other words, a plurality of insulating layers are arranged between the gate electrode GE and the source electrode SE and the drain electrode DE. However, there may also be only one insulating layer between the gate electrode GE and the source electrode SE and the drain electrode DE, and the present disclosure is not limited to this. Furthermore, in addition to the drive transistor DT, the pixel circuit may also include a switching transistor, a sensor transistor, and an emission control transistor, but is not limited to these.

[0032] Furthermore, the intermediate electrode TM can be arranged between the first insulating intermediate layer 113a and the second insulating intermediate layer 113b. As shown in Fig. As shown in Figure 2, the intermediate electrode TM is arranged to overlap the gate electrode GE of the drive transistor DT with the first insulating intermediate layer 113a in between, in order to form a capacitor together with the gate electrode GE of the drive transistor DT, but is not limited to this. The intermediate electrode TM can also contain a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), an alloy thereof, or several layers of different conductive materials, but is not limited to this.

[0033] Furthermore, the auxiliary electrode LE can be arranged on the gate insulating layer 112 and electrically connects the light-shielding layer LS below the buffer layer 111 to either the source electrode SE or the drain electrode DE of the drive transistor DT on the second insulating intermediate layer 113b. For example, the light-shielding layer LS can be electrically connected via the auxiliary electrode LE to either the source electrode SE or the drain electrode DE of the drive transistor DT to avoid acting as a floating gate. Therefore, fluctuations in the threshold voltage of the drive transistor DT caused by the floating light-shielding layer LS can be minimized.Although the light shielding layer LS is connected to the source electrode SE of the control transistor DT in the drawing, the light shielding layer LS can also be connected to the drain electrode DE of the control transistor DT, but is not limited to this.

[0034] Furthermore, the auxiliary electrode LE can be made of the same material or materials as the gate electrode GE, but is not limited to this. The auxiliary electrode LE can contain a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), an alloy thereof, or multiple layers of different conductive materials, but is not limited to this.

[0035] As shown, the capacitor Cst can be arranged on the gate insulating layer 112. In particular, the capacitor Cst can be, as in Fig. Figure 2 shows a first capacitor electrode Cst1 and a second capacitor electrode Cst2. As shown, the first capacitor electrode Cst1 can be located on the gate insulating layer 112, on the same layer as the gate electrode GE and the auxiliary electrode LE, and can be made of the same material or materials as the gate electrode GE and the auxiliary electrode LE, but is not limited to this. The first capacitor electrode Cst1 can be made of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), an alloy thereof, or several layers of different conductive materials, but is not limited to this.

[0036] Furthermore, the second capacitor electrode Cst2 can be arranged on the first insulating layer 113a, on the same layer as the intermediate electrode TM, and can be made of the same material or materials as the intermediate electrode TM, but is not limited to this. The second capacitor electrode Cst2 can contain a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), an alloy thereof, or several layers of different conductive materials, but is not limited to this. The second capacitor electrode Cst2 can be arranged to overlap the first capacitor electrode Cst1 with the first insulating layer 113a in between. The second capacitor electrode Cst2 can also be connected to the source electrode SE of the drive transistor DT.

[0037] Furthermore, the power line VDD can be arranged on the second insulating layer 113b and is electrically connected to the LED together with the control transistor DT, so that the LED emits light. The power line VDD can, for example, be a high-potential current line, but is not limited to this. As in Fig. As shown in Figure 2, the current-carrying conductor VDD is located on the same layer as the source electrode SE and the drain electrode DE and is made of the same material as the source electrode SE and the drain electrode DE, but is not limited to this. The current-carrying conductor VDD can also be a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), an alloy thereof, or several layers of different conductive materials, but is not limited to this.

[0038] Furthermore, the passivation layer 114 can be arranged on the drive transistor DT and the power line VDD, protecting them from the ingress of moisture or contaminants. For example, the passivation layer 114 can be a single layer or a double layer of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited to this. The passivation layer 114 can also be omitted depending on the type of substrate 110 or transistor.

[0039] Furthermore, the first planarization layer 115 can be arranged on the passivation layer 114 and planarize an upper part of the substrate 110 on which the drive transistor DT is arranged. The first planarization layer 115 can also be a single layer or a double layer and, for example, be made of photoresist or an acrylic-based organic material, but is not limited to this.

[0040] As in Fig. As shown in Figure 2, a plurality of reflective electrodes RE are spaced apart and arranged on the first planarization layer 115. Furthermore, the reflective electrodes RE electrically connect the LED to the power line VDD and the drive transistor DT and can act as a reflective plate, reflecting light emitted by the LED back to its top surface. The reflective electrodes RE can contain a conductive material with excellent reflective properties to reflect the light emitted by the LED back to its top surface. Therefore, the reflective electrodes RE can contain various conductive layers, taking into account the light reflection efficiency and resistance.For example, a reflective electrode (RE) can use an opaque conductive layer, such as silver (Ag), aluminum (Al), molybdenum (Mo), titanium (Ti), or an alloy thereof, and a transparent conductive layer, such as indium tin oxide (ITO), but the structure and material of the reflective electrode (RE) are not limited to these. For example, the reflective electrode (RE) can contain multiple layers of different metallic materials or a combination of multiple layers of different metallic materials coated with indium tin oxide (ITO).

[0041] Furthermore, the reflective electrodes RE, as in Fig. Figure 2 shows a first reflective electrode RE1 and a second reflective electrode RE2. Specifically, the first reflective electrode RE1 can electrically connect the driver transistor DT and the light-emitting diode LED. The first reflective electrode RE1 can be connected to the source electrode SE or the drain electrode DE of the driver transistor DT via contact holes formed in the passivation layer 114 and the first planarization layer 115. Furthermore, the first reflective electrode RE1 can be electrically connected to the first electrode 124 of the light-emitting diode LED via a first connecting electrode CE1.

[0042] Furthermore, the second reflective electrode RE2 electrically connects the power line VDD and the light-emitting diode LED. In particular, the second reflective electrode RE2 can be connected to the power line VDD via a contact hole formed in the passivation layer 114 and the first planarization layer 115, and can be electrically connected to the second electrode 125 of the light-emitting diode LED via a second connecting electrode CE2, which is described below.

[0043] Furthermore, the adhesive layer AD is formed on the front side of the substrate 110 on the reflective electrodes RE to fix the light-emitting diodes (LEDs) arranged on the adhesive layer AD. The adhesive layer AD can be made of a light-curing adhesive material or a thermally curing adhesive material that is hardened by heat or light. For example, the adhesive layer AD can be made of an acrylic-based material containing a photoresist, but this is not limited to such materials.

[0044] In several embodiments, including those using a thermally curable adhesive, the adhesive layer AD may contain a pigment, for example, a white / reflective pigment such as titanium dioxide (TiO2). As used in this example, "reflective" refers to the fact that more light is reflected than absorbed. The adhesive layer AD may also contain a black pigment, for example, carbon particles. In further embodiments, the adhesive layer AD may contain particles designed to scatter light and guide the scattered light back into individual light-emitting diodes (LEDs).

[0045] Furthermore, the light-emitting diodes (LEDs) can be arranged in each sub-pixel (SP) on the adhesive layer (AD). LEDs are elements that emit light when an electric current is applied and can include LEDs that emit red, green, and blue light, and combinations of these can produce various colored lights, including white. For example, LEDs can be standard light-emitting diodes (LEDs) or micro-LEDs, but are not limited to these.

[0046] As shown, each of the light-emitting diodes (LEDs) can contain a first semiconductor layer 121, an emission layer 122, a second semiconductor layer 123, a first electrode 124, a second electrode 125, and an encapsulation film 126. The first semiconductor layer 121 can be arranged on the adhesive layer AD, and the second semiconductor layer 123 can be arranged on top of the first semiconductor layer 121. Furthermore, the first semiconductor layer 121 and the second semiconductor layer 123 can be layers formed by doping a specific material with n-type and p-type impurities. For example, the first semiconductor layer 121 and the second semiconductor layer 123 can be layers doped with n-type and p-type impurities in a material such as gallium nitride (GaN), indium aluminum phosphide (InAlP), or gallium arsenide (GaAs).Furthermore, the p-type impurity can be magnesium (Mg), zinc (Zn) and beryllium (Be), and the n-type impurity can be silicon (Si), germanium (Ge) and tin (Sn), but is not limited to these.

[0047] As in Fig. As shown in Figure 2, a portion of the first semiconductor layer 121 can be arranged to project outwards from the second semiconductor layer 123. Furthermore, an upper surface of the first semiconductor layer 121 is formed by a portion that overlaps a lower surface of the second semiconductor layer 123 and a portion that is located on the outer surface of the lower surface of the second semiconductor layer 123. The light-emitting diode (LED) can be a lateral LED. However, the sizes and shapes of the first semiconductor layer 121 and the second semiconductor layer 123 can be modified into various forms, but are not limited to them.

[0048] For example, the first semiconductor layer 121 can protrude from the second semiconductor layer 123 in a certain direction. The first semiconductor layer 121 can also protrude outwards from a portion of the edge of the second semiconductor layer 123. Furthermore, a portion of the first semiconductor layer 121 can protrude outwards from the second semiconductor layer 123 in a certain direction.

[0049] As in Fig. As shown in Figure 2, the emission layer 122 can be arranged between the first semiconductor layer 121 and the second semiconductor layer 123 and is supplied with holes and electrons from the first semiconductor layer 121 and the second semiconductor layer 123 to emit light. The emission layer 122 can be formed by a single layer or a multiple quantum well (MQW) structure and can be made, for example, from indium gallium nitride (InGaN) or gallium nitride (GaN), but is not limited to these materials.

[0050] Furthermore, the first electrode 124 can be located on the first semiconductor layer 121 and electrically connects the drive transistor DT and the first semiconductor layer 121. In this case, the first semiconductor layer 121 is doped with an n-type impurity, and the first electrode 124 can be a cathode. The first electrode 124 can also be located on a top surface of the first semiconductor layer 121 that is exposed by the emission layer 122 and the second semiconductor layer 123. Additionally, the first electrode 124 can contain, but is not limited to, a conductive material, such as a transparent conductive material like indium tin oxide (ITO) or indium zinc oxide (IZO), or an opaque conductive material like titanium (Ti), gold (Au), silver (Ag), copper (Cu), an alloy thereof, or several conductive materials.

[0051] Furthermore, the first electrode 124 can be arranged such that it is closer to the substrate 110 than the emission layer 122. For example, the first semiconductor layer 121 can have a greater thickness in a region overlapping the emission layer 122 than in a region overlapping the first electrode 124. Accordingly, in the cross-sectional view, the first electrode 124 and the emission layer 122 are arranged on different planes.

[0052] Furthermore, the second electrode 125 can be located on the second semiconductor layer 123, and in particular on the upper surface of the second semiconductor layer 123. Moreover, the second semiconductor layer 123 is located on top of the first semiconductor layer 121, so that the second electrode 125, located on the upper surface of the second semiconductor layer 123, can be positioned higher than the first electrode 124, located on the upper surface of the first semiconductor layer 121. Additionally, the second electrode 125 is an electrode that electrically connects the current conductor VDD and the second semiconductor layer 123. In this case, the second semiconductor layer 123 is a semiconductor layer doped with a p-type impurity, and the second electrode 125 can be an anode.The second electrode 125 may contain a conductive material, for example a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), or an opaque conductive material such as titanium (Ti), gold (Au), silver (Ag), copper (Cu), an alloy thereof, or several conductive materials, but is not limited to this.

[0053] Next, the encapsulation film 126 covers the first semiconductor layer 121, the emission layer 122, the second semiconductor layer 123, the first electrode 124, and the second electrode 125. Specifically, the encapsulation film 126 is made of an insulating material to protect the first semiconductor layer 121, the emission layer 122, and the second semiconductor layer 123. Furthermore, contact holes are formed in the encapsulation film 126, exposing the first electrode 124 and the second electrode 125, respectively, to electrically connect a first connecting electrode CE1 and a second connecting electrode CE2 to the first electrode 124 and the second electrode 125, respectively, which are formed after the contact holes are created.

[0054] Furthermore, the adhesive layer AD and the LED can be arranged to be in direct contact with the first junction electrode CE1 on the adhesive layer AD and the LED. Additionally, the first junction electrode CE1 is located in each sub-pixel SP to electrically connect the LED and the driver transistor DT. Specifically, the first junction electrode CE1 can be connected to the first reflective electrode RE1 via the contact hole formed in the adhesive layer AD. Similarly, the first junction electrode CE1 can be electrically connected via the first reflective electrode RE1 to any of the source electrode SE and drain electrode DE of the driver transistor DT. For example, the first junction electrode CE1 can connect, but is not limited to, the first electrode 124 of the LED to the source electrode SE of the driver transistor DT.

[0055] Furthermore, the first connecting electrode CE1 can contain a reflective conductive material. In particular, the first connecting electrode CE1 can be formed, for example, from an opaque reflective conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), an alloy thereof, or from several conductive materials.

[0056] As in Fig. As shown in Figure 2, the first connecting electrode CE1 can also be arranged to cover part of a lower lateral surface of the LED while being in direct contact with the LED. For example, the first connecting electrode CE1 can be arranged to extend from a top surface of the first electrode 124 to cover the encapsulation film 126 located at a lower edge of the LED. As shown, the first connecting electrode CE1 can cover a lateral surface of the first semiconductor layer 121, which is located below the emission layer 122. Furthermore, the first connecting electrode CE1 can be arranged to cover the lateral surface of the first semiconductor layer 121 but not the lateral surface of the emission layer 122.Therefore, the upper surface of the first connecting electrode CE1 can be located between an upper surface of the first electrode 124 and a lower surface of the emission layer 122. Furthermore, the first connecting electrode CE1 extends from a lower lateral surface of the LED to contact the upper surface of the adhesive layer AD.

[0057] Furthermore, the second planarization layer 116 can be arranged on the first junction electrode CE1 and the LED to cover part of the LED's lateral surfaces, thereby fixing and protecting the LED. The second planarization layer 116 can also be arranged on the first junction electrode CE1 to cover the LED's lateral surface. Additionally, the second planarization layer 116 can have a thickness less than that of the LED. For example, the second planarization layer 116 can cover a lateral surface of the first semiconductor layer 121, which is located below the emission layer 122.

[0058] Furthermore, the second planarization layer 116 can also be arranged over the first electrode 124 and cover an upper surface of the first interconnect electrode CE1, which is arranged over the first electrode 124. Accordingly, the second planarization layer 116 can be arranged such that it overlaps the first electrode 124 of the LED and part of a lateral surface of the LED. Furthermore, the second planarization layer 116 can be arranged such that it covers the lateral surface of the first semiconductor layer 121, but not the lateral surface of the emission layer 122. Therefore, the upper surface of the second planarization layer 116 can be located between the upper surface of the first electrode 124 and the lower surface of the emission layer 122.

[0059] Furthermore, the upper surface of the second planarization layer 116 can expose a surface of the first connection electrode CE1, which is located on the side surface of the light-emitting diode LED. For example, with reference to Fig. 2 The upper surface of the second planarization layer 116 is arranged on the same plane as a surface of the first connecting electrode CE1 of the first connecting electrodes CE1, which is arranged above. Accordingly, the surface of the first connecting electrode CE1 of the first connecting electrodes CE1, which is arranged above, can be exposed by the second planarization layer 116.

[0060] As in Fig. As shown in Figure 2, the upper surface of the second planarization layer 116 and the top surface of the first connection electrode CE1 can be arranged such that they are located lower than the lower surface of the emission layer 122 of the LED. Accordingly, the light output of the emission layer 122 of the LED is not restricted by the first connection electrode CE1. Therefore, the first connection electrode CE1 is arranged so that it does not restrict the light path of the LED, thereby increasing the luminous efficacy of the LED. However, the present disclosure is not limited to this, and the upper surface of the second planarization layer 116 and the top surface of the first connection electrode CE1 can be arranged higher than the surface of the emission layer 122 of the LED, depending on the position of the emission layer 122 in the LED and the lateral structure of the LED.

[0061] Furthermore, the second planarization layer 116 can expose a lateral surface of the first connecting electrode CE1, which is located on the adhesive layer AD. For example, with reference to Fig. 2. The width of the lower surface of the second planarization layer 116 and the width of the upper surface of the first connecting electrode CE1 are equal, and the lateral surface of the second planarization layer 116 and the lateral surface of the first connecting electrode CE1 can be arranged on the same plane. Therefore, in a top view, a planar shape of the second planarization layer 116 and a planar shape of the first connecting electrode CE1 can be the same, and the lateral surface of the first connecting electrode CE1 can be exposed by the second planarization layer 116.

[0062] Furthermore, the second planarization layer 116 can contain a black material, such as a black component with high light absorption. Accordingly, the second planarization layer 116 can suppress color mixing that may occur between LEDs emitting light of different colors and suppress the reflection of external light.

[0063] Furthermore, the third planarization layer 117 is arranged on the adhesive layer AD, the first connecting electrode CE1, and the second planarization layer 116, and covers part of the lateral surfaces of the LEDs to fix and protect them. In addition, the third planarization layer 117 is arranged between the second planarization layer 116, d, and the second connecting electrode CE2 to planarize an upper part of the second planarization layer 116 and a lower part of the second connecting electrode CE2.

[0064] Furthermore, the third planarization layer 117 covers the upper part of the second planarization layer 116 and covers a portion of the upper lateral surface of the LED that is exposed by the second planarization layer 116. As shown, an upper surface of the third planarization layer 117 is positioned higher than the emission layer 122 of the LED and can be positioned at or below the upper surface of the second semiconductor layer 123. For example, an upper surface of the third planarization layer 117 can be positioned between the upper surface of the emission layer 122 and the upper surface of the second semiconductor layer 123, or at the same level as the upper surface of the second semiconductor layer 123.

[0065] Furthermore, the third planarization layer 117 extends from the upper part of the second planarization layer 116 to cover the lateral surface of the second planarization layer 116 and the lateral surface of the first connecting electrode CE1. Additionally, the third planarization layer 117 can cover the upper surface of the adhesive layer AD, which is located on the outside of the second planarization layer 116.

[0066] The third planarization layer 117 can also be a single layer or a double layer. The third planarization layer 117 can, for example, also be formed from a photoresist or an acrylic-based organic material, but is not limited to these.

[0067] Furthermore, as shown, the second connecting electrode CE2 can be arranged on the third planar layer 117 to electrically connect the LED and the power line VDD. Additionally, the second connecting electrode CE2 can be connected to the second reflective electrode RE2 via the contact hole formed in the third planar layer 117 and the adhesive layer AD. Accordingly, the second connecting electrode CE2 can be electrically connected to the power line VDD via the second reflective electrode RE2. For example, the second connecting electrode CE2 can connect the second electrode 125 of the LED to the power line VDD, but this is not limited to this connection.

[0068] Furthermore, the second connecting electrode CE2 can be made of a material different from that of the first connecting electrode CE1. For example, the second connecting electrode CE2 can be made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0069] As shown, the fourth planarization layer 118 can be arranged on top of the third planarization layer 117 and the second connecting electrode CE2. Specifically, the fourth planarization layer 118 planars an upper portion of the substrate 110 on which the light-emitting diode (LED) is mounted, in order to fix and protect the LED. Therefore, the fourth planarization layer 118 can also be referred to as a protective layer or top layer, but this is not limited to these terms. Furthermore, the fourth planarization layer 118 can be a single layer or a double layer and may be formed, for example, from photoresist or an acrylic-based organic material, but this is not limited to these terms.

[0070] The following describes a manufacturing process for a display device according to an embodiment of the present disclosure with reference to the Fig. Sections 3A to 3E are described together. First, with reference to Fig. 3A A light-emitting diode (LED) is arranged on an adhesive layer AD, and a metal layer ML is formed on the adhesive layer AD to cover the LED. Furthermore, the metal layer ML can be arranged over the entire substrate 110 and covers a top surface of the adhesive layer AD as well as a top surface and a side surface of the LED. The metal layer ML also covers a surface of an encapsulation film 126 of the LED and can cover the first electrode 124 and the second electrode 125, which are exposed through a contact hole in the encapsulation film 126. Additionally, the metal layer ML can cover the first reflective electrode RE1, which is exposed through contact holes in the passivation layer 114 and the first planarization layer 115.

[0071] With reference to Fig. In 3B, an initial second planarization layer 116' containing a photosensitive material is formed on the metal layer ML. Specifically, the initial second planarization layer 116' is formed such that it covers a portion of the metal layer ML. For example, the initial second planarization layer 116' can be formed to cover the metal layer ML extending from the contact holes of the passivation layer 114 and the first planarization layer 115, through which the source electrode SE of the driver transistor DT is exposed to a top surface, to a side surface of the light-emitting diode LED.

[0072] With reference to Fig. In step 3C, a portion of the initial second planarization layer 116' is removed to form a second planarization layer 116. For example, the initial second planarization layer 116' can be subjected to an ashing process to remove a portion of the initial second planarization layer 116' that covers an upper section of the LED. In particular, the ashing process is performed so that the second planarization layer 116 covers the upper surface of the metal layer ML on the first electrode 124 and a portion of the metal layer ML located on a lower lateral surface of the LED, but exposes an upper surface of the metal layer ML on the second electrode 125 and a portion of the metal layer ML located on an upper lateral surface of the LED.

[0073] Next, with reference to Fig. The metal layer ML, located in an area that does not overlap with the second planarization layer 116, is removed to form the first junction electrode CE1. For example, a photoprocess can be performed, and the second planarization layer 116 can be used as a mask for the first junction electrode CE1. Accordingly, the metal layer ML covering the second electrode 125 and the metal layer ML covering the upper lateral surface of the LED above the second planarization layer 116 are removed to form the first junction electrode CE1.

[0074] Next, with reference to Fig. The third planarization layer 117, the second junction electrode CE2, and the fourth planarization layer 118 are successively formed on the first junction electrode CE1. The third planarization layer 117 is formed such that it covers part of an upper lateral surface of the LED exposed by the second planarization layer 116. Furthermore, the third planarization layer 117 is formed such that it exposes the second electrode 125. Next, the second junction electrode CE2 and the fourth planarization layer 118 are formed on the third planarization layer 117. The second junction electrode CE2 is formed such that it covers an upper surface of the second electrode 125 exposed by the third planarization layer 117 and extends onto the second electrode 125 formed on the third planarization layer 117.Furthermore, the second connecting electrode CE2 can cover the second reflective electrode RE2, which is exposed through the contact hole of the third planarization layer 117. Subsequently, the fourth planarization layer 118 is formed, covering an upper surface of the second connecting electrode CE2.

[0075] In the following, a luminance corresponding to a viewing angle of a display device 100 according to an embodiment of the present disclosure is described with reference to Fig. 4 identified. In particular, Fig. 4 a diagram illustrating luminance corresponding to a viewing angle of a display device according to an embodiment of the present disclosure. The diagram shown in Fig. Example 4 shown is a display device 100 according to an embodiment of the present disclosure and a different display device according to a comparative embodiment, in which a first connecting electrode CE1 is formed from a transparent conductive material.

[0076] In Fig. Figure 4 indicates that the X-axis represents the viewing angle and the Y-axis represents the luminance. Furthermore, in the comparative representation, the luminance in the front direction, i.e., at a viewing angle of 0°, is 100%, and a relative luminance of this is denoted by a reference symbol %.

[0077] With reference to Fig. 4. It is confirmed in both the comparative embodiment and the embodiment of the present disclosure that a high luminance can be achieved in the front direction and in the lateral direction from 50° to 70°. Furthermore, it is confirmed that the luminance of the embodiment of the present disclosure is approximately 108% and that the front luminance is increased by approximately 8% compared to the comparative embodiment at a viewing angle of 0°.

[0078] Furthermore, the second junction electrode CE2 contains a transparent conductive material, while the first junction electrode CE1 contains a reflective conductive material. Accordingly, light emitted by the LED that is directed towards the first junction electrode CE1 can be reflected by the first junction electrode CE1. For example, light emitted by the LED that is directed towards the side surface of the first semiconductor layer 121 and the first electrode 124 can be reflected by the first junction electrode CE1.Accordingly, the light reflected from the first connecting electrode CE1 is reflected again by the first reflecting electrode RE1, which is located below the LED, to reach an area not covered by the first connecting electrode CE1. Thus, the light reflected from the first connecting electrode CE1 and the first reflecting electrode RE1 travels in a direction where the second semiconductor layer 125 of the LED is located and can pass through the second electrode 125 and the second connecting electrode CE2, which are made of a transparent conductive material.Accordingly, in the display device 100 according to the embodiment of the present disclosure, the front luminance can be improved compared to an example in which both the first connecting electrode CE1 and the second connecting electrode CE2 are formed from a transparent conductive material. Consequently, since the front luminance of the display device 100 is improved, low-power operation is possible.

[0079] Furthermore, the second planarization layer 116, which covers the side surface of the LED, contains a black material. Accordingly, the second planarization layer 116 fixes the LED and insulates it from peripheral components, suppressing color mixing and reflection of external light. Therefore, in the display device 100 according to the embodiment of the present disclosure, a separate black matrix, for example, a black bank, is not used over the LED. Consequently, the thickness of the display device 100 is reduced, and the process for forming the black bank and the number of masks used in the process can be minimized. Therefore, process optimization can be achieved by reducing process costs and time.

[0080] Furthermore, the second planarization layer 116, which covers the side surface of the LED, is used as a mask for the first junction electrode CE1. For example, the second planarization layer 116 can be formed according to the first junction electrode CE1 to structure it. Accordingly, no photoprocessing or masking process is performed to form the first junction electrode CE1, thus reducing process costs and time, and enabling process optimization.

[0081] Next up is in Fig. Figure 5 shows an enlarged cross-sectional view of a display device according to a further embodiment of the present disclosure. The display device 500 in Fig. 5 differs from the display device 100 in Fig. 1, Fig. 2, Fig. 3 to Fig. 4 by the fact that no third planarization layer 117 is arranged and only the second planarization layer 516 is different, while the remaining configurations are essentially the same, so that a redundant description is unnecessary.

[0082] With reference to Fig. A second planarization layer 516 is arranged on the first junction electrode CE1 and the light-emitting diode (LED). The second planarization layer 516 is positioned on the first junction electrode CE1 to cover the side surface of the LED while being in direct contact with it. Furthermore, the upper surface of the second planarization layer 516 is positioned higher than the emission layer 122 and can be positioned at or below the upper surface of the second semiconductor layer 123. For example, the upper surface of the second planarization layer 516 can be located between the upper surface of the emission layer 122 and the upper surface of the second semiconductor layer 123, or at the same level as the upper surface of the second semiconductor layer 123.

[0083] Furthermore, the second planarization layer 516 can cover an upper surface of the first connection electrode CE1, which is located above the first electrode 124, while in direct contact with the upper surface of the first connection electrode CE1. The second planarization layer 516 can also cover a lateral surface of the first connection electrode CE1. For example, the second planarization layer 516 can cover a lateral surface of the first connection electrode CE1, which is located on the lateral surface of the LED, and an upper surface of the LED, which is located above the first connection electrode CE1. Additionally, the second planarization layer 516 can cover a surface of the first connection electrode CE1 that is located on the upper surface of the first connection electrode CE1.

[0084] Furthermore, the second planarization layer 516 can cover the lateral surface of the first connecting electrode CE1, which is positioned above the adhesive layer AD, while being in direct contact with the lateral surface of the first connecting electrode CE1. For example, in a top view, an area of ​​the second planarization layer 516 can be larger than an area of ​​the first connecting electrode CE1. Accordingly, the second planarization layer 516 extends from the upper part of the first connecting electrode CE1 to cover the upper surface of the adhesive layer AD.

[0085] Furthermore, the second planarization layer 516 can contain a black material. Accordingly, the second planarization layer 516 can suppress color mixing that may occur between LEDs emitting light of different colors and suppress reflection of external light.

[0086] Furthermore, a lower surface of the second planarization layer 516 is in contact with an upper surface of the first connecting electrode CE1, and an upper surface of the second planarization layer 516 is located lower than the upper surface of the second electrode 125 and can be in contact with a lower surface of the second connecting electrode CE2. For example, the second planarization layer 516 can be formed from an insulating material to prevent the first connecting electrode CE1 and the second connecting electrode CE2 from being electrically connected.

[0087] Furthermore, the second planarization layer 516 can contain a plurality of contact holes that expose an upper surface of the second reflective electrode RE2. Additionally, the second connecting electrode CE2 can be positioned in the contact hole of the second planarization layer 516. Accordingly, the second connecting electrode CE2 can be connected to the second reflective electrode RE2 via the contact holes formed in the second planarization layer 516 and the adhesive layer AD.

[0088] The following describes a manufacturing process for a display device according to a further embodiment of the present disclosure with reference to the Fig. Sections 6A to 6D are described together. In particular, the Fig. 6A to 6D Views illustrating a manufacturing process for a display device according to a further embodiment of the present disclosure.

[0089] First, with reference to Fig. In 6A, a light-emitting diode (LED) is arranged on an adhesive layer AD, and a metal layer ML is formed on the adhesive layer AD to cover the LED. The metal layer ML is arranged over the entire substrate 110 and can cover a top surface of the adhesive layer AD and a top and side surface of the LED. In addition, the metal layer ML covers a surface of an encapsulation film 126 of the LED and can cover the first electrode 124 and the second electrode 125, which are exposed through a contact hole in the encapsulation film 126.

[0090] With reference to Fig. In step 6B, a photoresist PR containing a photosensitive material is formed on the metal layer ML to cover a portion of the metal layer ML. For example, the photoresist PR can be formed to cover the metal layer ML extending from the contact holes of the passivation layer 114 and the first planarization layer 115, through which the source electrode SE of the drive transistor DT is exposed to a top surface, to a side surface of the light-emitting diode LED.

[0091] With reference to Fig. In step 6C, the photoresist PR is used as a mask for the metal layer ML to form the first junction electrode CE1. For example, the photoresist PR can be subjected to an ashing process to remove a portion of it covering the top of the LED. Additionally, the ashing process can expose the top surface of the metal layer ML on the second electrode 125 and a portion of the metal layer ML located on a top lateral surface of the LED. The first junction electrode CE1 is then formed by removing the metal layer ML located in an area that does not overlap with the photoresist PR. Finally, the top surface of the first junction electrode CE1 is exposed by removing the photoresist PR.

[0092] Next, with reference to Fig. 6D, the second planarization layer 516, the second junction electrode CE2, and the fourth planarization layer 118 are formed on the first junction electrode CE1. The second planarization layer 516 is formed such that it covers a top surface and a side surface of the first junction electrode CE1. Furthermore, the second planarization layer 516 is formed such that it covers the top side surface of the LED, which is exposed in an upper part of the first junction electrode CE1. Additionally, the second planarization layer 516 is formed such that it exposes the second electrode 125.

[0093] Next, the second connecting electrode CE2 and the fourth planarization layer 118 are formed on the second planarization layer 516 to cover an upper surface of the second electrode 125 that protrudes from and extends onto the second electrode 125, which is to be formed on the second planarization layer 516. Then, the fourth planarization layer 118 is formed, covering the upper surface of the second connecting electrode CE2.

[0094] In the display device 500 according to a further embodiment of the present disclosure, the second connecting electrode CE2 contains a transparent conductive material, while the first connecting electrode CE1 contains a reflective conductive material. Accordingly, the light reflected from the first connecting electrode CE1 and the first reflective electrode RE1 moves towards the front of the light-emitting diode LED, thereby improving the luminance of the display device 500 and enabling low-power operation.

[0095] Furthermore, the second planarization layer 516, which covers the side surface of the LED, contains a black material. Accordingly, a separate black bank is not required, thus reducing the thickness of the display device 500 and decreasing the number of processes and masks, thereby saving process costs and time.

[0096] Furthermore, no separate planarization layer is formed above the second planarization layer 516; instead, the second connecting electrode CE2 is positioned. Accordingly, no separate process for forming an insulating layer is required, thus reducing not only the number of processes and masks but also saving process costs and time.

[0097] Next up is in Fig. Figure 7 shows an enlarged cross-sectional view of a display device according to a further embodiment of the present disclosure. Compared to the display device 500 from Fig. 5 differ only in the adhesive layer AD, the second planarization layer 716 and the first connecting electrode CE1 of the display device 700. Fig. 7, while the remaining configurations are essentially the same, so a redundant description is omitted.

[0098] With reference to Fig. 7. The adhesive layer AD is arranged on the reflective electrodes RE and contains a plurality of contact holes CH, each surrounding the light-emitting diodes (LEDs). For example, each of the contact holes CH can have a closed loop shape. Furthermore, each of the contact holes CH has a shape that surrounds an outer diameter of the LED, but is not limited to this.

[0099] Furthermore, the contact holes CH can expose an upper surface of the first reflective electrode RE1, which is located below the adhesive layer AD. For example, the adhesive layer AD can be formed from an island-like structure corresponding to the shape of each of the LEDs, and from a layer arranged on the outside of the LEDs to surround an island-like structure.

[0100] Furthermore, the LED and the first junction electrode CE1 are arranged on the adhesive layer AD. As shown, the first junction electrode CE1 extends from a lateral surface of the LED to cover the upper surface of the adhesive layer AD. Additionally, the first junction electrode CE1 can be positioned within the contact holes CH of the adhesive layer AD. Accordingly, the first junction electrode CE1 can be in contact with the upper surface of the first reflective electrode RE1 within the contact holes CH of the adhesive layer AD. Furthermore, the adhesive layer AD, located below the LED, can be covered by the first junction electrode CE1, the LED, and the first reflective electrode RE1.In other words, the adhesive layer AD located below the light-emitting diode LED can be covered by a reflective conductive material, except for a surface that is in contact with the light-emitting diode LED.

[0101] Furthermore, the second planarization layer 716 is arranged on the first connecting electrode CE1 and the light-emitting diode LED and planars an upper part of the first connecting electrode CE1. For example, the second planarization layer 716 can be arranged in the contact holes CH of the adhesive layer AD to planarize an upper part of the adhesive layer AD.

[0102] In the display device 700, the second connecting electrode CE2 contains a transparent conductive material, but the first connecting electrode CE1 can contain a reflective conductive material. Accordingly, the light reflected from the first connecting electrode CE1 and the first reflective electrode RE1 moves towards the front of the LED, and the front luminance of the display device 700 can be improved, thus enabling low-power operation.

[0103] Furthermore, the second planarization layer 716, which surrounds the side surface of the LED, contains a black material. Accordingly, no separate black layer is formed, thus reducing the thickness of the display device 700 and decreasing the number of processes and masks, thereby saving process costs and time.

[0104] Furthermore, no separate planarization layer is formed over the second planarization layer 716, while the second connecting electrode CE2 remains in place. Accordingly, no separate process is used to form an insulating layer, thus reducing not only the number of processes and masks, but also saving process costs and time.

[0105] Furthermore, the adhesive layer AD contains a plurality of contact holes CH, each surrounding the LED. Accordingly, the adhesive layer AD, located below the LED, can be covered by the first connecting electrode CE1 and the first reflective electrode RE1, except for the surface that is in contact with the LED. Therefore, any light emitted by the LED traveling in the direction in which the adhesive layer AD is oriented ( ) is reflected by the first connecting electrode CE1 and the first reflective electrode RE1 and travels towards the top of the LED. Thus, a problem where light emitted by the LED is contained within the adhesive layer AD and not emitted outwards can be suppressed.Accordingly, in the display device 700 according to a further embodiment of the present disclosure, the total luminance and the front luminance of the light-emitting diode LED are improved, so that it is possible to drive the light-emitting diode LED with low power.

[0106] Furthermore, the first connecting electrode CE1 and the first reflective electrode RE1 are electrically connected in each of the contact holes CH of the adhesive layer AD. Therefore, the contact area of ​​the first connecting electrode CE1 and the first reflective electrode RE1 can be increased, and the conduction resistance between the first connecting electrode CE1 and the first reflective electrode RE1, as well as between the first connecting electrode CE1 and the control transistor DT, can be reduced.

[0107] Various embodiments of the present disclosure can also be described as follows. According to one aspect of the present disclosure, a display device comprises a substrate in which a plurality of subpixels are defined; a plurality of drive transistors in each of the plurality of subpixels; a plurality of light-emitting diodes in each of the plurality of subpixels; a first connecting electrode covering a portion of a lower lateral surface of the plurality of light-emitting diodes and formed of a reflective conductive material; and a second connecting electrode in contact with the upper surfaces of the light-emitting diodes and formed of a transparent conductive material.

[0108] The display device can further include a first planarization layer on the drive transistors and a second planarization layer between the first and second junction electrodes, the latter having a thickness thinner than that of the LEDs. The second planarization layer can contain a black material.

[0109] The display device can further comprise a current conductor on the substrate, a plurality of first reflective electrodes connected to the drive transistors, a plurality of second reflective electrodes connected to the current conductor, and an adhesive layer on the plurality of first reflective electrodes and the plurality of second reflective electrodes. The first connecting electrode can be in contact with an upper surface of the adhesive layer. The display device can further comprise a third planarization layer between the second planarization layer and the second connecting electrode.

[0110] The third planarization layer can cover a lateral surface of the second planarization layer and a lateral surface of the first connecting electrode. The third planarization layer can contain a plurality of contact holes that expose part of the upper surfaces of the second reflecting electrodes and the second connecting electrode, and the second reflecting electrodes can be electrically connected in the contact holes of the third planarization layer.

[0111] The width of a lower surface of the second planarization layer can be equal to the width of an upper surface of the first connecting electrode. The second planarization layer can cover a lateral surface of the first connecting electrode. An upper surface of the second planarization layer can be in contact with a lower surface of the second connecting electrode.

[0112] The adhesive layer can contain multiple contact holes surrounding each of the light-emitting diodes. These contact holes in the adhesive layer can expose part of the upper surfaces of the first reflecting electrodes, and the first connecting electrode can make contact with these upper surfaces within the contact holes of the adhesive layer.

[0113] According to another aspect of the present disclosure, a display device comprises a substrate in which a plurality of sub-pixels are defined; a plurality of drive transistors in each of the sub-pixels; a first planarization layer on the drive transistors; a plurality of light-emitting diodes on the first planarization layer in each of the sub-pixels; a first interconnecting electrode electrically connected to the light-emitting diodes and formed from a reflective conductive material; a second interconnecting electrode electrically connected to the light-emitting diodes and formed from a transparent conductive material; and a second planarization layer arranged between the first and second interconnecting electrodes. The second planarization layer comprises a black material.

[0114] Each of the light-emitting diodes can contain a first semiconductor layer, an emissive layer on the first semiconductor layer, a second semiconductor layer on the emissive layer, a first electrode on the first semiconductor layer, and a second electrode on the second semiconductor layer. The first junction electrode can be electrically connected to the first electrode, and the second junction electrode can be electrically connected to the second electrode.

[0115] The second planarization layer can be arranged on the first junction electrode, and the second planarization layer can overlap the first electrode, but must not overlap the emission layer. The display device can further include a third planarization layer that covers a portion of the upper lateral surfaces of the LEDs exposed by the second planarization layer. The third planarization layer can cover one upper surface and one lateral surface of the second planarization layer.

[0116] The planar shape of the second planarization layer can be the same as the planar shape of the first interconnect electrode. The second planarization layer can contain a plurality of contact holes, and the second interconnect electrode can be arranged in the contact holes. The display device can further include a current conductor on the substrate and an adhesive layer on the current conductor and the driver transistors. The adhesive layer can contain a plurality of contact holes surrounding each of the light-emitting diodes.

Claims

[1] Display device (100, 500, 700), comprising: a substrate (110); a control transistor (DT) on the substrate (110); an adhesive layer (AD) on the substrate (110); a light-emitting diode (LED) on the adhesive layer (AD) overlapping the drive transistor (DT) and comprising a first semiconductor layer (121) on the adhesive layer (AD), an emission layer (122) on the first semiconductor layer (121), a second semiconductor layer (123) on the emission layer (122), a first electrode (124) on the first semiconductor layer (121) and a second electrode (125) on the second semiconductor layer (123), wherein the first electrode (124) is located closer to the substrate (110) than the emission layer (122) and the second electrode (125) is located higher than the first electrode (124); a reflective connecting electrode (CE1) that covers a lower lateral surface of the light-emitting diode (LED) and the first electrode (124) and electrically connects the first electrode (124) to the control transistor (DT); a power transmission line (VDD) on the substrate (110); and a transparent connecting electrode (CE2) that overlaps the reflective connecting electrode (CE1), contacts an upper surface of the light-emitting diode (LED) and electrically connects the second electrode (125) to the power line (VDD). [2] The display device (100, 500, 700) according to claim 1, which further comprises: a first planarization layer (115) covering the drive transistor (DT); and a second planarization layer (116, 516, 716) containing a black material that is positioned between the reflective connecting electrode (CE1) and the transparent connecting electrode (CE2) and has a thickness that is thinner than the thickness of the light-emitting diode (LED). [3] The display device (100, 500, 700) according to claim 2, which further comprises: a first reflective electrode (RE1) connected to the drive transistor (DT); and a second reflective electrode (RE2) connected to the current conductor (VDD) and the transparent connecting electrode (CE2), wherein the adhesive layer (AD) covers the first reflective electrode (RE1) and the second reflective electrode (RE2) and wherein the reflective connecting electrode (CE1) contacts an upper surface of the adhesive layer (AD). [4] The display device (100) according to claim 3, which further comprises: a third planarization layer (117) between the second planarization layer (116) and the second connecting electrode (CE2), wherein the third planarization layer (117) covers a lateral surface of the second planarization layer (116) and a lateral surface of the reflecting connecting electrode (CE1), wherein the third planarization layer (117) contains a contact hole that exposes part of the upper surface of the second reflecting electrode (RE2), and wherein the transparent connecting electrode (CE2) contacts the second reflective electrode (RE2) in the contact hole of the third planarization layer (117). [5] The display device (100, 500, 700) according to claim 3 or 4, wherein the reflective connecting electrode (CE1) and the first reflective electrode (RE1) reflect light in a forward direction of the light-emitting diode (LED) and through the transparent connecting electrode (CE2). [6] The display device (100) according to any one of claims 2 to 5, wherein the width of a lower surface of the second planarization layer (116) is equal to the width of an upper surface of the reflecting connecting electrode (CE1). [7] The display device (100, 500, 700) according to any one of claims 2 to 6, wherein the second planarization layer (116, 516) covers lateral surfaces of the reflective connecting electrode (CE1). [8] The display device (500, 700) according to claim 7, wherein an upper surface of the second planarization layer (516) contacts a lower surface of the transparent connecting electrode (CE2). [9] The display device (700) according to any one of claims 1 to 8, wherein the adhesive layer (AD) contains a first contact hole (CH) surrounding the light-emitting diode (LED), wherein the reflective connecting electrode (CE1) contacts an upper surface of the first reflective electrode (RE1) in the first contact hole (CH) of the adhesive layer (AD), wherein the adhesive layer (AD) contains a second contact hole, and wherein the second reflective electrode (RE2) contacts the transparent connecting electrode (CE2) in the second contact hole of the adhesive layer (AD). [10] The display device (100, 500, 700) according to any one of claims 1 to 9, wherein the first semiconductor layer (121) has a thickness in a region overlapping the emission layer (122) that is greater than the thickness in a region overlapping the first electrode (124), so that the first electrode (124) and the emission layer (122) are arranged on different planes. [11] The display device (100, 500, 700) according to any one of claims 1 to 10, further comprising: an encapsulation film (126) that encapsulates the light-emitting diode (LED) and has a first and a second contact hole that expose the first electrode (124) and the second electrode (125), respectively, so that the reflective connecting electrode (CE1) contacts the first electrode (124) and the transparent connecting electrode (CE2) contacts the second electrode (125). [12] The display device (100, 500, 700) according to claim 11, wherein the reflective connecting electrode (CE1) directly contacts the adhesive layer (AD) and the encapsulation film (126) of the light-emitting diode (LED). [13] The display device (100, 500, 700) according to claim 2 or 3, wherein the second planarization layer (116, 516, 716) is arranged on the reflective connecting electrode (CE1) and wherein the second planarization layer (116, 516, 716) overlaps the first electrode (124) but does not overlap the emission layer (122). [14] The display device (100) according to claim 13, further comprising: a third planarization layer (117) covering part of the upper lateral surfaces of the light-emitting diode (LED) exposed by the second planarization layer (116), wherein the third planarization layer (117) covers an upper surface and a lateral surface of the second planarization layer (116). [15] The display device (100) according to claim 14, wherein a planar shape of the second planarization layer (116) is the same as a planar shape of the reflecting connecting electrode (CE1). [16] The display device (500, 700) according to claim 13, wherein the second planarization layer (516, 716) contains a contact hole and wherein the second connecting electrode (CE2) is arranged in the contact hole of the second planarization layer (516, 716). [17] The display device (100, 500, 700) according to any one of claims 1 to 16, wherein the adhesive layer (AD) contains a reflective pigment. [18] The display device (100, 500, 700) according to claim 17, wherein the adhesive layer (AD) contains a black pigment.

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