INTEGRATED BACK-END-OF-LINE TRENCH CAPERATOR

Abstract

A method for forming an integrated circuit is disclosed herein. The method includes forming an electronic device over a substrate containing a semiconductor material, forming a pre-metal dielectric layer over the electronic device, forming a trench through the pre-metal dielectric layer and into the substrate, forming a capacitor dielectric layer over the pre-metal dielectric layer and within the trench, and forming a conductive material layer over the capacitor dielectric layer and within the trench, wherein the conductive material layer forms a first plate of a trench capacitor and the semiconductor material of the substrate forms a second plate of the trench capacitor.

Description

TECHNICAL AREA

[0001] The present disclosure relates generally to integrated semiconductor devices and in particular to integrated silicon trench capacitors. BACKGROUND

[0002] Integrated trench capacitors can be used in semiconductor devices to add capacitance to various integrated circuits. However, several problems arise when attempting to integrate trench capacitors into a manufacturing process flow for an integrated circuit. For example, trench capacitors can be difficult to integrate into existing process flows. Improvements in the integration of trench capacitors into semiconductor process flows are needed. SUMMARY

[0003] This document discloses methods for forming trench capacitors and integrated circuits (ICs), including such capacitors. An exemplary method involves forming an electronic device over a substrate, wherein the substrate comprises a semiconductor material; forming a pre-metal dielectric layer over the electronic device; forming a trench through the pre-metal dielectric layer and into the substrate; forming a capacitor dielectric layer over the pre-metal dielectric layer and within the trench; and forming a conductive material layer over the capacitor dielectric layer and within the trench, wherein the conductive material layer forms a first plate of a trench capacitor and the semiconductor material of the substrate forms a second plate of the trench capacitor.

[0004] Another exemplary process involves forming a silicide layer over a substrate, forming a pre-metal dielectric layer over the silicide layer, forming a trench through the pre-metal dielectric layer and into the substrate, forming a capacitor dielectric layer within the trench, and forming a conductive material layer within the trench, with part of the conductive material layer extending through the pre-metal dielectric layer and into the substrate.

[0005] Also disclosed herein is an integrated circuit (IC) device including a trench capacitor. The IC device comprises a pre-metal dielectric layer arranged over a substrate, the substrate comprising a semiconductor material, and a trench capacitor. The trench capacitor comprises a capacitor dielectric layer extending into multiple trenches formed through the pre-metal dielectric layer and into the substrate, and a conductive material extending into the multiple trenches. The device further comprises a metal layer arranged directly on the conductive material.

[0006] The foregoing features and elements can be combined in any combination without exclusivity, unless expressly stated otherwise herein. These features and elements, as well as the operation of the disclosed examples, will become clearer in light of the following description and accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Reference is made to the accompanying drawings, which are not necessarily to scale. Although the drawings illustrate various examples that employ the principles described herein, they do not limit the scope of protection of the claims. Fig. Figure 1 illustrates a flowchart of a process for forming a semiconductor device according to various examples. Fig. 2A, Fig. 2B, Fig. 2C, Fig. 2D, Fig. 2E, Fig. 2F, Fig. 2G, Fig. 2H, Fig. 2I, Fig. 2 years Fig. 2K, Fig. 2L, Fig. 2M, Fig. 2N, Fig. 20, Fig. 2P, Fig. 2Q, Fig. 2R, Fig. 2S, Fig. 2T, Fig. 2T', Fig. 2U, Fig. 2V, Fig. 2W and Fig. Figure 2X illustrates cross-sectional views of various semiconductor devices according to the process from Fig. 1 and the various associated examples. Fig. Figure 3 illustrates a flowchart of a process for forming a semiconductor device according to various examples. Fig. 4A, Fig. 4B, Fig. 4C, Fig. 4D, Fig. 4E, Fig. 4F, Fig. 4G and Fig. 4H illustrates cross-sectional views of a semiconductor device according to the process from Fig. 3 and the various associated examples. Fig. Figure 5 illustrates a cross-sectional view of a semiconductor device according to various examples. Fig. 6A, Fig. 6B, Fig. 6C, Fig. 6D, Fig. 6D' and Fig. Figure 6E illustrates top views of a semiconductor device according to various examples. DETAILED DESCRIPTION

[0008] The following detailed description is presented for illustrative purposes, not as a limitation. Benefits, advantages, and / or solutions to problems can be described with reference to various examples. The detailed description utilizes these examples and refers to the accompanying drawings, which illustrate the various examples described herein. The drawings, descriptions, and examples are described in sufficient detail to implement the disclosure. It is understood that connecting lines shown in the various drawings are intended to represent exemplary functional relationships and / or physical couplings between different elements, but that other relationships and / or couplings are possible while remaining within the scope of protection of this disclosure.It is further understood that the various drawings may not be to scale in order to simplify and clarify the detailed description herein. It is also understood that the descriptions and examples contained herein may enable the implementation of other examples using logical, chemical, and / or mechanical modifications without deviating from the idea and scope of protection of this disclosure. For example, the steps mentioned in method and process descriptions may be performed in a different order, additional process steps may be added, and / or process steps may be removed, while remaining within the scope of protection of this disclosure.

[0009] Any reference to singular objects and / or examples includes plural objects and / or examples, and any reference to more than one object and / or example may include a singular object and / or example. Likewise, references to "a," "an," or "the" may include one or more of the referenced objects unless otherwise specified. Any reference to connected, coupled, attached, affixed, or similar words and / or phrases may include partial, complete, temporary, removable, permanent, or other connection options. Any reference to contact or similar phrase may include minimal or reduced contact. All ranges used herein may include both the upper and lower values ​​of the ranges, including ratio limits disclosed herein.The stated values ​​may include at least the variation expected within the area in which the present disclosure is implemented, and would be understood and accepted to include values ​​that lie within 10% of a stated value. Likewise, the expressions "approximately," "about," or other similar expressions represent a quantity that is close to the stated value and that can still achieve the stated or desired result and / or perform the stated or desired function, and may refer to a quantity that lies within 10% of the stated value. The expression "essentially the same" with reference to two or more quantitative characteristics means that values ​​representing those characteristics lie within ± 2.5% of an average of the associated values.

[0010] The accompanying drawings and a detailed description of the drawings include reference numerals that may be repeated across several examples. The repetition of reference numerals is intentional for the sake of simplicity and clarity of description and is not intended to establish or suggest a relationship between different examples described herein. The examples and descriptions provided here are intended to be illustrative and not to be limiting beyond the scope of protection of the claims. The use of terms such as "on" and "over" may indicate that a first feature is formed such that it directly contacts a second feature, or it may indicate a relationship between the first and second features without direct contact between them, such as with additional features formed between them.For example, "on" can be used to indicate direct contact between the two, and "over" can be used to indicate one or more intermediate layers between the two.

[0011] Spatially relative terms, such as "lower", "upper", "horizontal", "vertical", "above", "over", "below", "underneath", "top", "bottom", "top", "bottom", etc., as well as derivatives thereof (e.g., "horizontal", "vertical", "downwards", "upwards", etc.), are used here for the sake of simplicity and are not intended to restrict the orientation of the various components, systems, facilities, devices, or other features. It is therefore understood and recognized that the use of spatially relative terms to implement this disclosure in different orientations remains within the scope of protection of this disclosure.

[0012] In general, the manufacturing processes of an integrated circuit (IC) can be divided into front-end-of-line (FEOL) and back-end-of-line (BEOL) processes. FEOL processes generally involve the fabrication of the various IC components of the IC device, such as transistors, resistors, inductors, and capacitors, while BEOL processes include, among other things, connecting the various components through one or more layers of metal interconnects, which may include silicides, contacts, metal traces, and vias. Among other differences between FEOL and BEOL processes, the temperatures of BEOL processes tend to be lower than those of FEOL processes. Trench capacitors can typically be partially fabricated during FEOL processes along with the other IC components. For example, reference is made to U.S. Patent No. 10,903,306 and U.S. Patent No.References are made to 11,195,958, which are incorporated herein in their entirety by reference. However, conventional trench capacitors may not provide adequate capacitor density for a given breakdown voltage requirement.

[0013] Several disclosed methods and devices of the present disclosure can be advantageously applied to DC-DC converters and other applications where robustness is required to enable the survival of a device during load transients, short-circuit currents, negative current flow, and other exceptional conditions. Although such examples are expected to provide improvements in performance, such as an improved safe operating area (SOA) and improved robustness, while maintaining or even reducing specific on-resistance, no particular result is a prerequisite of the present invention unless explicitly stated in a specific claim.

[0014] Several disclosed methods and devices of the present disclosure can be advantageously applied to the fabrication of IC devices incorporating integrated trench capacitors. Although such examples can be expected to provide a high capacitance density and / or reduced temperature of capacitor formation relative to some comparable baseline capacitors, no specific result is a prerequisite of the present invention unless explicitly stated in a particular claim.

[0015] Some described examples provide trench capacitors that can be added to a circuit design without affecting FEOL process flows with respect to other devices on the same substrate. Such capacitors can be formed after FEOL processes have been completed. That is to say, the methods disclosed here provide a modular approach to forming trench capacitors with increased capacitor density that meet the requirements of high-voltage breakdown. The devices formed using the methods disclosed here incorporate a trench capacitor using a doped substrate as a "bottom plate" or "bottom electrode" and a metallic material (e.g., tungsten (W)) as a "top plate" or "top electrode." Forming the top plate from the metallic material can provide a lower series resistance than a polysilicon core material.Furthermore, the first metal layer (e.g., the metal-one (M1) layer) formed during the BEOL processing steps (e.g., a metallization process) is formed directly on the top plate of the trench capacitor. This means there are no other intervening conductive features (e.g., conductive vias and / or contacts) between the first metal layer (e.g., the M1 layer) and the top plate of the trench capacitor. This direct contact can enable a higher capacitance density than baseline methods because there are no conductive features (e.g., conductive vias and / or contacts) to align to connect the top plate of the trench capacitor to the first metal layer (e.g., the M1 layer).Because the trench capacitors disclosed here are formed using BEOL processing steps, the trench capacitors and other structures already formed on the device substrate are exposed to lower temperatures than would otherwise occur if the trench capacitors were formed using certain FEOL process steps. Among other advantages, this aspect is expected to reduce the risk of defect formation caused by mechanical stress associated with the higher FEOL process temperatures.

[0016] As revealed here, the trench capacitors are formed after other IC components have formed during the FEOL processes and after a silicide layer and / or a pre-metal dielectric layer have formed in preparation for the formation of contacts and metal conductors between the IC components during the BEOL processes. A trench is formed through the pre-metal dielectric layer and the silicide layer and into the substrate. A capacitor dielectric forms over the pre-metal dielectric layer and within the trench, including along the sidewalls and bottom surfaces of the trench. A conductive material layer forms over the capacitor dielectric layer, including within the trench, to form a capacitor plate (e.g., the top plate). A second trench (e.g., a contact hole) is formed through the pre-metal dielectric layer to expose the silicide layer. A contact feature (e.g., a contact pin) is then formed.The metal contact is formed in the second trench and on the silicide layer positioned above the doped substrate (e.g., the bottom plate). Then, the first metal layer (e.g., the M1 layer) of the BEOL metallization process is formed directly on the capacitor plate (e.g., the top plate). This contrasts with trench capacitors formed using FEOL processing steps, where the metal interleaves typically include an additional vertical interleave (or "contact") to connect the BEOL interleaved metal layers to the capacitor electrodes. Additional process steps and advantages are described in more detail below.

[0017] Now, with reference to Fig. Figure 1 illustrates a flowchart of a process 100 for forming a trench capacitor in a substrate during BEOL processing according to various examples in the present disclosure. Prior to the steps of process 100, the substrate has completed FEOL processing. FEOL processing can be considered to include steps for forming components (e.g., electronic devices) including transistors, diffusion resistors, etc., and ending with the formation of a silicide layer to provide ohmic connections to such devices. BEOL processing can be considered to include those process steps required to form metallic interconnects and dielectric layers necessary for conducting signals between the various devices and for the input / output (I / O) connections of the integrated circuit.In various examples, and as used throughout the following description, the transistors may include field-effect transistors (FETs), bipolar transistors, bipolar-plus-complementary metal-oxide-semiconductor (BiCMOS) transistors, other transistors, or a combination thereof. Additional processes may be provided before, during, and after Procedure 100. As discussed below, Procedure 100 is described with reference to... Fig. 2A-2X described.

[0018] In this respect, Fig. 2A-2X schematic cross-sectional views of devices 200 and 200' at various stages of BEOL production (such as those produced using method 100 from Fig. 1 are associated) according to various aspects of the present disclosure. In various examples, the devices 200 and 200' can be an integrated circuit with completed FEOL processing. For the sake of simplicity, Fig. 2A-2T is illustrated and described without showing other components of the integrated circuit of device 200. Fig. 2U-2X illustrate devices 200 and 200' with a FET formed via FEOL processing steps, adjacent to the trench capacitor formed by method 100 during BEOL processing steps, as shown in Fig. 2A-2X illustrates this. Furthermore, as discussed in more detail below, the process for forming a trench capacitor in device 200 involves the use of a silicide blocking layer, whereas the process for forming a trench capacitor in device 200' takes place without the use of a silicide blocking layer. Therefore, illustrate Fig. 2A, Fig. 2C, Fig. 2E, Fig. 2G, Fig. 2I, Fig. 2K, Fig. 2L, Fig. 2M, Fig. 2N, Fig. 20, Fig. 2P, Fig. 2Q, Fig. 2R, Fig. 2S, Fig. 2T, Fig. 2U and Fig. 2V the process for forming the device 200, which involves the use of a silicide blocking layer, while Fig. 2B, Fig. 2D, Fig. 2F, Fig. 2H, Fig. 2 years Fig. 2W and Fig. 2X highlight some of the differences in forming device 200' without using a silicide blocking layer. Additional features may be added to devices 200 and 200', and some of the features described below may be substituted, modified, or eliminated in other examples of devices 200 and 200'.

[0019] At step 102 from Fig. 1. A substrate with a pre-metal dielectric layer is received during BEOL processing. As in Fig. 2A and Fig. Figure 2B illustrates examples of devices 200 and 200' obtained after completion of FEOL processing steps and after completion of one or more BEOL processes. Some examples include one or more transistors, resistors, and / or other components (e.g., FET 250 in Fig. 2U-2X) on devices 200 and 200' during FEOL processing. This means that the in Fig. Devices 200 and 200' shown in 2A-2T include one or more such devices (e.g., FET 250 in Fig. 2U-2X) that were previously formed during an FEOL processing step and prior to step 102. In some examples, one or more BEOL processing steps may have already taken place on devices 200 and 200', such as the formation of a pre-metal dielectric layer and / or other BEOL material layers.

[0020] In some examples, such as in Fig. As illustrated in Figure 2A, the apparatus 200 comprises a substrate 202, a silicide layer 204, a silicide blocking layer 206, a dielectric lining 208, a pre-metal dielectric layer (PMD) 210, and a first structured photoresist layer 212 with openings 214 formed through it. The substrate 202 can comprise a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, or any other suitable substrate. For example, the substrate 202 can be or include a bulk silicon wafer. In various examples, the substrate 202 can comprise a dielectric material, an epitaxially grown material, and / or any other material and / or layer on which the process described herein can be carried out. For example, the substrate 202 can comprise one or more epitaxially grown layers deposited on a semiconductor substrate (e.g.,silicon substrate). In some examples, the substrate 202, including epitaxially grown layers arranged on it, has doped regions (or troughs) formed therein, such that these doped regions of the substrate 202 form one of the capacitor plates of the subsequently formed trench capacitor, as described in more detail below.

[0021] The silicide layer 204 and the silicide blocking layer 206 are formed on the upper surface of the substrate 202. As shown, in various examples, the silicide layer 204 and the silicide blocking layer 206 can be distributed along the upper surface of the substrate 202 in the plane of the cross-sectional view. This means that the silicide blocking layer 206 blocks / prevents the formation of the silicide layer 204 wherever the silicide blocking layer 206 is present along the upper surface of the substrate 202. In some examples, the silicide layer 204 can be composed of silicon and at least one of cobalt, nickel, tungsten, or titanium (e.g., CoSi₂, Ni₂Si, WSi₂, and / or TiSi₂). The silicide layer 204 provides an ohmic connection for subsequently formed contacts above it and a low-resistance layer on the surface of the semiconductor substrate.In some examples, the silicide-blocking layer 206 includes an oxide material and / or a nitride material that blocks or prevents the formation of a silicide. In some examples, the silicide-blocking layer 206 may include silicon dioxide, silicon nitride, silicon oxynitride, other dielectric films, or a combination thereof. As described below, in some examples, the silicide-blocking layer 206 is positioned over portions of the substrate 202, with the trench capacitor being formed through these portions.

[0022] An optional dielectric lining 208 is formed over both the silicide layer 204 and the silicide blocking layer 206, and a PMD 210 is formed over the dielectric lining 208. The dielectric lining 208 can comprise one or more layers of a dielectric material, including an oxide and / or nitride material, such as silicon oxide and / or silicon nitride. The PMD 210 can comprise one or more layers of a dielectric material. The one or more layers of dielectric material in the PMD 210 can comprise oxide, nitride, and / or carbide materials, such as silicon oxide, silicon nitride, silicon oxynitride, and / or silicon carbide, or the like, or a combination thereof. The use of the term silicon dioxide throughout this entire disclosure includes materials such as silicon monoxide (SiO) and / or silicon dioxide (SiO2) and / or a non-stoichiometric mixture of the two.In various examples, the thickness of the PMD 210 can be determined based on one or more design parameters of the device 200. Accordingly, the initial thickness of the PMD 210 can be greater than the designed thickness to compensate for material loss during one or more of the process steps described below.

[0023] A first structured photoresist layer 212 is formed over the PMD 210. As shown, the first structured photoresist layer 212 is formed directly on the PMD 210 and has openings 214 that expose an upper surface of the PMD 210. The first structured photoresist layer 212 can be any photoresist material, including either positive or negative photoresist materials, or it can be a suitably structured hard mask.

[0024] As discussed previously, illustrates Fig. 2B Device 200', which is processed without the use of a silicide blocking layer. In this respect, Device 200' includes similar layers to Device 200, such as the substrate 202, the silicide layer 204, the dielectric lining 208, the PMD 210, and the first structured photoresist layer 212. The description of these layers is similar to the description given previously for Device 200. As shown, Device 200' includes the silicide layer 204, which extends over the top surface of the substrate 202. Optionally, the silicide layer 204 can be continuous. That is, unlike Device 200, the silicide layer 204 of Device 200' is not interrupted by a silicide blocking layer over the top surface of the substrate 202.

[0025] At step 104 from Fig. 1. A trench is formed through the predielectric material and into the substrate. As in Fig. As shown in Figure 2C-2H, dielectric trenches 216 and expanded trenches 218 are formed in the devices 200 and 200'. In some examples, as in Fig. As illustrated in Figure 2C, dielectric trenches 216 of the device 200 are formed by the PMD 210, the dielectric lining 208 and the silicide blocking layer 206 using the first structured photoresist layer 212 and the openings 214 as a mask.

[0026] In particular, as previously discussed, the dielectric trenches 216 in the device 200 are formed through the silicide blocking layer 206, leaving portions 206' of the silicide blocking layer 206 after trench formation. As discussed in more detail below, these portions 206' increase the distance (e.g., dielectric buffer) between the silicide layer 204 and the capacitor plate, or a terminal, subsequently formed in the dielectric trenches 216. In some examples, the remaining portions 206' of the silicide blocking layer 206 prevent the silicide layer 204 from being exposed during the trench etching processes, which can reduce cross-contamination of the silicide materials from the silicide layer 204 into the substrate 202 (e.g., incorporation of silicide materials into trench walls). In various examples, reducing cross-contamination improves the quality of the silicon trench capacitor (e.g.,higher breakdown voltage, less current leakage loss, etc.). After the formation of the dielectric trenches 216, parts (e.g., the upper surface) of the substrate 202 are exposed within the trenches.

[0027] With reference to device 200', as in Fig. Figure 2D illustrates the formation of dielectric trenches 216 through the PMD 210 and the dielectric lining 208 using the first structured photoresist layer 212 and the openings 214 as a mask. After the formation of the dielectric trenches 216 in the device 200', portions of the silicide layer 204 within the openings 214 are exposed. As discussed in more detail below, subsequent processing steps extend the dielectric trenches 216 through the silicide layer 204 into the substrate 202, so that portions of a capacitor dielectric layer subsequently formed in the trenches abut remaining portions of the silicide layer 204. This means that, unlike device 200, where a silicide blocking layer provides an additional buffer, device 200' allows the silicide layer 204 to be directly adjacent to a capacitor dielectric layer that is subsequently formed in the trenches.

[0028] In various examples, one or more etching processes can be used to form dielectric trenches 216 in the devices 200 and 200'. In various examples, the one or more etching processes can involve dry etching, wet etching, or a combination thereof. In various examples, one or more etching processes can be used to etch through the PMD 210, the dielectric lining 208, and / or the silicide blocking layer 206 to form dielectric trenches 216 in the device 200. In various other examples, one or more etching processes can be used to etch through the PMD 210 and the dielectric lining 208 to form the dielectric trenches 216 in the device 200'. In various examples, a first etching process can be used to form dielectric trenches 216 through the PMD 210.In various examples, a second etching process can be used to widen the dielectric trenches 216 through the dielectric lining 208. In various examples, a third etching process can be used to widen the dielectric trenches 216 through the silicide blocking layer 206 in the device 200.

[0029] As in Fig. 2E and Fig. As shown in Figure 2F, the first structured photoresist layer 212 is removed by the devices 200 and 200'. In some examples, the first structured photoresist layer 212 can be removed by a plasma ashing process. In some other examples, as described below, a first structured photoresist layer 212 can be removed in a subsequent process step of the method 100.

[0030] As in Fig. 2G and Fig. As shown in Figure 2H, the dielectric trenches 216 are extended into the substrate 202, forming extended trenches 218 in devices 200 and 200'. In various examples, the extended trenches 218 can be formed after removal of the first structured photoresist layer 212. In other examples, the extended trenches 218 can be formed before removal of the first structured photoresist layer 212. In device 200, as shown in Figure 2H, the dielectric trenches 216 are extended into the substrate 202, forming extended trenches 218 in devices 200 and 200'. In various examples, the extended trenches 218 can be formed before removal of the first structured photoresist layer 212. Fig. Figure 2G illustrates the dielectric trenches 216 being enlarged by removing portions of the substrate 202 to form the enlarged trenches 218. In the device 200', as shown in Fig. Figure 2H illustrates that the dielectric trenches 216 were enlarged by removing parts of the silicide layer 204 and the substrate 202 to form the enlarged trenches 218.

[0031] In various examples, one or more etching processes can be used to form the enlarged trenches 218 in the devices 200 and 200'. In various examples, the one or more etching processes can involve wet etching, dry etching, or a combination thereof. In some examples, with respect to the device 200', a silicide etching process can be performed, followed by a silicon etching process if the substrate 202 contains silicon material (e.g., Fig. 2H). The silicide etching process removes portions of the silicide layer 204 to expose an upper surface of the substrate 202, and the silicon etching process widens the widened trenches 218 into the substrate 202. In some examples, with reference to the apparatus 200, a silicon etching process can be carried out to remove portions of the substrate 202 (e.g., silicon substrate) without the silicide etching process (e.g., Fig. 2G) to remove, since the previously removed portions of the silicide-blocking layer 206 prevented silicide formation in the areas through which the enlarged trenches are formed. In some examples, the one or more etching processes may involve one or more dry etching processes, including the use of chlorine (Cl), fluorine (F), bromine (Br), other etchants, or a combination thereof.

[0032] As previously described, in some examples, the substrate 202 includes epitaxially grown layers with doped regions (or troughs) formed therein, such that these doped regions of the substrate 202 form one of the capacitor plates of the subsequently formed trench capacitor, as described in more detail below. In various examples, an angled implantation process can be performed on the sidewall surfaces of the expanded trenches 218 after the formation of the expanded trenches 218. (See, e.g., BUS Patent No. 11,195,958.) Such an implantation process implants a dopant (e.g., arsenic (As), phosphorus (P), etc.) into the sidewalls of the expanded trenches 218. In some examples, the implantation process can involve an oblique implantation process.The implanted doping material in the side walls of the enlarged trenches 218 can help in reducing a series resistance of the parts of the substrate 202 that form one of the capacitor plates of the subsequently formed trench capacitor.

[0033] At step 106 from Fig. 1. A capacitor dielectric layer is formed in the trench. As in Fig. 2I and Fig. As shown in Figure 2J, a capacitor dielectric layer 220 is formed in the expanded trenches 218 in the devices 200 and 200'. In particular, the capacitor dielectric layer 220 is formed over the PMD 210 and in the expanded trenches 218, including along the side walls and lower surfaces of the expanded trenches 218. In some examples for the device 200, as in Fig. As shown in Figure 2I, a capacitor dielectric layer 220 is formed along the side walls of the PMD 210, the side walls of the dielectric lining 208, the side walls of the parts 206' of the silicide blocking layer 206, and the side walls and lower surfaces of the substrate 202. In some other examples for the device 200', as in Fig. As shown in Figure 2J, a capacitor dielectric layer 220 is formed along side walls of the PMD 210, side walls of the dielectric lining 208, side walls of the silicide layer 204 and side walls and lower surfaces of the substrate 202.

[0034] In various examples, the capacitor dielectric layer 220 can be formed by one or more processes, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), thermal oxidation, other suitable formation processes, or a combination thereof. In various examples, the capacitor dielectric layer 220 can be formed as one or more layers formed during one or more process steps. In various examples, the capacitor dielectric layer 220 can include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, any other high-k dielectric material, another suitable dielectric material, or a combination thereof. In some examples, the capacitor dielectric layer 220 can be a multilayer film including an oxide / nitride / oxide configuration.

[0035] Fig. 2K-2X and their descriptions below are given with reference to the examples for device 200, which includes the silicide-blocking layer 206, and do not include examples for device 200' formed without the silicide-blocking layer 206. This is for the sake of simplicity and to facilitate the subsequent discussion. In particular, the steps of method 100 below are similar regardless of whether the silicide-blocking layer 206 is present or not. Accordingly, the examples for device 200' without the silicide-blocking layer 206 are omitted for the sake of simplicity in the discussion. Fig. 2K-2X (except Fig. 2T') not illustrated.

[0036] At step 108 from Fig. 1. A conductive plug is formed in the trench above the capacitor dielectric layer. As in Fig. As shown in Figure 2K, a capacitor plate 222, including conductive plugs 221, is formed in the expanded trenches 218. In some examples, a conductive material layer (e.g., layer(s) of electrically conductive trench fill material and / or barrier layers) is formed over the capacitor dielectric layer 220 and within the expanded trenches 218. A planarization process (e.g., a chemical-mechanical polishing (CMP) process) is then performed to remove the excess portions of the conductive material layer to form the capacitor plate 222. In some examples, as in Fig. As shown in Figure 2K, the planarization process removes the overhanging portions of the conductive material layer and exposes the capacitor dielectric layer 220, which is arranged above the PMD 210. In some other examples, such as in Fig. As shown in Figure 2L, the planarization process removes the overhanging portions of the conductive material layer arranged above PMD 210, as well as portions of the capacitor dielectric layer 220 arranged above PMD 210, to expose PMD 210. As shown, after the planarization process of the conductive material layer, one or more conductive plugs 221 are arranged in the enlarged grooves 218. The capacitor plate 222 incorporates the one or more conductive plugs 221, which are electrically connected in parallel, as described below.

[0037] In various examples, the conductive plugs 221 of the capacitor plate 222 can include one or more layers of metal and / or metal alloys. In various examples, the conductive plugs 221 of the capacitor plate 222 can include a tungsten metal. In various examples, the conductive plugs 221 of the capacitor plate 222 can be a multilayer material layer that includes one or more barrier layers and / or layer(s) of an electrically conductive trench filler. For example, the conductive plugs 221 of the capacitor plate 222 can include tantalum (Ta), titanium (Ti), and / or titanium nitride (TiN) barrier layers and a W, TiW, and / or TaN conductive filler layer. In various other examples, the conductive plugs 221 of the capacitor plate 222 can include aluminum (Al), copper (Cu), doped polycrystalline silicon, alloys thereof, or other suitable conductive materials.In various examples, the capacitor plate 222 can be formed using one or more processes. In these various examples, the one or more processes used to form the capacitor plate 222 can include a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, a sputtering process, an evaporation process, other suitable processes, or a combination thereof.

[0038] As discussed in more detail below and as in Fig. 2K and Fig. As shown in Figure 2L, a trench capacitor 240 is formed in the device 200 as a result of the formation of the capacitor plate 222. In particular, the capacitor plate 222 and the substrate 202 form the capacitor plates of the trench capacitor 240. In this respect, as discussed previously, the substrate 202, including epitaxially grown layers arranged on it, can have doped regions (or wells) formed therein, such that these doped regions of the substrate 202 form a first capacitor plate (e.g., lower capacitor plate) of the trench capacitor 240. Furthermore, in some examples, the capacitor plate 222 forms a second plate (e.g., an upper capacitor plate) of the trench capacitor 240. As shown, the trench capacitor 240 also includes the capacitor dielectric layer 220, which is located between the substrate 202 (e.g., the first capacitor plate) and the capacitor plate 222 (e.g.,the second capacitor plate) is positioned, thus isolating the two plates from each other.

[0039] Furthermore, as previously described and in Fig. 2K and Fig. Figure 2L shows the device 200 parts 206' of the silicide blocking layer 206, which adjoin the capacitor dielectric layer 220. This increases the distance between the silicide layer 204 and the capacitor plate 222, partly due to the parts 206' of the silicide blocking layer 206. That is, these parts 206' of the silicide blocking layer 206 increase the distance (e.g., dielectric buffer) between the silicide layer 204 and the capacitor plate 222. In some examples, parts 206' of the silicide blocking layer 206 prevent the silicide layer 204 from being exposed during trench etching processes, which can reduce cross-contamination of the silicide materials from the silicide layer 204 into the substrate 202 (e.g., incorporation of silicide materials into trench walls). In various examples, reducing cross-contamination improves the quality of the silicon trench capacitor (e.g.,higher breakdown voltage, less current leakage loss, etc.).

[0040] At step 110 from Fig. 1. A contact opening is formed by the dielectric material. As in Fig. As shown in Figure 2M-2P, the contact openings 228 are formed through the PMD 210. A second structured photoresist layer 224 is formed over the device 200 and has openings 226 formed through it, exposing underlying areas through which contact openings are subsequently formed. In some examples, as in Fig. As shown in Figure 2M, the second structured photoresist layer 224 is formed over the capacitor dielectric layer 220. This means that Fig. 2M from the process of the device 200 Fig. 2K follows, whereby the planarization process stops at the capacitor dielectric layer 220, so that the second structured photoresist layer 224 is formed on it. Therefore, in Fig. 2M Openings 226 of the second structured photoresist layer 224 Parts of the underlying capacitor dielectric layer 220 free. In some other examples, as in Fig. As shown in 2N, the second structured photoresist layer 224 is formed above the PMD 210. This means that Fig. 2N the process of the device 200 from Fig. 2L follows, whereby the planarization process removes the capacitor dielectric layer 220 to expose the underlying PMD 210, so that the second structured photoresist layer 224 is formed on the PMD 210. Therefore, in Fig. 2N Openings 226 of the second structured photoresist layer 224 parts of the underlying PMD 210 free.

[0041] As in Fig. 20 and Fig. As shown in Figure 2P, contact openings 228 are formed through the PMD 210 using the second structured photoresist layer 224 as a mask. In some examples, as in Fig. As shown in Figure 20, the contact openings 228 are formed through the capacitor dielectric layer 220, the PMD 210, and the dielectric lining 208, thereby exposing the silicide layer 204. This means that Fig. 2O the process of the device 200 from Fig. 2M follows, wherein the capacitor dielectric layer 220 is arranged over the PMD 210, such that the contact openings 228 extend through various layers, including the portions of the capacitor dielectric layer 220 that are arranged over the PMD 210. Therefore, portions of the capacitor dielectric layer 220 define portions of the sidewalls of the contact openings 228. In some other examples, such as in Fig. As illustrated in Figure 2P, the contact openings 228 are formed through the PMD 210 and the dielectric lining 208, exposing the silicide layer 204. In various examples, one or more etching processes can be used to etch through the PMD 210 and the dielectric lining 208. This means that Fig. 2P from the process of the device 200 Fig. 2N follows, whereby the capacitor dielectric layer 220 above the PMD 210 has been removed. Therefore, in contrast to Fig. 20, side walls of contact openings 228 partially defined by discontinuous parts of the capacitor dielectric layer 220, since this layer above the PMD 210 was removed, as previously described with reference to Fig. 2L discussed. The one or more etching processes for forming the contact openings 228 may involve a wet etching process, a dry etching process, other suitable processes, or a combination thereof. In various examples, the one or more etching processes may be similar to those previously discussed in Fig. 2A-2F were described.

[0042] As in Fig. 2Q and Fig. As shown in Figure 2R, the second structured photoresist layer 224 can be removed from the device 200 before the contacts 230 are formed. In various examples, as in Fig. As shown in 2Q, the second structured photoresist layer 224 can be removed, exposing the capacitor dielectric layer 220. This means that Fig. 2Q the process of the device 200 from Fig. 2O follows, wherein the capacitor dielectric layer 220 is arranged above the PMD 210, such that the removal of the second structured photoresist layer 224 exposes parts of the capacitor dielectric layer 220 that is arranged above the PMD 210. In some other examples, such as in Fig. As shown in 2R, the second structured photoresist layer 224 can be removed, exposing the PMD 210. This means that Fig. 2R from the process of the device 200 Fig. 2P follows, whereby the capacitor dielectric layer 220 above the PMD 210 has been removed. Therefore, the removal of the second structured photoresist layer 224 exposes the underlying PMD 210. Furthermore, as in Fig. 2Q and Fig. Figure 2R shows the removal of the second structured photoresist layer 224 and also frees the conductive plugs 221 of the capacitor plate 222. In various examples, the second structured photoresist layer 224 can be removed by one or more processes, including a plasma ashing process.

[0043] In step 112, contacts are formed in the contact openings. As in Fig. 2S and Fig. As shown in Figure 2T, a conductive material layer (e.g., a layer of electrically conductive backfill material and / or barrier layers) is formed in contact openings 228, and a planarization process is carried out to form contacts 230. In various examples, the conductive material layer can be similar to the conductive material layer used in the capacitor plate 222 previously shown in Figure 2T. Fig. 2K and Fig. 2L was described. In various other examples, the conductive material layer of the contacts 230 can (i) include one or more metal barrier and / or adhesion layers (e.g., TiN, TaN, or the like, or a combination thereof) conformally in respective contact openings 228 and (ii) a filler metal (e.g., Al, Cu, W, or the like, or a combination thereof) over and / or on the metal barrier and / or adhesion layer(s). In various examples, the planarization process used to form the contacts 230 can include one or more CMP processes and / or other suitable planarization processes. In some examples, as in Fig. As shown in Figure 2S, the planarization process can be carried out to remove excess conductive material (e.g., the overhang of the conductive material), exposing the upper surface of the capacitor dielectric layer 220. That is to say, Fig. 2S from the process of the device 200 Fig. 2Q follows, wherein the capacitor dielectric layer 220 is arranged above the PMD 210, such that the respective upper surfaces of the capacitor dielectric layer 220 and the contacts 230 are planarized. In some other examples, the method 100 of Fig. 2Q to Fig. 2T, where the planarization process can be carried out to remove excess conductive material (e.g., the overhang of conductive material) used to form the contacts 230, a portion of the conductive material from the capacitor plate 222, and the capacitor dielectric layer 220, exposing the top surface of the PMD 210. In some other examples, the process can be 100 of Fig. 2R to Fig. 2T, where the planarization process can be carried out to remove excess conductive material (e.g., the overhang of conductive material) used to form the contacts 230, thereby exposing the upper surface of PMD 210. That is to say that Fig. 2T in this example, the process of device 200 from Fig. 2R follows, whereby the capacitor dielectric layer 220 has already been removed above the PMD 210, so that the respective upper surfaces of the PMD 210 and the contacts 230 are planarized.

[0044] Now, with reference to Fig. 6A-6E are in conjunction with Fig. 2T and Fig. 2T' Top views of device 200 or device 200' are shown. Each of Fig. Figures 6A-6E show a different top view (e.g., in the negative y-direction) at a given depth, as in Fig. 2T and Fig. 2T' is indicated. In this respect, Fig. 6A, Fig. 6B, Fig. 6C, Fig. 6D and Fig. 6E Top views of the device 200, while Fig. Figure 6D' shows a top view of device 200'.

[0045] With reference to Fig. 6A is a top view of device 200 in the in Fig. 2T is shown by a line 6A indicating the height. In this respect, it shows Fig. Figure 6A shows a plan view in one plane through the PMD 210 in the device 200, showing the conductive plugs 221, the capacitor dielectric layer 220, and the contacts 230. As shown, the capacitor dielectric layer 220 and the conductive plugs 221 are further formed by the dielectric lining 208, as previously described. In addition, in some examples, as shown, the conductive plugs 221 and / or the contacts 230 may have a circular cross-sectional shape. In other examples, the conductive plugs 221 and / or the contacts 230 may have other cross-sectional shapes, such as square, oval, triangular, rectangular, or the like, or a combination thereof.

[0046] Various examples, such as in Fig. As shown in Figure 6A, the contacts 230 can be aligned in a linear row (or column). In other examples, the contacts 230 may include contacts that are not aligned in a linear row (or column), so that one or more contacts are offset from an adjacent contact. Furthermore, there can be any number of contacts 230, and the exact number shown in Figure 6A is not specified. Fig. Figure 6A is shown as an example and should not be interpreted as limiting.

[0047] Various examples, such as in Fig. As shown in Figure 6A, the conductive plugs 221 can form a checkerboard pattern (e.g., offset from one another) or a hexagonal array. In other examples, the conductive plugs 221 can be oriented in any way with respect to one another, including in rows and / or columns. In other examples, the conductive plugs 221 can include plugs that are not aligned in a linear row (or column), such that one or more conductive plugs are offset from an adjacent conductive plug. Furthermore, there can be any number of conductive plugs 221, and the exact number shown in Figure 6A is not specified. Fig. Figure 6A is shown as an example and should not be interpreted as limiting.

[0048] Fig. Figure 6B shows a top view of the device 200 in the Fig. 2T by a line 6B indicates the height. In this respect, it shows Fig. Figure 6B shows a top view in one plane in the device 200 through parts 206' of the silicide blocking layer 206. As shown, the capacitor dielectric layer 220 and the conductive plugs 221 are formed by the dielectric lining 208 and parts 206' of the silicide blocking layer 206, as previously described.

[0049] Fig. Figure 6C shows a top view of the device 200 in the Fig. 2T by a line 6C indicated height. In this respect, it shows Fig. Figure 6C shows a top view in one plane of the device 200, which is positioned below the PMD 210 and through the dielectric lining 208. As shown, the capacitor dielectric layer 220, the conductive plugs 221, and the contacts 230 are formed by the dielectric lining 208 and parts 206' of the silicide blocking layer 206, as previously described.

[0050] Fig. Figure 6D shows a top view of the device 200 in the in Fig. 2T through a line 6D specified height. In this respect, it shows Fig. Figure 6D shows a top view in one plane of the device 200, positioned below the dielectric lining 208, and through the silicide layer 204 and the substrate 202. As shown, the capacitor dielectric layer 220 and the conductive plugs 221 are laterally surrounded by the silicide layer 204 and portions of the substrate 202 at the same level as previously described. As shown, portions of the substrate 202 prevent the silicide layer 204 from adjoining the capacitor dielectric layer 220. Furthermore, Figure 6D shows... Fig. 6D the silicide layer 204, which ends at an insulation feature 266 in the device 200.

[0051] Now, with reference to Fig. 6D' and Fig. 2T' shows Fig. 6D' a top view for the device 200' in the in Fig. 2T' by a line 6D' indicates the height. In this respect, it shows Fig. 6D' a top view in one plane in the device 200', which is at the same height as Fig. 6D is positioned. In contrast to the device 200 at this height, the silicide layer 204 extends to the dielectric layer 220 due to the absence of the silicide blocking layer 206. Therefore, the capacitor dielectric layer 220 borders the silicide layer 204, as previously described.

[0052] Fig. Figure 6E shows a top view of the device 200 in the Fig. 2T indicates a height through a line 6E. In this respect, it shows Fig. Figure 6E shows a top view in one plane of the device 200, which is positioned by the substrate 202. As shown, the capacitor dielectric layer 220 and the conductive plugs 221 are formed by the substrate 202, as previously described.

[0053] In several examples, steps 110 and 112 can be performed simultaneously with the contacting of contacts to other FEOL features and components. In several examples, steps 110 and 112 can be performed as previously described even if a silicon trench capacitor, such as the one described here, is not formed. In this respect, the silicon trench capacitor described here is modular and can be added to or removed from integrated semiconductor devices with little or no change to the processes used for other components.

[0054] At step 114 from Fig. 1. A metal layer is formed over the PMD for connection to the conductive plugs and contacts. As in Fig. Figure 2U shows the device 200 including the trench capacitor 240, a FET 250, and a structured metal layer 232 connected to the various components shown. When connected by the structured metal layer 232, the conductive plugs 221 act as a capacitor plate 222. The trench capacitor 240 is formed by steps 102-112 of method 100 as part of a BEOL process, as described previously. The FET 250 is formed during an FEOL process prior to step 102 of method 100, as described previously. Furthermore, Fig. 2U the process of the device 200 from Fig. 2S, wherein the capacitor dielectric layer 220 is arranged above the PMD 210, such that the structured metal layer 232 is formed on the capacitor dielectric layer 220. Therefore, the capacitor dielectric layer 220 is positioned between the structured metal layer 232 and the upper surface of the PMD 210. In various examples, the structured metal layer 232 can comprise a metal and / or a metal alloy. In various examples, the metal and / or metal alloy can be or comprise Al, Cu, an aluminum-copper alloy (AlCu), or the like.

[0055] The FET 250 comprises a doped well 252, a first source / drain region 254, a second source / drain region 256, a gate stack 258, a first source / drain contact 260, a second source / drain contact 262, a gate contact 264, and an insulating feature 266. As shown, the doped well 252 is located in the substrate 202 beneath the first source / drain region 254, the second source / drain region 256, and the gate stack 258. In various examples, one or more processes can be performed on the semiconductor substrate to form the doped well 252. The doped well 252 contains an n-type or p-type dopant and can be lightly or heavily doped in various examples. In various examples, the doped trough 252 can have an opposite doping of the substrate 202 of the trench capacitor 240.

[0056] The first source / drain region 254 and the second source / drain region 256 can be arranged in or on the substrate 202. In various examples, one or more materials can be formed, deposited, or grown on the substrate 202 to create the first source / drain region 254 and the second source / drain region 256. For example, an etching process can be performed on the substrate 202 to create depressions in which an epitaxial growth process is then carried out to grow a semiconductor material to form the first source / drain region 254 and the second source / drain region 256. In other examples, the substrate 202 is doped to create the first source / drain region 254 and the second source / drain region 256. In various examples, the first source / drain region 254 and the second source / drain region 256 can undergo a doping process, such as one or more ion implantation processes.The first source / drain region 254 and the second source / drain region 256 can be doped with p-type or n-type dopants, depending on the desired design requirements. Furthermore, as shown, the silicide layer 204 is applied to the first source / drain region 254 and the second source / drain region 256.

[0057] The gate stack 258 is arranged above the substrate 202 between the first source / drain region 254 and the second source / drain region 256. The gate stack 258 (e.g., gate structure) can include a gate dielectric layer and a gate electrode layer. The gate dielectric layer can include any gate dielectric material, including a high-k dielectric material (e.g., dielectric constant greater than silicon dioxide). In various examples, the gate dielectric material layer can include materials such as silicon dioxide, hafnium oxide, and / or zirconium oxide. The gate electrode layer can include any gate electrode material layer(s). In various examples, the gate electrode layer can include polycrystalline silicon, also known as polysilicon. In other examples, the gate electrode layer may contain other metals or metal alloys.For example, the gate electrode layer can contain metal alloys such as TiN and / or TaN. In other examples, the gate electrode layer can contain Cu, W, and / or Al.

[0058] The first source / drain contact 260 and the second source / drain contact 262 extend through the capacitor dielectric layer 220, the PMD 210, the electrical lining 208, and to the silicide layer 204, which is arranged above the first source / drain region 254 and the second source / drain region 256, respectively. The gate contact 264 extends through the capacitor dielectric layer 220, the PMD 210, and the dielectric lining 208 to the gate stack 258. In some examples, the first source / drain contact 260, the second source / drain contact 262, and the gate contact 264 can be formed during the same process previously discussed with reference to the formation of the contacts 230. In other examples, the first source / drain contact 260, the second source / drain contact 262 and the gate contact 264 can be formed during a different BEOL process that occurs before and / or after the formation of the contacts 230, as discussed previously.In various examples, the first source / drain contact 260, the second source / drain contact 262 and the gate contact 264 can each (i) conform to one or more metal barrier and / or adhesion layers (e.g. TiN, TaN or the like or a combination thereof) in a respective trench through the dielectric lining 208 and (ii) include a filler metal (e.g. Al, Cu, W or the like or a combination thereof) over and / or on the metal barrier and / or adhesion layer(s).

[0059] As shown, the insulation feature 266 provides electrical insulation between the respective parts of the substrate containing the trench capacitor 240 and the FET 250. In various examples, the insulation feature 266 can include a shallow trench insulation (STI) structure and / or a deep trench insulation structure. The insulation feature 266 electrically isolates the trench capacitor 240 from the FET 250. In various examples, the insulation feature 266 can include dielectric materials that provide electrical insulation, such as silicon dioxide, silicon nitride, silicon oxynitride, or the like, and / or a combination thereof.

[0060] As in Fig. As shown in Figure 2U and in various examples, the structured metal layer 232 of the device 200 is formed over the capacitor dielectric layer 220, the capacitor plate 222, and the various contact features (e.g., the first source / drain contact 260, the second source / drain contact 262, the gate contact 264, and the contacts 230). In particular, in some examples, the structured metal layer 232 of the device 200 is formed directly on the respective upper surfaces of the capacitor dielectric layer 220, the capacitor plate 222, and the various contact features (e.g., the first source / drain contact 260, the second source / drain contact 262, the gate contact 264, and the contacts 230). In some examples, in particular, the structured metal layer 232 is formed over the trench capacitor 240 and physically contacts the capacitor dielectric layer 220, the capacitor plate 222 and the contacts 230.Furthermore, in some examples, the structured metal layer 232 is formed over the FET 250 and physically contacts the capacitor dielectric layer 220, the first source / drain contact 260, the second source / drain contact 262, and the gate contact 264 associated with the FET 250. In various examples, one or more parts of the structured metal layer 232 can contact both the trench capacitor 240 and the FET 250. As shown, the structured metal layer 232 includes respective metal conductors 233a-e that are connected to the first source / drain contact 260, the gate contact 264, the second source / drain contact 262, the contacts 230, and the capacitor plate 222 of the trench capacitor 240.

[0061] In contrast to trench capacitors formed during FEOL process steps, the formation of trench capacitor 240 during BEOL processes advantageously allows a first metal layer (e.g., M1 layer) to be directly connected to conductive plugs 221 of the capacitor plate 222 of trench capacitor 240. This means that the BEOL process formation of trench capacitor 240 allows the top plate (e.g., capacitor plate 222) of the trench capacitor to be directly connected to the first metal layer (e.g., metal layer 1) without the use of conductive vias and / or additional contacts.As a result, the capacitor density can be increased because there are no contact placement alignment tolerance problems that are normally associated with aligning the trench capacitor formed during FEOL process steps with conductive vias and / or contacts formed during a BEOL process to connect to the trench capacitor.

[0062] In other examples, such as in Fig. As shown in 2V, the process for device 200 can alternatively be performed by Fig. 2T to Fig. 2V passes over the device 200 during the formation of the structured metal layer 232. The device 200 in Fig. 2V is the device 200 in Fig. 2U similar, except with regard to the capacitor dielectric layer 220. In contrast to Fig. 2U, the capacitor dielectric layer 220 was at some point during the process disclosed by method 100 (see Fig. 2L and Fig. 2T), for which in Fig. The device 200 shown is removed from the upper surface of the PMD 210. Therefore, the structured metal layer 232 is formed over the PMD 210, the capacitor plate 222, and the various contact features (e.g., the first source / drain contact 260, the second source / drain contact 262, the gate contact 264, and the contacts 230). In particular, in some examples, the structured metal layer 232 of the device 200 is formed directly on the respective upper surfaces of the PMD 210, the capacitor plate 222, the capacitor dielectric layer 220 lining the capacitor plate, and the various contact features (e.g., the first source / drain contact 260, the second source / drain contact 262, the gate contact 264, and the contacts 230).Therefore, in some examples, the structured metal layer 232 is formed over the trench capacitor 240 and physically contacts the PMD 210, the capacitor dielectric layer 220, the capacitor plate 222, and the contacts 230. Furthermore, in some examples, the structured metal layer 232 is also formed over the FET 250 and physically contacts the PMD 210, the first source / drain contact 260, the second source / drain contact 262, and the gate contact 264. In various examples, one or more parts of the structured metal layer 232 can contact both the trench capacitor 240 and the FET 250.

[0063] Fig. 2W and Fig. Figures 2X show the device 200' after it has completed steps 102-114 of method 100. As previously described, the device 200' differs from the device 200 in that it lacks a silicide blocking layer used during the processing steps of method 100. The absence of a silicide blocking layer can cause the silicide layer 204 to abut (e.g., physically contact) parts of the trench capacitor 240. In particular, in some examples, as shown in Fig. 2W and Fig. 2X and in a top view in Fig. 6D' shown, to the capacitor dielectric layer 220 of the trench capacitor 240 in the Fig. 2W and Fig. 2X device shown 200' (e.g., physically contacts it).

[0064] Furthermore, the following Fig. 2W the process of the device 200' from process steps similar to those in Fig. Figure 2S shows the capacitor dielectric layer 220 arranged above the PMD 210, such that the structured metal layer 232 is formed on the capacitor dielectric layer 220. Therefore, the capacitor dielectric layer 220 is positioned between the structured metal layer 232 and the upper surface of the PMD 210. Furthermore, the following Fig. 2X the process of the device 200' from the process steps similar to those that are in Fig. 2T are shown, wherein the capacitor dielectric layer 220 at any time during the process disclosed by method 100 (see Fig. 2 L and Fig. 2T), was removed from the upper surface of PMD 210. Therefore, the structured metal layer 232 is formed on PMD 210, capacitor plate 222, and the various contact features (e.g., the first source / drain contact 260, the second source / drain contact 262, gate contact 264, and contacts 230). All other features of the device 200' in Fig. 2W and Fig. 2X are the characteristics of the previously mentioned with reference to Fig. Device 200 described in 2U or 2V is similar. For the sake of brevity and clarity, similar features between device 200 and 200' are not repeated here.

[0065] Accordingly, the steps of procedure 100, as previously referred to, represent Fig. Procedure 2A-2X describes steps for forming a trench capacitor while BEOL is ready. This means that trench capacitors are formed after forming other components, such as transistors, resistors, inductors, and other capacitors, after forming a PMD across the device, and before forming the metal connections between the various components. In various examples, trench capacitors formed using the steps of Procedure 100 can exhibit a higher capacitor density for a given voltage node or breakdown requirement.

[0066] Furthermore, there is a reduced risk of defect formation in the trench capacitor because it is formed during the lower temperatures used in BEOL processing compared to the higher temperatures used during FEOL processing steps. Other advantages include connecting the top plate of the trench capacitor directly to metal conductors (e.g., metal layer 1) without the use of vias and / or additional contacts. This means that the disclosed process forms the first metal layer (e.g., M1 layer) of the BEOL metallization process directly on the capacitor plate (e.g., the top plate). This contrasts with trench capacitors formed during FEOL processing steps, where the first metal layer (e.g., M1 layer) of the BEOL metallization process is not directly on the capacitor plate (e.g., the top plate).Instead of being formed on the top plate, the capacitor is formed on intermediate conductive vias that are first formed on the capacitor plate. This allows for increased capacitor density, as there are no placement-alignment tolerance issues associated with a conductive via (e.g., a contact). Therefore, the capacitor trenches can be packed more densely. The increased density occurs because the trenches used to form the capacitor plate can be narrower for a given manufacturing node. The narrower trench width increases the capacitance per unit area. Furthermore, forming the top plate of the trench capacitor from a metal (e.g., tungsten) reduces the series resistance of the trench capacitor compared to a poly-core. The metal can be used due to the lower processing temperatures of BEOL processes.Accordingly, the silicon trench capacitor described here is modular, flexible and can be adapted to fit the design parameters of a variety of integrated semiconductor devices.

[0067] Now, with reference to Fig. Figure 3 illustrates a flowchart of a process 300 for forming a trench capacitor in a substrate during BEOL processing, as shown in various examples from this disclosure. Prior to the steps of process 300, the substrate has completed FEOL processing. Typically, FEOL processing involves forming integrated circuit components, including transistors, resistors, capacitors, inductors, etc., and BEOL processing involves forming silicide layers and metal interleaves to connect each of the integrated circuit components. In various examples, and as used throughout the following description, the transistors may include FETs, bipolar transistors, BiCMOS transistors, other transistors, or a combination thereof. Additional processes may be provided before, during, and after process 300.As discussed below, the procedure 300 is with reference to . Fig. 4A-4H described.

[0068] In this respect, Fig. 4A-4H Schematic cross-sectional views of a device 400 at various stages of production (such as those produced using method 300). Fig. 3 are associated) according to various aspects of the present disclosure. In various examples, the device 400 can be an integrated circuit with completed FEOL processing, wherein transistors, resistors, inductors, capacitors and / or other components were formed during various processing steps prior to the steps of the method 300. For ease of discussion, Fig. 4A-4F are illustrated and described without showing other components of the integrated circuit of device 400. Fig. 4G and Fig. Figure 4H illustrates a FET adjacent to the trench capacitor formed by method 300 and in Fig. Figures 4A-4F illustrate this. Additional features may be added to the device 400, and some of the features described below may be substituted, modified, or eliminated in other examples of the device 400.

[0069] Device 400 includes similar layers to those in Fig. 2A-2X The device 200 described above, including a substrate 402, a silicide layer 404, a silicide blocking layer 406, a dielectric lining 408, a PMD 410, a capacitor dielectric layer 420, a structured photoresist layer 424, a conductive plug 421, a capacitor plate 422, contacts 430, and a structured metal layer 432, descriptions of which may not be repeated below. In various examples, the device 400 can be formed without the silicide blocking layer 406, similar to various examples of the device 200 described above.

[0070] At step 302 from Fig. 3. A substrate with a PMD over it is received for BEOL processing. The substrate is received after completion of FEOL processing steps, such as forming transistors, resistors, capacitors, inductors, and / or other components, and after completion of one or more BEOL processes. As in Fig. As shown in Figure 4A, the device 400 is received after FEOL processing and one or more BEOL processes have been completed. In some examples, one or more transistors, resistors, capacitors, inductors, and / or other components (e.g., FET 450 in) are used. Fig. 4G and Fig. 4H) on the device 400 during FEOL processing. In some examples, a silicide layer, a dielectric layer, and / or other BEOL material layers can be formed over the device 400. Accordingly, in various examples, the device 400 includes the silicide layer 404 and the silicide blocking layer 406, which are formed over an upper surface of the substrate 402. In various examples, the silicide layer 404 and the silicide blocking layer 406 can be distributed along an upper surface of the substrate 402, as shown in Fig. Figure 4A shows the dielectric lining 408 being formed over both the silicide layer 404 and the silicide blocking layer 406, and a PMD 410 being formed over the dielectric lining 408.

[0071] At step 304 from Fig. 3. A trench is formed through the PMD and into the substrate. For the sake of clarity and brevity, the following is shown in Fig. Device 400 shown in 4A Fig. The device shown in 2I is similar to the device 200. That is to say, the process previously described with reference to method 100, which is used to form the in Fig. The device shown in 2I 200 is used equally for forming the in Fig. The device shown in 4A can be used. Therefore, the devices used to form the images in Fig. The device shown in 4A used process steps similar to those previously described with reference to Fig. 2A-2I were discussed. As in Fig. As shown in Figure 4A, enlarged trenches 418 are formed through the PMD 410, the dielectric lining 408, and the silicide blocking layer 406, extending into the substrate 402. The enlarged trenches 418 can be formed using one or more etching processes. In various examples, the one or more etching processes may be similar to those previously described in Fig. 2C-2H were described.

[0072] At step 306 from Fig. 3. A capacitor dielectric layer is formed in the trench. Continuing with Fig. 4A The capacitor dielectric layer 420 can be formed over the PMD 410 and in the expanded trenches 418. In particular, the capacitor dielectric layer 420 can be formed along the sidewalls of the PMD 410, the sidewalls of the dielectric lining 408, the sidewalls of the silicide blocking layer 406, and the sidewalls and lower surfaces of the expanded trenches 418. In various examples, the capacitor dielectric layer 420 can be formed using processes similar to those previously described in Fig. 2I and Fig. 2J with reference to the formation of the capacitor dielectric layer 220 were described.

[0073] At step 308 from Fig. 3. A sacrificial material layer is formed in the trench above the capacitor dielectric layer. As in Fig. As shown in Figure 4B, a sacrificial layer 425 is formed in expanded trenches 418, including over the capacitor dielectric layer 420. In various examples, the sacrificial layer 425 fills the expanded trenches 418 (e.g., up to and / or above an upper surface of the PMD 410 and / or the capacitor dielectric layer 420). After the expanded trenches 418 are filled with the sacrificial layer 425, a structured photoresist layer 424 is formed over the device 400. In particular, the structured photoresist layer 424 is formed over the sacrificial layer 425 and the capacitor dielectric layer 420. In some examples, the sacrificial layer 425 can be an antireflective coating material, such as a bottom antireflective coating (BARC). In other examples, the sacrificial layer 425 can be a photoresist material.In other examples, the sacrificial layer 425 can be a combination of an antireflective coating material and a photoresist material. In various examples, the structured photoresist layer 424 and the sacrificial layer 425 can be the same material or have different material compositions. In various examples, the structured photoresist layer 424 and the sacrificial layer 425 can be formed using the same or different processes. Initial openings 426 are formed by the structured photoresist layer 424, exposing the sacrificial layer 425. In various examples, the initial openings 426 are offset by the sacrificial layer 425, which fills the enlarged trenches 418.In other words, the first openings 426 are formed over parts of the silicide layer 404, which are covered by various layers including parts of the capacitor dielectric layer 420, which is arranged over the upper surface of the PMD 410.

[0074] At step 310 from Fig. 3. A contact opening is formed by the PMD, which lands on a silicide layer. As in Fig. As shown in Figure 4C, the contact openings 428 are formed by the sacrificial layer 425, the capacitor dielectric layer 420, the PMD 410, and the dielectric lining 408 to expose portions of the silicide layer 404. In various examples, the contact openings 428 can be formed using one or more etching processes. In various examples, the contact openings 428 (e.g., contact holes) can be similar to those previously shown in Fig. 20 and Fig. The contact opening 228 described in procedure 100 is formed as described in step 2P. As in Fig. As shown in Figure 4C and in some examples, the contact openings 428 expose an upper surface of the silicide layer 404.

[0075] At step 312 from Fig. 3. The layer of sacrificial material is removed from the trench. As in Fig. As shown in Figure 4D, the structured photoresist layer 424 and the sacrificial layer 425 are removed from the device 400, exposing the capacitor dielectric layer 420 within the enlarged trenches 418 and exposing portions of the capacitor dielectric layer 420 that are located above the PMD 410, which was previously covered by the structured photoresist layer 424 and / or the sacrificial layer 425. In various examples, the structured photoresist layer 424 can be removed using one or more processes, and the sacrificial layer 425 can be removed using one or more other processes. In various examples, the structured photoresist layer 424 and the sacrificial layer 425 can be removed using the same one or more processes.In various examples, one or more processes may include plasma ashing, a chemical for wet photoresist removal, a piranha solution (H2SO4 and H2O2), other suitable processes, or combinations thereof.

[0076] At step 314 from Fig. 3. A conductive material layer is formed in the trench and the contact opening to create a capacitor plate in the trench and a contact in the contact opening. As shown in Fig. As shown in Figure 4E, a conductive material layer (e.g., layer(s) of an electrically conductive trench fill material and / or barrier layers) is formed over the capacitor dielectric layer 420 and in the widened trenches 418 and the contact openings 428. A planarization process (e.g., a CMP process) is then performed to remove excess portions of the conductive material layer to form the conductive plugs 421 and the contacts 430. As shown, after the planarization process of the conductive material layer, the one or more conductive plugs 421 are positioned in the widened trenches 418. The one or more conductive plugs 421 form the capacitor plate 422 after being electrically coupled together, as described below.

[0077] In some examples, such as in Fig. As shown in Figure 4E, the planarization process removes portions of the overhang of the conductive material layer (e.g., layer(s) of an electrically conductive trench fill material and / or barrier layers) and exposes portions of the capacitor dielectric layer 220 that are located above the upper surface of the PMD 210. In some other examples, such as in Fig. As shown in Figure 4F, the planarization process removes portions of the overhang of the conductive material layer (e.g., layer(s) of an electrically conductive trench filler and / or barrier layers) as well as portions of the capacitor dielectric layer 220 that are positioned above the PMD 210 to expose the PMD 210. Because in some examples the conductive plugs 421 and the contacts 430 are formed during the same process, these features may have the same material compositions. In various examples, the conductive plugs 421 and contacts 430 may contain similar materials to those previously described in Fig. 2K, Fig. 2L, Fig. 2S and Fig. 2T were described.

[0078] As a result of the formation of the capacitor plate 422, a trench capacitor 440 is formed in the device 400. In particular, the conductive plugs 421 and the substrate 402 function as the capacitor plates of the trench capacitor 440. In this respect, as previously discussed and similar to the substrate 202, the substrate 402, including epitaxially grown layers arranged on it, can have doped regions (or wells) formed therein, such that these doped regions of the substrate 402 form a first capacitor plate (e.g., lower capacitor plate) of the trench capacitor 440. Furthermore, in some examples, the capacitor plate 422 forms a second plate (e.g., an upper capacitor plate) of the trench capacitor 440. As shown, the trench capacitor 440 also includes the capacitor dielectric layer 420, which is located between the substrate 202 (e.g., the first capacitor plate) and the capacitor plate 422 (e.g.,the second capacitor plate) is positioned, thus isolating the two layers from each other.

[0079] Furthermore, the device includes 400 parts 406' of the silicide blocking layer 406, which are adjacent to the capacitor dielectric layer 420. This increases the distance between the silicide layer 404 and the conductive plug 421, partly due to the parts 406' of the silicide blocking layer 406. That is, these parts 406' of the silicide blocking layer 406 increase the distance (e.g., dielectric buffer) between the silicide layer 404 and the conductive plug 421. In some examples, the remaining parts 406' of the silicide blocking layer 406 prevent the silicide layer 404 from being exposed during trench etching processes, which can reduce cross-contamination of the silicide materials from the silicide layer 404 into the substrate 402 (e.g., incorporation of silicide materials into trench walls). In various examples, reducing cross-contamination improves the quality of the silicon trench capacitor (e.g.,higher breakdown voltage, less current leakage loss, etc.).

[0080] In step 316, a metal layer is formed over the PMD to connect the capacitor plate and the contact. As shown in Fig. 4G and Fig. Figure 4H illustrates the device 400, including the trench capacitor 440 and a FET 450. The trench capacitor 440 is formed by steps 302-316 of the process 300 as part of a BEOL process, as described previously. The FET 450 is formed during an FEOL process prior to step 302 of the process 300, as described previously. The FET 450 incorporates features similar to those previously described with reference to the FET 250 and may not be described again here. The FET 450, for example, includes a doped trough 452, a first source / drain region 454, a second source / drain region 456, a gate stack 458, a first source / drain contact 460, a second source / drain contact 462, a gate contact 464, and an isolation feature 466. In various examples, the isolation feature 466 can include a shallow trench isolation (STI) structure and a deep trench isolation structure.The insulation feature 466 electrically isolates the trench capacitor 440 from the FET 450.

[0081] As in Fig. As shown in Figure 4G and in various examples, a structured metal layer 432 is formed over the capacitor dielectric layer 420, which is arranged over the PMD 410. In particular, it follows Fig. 4G from the process of the device 400 Fig. 4E, wherein the capacitor dielectric layer 420 is arranged above the PMD 410, such that the structured metal layer 432 is formed on the capacitor dielectric layer 420. Therefore, the capacitor dielectric layer 420 is positioned between the structured metal layer 432 and the upper surface of the PMD 410.

[0082] As shown, the structured metal layer 432 is formed over the trench capacitor 440, so that the structured metal layer 432 physically contacts the capacitor dielectric layer 420, the conductive plugs 421, and the contacts 430. The conductive plugs 421, which are connected in parallel by the structured metal layer 432, act as the capacitor plate 422. The structured metal layer 432 is further formed over the FET 450, so that the structured metal layer 432 physically contacts the capacitor dielectric layer 420, the first source / drain contact 460, the second source / drain contact 462, and the gate contact 464. In various examples, one or more parts of the structured metal layer 432 can contact both the trench capacitor 440 and the FET 450.As shown, the structured metal layer 432 includes respective metal conductors 433a-e which are connected to the first source / drain contact 460, the gate contact 464, the second source / drain contact 462, the contacts 430 and the conductive plugs 421 of the trench capacitor 240.

[0083] In contrast to trench capacitors formed during FEOL process steps, the formation of trench capacitor 440 during BEOL processes advantageously allows the first metal layer (e.g., M1 layer) of the BEOL metallization process to be directly connected to the conductive plugs 421 of the trench capacitor 440. This means that the BEOL process formation of trench capacitor 440 allows the top plate (e.g., capacitor plate 422) of the trench capacitor to be directly connected to the first metal layer (e.g., M1 layer) without the use of conductive vias and / or additional contacts.As a result, the capacitor density can be increased because there are no contact placement alignment tolerance problems that are normally associated with aligning the trench capacitor formed during FEOL process steps with conductive vias and / or contacts formed during a BEOL process to connect to the trench capacitor.

[0084] In other examples, such as in Fig. As shown in 4H, the process for device 400 can alternatively be carried out by Fig. 4F to Fig. 4H passes over the device 400 during the formation of the structured metal layer 432. The device 400 in Fig. 4H is the device 400 in Fig. 4G similar, except with regard to the capacitor dielectric layer 420. In contrast to Fig. 4G the capacitor dielectric layer 420 was during the process disclosed by method 300 (see Fig. 4F), for which in Fig. The device 400 shown in Figure 4H is removed from the upper surface of the PMD 410. Therefore, the structured metal layer 432 is formed over the PMD 410, the capacitor plate 422, and the various contact features (e.g., the first source / drain contact 460, the second source / drain contact 462, the gate contact 464, and the contacts 430). In particular, in some examples, the structured metal layer 432 of the device 400 is formed directly on the respective upper surfaces of the PMD 410, the capacitor plate 422, the capacitor dielectric layer 420 lining the capacitor plate, and the various contact features (e.g., the first source / drain contact 460, the second source / drain contact 462, the gate contact 464, and the contacts 430).Therefore, in some examples, the structured metal layer 432 is formed over the trench capacitor 440 and physically contacts the PMD 410, the capacitor dielectric layer 420, the capacitor plate 422, and the contacts 430. Furthermore, in some examples, the structured metal layer 432 is also formed over the FET 450 and physically contacts the PMD 410, the first source / drain contact 460, the second source / drain contact 462, and the gate contact 464. In various examples, one or more parts of the structured metal layer 432 can contact both the trench capacitor 440 and the FET 450.

[0085] Accordingly, the steps of procedure 300, as previously referred to, represent Fig. Sections 4A-4H describe steps for forming a trench capacitor during BEOL (Build-Only Oriented Orientation). This means that trench capacitors are formed after the formation of other components, such as transistors, resistors, inductors, and other capacitors, after the formation of a PMD (Process-Mechanical Device) over the device, and before the formation of the metal connections between the various components. Trench capacitors formed using the steps of Procedure 300 exhibit improved high-voltage breakdown for the capacitor density. There is also a reduced risk of defect formation in the trench capacitor because it is formed during the lower temperatures used in BEOL processing compared to the higher temperatures used during FEOL (Fail-Only Oriented Orientation) processing steps. Other advantages include the ability to connect the top plate of the trench capacitor directly to metal leads (e.g., wires, cables, etc.).Metal layer 1), without using vias and / or additional contacts. This means that the disclosed process forms the first metal layer (e.g., M1 layer) of the BEOL metallization process directly on the capacitor plate (e.g., the top plate). This contrasts with trench capacitors formed during FEOL processing steps, where the first metal layer (e.g., M1 layer) of the BEOL metallization process is not formed directly on the capacitor plate (e.g., the top plate), but instead on intermediate conductive vias that are first formed on the capacitor plate. Because of this, the capacitor density can be increased, as there are no placement-orientation tolerance issues associated with a conductive via (e.g., contact). Furthermore, forming the top plate of the trench capacitor from a metal (e.g., tungsten) reduces the series resistance of the trench capacitor compared to a polysilicon core.The metal material for the capacitor plate (e.g., top plate) can be used due to the lower processing temperature of the BEOL processes.

[0086] Now, with reference to Fig. Figure 5 illustrates a device 500 according to various examples in the present disclosure. The device 500 can be formed using either method 100 or method 300. Similar to device 200 and device 400, device 500 includes a trench capacitor 540 and a bipolar transistor 550. In various examples, the trench capacitor 540 and the bipolar transistor 550 can be formed over a buried n-type layer 572, which is formed over a p-type substrate 574. In various examples, the p-type substrate 574 can include one or more semiconductor layers. In various examples, the p-type substrate 574 can be doped with one or more p-type dopants, such as boron. The buried n-type layer 572 is formed over the p-type substrate 574.In various examples, the buried n-type layer 572 can be doped with one or more n-type dopants, such as arsenic, phosphorus and antimony.

[0087] The device 500, and in particular the trench capacitor 540, further comprises similar layers to those of the previously described device 200 and device 400, including a substrate 502, a silicide layer 504, a silicide blocking layer 506, a dielectric lining 508, a PMD 510, a capacitor dielectric layer 520, a conductive plug 521, a capacitor plate 522, contacts 530, and a structured metal layer 532, the descriptions of which are not repeated below. The trench capacitor 540 further comprises a deep n-trough 536 formed in the substrate 502. The deep n-trough 536 forms a plate of the trench capacitor 540. In various examples, the deep n-trough 536 can be doped with one or more n-type dopants, such as arsenic, phosphorus, and antimony. In various examples, the deep n-trough 536 extends from the silicide layer 504 to the buried n-type layer 572.

[0088] The bipolar transistor 550 includes a base region 554, a collector region 556, an emitter region 558, a base contact 560, a collector contact 562, an emitter contact 564, shallow trench insulation structures 566, deep trench insulation structures 568 and a deep collector region 570.

[0089] Collector region 556 is formed above the buried n-type layer 572. In various examples, collector region 556 can be doped using one or more n-type dopants, such as arsenic, phosphorus, and antimony. In various examples, collector region 556 can have a higher dopant concentration than the buried n-type layer 572. In various examples, as in Fig. As shown in Figure 5, the bipolar transistor 550 can include the deep collector region 570, over which the silicide layer 504 is formed. In various examples, the collector region 570 extends from the silicide layer 504 to the buried n-type layer 572. In various examples, the deep collector region 570 can have a higher dopant concentration than the collector region 556. The base region 554 is formed over the collector region 556. The base region 554 can be doped with one or more p-type dopants, such as boron. The emitter region 558 is formed over the base region 554. The emitter region 558 can be doped with one or more n-type dopants. In various examples, the emitter region 558 can have a higher dopant concentration than the collector region 556.In various examples, the 550 bipolar transistor can alternatively incorporate a pnp transistor using a buried p-type layer. Other alternative bipolar transistor designs are possible and are within the scope of this disclosure.

[0090] The base contact 560, collector contact 562, and emitter contact 564 can be formed using similar processes to those used for the capacitor plate 522 and / or the contacts 530. For example, the base contact 560, collector contact 562, and / or emitter contact 564 can (i) incorporate one or more metal barrier and / or adhesion layers (e.g., Ti, Ta, TiN, TaN, or the like, or a combination thereof) conformally within the respective contact openings 228, and (ii) incorporate a filler metal (e.g., Al, Cu, W, or the like, or a combination thereof) over and / or on the metal barrier and / or adhesion layer(s). As shown, the structured metal layer 532 includes respective metal conductors 533a-h which are connected to the base contact 560, the collector contact 562, the emitter contact 564, the contacts 530 and the capacitor plate 522 of the trench capacitor 540.In particular, the metal leads 533d, 533 and 533h are connected to the contacts 530, and the metal leads 533e and 533g are connected to the conductive plugs 521 of the capacitor plate 522. As previously described, a first plate of the trench capacitor 540 (e.g., a lower plate) is formed by the deep n-trough 536, and a second plate of the trench capacitor 540 (e.g., an upper plate) is formed by the capacitor plate 522, including the conductive plugs 521.

[0091] Device 500 illustrates different structures that can be fabricated using method 100 and / or method 300. For example, device 500 includes the bipolar transistor 550, in contrast to the FET 450 of device 400 or the FET 250 of device 200. However, the trench capacitor 540 can be formed using similar processes to trench capacitors 240 and / or 440 during a BEOL process. Furthermore, trench capacitor 540 includes an additional contact 530 located between the conductive plugs 521 of the capacitor plate 522. This additional contact feature between parts of a capacitor plate (e.g., conductive plugs 521), as shown in Fig.Figure 5 shows that the structure can be formed in all of the examples disclosed herein (e.g., devices 200, 200', and / or 400). This illustrates the variations of structures that are possible using the methods described herein. The methods described herein are modular and capable of being added to the BEOL processing of many semiconductor devices with little or no change to the layout of the various components of the semiconductor devices.

[0092] Accordingly, the procedures described here provide steps for forming devices, including a trench capacitor, that are formed during BEOL processing. That is, after forming other components, such as transistors, resistors, inductors, and other capacitors, after forming a PMD over the device, and before forming the metal connections between the various components. Forming trench capacitors during BEOL processing, as described here, improves capacitor density within the semiconductor devices for a given breakdown requirement. In particular, the metal leads (e.g., Metal Layer 1) are formed directly on the top plate of the trench capacitor. This eliminates the limitations and alignment tolerance problems associated with vias used to connect components to the metal leads.Furthermore, there is a reduced risk of defect formation in the trench capacitor due to the lower temperatures used in BEOL processing.

[0093] Finally, it is understood that any of the concepts described above may be used alone or in combination with any or all of the other concepts described above. Although various examples have been disclosed and described, it is understood, recognized, and / or intended that certain modifications would fall within the scope of protection of this disclosure. Accordingly, the description is not intended to be exhaustive or to limit the principles described or illustrated herein to any precise form. Many modifications and variations are possible in light of the above teachings. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] US 10,903,306

[0012] US 11,195,958 [0012, 0032]

Claims

[1] Method for forming an integrated circuit comprising the following: Forming an electronic device over a substrate, wherein the substrate includes a semiconductor material; Forming a pre-metal dielectric layer over the electronic device; Forming a trench through the pre-metal dielectric layer and into the substrate; Forming a capacitor dielectric layer over the pre-metal dielectric layer and within the trench; and Forming a conductive material layer over the capacitor dielectric layer and within the trench, wherein the conductive material layer forms a first plate of a trench capacitor and the semiconductor material of the substrate forms a second plate of the trench capacitor. [2] The method of claim 1, further comprising: Formation of a silicide layer over the substrate; After the formation of the conductive material layer, a contact opening is formed through the pre-metal dielectric layer, exposing part of the silicide layer; and Formation of a contact feature within the contact opening above the silicide layer. [3] Method according to claim 2, wherein forming the contact opening through the pre-metal dielectric layer to expose part of the silicide layer further includes forming the contact opening through the capacitor dielectric layer, such that part of the capacitor dielectric layer is removed during the formation of the contact opening. [4] The method of claim 1, further comprising: Formation of a silicide layer over the substrate; and After forming the trench through the pre-metal dielectric layer and into the substrate, a contact opening is formed through the pre-metal dielectric layer, exposing the silicide layer, and the formation of the conductive material layer further includes the formation of the conductive material layer in the contact opening above the silicide layer. [5] The method of claim 1, further comprising: Forming a metal conduit directly on the conductive material layer located within the trench. [6] The method of claim 1, further comprising: Forming a silicide blocking layer over the substrate, wherein forming the trench through the pre-metal dielectric layer and into the substrate involves forming the trench through the silicide blocking layer, and wherein the capacitor dielectric layer adjoins the silicide blocking layer after the capacitor dielectric layer has been formed above the pre-metal dielectric layer and within the trench. [7] The method of claim 1, further comprising: Formation of a silicide layer over the substrate, and wherein the capacitor dielectric layer borders the silicide layer after the capacitor dielectric layer has been formed above the pre-metal dielectric layer and within the trench. [8] Method according to claim 1, wherein the conductive material layer comprises a tungsten material. [9] Procedure comprising the following: Formation of a silicide layer over a substrate; Formation of a pre-metal dielectric layer over the silicide layer; Forming a trench through the pre-metal dielectric layer and into the substrate; Forming a capacitor dielectric layer over the pre-metal dielectric layer and within the trench; and Forming a conductive material layer over the capacitor dielectric layer and within the trench, wherein part of the conductive material layer extends through the pre-metal dielectric layer and into the substrate after the conductive material layer has been formed over the capacitor dielectric layer and within the trench, and wherein the conductive material layer forms a first plate of a trench capacitor and the substrate forms a second plate of the trench capacitor. [10] The method of claim 9, further comprising: Forming a metal conduit directly on the conductive material layer located within the trench. [11] The method of claim 10, further comprising: Planarizing, prior to forming the metal conductor, the capacitor dielectric layer, and the conductive material layer, to expose an upper surface of the pre-metal dielectric layer, and where forming the metal conduction directly on the conductive material layer located within the trench involves forming the metal conduction directly on the exposed upper surface of the pre-metal dielectric layer. [12] The method of claim 9, further comprising: Forming a contact opening through the pre-metal dielectric layer, which exposes part of the silicide layer; and Formation of a contact feature in the contact opening above the silicide layer. [13] The method of claim 9, further comprising: Forming a contact opening through the pre-metal dielectric layer to a part of the silide layer, the formation of the conductive material layer further includes the formation of the conductive material layer in the contact opening above the part of the silicide layer. [14] The method of claim 13, further comprising: Forming, prior to the formation of the contact opening, a sacrificial layer in the trench; and Remove the sacrificial layer from the trench before the formation of the conductive material layer. [15] Method according to claim 14, wherein the sacrificial layer includes an anti-reflective coating layer. [16] Device comprising the following: a pre-metal dielectric layer arranged over a substrate, wherein the substrate comprises a semiconductor material; a trench capacitor that includes the following: a capacitor dielectric layer extending into several trenches formed through the pre-metal dielectric layer and into the substrate; and a conductive material extending into the multiple trenches; and a metal layer placed directly on top of the conductive material. [17] Device according to claim 16, wherein the capacitor dielectric layer is arranged above the substrate between the metal layer and an upper surface of the pre-metal dielectric layer. [18] Device according to claim 16, wherein the metal layer directly contacts an upper surface of the pre-metal dielectric layer. [19] Device according to claim 16, further comprising: a silicide layer arranged above the substrate; and a contact feature extending to the silicide layer, wherein the contact feature and the conductive material of the trench capacitor extend to substantially the same height above an upper surface of the substrate. [20] Device according to claim 16, further comprising: a silicide layer arranged above the substrate; and a silicide blocking layer arranged above the substrate adjacent to the silicide layer, and wherein the capacitor dielectric layer extends through and borders the silicide blocking layer.

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