Semiconductor element, method for its manufacture, semiconductor substrate and crystal layer structure

Abstract

Semiconductor element (10, 20, 30) comprising: a base substrate (11, 21, 31) comprising a Ga2O3-based crystal having a thickness of not less than 0.05 µm and not more than 50 µm; an epitaxial layer (12, 22, 32) comprising a Ga2O3-based crystal formed on the substrate (11, 21, 31), and a support substrate (17, 37, 52) formed from a material with higher thermal conductivity than the Ga2O3-based crystal and attached to a lower surface of the base substrate (11, 21, 31), and / or a support substrate (15, 51) formed from a material with higher thermal conductivity than the Ga2O3-based crystal and attached to an upper surface of the epitaxial layer (12, 22, 32).

Description

[Technical field]

[0001] The invention relates to a semiconductor element, a method for manufacturing the semiconductor element, a semiconductor substrate and a crystal layer structure. [State of the art]

[0002] A Schottky diode based on Ga2O3, which has an n + -Semiconductor layer containing a high concentration of an n-doping agent, and an n - A semiconductor layer formed on top of this, containing a relatively low concentration of an n-type dopant, is known as a conventional semiconductor device (see, e.g., JP 2013-102081A). Both the n + -semiconductor layer as well as the n - -The semiconductor layer is formed from a semiconductor based on Ga2O3.

[0003] In this Schottky diode, the n +-Semiconductor layer in ohmic contact with an electrode connected to it and the n - -Semiconductor layer in Schottky contact with another electrode connected to it.

[0004] EP 2 765 610 A1 describes a semiconductor device based on β-Ga2O3, comprising an n-type β-Ga2O3 substrate and a β-Ga2O3 single-crystal layer epitaxially grown on it. The focus here is on achieving high crystal quality through homoepitaxy.

[0005] HIGASHIWAKI, M. [et al.]: Development of gallium oxide power devices. In: Phys. Status Solidi A, Vol. 211, 2013, pp. 21–26, provides an overview of Ga2O3 power devices such as MESFETs and Schottky barrier diodes on native substrates. The publication explicitly discusses the material properties of β-Ga2O3 and points out that the thermal conductivity of β-Ga2O3 is significantly lower than that of other semiconductors, which represents a weakness for power applications.

[0006] EP 2 754 736 A1 discloses a crystal layer structure in which a β-Ga2O3-based substrate with a specific plane orientation is used (rotated by 50° to 90° with respect to the (100) plane) to increase the growth rate of the epitaxial layer.

[0007] DE 11 2004 002 033 T5 describes a method for producing a compound semiconductor substrate, in particular for GaAs or InP. In this process, a functional layer is created on a growth substrate, a temporary support substrate is applied, the growth substrate is removed, and finally a thermally conductive substrate (such as diamond or SiC) is permanently bonded before the temporary support is removed. This method aims to improve the heat dissipation of conventional compound semiconductors.

[0008] US 2015 / 0279927 A1 discloses a crystalline multilayer structure with a corundum-structured crystalline oxide thin film (e.g., α-Ga₂O₃) on a base substrate such as sapphire. It teaches that a film thickness of 1 µm or more is advantageous to avoid an increase in electrical resistance during annealing. [Summary of the invention][Technical problem]

[0009] In publication JP 2013 - 102 081 A, a substrate based on β-Ga2O3 is described as the n + A semiconductor layer is used, and the substrate thickness based on Ga2O3 is as large as 600 µm. Since the thermal conductivity of Ga2O3 is lower than that of commonly known semiconductor materials such as Si or GaAs, Ga2O3-based elements containing a Ga2O3 substrate generate more heat for a given amount of electric current than elements of the same thickness containing a Si substrate.

[0010] For this reason, in the Schottky diode disclosed in publication JP 2013 - 102 081 A, it is difficult to dissipate heat generated during operation via the side of the n + -semiconductor layer, so that its heat dissipation property becomes poor. Furthermore, it is difficult to improve the heat dissipation property by reducing the thickness of the n +-to improve the semiconductor layer, as this can cause a significant reduction in the dielectric strength property.

[0011] Therefore, it is an object of the invention to provide a semiconductor element based on Ga2O3, which has the property of excellent heat dissipation and the property of excellent dielectric strength, as well as a method for manufacturing the semiconductor element and a semiconductor substrate and a crystal layer structure that are available for manufacturing the semiconductor element. [Solution to the problem]

[0012] The invention is defined in the independent claims. The dependent claims define embodiments of the invention. [Advantageous effects of the invention]

[0013] In accordance with the invention, a semiconductor element based on Ga2O3, which has the property of excellent heat dissipation and the property of excellent dielectric strength, as well as a method for manufacturing the semiconductor element and a semiconductor substrate and a crystal layer structure available for manufacturing the semiconductor element, can be created. [Brief description of the drawings] Fig. Figure 1 is a vertical cross-sectional view showing a Schottky diode in a first embodiment. Fig. Figure 2A is a vertical cross-sectional view showing an exemplary process of manufacturing the Schottky diode in the first embodiment. Fig. Figure 2B is a vertical cross-sectional view showing the exemplary process of manufacturing the Schottky diode in the first embodiment. Fig. Figure 2C is a vertical cross-sectional view showing the exemplary process of manufacturing the Schottky diode in the first embodiment. Fig. 2D is a vertical cross-sectional view showing the exemplary process of manufacturing the Schottky diode in the first embodiment. Fig. Figure 3A is a vertical cross-sectional view showing the exemplary process of manufacturing the Schottky diode in the first embodiment. Fig. Figure 3B is a vertical cross-sectional view showing the exemplary process of manufacturing the Schottky diode in the first embodiment. Fig. Figure 4A is a vertical cross-sectional view showing an exemplary process of manufacturing the Schottky diode in the first embodiment. Fig. Figure 4B is a vertical cross-sectional view showing the exemplary process of manufacturing the Schottky diode in the first embodiment. Fig. Figure 4C is a vertical cross-sectional view showing the exemplary process of manufacturing the Schottky diode in the first embodiment. Fig. Figure 5A is a vertical cross-sectional view showing an exemplary process of manufacturing the Schottky diode in the first embodiment. Fig. Figure 5B is a vertical cross-sectional view showing the exemplary process of manufacturing the Schottky diode in the first embodiment. Fig. Figure 5C is a vertical cross-sectional view showing the exemplary process of manufacturing the Schottky diode in the first embodiment. Fig. 5D is a vertical cross-sectional view showing the exemplary process of manufacturing the Schottky diode in the first embodiment. Fig. Figure 5E is a vertical cross-sectional view showing the exemplary process of manufacturing the Schottky diode in the first embodiment. Fig. Figure 6A is a vertical cross-sectional view showing an exemplary process of manufacturing the Schottky diode in the first embodiment. Fig. Figure 6B is a vertical cross-sectional view showing the exemplary process of manufacturing the Schottky diode in the first embodiment. Fig. Figure 6C is a vertical cross-sectional view showing the exemplary process of manufacturing the Schottky diode in the first embodiment. Fig. Figure 7 is a vertical cross-sectional view showing a vertical transistor in a second embodiment. Fig. Figure 8A is a vertical cross-sectional view showing an exemplary process of manufacturing the vertical transistor in the second embodiment. Fig. Figure 8B is a vertical cross-sectional view showing the exemplary process of manufacturing the vertical transistor in the second embodiment. Fig. Figure 8C is a vertical cross-sectional view showing the exemplary process of manufacturing the vertical transistor in the second embodiment. Fig. Figure 8D is a vertical cross-sectional view showing the exemplary process of manufacturing the vertical transistor in the second embodiment. Fig. Figure 9A is a vertical cross-sectional view showing the exemplary process of manufacturing the vertical transistor in the second embodiment. Fig. Figure 9B is a vertical cross-sectional view showing the exemplary process of manufacturing the vertical transistor in the second embodiment. Fig. Figure 9C is a vertical cross-sectional view showing the exemplary process of manufacturing the vertical transistor in the second embodiment. Fig. Figure 10A is a vertical cross-sectional view showing an exemplary process of manufacturing the vertical transistor in the second embodiment. Fig. Figure 10B is a vertical cross-sectional view showing the exemplary process of manufacturing the vertical transistor in the second embodiment. Fig. Figure 10C is a vertical cross-sectional view showing the exemplary process of manufacturing the vertical transistor in the second embodiment. Fig. Figure 11A is a vertical cross-sectional view showing an exemplary process of manufacturing the vertical transistor in the second embodiment. Fig. Figure 11B is a vertical cross-sectional view showing the exemplary process of manufacturing the vertical transistor in the second embodiment. Fig. Figure 11C is a vertical cross-sectional view showing the exemplary process of manufacturing the vertical transistor in the second embodiment. Fig. Figure 11D is a vertical cross-sectional view showing the exemplary process of manufacturing the vertical transistor in the second embodiment. Fig. Figure 12 is a vertical cross-sectional view showing the exemplary process of manufacturing the vertical transistor in the second embodiment. Fig. Figure 13A is a vertical cross-sectional view showing an exemplary process of manufacturing the vertical transistor in the second embodiment. Fig. Figure 13B is a vertical cross-sectional view showing the exemplary process of manufacturing the vertical transistor in the second embodiment. Fig. Figure 13C is a vertical cross-sectional view showing the exemplary process of manufacturing the vertical transistor in the second embodiment. Fig. Figure 14 is a vertical cross-sectional view showing a lateral transistor in a third embodiment. Fig. Figure 15A is a vertical cross-sectional view showing an exemplary process of manufacturing the lateral transistor in the third embodiment. Fig. Figure 15B is a vertical cross-sectional view showing the exemplary process of manufacturing the lateral transistor in the third embodiment. Fig. Figure 15C is a vertical cross-sectional view showing the exemplary process of manufacturing the lateral transistor in the third embodiment. Fig. Figure 15D is a vertical cross-sectional view showing the exemplary process of manufacturing the lateral transistor in the third embodiment. Fig. Figure 15E is a vertical cross-sectional view showing the exemplary process of manufacturing the lateral transistor in the third embodiment. Fig. Figure 16A is a vertical cross-sectional view showing an exemplary process of manufacturing the lateral transistor in the third embodiment. Fig. Figure 16B is a vertical cross-sectional view showing the exemplary process of manufacturing the lateral transistor in the third embodiment. Fig. Figure 16C is a vertical cross-sectional view showing the exemplary process of manufacturing the lateral transistor in the third embodiment. Fig. Figure 17A is a vertical cross-sectional view showing an exemplary process of manufacturing the lateral transistor in the third embodiment. Fig. Figure 17B is a vertical cross-sectional view showing the exemplary process of manufacturing the lateral transistor in the third embodiment. Fig. Figure 17C is a vertical cross-sectional view showing the exemplary process of manufacturing the lateral transistor in the third embodiment. Fig. Figure 17D is a vertical cross-sectional view showing the exemplary process of manufacturing the lateral transistor in the third embodiment. Fig. Figure 17E is a vertical cross-sectional view showing the exemplary process of manufacturing the lateral transistor in the third embodiment. Fig. Figure 18A is a vertical cross-sectional view showing an exemplary process of manufacturing the lateral transistor in the third embodiment. Fig. Figure 18B is a vertical cross-sectional view showing the exemplary process of manufacturing the lateral transistor in the third embodiment. Fig. Figure 18C is a vertical cross-sectional view showing the exemplary process of manufacturing the lateral transistor in the third embodiment. Fig. Figure 19A is a vertical cross-sectional view showing an exemplary process of manufacturing the lateral transistor in the third embodiment. Fig. Figure 19B is a vertical cross-sectional view showing the exemplary process of manufacturing the lateral transistor in the third embodiment. Fig. Figure 19C is a vertical cross-sectional view showing the exemplary process of manufacturing the lateral transistor in the third embodiment. Fig. Figure 19D is a vertical cross-sectional view showing the exemplary process of manufacturing the lateral transistor in the third embodiment. Fig. Figure 20A is a vertical cross-sectional view showing an exemplary process of manufacturing the lateral transistor in the third embodiment. Fig. Figure 20B is a vertical cross-sectional view showing the exemplary process of manufacturing the lateral transistor in the third embodiment. Fig. Figure 21 is a vertical cross-sectional view showing a Schottky diode in a fourth embodiment. Fig. Figure 22A is a vertical cross-sectional view showing an exemplary process of manufacturing the Schottky diode in the fourth embodiment. Fig. Figure 22B is a vertical cross-sectional view showing the exemplary process of manufacturing the Schottky diode in the fourth embodiment. Fig. Figure 22C is a vertical cross-sectional view showing the exemplary process of manufacturing the Schottky diode in the fourth embodiment. Fig. Figure 22D is a vertical cross-sectional view showing the exemplary process of manufacturing the Schottky diode in the fourth embodiment. Fig. Figure 22E is a vertical cross-sectional view showing the exemplary process of manufacturing the Schottky diode in the fourth embodiment. Fig. Figure 23A is a vertical cross-sectional view showing the exemplary process of manufacturing the Schottky diode in the fourth embodiment. Fig. Figure 23B is a vertical cross-sectional view showing the exemplary process of manufacturing the Schottky diode in the fourth embodiment. Fig. Figure 23C is a vertical cross-sectional view showing the exemplary process of manufacturing the Schottky diode in the fourth embodiment. Fig. Figure 23D is a vertical cross-sectional view showing the exemplary process of manufacturing the Schottky diode in the fourth embodiment. Fig. 24A is a vertical cross-sectional view showing the Schottky diode with support substrates attached on both sides. Fig. 24B is a vertical cross-sectional view showing the vertical transistor with support substrates attached on both sides. Fig. 24C is a vertical cross-sectional view showing the lateral transistor with support substrates attached on both sides. Fig. Figure 25 is a vertical cross-sectional view showing a Schottky diode in a sixth embodiment. Fig. Figure 26A is a vertical cross-sectional view showing an exemplary process of manufacturing the Schottky diode in the sixth embodiment. Fig. Figure 26B is a vertical cross-sectional view showing the exemplary process of manufacturing the Schottky diode in the sixth embodiment. Fig. Figure 26C is a vertical cross-sectional view showing the exemplary process of manufacturing the Schottky diode in the sixth embodiment. Fig. Figure 26D is a vertical cross-sectional view showing the exemplary process of manufacturing the Schottky diode in the sixth embodiment. Fig. Figure 26E is a vertical cross-sectional view showing the exemplary process of manufacturing the Schottky diode in the sixth embodiment. Fig. Figure 27 is a vertical cross-sectional view showing a vertical transistor in a seventh embodiment. Fig. Figure 28A is a vertical cross-sectional view showing an exemplary process of manufacturing the vertical transistor in the seventh embodiment. Fig. Figure 28B is a vertical cross-sectional view showing the exemplary process of manufacturing the vertical transistor in the seventh embodiment. Fig. Figure 28C is a vertical cross-sectional view showing the exemplary process of manufacturing the vertical transistor in the seventh embodiment. Fig. Figure 28D is a vertical cross-sectional view showing the exemplary process of manufacturing the vertical transistor in the seventh embodiment. Fig. Figure 29 is a vertical cross-sectional view showing the exemplary process of manufacturing the vertical transistor in the seventh embodiment. Fig. Figure 30 is a vertical cross-sectional view showing a vertical transistor in an eighth embodiment. Fig. Figure 31 is a vertical cross-sectional view showing a Schottky diode in a ninth embodiment. Fig. Figure 32A is a vertical cross-sectional view showing an exemplary process of manufacturing the Schottky diode in the ninth embodiment. Fig. Figure 32B is a vertical cross-sectional view showing the exemplary process of manufacturing the Schottky diode in the ninth embodiment. Fig. Figure 32C is a vertical cross-sectional view showing the exemplary process of manufacturing the Schottky diode in the ninth embodiment. Fig. Figure 32D is a vertical cross-sectional view showing the exemplary process of manufacturing the Schottky diode in the ninth embodiment. Fig. Figure 32E is a vertical cross-sectional view showing the exemplary process of manufacturing the Schottky diode in the ninth embodiment. Fig. Figure 33 is a vertical cross-sectional view showing a vertical transistor in a tenth embodiment. Fig. Figure 34A is a vertical cross-sectional view showing an exemplary process of manufacturing the vertical transistor in the tenth embodiment. Fig. Figure 34B is a vertical cross-sectional view showing the exemplary process of manufacturing the vertical transistor in the tenth embodiment. Fig. Figure 34C is a vertical cross-sectional view showing the exemplary process of manufacturing the vertical transistor in the tenth embodiment. Fig. Figure 34D is a vertical cross-sectional view showing the exemplary process of manufacturing the vertical transistor in the tenth embodiment. Fig. Figure 35A is a vertical cross-sectional view showing the exemplary process of manufacturing the vertical transistor in the tenth embodiment. Fig. Figure 35B is a vertical cross-sectional view showing the exemplary process of manufacturing the vertical transistor in the tenth embodiment. Fig. Figure 35C is a vertical cross-sectional view showing the exemplary process of manufacturing the vertical transistor in the tenth embodiment. Fig. Figure 35D is a vertical cross-sectional view showing the exemplary process of manufacturing the vertical transistor in the tenth embodiment. [Description of embodiments][First embodiment]

[0014] The first embodiment is a vertical semiconductor element implemented as a Schottky diode. (Structure of the semiconductor element)

[0015] Fig. Figure 1 is a vertical cross-sectional view showing a Schottky diode 10 in the first embodiment. The Schottky diode 10 is provided with a substrate 11, an epitaxial layer 12 formed by epitaxial growth on the substrate 11, a cathode electrode 13 formed on a lower surface of the substrate 11 (a surface opposite the surface in contact with the epitaxial layer 12) and in ohmic contact with the substrate 11, and an anode electrode 14 formed on an upper surface of the epitaxial layer 12 (a surface opposite the surface in contact with the substrate 11) and in Schottky contact with the epitaxial layer 12.

[0016] In the Schottky diode 10, the height of the Schottky barrier at the interface between the anode electrode 14 and the epitaxial layer 12 is lowered by applying a forward bias between the anode electrode 14 and the cathode electrode 13, whereby a current flows from the anode electrode 14 to the cathode electrode 13. Conversely, the height of the Schottky barrier at the interface between the anode electrode 14 and the epitaxial layer 12 is raised, and no current flows, when a reverse bias is applied between the anode electrode 14 and the cathode electrode 13.

[0017] The base substrate 11 and the epitaxial layer 12 are formed from a Ga₂O₃ crystal and contain an n-type dopant. Preferably, the n-type dopant is a group IV element such as Si or Sn. The concentration of the n-type dopant in the base substrate 11 is higher than the concentration of the n-type dopant in the epitaxial layer 12.

[0018] The Ga₂O₃-based crystal is either a Ga₂O₃ crystal or a Ga₂O₃ crystal containing substitution defects such as Al or In. Preferably, the Ga₂O₃-based crystal is a single crystal. Furthermore, the Ga₂O₃-based crystal is preferably in the β-form.

[0019] The thickness of the base substrate 11 is reduced during the manufacturing process of the Schottky diode 10 and is therefore smaller than that of conventional base substrates used to form semiconductor substrates. Because the base substrate 11 is thin, heat generated in the Schottky diode 10 can be effectively dissipated through it. Thus, the Schottky diode 10 exhibits excellent heat dissipation. Preferably, the thickness of the base substrate 11 is no more than 50 µm, further improving the heat dissipation. The thinner the base substrate 11, the better the heat dissipation properties of the Schottky diode 10.

[0020] If the thickness of the base substrate 11 is reduced by polishing, the base substrate 11 is preferably processed to a thickness of not less than 10 µm, so that the thickness change on a substrate surface is suppressed.

[0021] If etching is performed after polishing to further reduce the thickness of the base substrate 11, the base substrate 11 can be processed to a thickness of less than 10 µm to further improve heat dissipation. However, the thickness of the base substrate 11 is preferably not less than 0.05 µm so that it has an ohmic contact with the cathode electrode 13.

[0022] The Ga2O3-based crystals exhibit a higher breakdown field strength than semiconductor materials commonly used to form conventional semiconductor substrates or layers, such as Si, SiC, or GaN. This allows the epitaxial layer 12 to have a reduced thickness, while preventing a reduction in the dielectric strength of the Schottky diode 10. Consequently, the overall thickness of the Schottky diode 10 can be reduced, and heat dissipation can be further improved. Thus, the Schottky diode 10 exhibits both high heat dissipation and high dielectric strength.

[0023] The main surface of the base substrate 11 is, for example, a surface rotated by not less than 50° and not more than 90° relative to the (100) plane of the single crystal based on β-Ga₂O₃. In other words, the angle θ (0 < θ ≤ 90°) formed between the main surface of the base substrate 11 and the (100) plane is not less than 50°. Examples of surfaces rotated by not less than 50° and not more than 90° relative to the (100) plane include a (010) plane, a (001) plane, a (-201) plane, a (101) plane, and a (310) plane.

[0024] If the main surface of the substrate 11 is rotated by no less than 50° and no more than 90° relative to the (100) plane, it is possible to effectively suppress the re-evaporation of the β-Ga₂O₃-based crystal starting materials from the substrate 11 during the epitaxial growth of the β-Ga₂O₃-based crystal on the substrate 11. Specifically, the percentage of re-evaporated starting material can be reduced to no more than 40% if the main surface of the substrate 11 is rotated by no more than 50° and no more than 90° relative to the (100) plane, where a percentage of re-evaporated starting material during the growth of the β-Ga₂O₃-based crystal at a growth temperature of 500°C is defined as 0%.Thus, it is possible to use no less than 60% of the supplied starting material to form the β-Ga2O3-based crystal, which is preferred from the point of view of the growth rate and the production cost of the β-Ga2O3-based crystal.

[0025] In the β-Ga2O3 crystal, the (100) plane coincides with the (310) plane when rotated by 52.5° about the c-axis, and coincides with the (010) plane when rotated by 90°. Meanwhile, the (100) plane coincides with the (101) plane when rotated by 53.8° about the b-axis, coincides with the (001) plane when rotated by 76.3°, and coincides with the (-201) plane when rotated by 53.8°.

[0026] Alternatively, the main surface of the base substrate 11 is the (010) plane or a surface rotated with respect to the (010) plane within an angular range of no more than 37.5°. In this case, it is possible to provide a steep interface between the base substrate 11 and the epitaxial layer 12, and it is also possible to control the thickness of the epitaxial layer 12 with high precision. Furthermore, it is possible to prevent uneven uptake of the element by the epitaxial layer 12 and thus obtain a homogeneous epitaxial layer 12. It is noted that this results in the (010) plane coinciding with the (310) plane when rotated by 37.5° about the c-axis.

[0027] Meanwhile, it is known that the β-Ga2O3-based crystal exhibits high thermal conductivity in the

[010] direction (the b-axis direction). For example, a β-Ga2O3 crystal has a thermal conductivity of 13.6 W / (mK) in the

[100] direction (the a-axis direction), but a thermal conductivity of 22.8 W / (mK) in the

[010] direction (the b-axis direction), which is almost twice the thermal conductivity in the

[100] direction.

[0028] Based on this, the thermal conductivity of the base substrate 11 in the thickness direction can be increased by using the base substrate 11 with a (010)-oriented main surface. Thus, the plane orientation of the main surface of the base substrate 11 is preferably (010).

[0029] The thickness of the epitaxial layer 12 is, for example, 0.4 to 30 µm.

[0030] The anode electrode 14 is made of a metal such as Pt or Ni. The anode electrode 14 can have a layered structure formed by layers of different metal films, such as Pt / Au or Pt / Al. Furthermore, the epitaxial layer 12 can have an electrode termination structure. The electrode termination structure can be, for example, a field plate structure configured such that insulating films are formed on the surface of the epitaxial layer 12 on both sides of the anode electrode 14, a protective ring structure formed by implanting acceptor ions into a surface of the epitaxial layer 12 on both sides of the anode electrode 14, a mesa structure configured such that sections of the epitaxial layer 12 on both sides of the anode electrode 14 are removed, or a combination thereof.

[0031] The cathode electrode 13 is made of a metal such as titanium. The cathode electrode 13 can have a layered structure formed by layers of different metal films such as titanium / Au or titanium / Al.

[0032] The following describes, along with specific examples, a method for fabricating the Schottky diode 10 in the first embodiment. However, the method for fabricating the Schottky diode 10 is not limited to the examples described below. (Semiconductor element manufacturing process 1)

[0033] The Fig. Figures 2A to 2D, 3A and 3B are vertical cross-sectional views showing an exemplary process for manufacturing the Schottky diode 10 in the first embodiment. In the Fig. In the example shown in 2A to 2D, 3A and 3B, the thickness of the base substrate 11 is reduced by polishing.

[0034] As in Fig. As shown in Figure 2A, the epitaxial layer 12 is first formed on the base substrate 11.

[0035] To obtain the base substrate 11, for example, a β-Ga₂O₃ single crystal grown using the EFG method and containing a high concentration of an n-type dopant is cut and polished to a desired thickness. The thickness of the base substrate 11 before polishing is, for example, 600 µm.

[0036] The epitaxial layer 12 is formed by epitaxial growth of a β-Ga2O3 single crystal on the substrate 11, e.g. using the HVPE process, the PLD process (pulsed laser deposition process), the CVD process (chemical vapor deposition process) or the molecular beam epitaxy process (MBE process).

[0037] The method for introducing an n-doping agent into the epitaxial layer 12 is, for example, the epitaxy of a Ga2O3 crystal film containing an n-doping agent, or ion implantation of an n-doping agent into a grown Ga2O3 crystal film.

[0038] As in Fig. As shown in Figure 2B, the epitaxial layer 12 is subsequently attached to a support substrate 15 via an adhesive layer 16 formed from resin, etc.

[0039] The material used here for the support substrate 15 is, for example, metal, resin or ceramic, etc., but is not limited to this.

[0040] As in Fig. As shown in Figure 2C, the thickness of the base substrate 11 supported by the support substrate 15 is subsequently reduced by polishing to not less than 10 µm and not more than 50 µm.

[0041] The polishing carried out on the base substrate 11 is, for example, CMP (chemical-mechanical polishing) using a silicon oxide colloid slurry.

[0042] After the thickness has been reduced, the base substrate 11 can be separated from the support substrate 15. In this case, a crystal layer structure is obtained, comprising the base substrate 11, which is formed from a Ga2O3-based crystal and has a thickness of not less than 10 µm and not more than 50 µm, and the epitaxial layer 12, which is formed from a Ga2O3-based crystal and has grown epitaxially on the base substrate 11.

[0043] As in Fig. As shown in 2D, the cathode electrode 13 is subsequently formed on the lower surface of the base substrate 11 (a surface opposite the surface in contact with the epitaxial layer 12).

[0044] To form the cathode electrode 13, a mask pattern is formed on the base substrate 11 by photolithography, a metal film made of Ti / Au etc. is then deposited on the entire surface of the base substrate 11, and the mask pattern and the metal film on it are then removed by lifting.

[0045] Since the base substrate 11 contains a high concentration of an n-doping agent, the base substrate 11 is in ohmic contact with the cathode electrode 13.

[0046] As in Fig. As shown in Figure 3A, a support substrate 17 is subsequently prepared, which has an electrode 18 on one side, and the base substrate 11 is attached to the support substrate 17 by bonding the cathode electrode 13 to the electrode 18.

[0047] The material of the support substrate 17 is not specifically limited. However, if the support substrate 17 is retained as a support substrate for the Schottky diode 10, as described later, it is preferably made of a material with a higher thermal conductivity than β-Ga₂O₃, e.g., a metal such as Al, a nitride such as AlN, SiN, or GaN, an oxide such as SiO₂ or Al₂O₃, or SiC, Si, GaAs, or diamond, etc. The electrode 18 is made, for example, of Au. The cathode electrode 13 is bonded to the electrode 18, for example, by applying pressure, heat, a combination of pressure and ultrasonic vibration, or pressure and a combination of pressure and ultrasonic vibration.

[0048] As in Fig. As shown in Figure 3B, the epitaxial layer 12 supported by the support substrate 17 is subsequently separated from the support substrate 15 and from the adhesive layer 16, and the anode electrode 14 is then formed on the upper surface of the epitaxial layer 12 (a surface opposite the surface in contact with the base substrate 11).

[0049] To form the anode electrode 14, a mask pattern is formed on the epitaxial layer 12 by photolithography, whereupon a metal film made of Pt / Au etc. is deposited on the entire surface of the epitaxial layer 12 and the mask pattern and the metal film on it are removed by lifting.

[0050] Since the epitaxial layer 12 contains a low concentration of the n-doping agent, the epitaxial layer 12 is in Schottky contact with the anode electrode 14.

[0051] Since the anode electrode 14 is formed after polishing the base substrate 11 in this manufacturing process, damage to the anode electrode 14 never occurs during the polishing of the base substrate 11, making it possible to improve the yield of the Schottky diode 10.

[0052] The support substrate 17 can be retained as a support substrate for the completed Schottky diode 10. In this case, external power can be supplied to the cathode electrode 13 via the electrode 18 of the support substrate 17. If the support substrate 17 is electrically conductive, the external power can be supplied to the cathode electrode 13 via the support substrate 17 and the electrode 18. Alternatively, the Schottky diode 10 can be separated from the support substrate 17 and then attached to a different support substrate. (Semiconductor element manufacturing process 2)

[0053] The Fig. Figures 4A to 4C are vertical cross-sectional views showing an exemplary process for the fabrication of the Schottky diode 10 in the first embodiment. In the Fig. In the example shown in 4A to 4C, the thickness of the base substrate 11 is reduced by polishing and subsequent etching.

[0054] As in Fig. As shown in 4A, the one in Fig. The process shown in 2A to 2C is carried out up to polishing to reduce the thickness of the base substrate 11.

[0055] As in Fig. As shown in Figure 4B, the thickness of the base substrate 11, supported by the support substrate 15, is subsequently further reduced by etching. The thickness of the base substrate 11 can be reduced to less than 10 µm by this etching.

[0056] The etching carried out on the base substrate 11 is, for example, dry etching such as RIE (reactive ion etching) or wet etching using H2SO4 or H3PO4 etc. as an etchant.

[0057] After reducing the thickness, the base substrate 11 can be separated from the support substrate 15. In this case, a crystal layer structure is obtained, comprising the base substrate 11, which is formed from a Ga2O3-based crystal and has a thickness of not less than 0.05 µm and not more than 50 µm, and the epitaxial layer 12, which is formed from a Ga2O3-based crystal and has grown epitaxially on the base substrate 11.

[0058] As in Fig. As shown in Figure 4C, the cathode electrode 13 is subsequently formed on the lower surface of the base substrate 11.

[0059] Then, in the same way as in the Fig. 3A and Fig. In the process shown in Figure 3B, the base substrate 11 is attached to the support substrate 17, the epitaxial layer 12 is separated from the support substrate 15 and from the adhesive layer 16, and the anode electrode 14 is then formed. (Semiconductor element manufacturing process 3)

[0060] The Fig. Figures 5A to 5E are vertical cross-sectional views showing an exemplary process for the fabrication of the Schottky diode 10 in the first embodiment. In the Fig. In the example shown in 5A to 5E, the thickness of the base substrate 11 is reduced by polishing.

[0061] As in Fig. As shown in Figure 5A, the epitaxial layer 12 is first formed on the base substrate 11.

[0062] As in Fig. As shown in Figure 5B, the anode electrode 14 is subsequently formed on the upper surface of the epitaxial layer 12 (a surface opposite the surface in contact with the base substrate 11).

[0063] As in Fig. As shown in Figure 5C, the support substrate 15, which has an electrode 19 on one side, is prepared, and the epitaxial layer 12 is attached to the support substrate 15 by bonding the anode electrode 14 to the electrode 19. The material of the support substrate 15 is not specifically limited. However, the support substrate 15 is preferably made of a material that has a higher thermal conductivity than β-Ga₂O₃, e.g., a metal such as Al, a nitride such as AlN, SiN, or GaN, an oxide such as SiO₂ or Al₂O₃, or SiC, Si, GaAs, or diamond, etc., if it is to be retained as a support substrate for the Schottky diode 10 as described later.

[0064] Electrode 19 is made of, for example, gold. The anode electrode 14 is bonded to electrode 19, for example, by applying pressure, heat, a combination of pressure and ultrasonic vibration, or pressure and a combination of pressure and ultrasonic vibration.

[0065] As in Fig. As shown in 5D, the thickness of the base substrate 11 supported by the support substrate 15 is subsequently reduced by polishing to not less than 10 µm and not more than 50 µm.

[0066] As in Fig. As shown in Figure 5E, the cathode electrode 13 is subsequently formed on the lower surface of the base substrate 11 (a surface opposite the surface in contact with the epitaxial layer 12).

[0067] The support substrate 15 can be retained as a support substrate for the completed Schottky diode 10. In this case, external power can be supplied to the anode electrode 14 via the electrode 19 of the support substrate 15. If the support substrate 15 is electrically conductive, external power can be supplied to the anode electrode 14 via the support substrate 15 and the electrode 19. Alternatively, the Schottky diode 10 can be separated from the support substrate 15 and then attached to a different support substrate. (Semiconductor element manufacturing process 4)

[0068] The Fig. Figures 6A to 6C are vertical cross-sectional views showing an exemplary process for the fabrication of the Schottky diode 10 in the first embodiment. In the Fig. In the example shown in 6A to 6C, the thickness of the base substrate 11 is reduced by polishing and subsequent etching.

[0069] As in Fig. As shown in 6A, the following is shown first: Fig. The process shown in 5A to 5D is carried out up to polishing to reduce the thickness of the base substrate 11.

[0070] As in Fig. As shown in Figure 6B, the thickness of the base substrate 11, supported by the support substrate 15, is subsequently further reduced by etching. The thickness of the base substrate 11 can be reduced to less than 10 µm by this etching.

[0071] As in Fig. As shown in Figure 6C, the cathode electrode 13 is subsequently formed on the lower surface of the base substrate 11.

[0072] After the base substrate 11 has been polished and etched, the anode electrode 14 can be formed. [Second embodiment]

[0073] The second embodiment is a vertical semiconductor element implemented as a vertical transistor having a MISFET (metal insulator semiconductor field-effect transistor) structure. (Structure of the semiconductor element)

[0074] Fig. Figure 7 is a vertical cross-sectional view showing a vertical transistor 20 in the second embodiment. The vertical transistor 20 has an epitaxial layer 22 formed on a substrate 21, a gate electrode 23 covered with a gate insulating film 24 and embedded in the epitaxial layer 22, and contact areas 25 formed in the epitaxial layer 22 such that they are located on both sides of the gate electrode 23. +-areas 28, which are formed on the respective sides of the contact areas 25, are provided with a source electrode 26, which is formed on the epitaxial layer 22 and is connected to the contact areas 25, and with a drain electrode 27, which is formed on a surface of the base substrate 21 on the side opposite the epitaxial layer 22.

[0075] The vertical transistor 20 is a vertical semiconductor device in which the source electrode 26 and the drain electrode 27 are arranged on top and below the device, respectively, thus allowing current to flow in a vertical direction. When a voltage not less than the threshold value is applied to the gate electrode 23, channels are formed in the epitaxial layer 22 in regions on both sides of the gate electrode 23, enabling current to flow from the source electrode 26 to the drain electrode 27.

[0076] The base substrate 21 is formed from a Ga₂O₃ crystal and contains an n-type dopant. Preferably, the n-type dopant is an element of group IV, such as Si or Sn. The concentration of the n-type dopant in the base substrate 21 is higher than the concentration of the n-type dopant in the epitaxial layer 22.

[0077] The thickness of the base substrate 21 is the same as the thickness of the base substrate 11 in the first embodiment. Since the base substrate 21 is thin, heat generated in the vertical transistor can be effectively dissipated through the base substrate 21. Thus, the vertical transistor 20 exhibits excellent heat dissipation.

[0078] The epitaxial layer 22 is formed from a Ga2O3-based crystal, which exhibits a high breakdown field strength. This allows for a smaller thickness than elements formed using other semiconductor materials, while simultaneously preventing a reduction in the voltage withstand capability of the vertical transistor 20. As a result, the overall thickness of the vertical transistor 20 can be reduced, and heat dissipation can be further improved. Thus, the vertical transistor 20 exhibits both high heat dissipation and high voltage withstand capability.

[0079] The plane orientation of the main surface of the base substrate 21 is also the same as that of the base substrate 11 in the first embodiment, wherein (010) is particularly preferred.

[0080] The epitaxial layer 22 is formed from a Ga₂O₃-based crystal and has a layered structure in which a layer 22b, which is undoped or contains a p-type dopant, is deposited on a layer 22a containing a low concentration of an n-type dopant. Preferably, the n-type dopant is an element of group IV such as Si or Sn. Preferably, the p-type dopant is Fe or an element of group II such as Be, Mg, or Zn. The gate electrode 23 is formed mainly in layer 22b.

[0081] The thickness of layer 22a, which contains a low concentration of the n-doping agent, is, for example, 0.4 to 40 µm, and the thickness of layer 22b, which is undoped or contains a p-doping agent, is, for example, 0.1 to 10 µm.

[0082] The gate electrode 23, the source electrode 26, and the drain electrode 27 are, for example, made of a metal such as Au, Al, Ti, Sn, Ge, In, Ni, Co, Pt, W, Mo, Cr, Cu, or Pb; of an alloy containing two or more such metals; of a conductive compound such as ITO; or of a conductive polymer. The conductive polymer to be used is, for example, a polythiophene derivative (PEDOT: poly-(3,4-)ethylenedioxythiophene) doped with polystyrenesulfonate (PSS), or a polypyrrole derivative doped with TCNA, etc. Alternatively, the gate electrode 23 can have a two-layer structure composed of two different metals, e.g., Al / Ti, Au / Ni, or Au / Co.

[0083] The gate insulating film 24 is made of an insulating material such as SiO2, AlN, SiN, Al2O3 or β-(Al x Ga 1-x )2O3 (0 ≤ x ≤ 1). Of these, the β-(Al x Ga 1-x)2O3 can be grown as a single crystal film on a β-Ga2O3 crystal, enabling the formation of a good semiconductor-insulating film interface with fewer interface states, resulting in better gate properties than when using other insulating films.

[0084] The contact areas 25 are areas with a high concentration of the n-doping agent, which are formed in layer 22b of the epitaxial layer 22. The p + -Regions 28 are areas with a high p-doping agent concentration, which are formed in layer 22b of the epitaxial layer 22. The two contact regions 25 and the p + -Areas 28 are in ohmic contact with the source electrode 26.

[0085] The following section describes a method for fabricating the vertical transistor 20 in its second embodiment, along with specific examples. However, the method for fabricating the vertical transistor 20 is not limited to the examples described below. (Semiconductor element manufacturing process 1)

[0086] The Fig. Figures 8A to 8D and 9A to 9D are vertical cross-sectional views showing an exemplary process for fabricating the vertical transistor 20 in the second embodiment. In the Fig. In the example shown in 8A to 8D and 9A to 9D, the thickness of the base substrate 21 is reduced by polishing.

[0087] As in Fig. As shown in Figure 8A, the epitaxial layer 22 is first formed on the base substrate 21.

[0088] The base substrate 21 is the same substrate as the base substrate 11 in the first embodiment and has a thickness of, for example, 600 µm before polishing. The process of forming the epitaxial layer 22 is similar to the process of forming the epitaxial layer 12 in the first embodiment, but differs in that the dopant to be doped is changed during epitaxy, so that layer 22a and layer 22b are formed.

[0089] As in Fig. As shown in Figure 8B, the gate electrode 23, the gate insulating film 24, the contact areas 25 and the p are subsequently shown in the epitaxial layer 22. + -Areas 28 trained.

[0090] First, ions of an n-type dopant are implanted at a high dose into the upper surface of the epitaxial layer 22 (a surface opposite the surface in contact with the substrate 21) to form the contact area 25. Additionally, ions of a p-type dopant are implanted at a high dose to form the p-type + -areas 28 are to be formed. Subsequently, the implantation damage is repaired by annealing in a nitrogen atmosphere, etc.

[0091] Subsequently, a trench is formed on the epitaxial layer 22 by dry etching to divide the contact area 25, and the gate electrode 23, covered with the gate insulating film 24, is embedded in the trench. Specifically, the gate insulating film 24 is formed on the underside and sides of the trench by deposition and etching, the gate electrode 23 is formed on top of this by deposition and etching, and finally, the gate insulating film 24 is formed on the top side of the gate electrode 23 by deposition and etching.

[0092] As in Fig. As shown in Figure 8C, the epitaxial layer 22 is subsequently attached to the support substrate 15 via the adhesive layer 16. The material used for the support substrate 15 here is, for example, metal, resin, or ceramic, etc., but is not limited to this. The adhesive layer 16 is the same as the one used in the first embodiment.

[0093] As in Fig. As shown in Figure 8D, the thickness of the base substrate 21 supported by the support substrate 15 is subsequently reduced by polishing to not less than 10 µm and not more than 50 µm.

[0094] The polishing performed on the base substrate 21 is the same as the polishing performed on the base substrate 11 in the first embodiment.

[0095] As in Fig. As shown in Figure 9A, the drain electrode 27 is subsequently formed on the lower surface of the base substrate 21 (a surface opposite the surface in contact with the epitaxial layer 22).

[0096] To form the drain electrode 27, a mask pattern is formed on the base substrate 21 by photolithography, a metal film is then deposited on the entire surface of the base substrate 21, and the mask pattern and the metal film on it are removed by lifting.

[0097] As in Fig. As shown in Figure 9B, the support substrate 17, which has the electrode 18 on one side, is prepared, and the base substrate 21 is attached to the support substrate 17 by bonding the drain electrode 27 to the electrode 18. The material of the support substrate 17 is not specifically limited. However, if the support substrate 17 is to be retained as a support substrate for the vertical transistor 20, as described later, it is preferably made of a material that has a higher thermal conductivity than β-Ga₂O₃, e.g., a metal such as Al, a nitride such as AlN, SiN, or GaN, an oxide such as SiO₂ or Al₂O₃, or SiC, Si, GaAs, or diamond, etc. The electrode 18 is the same as the one used in the first embodiment.

[0098] As in Fig. As shown in Figure 9C, the epitaxial layer 22 supported by the support substrate 17 is subsequently separated from the support substrate 15 and from the adhesive layer 16, and the source electrode 26 is then formed on the upper surface of the epitaxial layer 22 (a surface opposite the surface in contact with the base substrate 21).

[0099] To form the source electrode 26, a mask pattern is formed on the epitaxial layer 22 by photolithography, a metal film made of Pt / Au etc. is then deposited on the entire surface of the epitaxial layer 22, and the mask pattern and the metal film on it are removed by lifting.

[0100] Since the source electrode 26 is formed after polishing the base substrate 21 in this manufacturing process, damage to the source electrode 26 never occurs during the polishing of the base substrate 21, making it possible to improve the yield of the vertical transistor 20.

[0101] The support substrate 17 can be retained as a support substrate for the completed vertical transistor 20. In this case, external power can be supplied to the drain electrode 27 through the electrode 18 of the support substrate 17. If the support substrate 17 is electrically conductive, external power can be supplied to the drain electrode 27 through the support substrate 17 and the electrode 18. Alternatively, the vertical transistor 20 can be detached from the support substrate 17 and then attached to a different support substrate. (Semiconductor element manufacturing process 2)

[0102] The Fig. Figures 10A to 10C are vertical cross-sectional views showing an exemplary process for the fabrication of the vertical transistor 20 in the second embodiment. In the Fig. In the example shown in 10A to 10C, the thickness of the base substrate 21 is reduced by polishing and subsequent etching.

[0103] As in Fig. As shown in 10A, the following will be shown first: Fig. The process shown in 8A to 8D is carried out up to polishing to reduce the thickness of the base substrate 21.

[0104] As in Fig. As shown in Figure 10B, the thickness of the base substrate 21, which is supported by the support substrate 15, is subsequently further reduced by etching. The thickness of the base substrate 21 can be reduced to less than 10 µm by this etching.

[0105] The etching carried out on the base substrate 21 is the same as the etching carried out on the base substrate 11 in the first embodiment.

[0106] As in Fig. As shown in Figure 10C, the drain electrode 27 is subsequently formed on the lower surface of the base substrate 21.

[0107] In the same way as in the Fig. 9B and Fig. In the process shown in Figure 9C, the base substrate 21 is then attached to the support substrate 17, the epitaxial layer 22 is separated from the support substrate 15 and from the adhesive layer 16, and the source electrode 26 is then formed. (Semiconductor element manufacturing process 3)

[0108] The Fig. Figures 11A to 11D and 12 are vertical cross-sectional views showing an exemplary process for the fabrication of the vertical transistor 20 in the second embodiment. In the Fig. In the example shown in 11A to 11D and 12, the thickness of the base substrate 21 is reduced by polishing.

[0109] As in Fig. As shown in Figure 11A, the epitaxial layer 22 is first formed on the base substrate 21.

[0110] As in Fig. As shown in Figure 11B, the gate electrode 23, the gate insulating film 24, the contact areas 25 and the p are subsequently shown in the epitaxial layer 22. + -areas 28 are formed and the source electrode 26 is then formed on the epitaxial layer 22.

[0111] As in Fig. As shown in Figure 11C, the support substrate 15, which has the electrode 19 on one side, is subsequently prepared, and the epitaxial layer 22 is attached to the support substrate 15 by bonding the source electrode 26 to the electrode 19. The material of the support substrate 15 is not specifically limited. However, if the support substrate 15 is to be retained as a support substrate for the vertical transistor 20, as described later, it is preferably formed from a material that has a higher thermal conductivity than β-Ga₂O₃, e.g., from a metal such as Al, from a nitride such as AlN, SiN, or GaN, from an oxide such as SiO₂ or Al₂O₃, or from SiC, Si, GaAs, or from diamond, etc.

[0112] As in Fig. As shown in Figure 11D, the thickness of the base substrate 21 supported by the support substrate 15 is subsequently reduced by polishing to not less than 10 µm and not more than 50 µm.

[0113] As in Fig. As shown in Figure 12, the drain electrode 27 is subsequently formed on the lower surface of the base substrate 21 (a surface opposite the surface in contact with the epitaxial layer 22).

[0114] The support substrate 15 can be retained as a support substrate for the completed vertical transistor 20. In this case, external power can be supplied to the source electrode 26 through the electrode 19 of the support substrate 15. If the support substrate 15 is electrically conductive, external power can be supplied to the source electrode 26 through the support substrate 15 and the electrode 19. Alternatively, the vertical transistor 20 can be separated from the support substrate 15 and then attached to a different support substrate. (Semiconductor element manufacturing process 4)

[0115] The Fig. Figures 13A to 13C are vertical cross-sectional views showing an exemplary process for the fabrication of the vertical transistor 20 in the second embodiment. In the Fig. In the example shown in 13A to 13C, the thickness of the base substrate 21 is reduced by polishing and subsequent etching.

[0116] As in Fig. As shown in 13A, the following is shown first: Fig. The process shown in 11A to 11D is carried out up to polishing to reduce the thickness of the base substrate 21.

[0117] As in Fig. As shown in Figure 13B, the thickness of the base substrate 21, which is supported by the support substrate 15, is subsequently further reduced by etching. The thickness of the base substrate 21 can be reduced to less than 10 µm by this etching.

[0118] As in Fig. As shown in Figure 13C, the drain electrode 27 is subsequently formed on the lower surface of the base substrate 21. [Third embodiment]

[0119] The third embodiment is a lateral semiconductor element implemented as a lateral transistor having a MESFET (metal-semiconductor field-effect transistor) structure. (Structure of the semiconductor element)

[0120] Fig. Figure 14 is a vertical cross-sectional view showing a lateral transistor 30 in the third embodiment. The lateral transistor 30 is provided with an epitaxial layer 32 formed on a substrate 31 and with a gate electrode 33, a source electrode 34, and a drain electrode 35 arranged on the epitaxial layer 32. The gate electrode 33 is positioned between the source electrode 34 and the drain electrode 35.

[0121] The gate electrode 33 is in contact with the upper surface of the epitaxial layer 32 (a surface opposite the surface in contact with the substrate 31), with a Schottky junction formed between them. Meanwhile, the source electrode 34 and the drain electrode 35 are in contact with the upper surface of the epitaxial layer 32, with ohmic junctions formed between them.

[0122] The basic substrate 31 is formed from a Ga2O3-based crystal containing a p-doping agent such as Mg, Be, Zn or Fe and exhibiting high electrical resistance.

[0123] The thickness of the base substrate 31 is the same as the thickness of the base substrate 11 in the first embodiment. Since the base substrate 31 is thin, heat generated in the lateral transistor 30 can be effectively dissipated through the base substrate 31. Thus, the lateral transistor 30 exhibits excellent heat dissipation.

[0124] The plane orientation of the main surface of the base substrate 31 is also the same as that of the base substrate 11 in the first embodiment, with (010) being particularly preferred. Furthermore, one or two buffer layers can be provided between the base substrate 31 and the epitaxial layer 32. The buffer layer exhibits high resistance and can be considered part of the base substrate 31.

[0125] The epitaxial layer 32 is formed from a Ga₂O₃-based crystal and contains an n-type dopant. The concentration of the n-type dopant is higher around the contact areas with the source electrode 34 and the drain electrode 35 than in other sections. The thickness of the epitaxial layer 32 is, for example, 0.1 to 1 µm.

[0126] Since the epitaxial layer 32 is formed from a Ga2O3-based crystal, which exhibits a high breakdown field strength, the lateral transistor 30 possesses the property of excellent voltage withstand capability. Thus, the lateral transistor 30 exhibits both the property of high heat dissipation and the property of high voltage withstand capability.

[0127] The gate electrode 33, the source electrode 34, and the drain electrode 35 are, for example, made of a metal such as Au, Al, Ti, Sn, Ge, In, Ni, Co, Pt, W, Mo, Cr, Cu, or Pb; of an alloy containing two or more such metals; of a conductive compound such as ITO; or of a conductive polymer. The conductive polymer to be used is, for example, a polythiophene derivative (PEDOT: poly-(3,4-)ethylenedioxythiophene) doped with polystyrenesulfonate (PSS), or a polypyrrole derivative doped with TCNA, etc. Alternatively, the gate electrode 33 can have a two-layer structure composed of two different metals, e.g., Al / Ti, Au / Ni, or Au / Co.

[0128] In the lateral transistor 30 it is possible to change the thickness of a depletion layer formed under the gate electrode 33 in the epitaxial layer 32 by controlling the bias voltage applied to the gate electrode 33 and thereby controlling the drain current.

[0129] The following section describes a method for fabricating the lateral transistor 30 in its third embodiment, along with specific examples. However, the method for fabricating the lateral transistor 30 is not limited to the examples described below. (Semiconductor element manufacturing process 1)

[0130] The Fig. Figures 15A to 15E are vertical cross-sectional views showing an exemplary process for the fabrication of the lateral transistor 30 in the third embodiment. In the Fig. In the example shown in 15A to 15E, the thickness of the base substrate 31 is reduced by polishing.

[0131] As in Fig. As shown in Figure 15A, the epitaxial layer 32 is first formed on the base substrate 31.

[0132] The base substrate 31 is the same substrate as the base substrate 11 in the first embodiment and has a thickness of, for example, 600 µm before polishing. The process for forming the epitaxial layer 32 is the same as the process for forming the epitaxial layer 12 in the first embodiment.

[0133] As in Fig. As shown in Figure 15B, the epitaxial layer 32 is subsequently attached to the support substrate 15 via the adhesive layer 16. The material used for the support substrate 15 here is, for example, metal, ceramic resin, etc., but is not limited to these. The adhesive layer 16 is the same as the one used in the first embodiment.

[0134] As in Fig. As shown in 15C, the thickness of the base substrate 31 supported by the support substrate 15 is subsequently reduced by polishing to not less than 10 µm and not more than 50 µm.

[0135] The polishing performed on the base substrate 31 is the same as the polishing performed on the base substrate 11 in the first embodiment.

[0136] As in Fig. As shown in Figure 15D, a support substrate 37 is subsequently attached to the lower surface of the base substrate 31 (a surface opposite the surface in contact with the epitaxial layer 32). The material of the support substrate 37 is not specifically limited. However, if the support substrate 37 is to be retained as a support substrate for the lateral transistor 30, as described later, it is preferably formed from a material having a higher thermal conductivity than β-Ga₂O₃, e.g., from a metal such as Al, from a nitride such as AlN, SiN, or GaN, from an oxide such as SiO₂ or Al₂O₃, or from SiC, Si, or GaAs, or from diamond, etc.

[0137] The base substrate 31 is attached to the support substrate 37 using a solder (Au-Sn, Sn-Ag-Cu or Si-Ge), an Ag paste, a resin or an inorganic material, etc.

[0138] As in Fig. As shown in Figure 15E, the epitaxial layer 32, supported by the support substrate 37, is subsequently separated from the support substrate 15 and the adhesive layer 16. Then, the gate electrode 33, the source electrode 34, and the drain electrode 35 are formed on the upper surface of the epitaxial layer 32 (a surface opposite the surface in contact with the base substrate 31).

[0139] To form the gate electrode 33, the source electrode 34 and the drain electrode 35, a mask pattern is formed on the epitaxial layer 32 by photolithography, a metal film is then deposited on the entire surface of the epitaxial layer 32 and the mask pattern and the metal film on it are removed by lifting.

[0140] Since the gate electrode 33, the source electrode 34 and the drain electrode 35 are formed in this manufacturing process after polishing the base substrate 31, damage to the gate electrode 33, the source electrode 34 and the drain electrode 35 never occurs during the polishing of the base substrate 31, and it is therefore possible to improve the yield of the lateral transistor 30.

[0141] The support substrate 37 can be retained as a support substrate for the completed lateral transistor 30. Alternatively, the lateral transistor 30 can be separated from the support substrate 37 and then attached to a different support substrate. (Semiconductor element manufacturing process 2)

[0142] The Fig. Figures 16A to 16C are vertical cross-sectional views showing an exemplary process for the fabrication of the lateral transistor 30 in the third embodiment. In the Fig. In the example shown in 16A to 16C, the thickness of the base substrate 31 is reduced by polishing and subsequent etching.

[0143] As in Fig. As shown in 16A, the following is first shown: Fig. The process shown in 15A to 15C is carried out up to polishing to reduce the thickness of the base substrate 31.

[0144] As in Fig. As shown in Figure 16B, the thickness of the base substrate 31, supported by the support substrate 15, is subsequently further reduced by etching. The thickness of the base substrate 31 can be reduced to less than 10 µm by this etching.

[0145] The etching carried out on the base substrate 31 is the same as the etching carried out on the base substrate 11 in the first embodiment.

[0146] As in Fig. As shown in Figure 16C, the support substrate 37 is subsequently attached to the lower surface of the base substrate 31.

[0147] The epitaxial layer 32 is then separated from the supporting substrate 15 and from the adhesive layer 16, and subsequently, in the same manner as in the Fig. The process shown in Figure 15E forms the gate electrode 33, the source electrode 34 and the drain electrode 35. (Semiconductor element manufacturing process 3)

[0148] The Fig. Figures 17A to 17E are vertical cross-sectional views showing an exemplary process for the fabrication of the lateral transistor 30 in the third embodiment. In the Fig. In the example shown in 17A to 17E, the thickness of the base substrate 31 is reduced by polishing.

[0149] As in Fig. As shown in Figure 17A, the epitaxial layer 32 is first formed on the base substrate 31.

[0150] As in Fig. As shown in Figure 17B, the gate electrode 33, the source electrode 34 and the drain electrode 35 are subsequently formed on the upper surface of the epitaxial layer 32.

[0151] As in Fig. As shown in Figure 17C, the support substrate 15 is subsequently prepared, which has an adhesive layer 36 made of resin, etc., on one side, and the epitaxial layer 32 is attached to the support substrate 15 by bonding the adhesive layer 36 to the upper surface of the epitaxial layer 32, on which the gate electrode 33, the source electrode 34, and the drain electrode 35 are provided. The material used for the support substrate 15 here is, for example, metal, resin, or ceramic, etc., but is not limited to this.

[0152] As in Fig. As shown in Figure 17D, the thickness of the base substrate 31 supported by the support substrate 15 is subsequently reduced by polishing to not less than 10 µm and not more than 50 µm.

[0153] As in Fig. As shown in Figure 17E, the support substrate 37 is subsequently attached to the lower surface of the base substrate 31, and the epitaxial layer 32 supported by the support substrate 37 is separated from the support substrate 15 and the adhesive layer 16. The material of the support substrate 37 is not specifically limited. However, if the support substrate 37 is to be retained as a support substrate for the lateral transistor 30, as described later, it is preferably formed from a material that has a higher thermal conductivity than β-Ga₂O₃, e.g., from a metal such as Al, from a nitride such as AlN, SiN, or GaN, from an oxide such as SiO₂ or Al₂O₃, or from SiC, Si, GaAs, or from diamond, etc.

[0154] The support substrate 37 can be retained as a support substrate for the completed lateral transistor 30. Alternatively, the lateral transistor 30 can be separated from the support substrate 37 and then attached to a different support substrate. (Semiconductor element manufacturing process 4)

[0155] The Fig. Figures 18A to 18C are vertical cross-sectional views showing an exemplary process for the fabrication of the lateral transistor 30 in the third embodiment. In the Fig. In the example shown in 18A to 18C, the thickness of the base substrate 31 is reduced by polishing and subsequent etching.

[0156] As in Fig. As shown in 18A, the following is shown first: Fig. The process shown in 17A to 17D is carried out up to polishing to reduce the thickness of the base substrate 31.

[0157] As in Fig. As shown in Figure 18B, the thickness of the base substrate 31, supported by the support substrate 15, is subsequently further reduced by etching. The thickness of the base substrate 31 can be reduced to less than 10 µm by this etching.

[0158] As in Fig. As shown in Figure 18C, the support substrate 37 is subsequently attached to the lower surface of the base substrate 31 and the epitaxial layer 32 supported by the support substrate 37 is separated from the support substrate 15 and from the adhesive layer 36. (Semiconductor element manufacturing process 5)

[0159] The Fig. Figures 19A to 19D are vertical cross-sectional views showing an exemplary process for the fabrication of the lateral transistor 30 in the third embodiment. In the Fig. In the example shown in 19A to 19D, the thickness of the base substrate 31 is reduced by polishing.

[0160] As in Fig. As shown in Figure 19A, the epitaxial layer 32 is first formed on the base substrate 31.

[0161] As in Fig. As shown in Figure 19B, the gate electrode 33, the source electrode 34 and the drain electrode 35 are subsequently formed on the upper surface of the epitaxial layer 32.

[0162] As in Fig. As shown in Figure 19C, the support substrate 15, which has electrodes 38a, 38b, and 38c on one side, is subsequently prepared, and the epitaxial layer 32 is attached to the support substrate 15 by bonding the gate electrode 33, the source electrode 34, and the drain electrode 35 to the electrodes 38a, 38b, and 38c in that order. The material of the support substrate 15 is not specifically limited. However, if the support substrate 15 is to be retained as a support substrate for the lateral transistor 30, as described later, it is preferably formed from a material that has a higher conductivity than β-Ga₂O₃, e.g., from a metal such as Al, from a nitride such as AlN, SiN, or GaN, from an oxide such as SiO₂ or Al₂O₃, or from SiC, Si, GaAs, or from diamond, etc.

[0163] As in Fig. As shown in Figure 19D, the thickness of the base substrate 31 supported by the support substrate 15 is subsequently reduced by polishing to not less than 10 µm and not more than 50 µm.

[0164] The support substrate 15 can be retained as a support substrate for the completed lateral transistor 30. However, in this case, the support substrate 15 must possess insulating properties. Furthermore, in this case, external power can be supplied to the gate electrode 33, the source electrode 34, and the drain electrode 35 via the electrodes 38a, 38b, and 38c of the support substrate 15. Alternatively, the lateral transistor 30 can be detached from the support substrate 15 and then attached to a different support substrate. (Semiconductor element manufacturing process 6)

[0165] The Fig. 20A and Fig. Figures 20B are vertical cross-sectional views showing an exemplary process for the fabrication of the lateral transistor 30 in the third embodiment. In the Fig. 20A and Fig. In the example shown in 20B, the thickness of the base substrate 31 is reduced by polishing and subsequent etching.

[0166] As in Fig. 20A is shown first, the one in the Fig. The process shown in 19A to 19D is carried out up to polishing to reduce the thickness of the base substrate 31.

[0167] As in Fig. As shown in Figure 20B, the thickness of the base substrate 31, supported by the support substrate 15, is subsequently further reduced by etching. The thickness of the base substrate 31 can be reduced to less than 10 µm by this etching. (The change)

[0168] The lateral transistor 30 can be a MISFET in which the gate electrode 33 is formed via a gate insulating film on the epitaxial layer 32.

[0169] In this case, the gate insulating film is made of an insulating material such as SiO2, AlN, SiN, Al2O3 or β-(Al x Ga 1-x )2O3 (0 ≤ x ≤ 1). Of course, the β-(Al x Ga 1-x )2O3 can be grown as a single crystal film on a β-Ga2O3 crystal, allowing a good semiconductor-insulating film interface to be formed with fewer interface states, resulting in better gate properties than when using other insulating films.

[0170] In this case, the epitaxial layer 32 can be an undoped layer that does not contain a dopant, or a p-layer that contains a p-dopant such as Be, Mg or Zn.

[0171] If the lateral transistor 30 is a MISFET, each MESFET fabrication process described above is performed in addition to a gate insulating film formation process. The gate insulating film is formed, for example, by deposition and etching. [Fourth embodiment]

[0172] The fourth embodiment is a vertical semiconductor element implemented as a Schottky diode. (Structure of the semiconductor element)

[0173] Fig. Figure 21 is a vertical cross-sectional view showing a Schottky diode 40 in the fourth embodiment. The Schottky diode 40 is provided with an epitaxial layer 42, with an ion-implanted layer 41 formed on a surface of the epitaxial layer 42, with a cathode electrode 43 formed on a lower surface of the epitaxial layer 42 (on a surface on which the ion-implanted layer 41 is provided) and in ohmic contact with the epitaxial layer 42, and with an anode electrode 44 formed on an upper surface of the epitaxial layer 42 (a surface on which the ion-implanted layer 41 is not provided) and in Schottky contact with the epitaxial layer 42.

[0174] In the Schottky diode 40, the height of the Schottky barrier at an interface between the anode electrode 44 and the epitaxial layer 42 is lowered by applying a forward bias between the anode electrode 44 and the cathode electrode 43, whereby, in the same manner as in the Schottky diode 10 in the first embodiment, a current flows from the anode electrode 44 to the cathode electrode 43. Conversely, the height of the Schottky barrier at the interface between the anode electrode 44 and the epitaxial layer 42 is increased, and no current flows when a reverse bias is applied between the anode electrode 44 and the cathode electrode 43.

[0175] The epitaxial layer 42 is formed in the same way as the epitaxial layer 12 in the first embodiment from a crystal based on Ga2O3 and contains an n-doping agent.

[0176] The ion-implanted layer 41 is a layer formed by implanting a high dose of an n-type dopant into the epitaxial layer 42 and has a higher concentration of the n-type dopant than the epitaxial layer 42. Furthermore, the ion-implanted layer 41 is formed near the surface of the epitaxial layer 42 and is evidently thinner than the epitaxial layer 42. Preferably, the n-type dopant is a group IV element such as Si or Sn. To reduce the conduction loss of the Schottky diode, it is particularly preferred to use Si as an n-type dopant, since the activation rate of Si, when implanted with a high dose, is higher than that of Sn.

[0177] In the Schottky diode 40, a base substrate, which serves as a foundation for the epitaxy of the epitaxial layer 42 (e.g., a base substrate 45 described later), is removed and replaced by the ion-implanted layer 41, which is intended to be in ohmic contact with the cathode electrode 43. Thus, a heat dissipation path to the ion-implanted layer 41 does not pass through the base substrate, and heat is efficiently dissipated. Therefore, the Schottky diode 40 exhibits excellent heat dissipation. Furthermore, the use of the ion implantation technique allows for a higher donor concentration than a method in which impurities are introduced during substrate growth, thereby reducing the conduction loss of the Schottky diode.

[0178] The thickness of the epitaxial layer 42 is, for example, 0.4 to 30 µm. Meanwhile, the thickness of the ion-implanted layer 41 is preferably not less than 0.05 µm, so that the ion-implanted layer 41 is in ohmic contact with the cathode electrode 43.

[0179] Since the epitaxial layer 42 is formed from a Ga2O3-based crystal exhibiting a high breakdown field strength, a reduction in the dielectric strength of the Schottky diode 40 can be prevented even when the base substrate 45 is removed. Thus, the Schottky diode 40 exhibits both high heat dissipation and high dielectric strength properties.

[0180] The materials of the anode electrode 44 and the cathode electrode 43 are the same as those for the anode electrode 14 and the cathode electrode 13 respectively in the first embodiment. (Semiconductor element manufacturing process)

[0181] The Fig. Figures 22A to 22E and 23A to 23D are vertical cross-sectional views showing an exemplary process for the fabrication of the Schottky diode 40 in the fourth embodiment. In the Fig. In the example shown in 22A to 22E and 23A to 23D, the base substrate is removed by polishing, etc.

[0182] As in Fig. As shown in Figure 22A, the epitaxial layer 42 is first formed on the base substrate 45.

[0183] The base substrate 45 is the same substrate as the base substrate 11 in the first embodiment and has a thickness of, for example, 600 µm before polishing, etc. The base substrate 45 may not contain an n-doping agent. The process of forming the epitaxial layer 42 is the same as the process of forming the epitaxial layer 12 in the first embodiment.

[0184] As in Fig. As shown in Figure 22B, the epitaxial layer 42 is subsequently attached to the support substrate 15 via the adhesive layer 16. The material used for the support substrate 15 here is, for example, metal, resin, or ceramic, etc., but is not limited to this. The adhesive layer 16 is the same as the one used in the first embodiment.

[0185] As in Fig. As shown in Figure 22C, the thickness of the base substrate 45 supported by the support substrate 15 is subsequently reduced by polishing and is finally removed by further continuous polishing.

[0186] The method for removing the base substrate 45 is not limited to polishing and can be a combination of polishing with another process such as etching.

[0187] As in Fig. As shown in Figure 22D, ions of an n-doping agent are subsequently implanted into the lower surface of the epitaxial layer 42.

[0188] As in Fig. As shown in Figure 22E, the n-doping agent implanted into the epitaxial layer 42 is subsequently activated by annealing, thereby forming the ion-implanted layer 41. The annealing is carried out, for example, for 30 minutes in an inert atmosphere at 800 to 1000 °C.

[0189] As in Fig. As shown in Figure 23A, the cathode electrode 43 is subsequently formed on the lower surface of the epitaxial layer 42 such that it is in contact with the ion-implanted layer 41. Since the ion-implanted layer 41 contains a high concentration of an n-type dopant, it is in ohmic contact with the cathode electrode 43. The process of forming the cathode electrode 43 is the same as the process of forming the cathode electrode 13 in the first embodiment.

[0190] As in Fig. As shown in Figure 23B, a support substrate 47 is subsequently prepared which has an electrode 48 on one side, and the epitaxial layer 42 is attached to the support substrate 47 by bonding the cathode electrode 43 to the electrode 48.

[0191] The material of the support substrate 47 is not specifically limited. However, if the support substrate 47 is retained as a support substrate for the Schottky diode 40, as described later, it is preferably made of a material with a higher thermal conductivity than β-Ga₂O₃, e.g., a metal such as Al, a nitride such as AlN, SiN, or GaN, an oxide such as SiO₂ or Al₂O₃, or SiC, Si, GaAs, or diamond, etc. The electrode 48 is made, for example, of Au. The cathode electrode 43 is bonded to the electrode 48 by applying, for example, pressure, heat, a combination of pressure and ultrasonic vibration, or pressure and a combination of pressure and ultrasonic vibration.

[0192] As in Fig. As shown in Figure 23C, the epitaxial layer 42 supported by the support substrate 47 is subsequently separated from the support substrate 15 and from the adhesive layer 16.

[0193] As in Fig. As shown in Figure 23D, the anode electrode 44 is subsequently formed on the upper surface of the epitaxial layer 42. Since the epitaxial layer 42, unlike the ion-implanted layer 41, contains a low concentration of an n-type dopant, the epitaxial layer 42 is in Schottky contact with the anode electrode 44. The process of forming the anode electrode 44 is the same as the process of forming the anode electrode 14 in the first embodiment.

[0194] The support substrate 47 can be retained as a support substrate for the completed Schottky diode 40. In this case, external power can be supplied to the cathode electrode 43 via the electrode 48 of the support substrate 47. If the support substrate 47 is electrically conductive, external power can be supplied to the cathode electrode 43 via the support substrate 47 and the electrode 48. Alternatively, the Schottky diode 40 can be separated from the support substrate 47 and then attached to a different support substrate. [Fifth embodiment]

[0195] In the fifth embodiment, support substrates are attached to both surfaces of a Schottky diode, a vertical transistor and a lateral transistor as semiconductor elements in order to improve heat dissipation. (Structure of the semiconductor element)

[0196] Fig. Figure 24A is a vertical cross-sectional view showing the Schottky diode 10 in the first embodiment with support substrates attached on both sides.

[0197] A support substrate 51 has an electrode 53 on one side, and the epitaxial layer 12 is attached to the support substrate 51 by bonding the anode electrode 14 to the electrode 53. A support substrate 52 has an electrode 54 on one side, and the base substrate 11 is attached to the support substrate 52 by bonding the cathode electrode 13 to the electrode 54.

[0198] Preferably, the material of the support substrates 51 and 52 is a material that has a higher thermal conductivity than β-Ga2O3, e.g. a metal such as Al, a nitride such as AlN, SiN or GaN, an oxide such as SiO2 or Al2O3 or SiC, Si, GaAs or diamond, etc.

[0199] The same configuration can also be assumed if the Schottky diode 40 in the fourth embodiment is used instead of the Schottky diode 10. In this case, the epitaxial layer 42 and the ion-implanted layer 41 of the Schottky diode 40 are attached to the support substrates 51 and 52, respectively.

[0200] Fig. Figure 24B is a vertical cross-sectional view showing the vertical transistor 20 in the second embodiment with support substrates attached on both sides.

[0201] The epitaxial layer 22 is attached to the support substrate 51 by bonding the source electrode 26 to the electrode 53. The base substrate 21 is attached to the support substrate 52 by bonding the drain electrode 27 to the electrode 54.

[0202] In the fifth embodiment, external power can be supplied to the Schottky diode 10 and the vertical transistor 20 via electrodes 53 and 54. If the support substrates 51 and 52 are electrically conductive, external power can be supplied via the support substrates 51 and 52 and the electrodes 53 and 54.

[0203] Fig. Figure 24C is a vertical cross-sectional view showing the lateral transistor 30 in the third embodiment with support substrates attached on both sides.

[0204] The support substrate 51 has electrodes 53a, 53b and 53c on one side, and the epitaxial layer 32 is attached to the support substrate 51 by bonding the source electrode 53a, the drain electrode 53b and the adhesive layer 53c to the electrodes 53a, 53b and 53c. Meanwhile, the base substrate 31 is attached to the support substrate 52.

[0205] The support substrates attached to both sides of the semiconductor element, as described above, allow heat to be efficiently dissipated through the two surfaces, thereby improving the heat dissipation efficiency of the semiconductor element. [Sixth embodiment]

[0206] The sixth embodiment is a vertical semiconductor element implemented as a Schottky diode. (Structure of the semiconductor element)

[0207] Fig. Figure 25 is a vertical cross-sectional view showing a Schottky diode 60 in the sixth embodiment. The Schottky diode 60 is provided with an epitaxial layer 62, with a highly thermally conductive substrate 61 bonded to a surface of the epitaxial layer 62, with a cathode electrode 63 formed on a lower surface of the highly thermally conductive substrate 61 (a surface opposite the surface in contact with the epitaxial layer 62) and in ohmic contact with the highly thermally conductive substrate 61, and with an anode electrode 64 formed on an upper surface of the epitaxial layer 62 (a surface opposite the surface in contact with the highly thermally conductive substrate 61) and in Schottky contact with the epitaxial layer 62.

[0208] In the Schottky diode 60, in the same way as in the Schottky diode 10 in the first embodiment, the height of the Schottky barrier at an interface between the anode electrode 64 and the epitaxial layer 62 is lowered by applying a forward bias between the anode electrode 64 and the cathode electrode 63, whereby a current flows from the anode electrode 64 to the cathode electrode 63. Conversely, the height of the Schottky barrier at the interface between the anode electrode 64 and the epitaxial layer 62 is increased, and no current flows, when a reverse bias is applied between the anode electrode 64 and the cathode electrode 63.

[0209] The epitaxial layer 62 is formed in the same way as the epitaxial layer 12 in the first embodiment from a crystal based on Ga2O3 and contains an n-doping agent.

[0210] The highly thermally conductive substrate 61 is made of a material with a higher thermal conductivity than a Ga₂O₃-based crystal, such as AlN or Si, and contains an n-type dopant. The concentration of the n-type dopant in the highly thermally conductive substrate 61 is higher than that of the epitaxial layer 62.

[0211] In the Schottky diode 60, a base substrate used as a basis for the epitaxy of the epitaxial layer 62, e.g., a base substrate 65 described later, is removed, and the highly thermally conductive substrate 61 is used as a layer in ohmic contact with the cathode electrode 63. Since the thermal conductivity of the highly thermally conductive substrate 61 is higher than that of the base substrate 65 formed from a Ga₂O₃-based crystal, heat dissipation can be improved by using the highly thermally conductive substrate 61 as a layer intended to be in ohmic contact with the cathode electrode 63. Thus, the Schottky diode 60 exhibits the property of excellent heat dissipation.

[0212] Furthermore, a reduction in the thickness of the Schottky diode 60 to improve heat dissipation is not necessary, since the highly thermally conductive substrate 61 has a high thermal conductivity.

[0213] The thickness of the epitaxial layer 62 is, for example, 0.4 to 30 µm. Meanwhile, the thickness of the highly thermally conductive substrate 61 is preferably not less than 0.05 µm, so that the highly thermally conductive substrate 61 is in ohmic contact with the cathode electrode 63.

[0214] The materials of the anode electrode 64 and the cathode electrode 63 are the same as those for the anode electrode 14 and the cathode electrode 13 respectively in the first embodiment.

[0215] The following describes a method for manufacturing the Schottky diode 60 in its sixth embodiment, along with a specific example. However, the method for manufacturing the Schottky diode 60 is not limited to the example described below. (Semiconductor element manufacturing process)

[0216] The Fig. Figures 26A to 26E are vertical cross-sectional views showing an exemplary process for the fabrication of the Schottky diode 60 in the sixth embodiment. In the Fig. In the example shown in 26A to 26E, the base substrate is removed by polishing.

[0217] As in Fig. As shown in Figure 26A, the epitaxial layer 62 is first formed on the base substrate 65.

[0218] The base substrate 65 is the same base substrate as the base substrate 11 in the first embodiment and has a thickness of, for example, 600 µm before polishing, etc. The base substrate 65 cannot contain an n-doping agent. The process for forming the epitaxial layer 62 is the same as the process for forming the epitaxial layer 12 in the first embodiment.

[0219] As in Fig. As shown in Figure 26B, the highly thermally conductive substrate 61 is subsequently bonded to the upper surface of the epitaxial layer 62. For example, direct bonding agents such as surface-activated soil are used to bond the highly thermally conductive substrate 61 to the epitaxial layer 62. In the case of using surface-activated bonding agents, the respective contact surfaces of the epitaxial layer 62 and the highly thermally conductive substrate 61 are etched, for example, with an argon plasma to remove surface layers for activation, and the activated surfaces are then bonded together. Although a high-strength bond can be obtained at room temperature using this method, heat or pressure can also be applied. The epitaxial layer 62 and the highly thermally conductive substrate 61, which are bonded by surface-activated soil, are in ohmic contact with each other at a bonding interface between them.

[0220] As in Fig. As shown in Figure 26C, the thickness of the base substrate 65, which is supported by the highly thermally conductive substrate 61, is subsequently reduced by polishing and is finally removed by further continuous polishing.

[0221] The method for removing the base substrate 65 is not limited to polishing and can be a combination of polishing with another process such as etching.

[0222] As in Fig. As shown in Figure 26D, the anode electrode 64 is subsequently formed on a surface of the epitaxial layer 62 on the side opposite the highly thermally conductive substrate 61. Since the epitaxial layer 62 contains a low concentration of an n-type dopant, the epitaxial layer 62 is in Schottky contact with the anode electrode 64. The process of forming the anode electrode 64 is the same as the process of forming the anode electrode 14 in the first embodiment.

[0223] As in Fig. As shown in Figure 26E, the cathode electrode 63 is subsequently formed on a surface of the highly thermally conductive substrate 61 on the side opposite the epitaxial layer 62. Since the highly thermally conductive substrate 61 contains a high concentration of the n-doping agent, the highly thermally conductive substrate 61 is in ohmic contact with the cathode electrode 63. The process of forming the cathode electrode 63 is the same as the process of forming the cathode electrode 63 in the first embodiment. [Seventh embodiment]

[0224] The seventh embodiment is a vertical semiconductor element implemented as a vertical transistor having a MISFET structure. (Structure of the semiconductor element)

[0225] Fig. Figure 27 is a vertical cross-sectional view showing a vertical transistor 70 in the seventh embodiment. The vertical transistor 70 is equipped with an epitaxial layer 72, a highly thermally conductive substrate 71 bonded to a surface of the epitaxial layer 72, a gate electrode 73 covered with a gate insulating film 74 and embedded in the epitaxial layer 72, and contact areas 75 formed in the epitaxial layer 72 such that they are located on both sides of the gate electrode 73. + -areas 79, which are formed on respective sides of the contact areas 75, are provided with a source electrode 76, which is formed on the epitaxial layer 72 and which is connected to the contact areas 75, and with a drain electrode 77, which is formed on a surface of the highly thermally conductive substrate 71 on the side opposite the epitaxial layer 72.

[0226] The vertical transistor 70 is a vertical semiconductor device in which the source electrode 76 and the drain electrode 77 are arranged on top of and below the device, respectively, and a current flows in a vertical direction. When a voltage not less than the threshold value is applied to the gate electrode 73, channels are formed in the epitaxial layer 72 in regions on both sides of the gate electrode 73, allowing a current to flow from the source electrode 76 to the drain electrode 77.

[0227] The highly thermally conductive substrate 71 is made of a material with a higher thermal conductivity than the Ga₂O₃-based crystal, such as AlN or Si, and contains an n-type dopant. The concentration of the n-type dopant in the highly thermally conductive substrate 71 is higher than that of the epitaxial layer 72.

[0228] In the vertical transistor 70, a base substrate used as a foundation for the epitaxy of the epitaxial layer 72, e.g., a base substrate 78 described later, is removed, and the highly thermally conductive substrate 71 is used as a layer intended to be in ohmic contact with the drain electrode 77. Since the thermal conductivity of the highly thermally conductive substrate 71 is higher than that of the base substrate 78 formed from a Ga₂O₃ crystal, heat dissipation can be improved by using the highly thermally conductive substrate 71 as a layer intended to be in ohmic contact with the drain electrode 77. Thus, the vertical transistor 70 exhibits the property of excellent heat dissipation.

[0229] Furthermore, a reduction in the thickness of the vertical transistor 70 to improve heat dissipation is not necessary, since the highly thermally conductive substrate 71 has a high thermal conductivity.

[0230] The gate electrode 73, the gate insulating film 74, the contact area 75, the source electrode 76, the drain electrode 77 and the p + -Area 79 are in this order the same as the gate electrode 23, the gate insulating film 24, the contact area 25, the source electrode 26, the drain electrode 27 and the p + -Area 28 in the second embodiment. The epitaxial layer 72 is also composed of layers 72a and 72b, which are the same as layers 22a and 22b of the epitaxial layer 22 in the second embodiment.

[0231] In the following, a method for fabricating the vertical transistor 70 in the seventh embodiment is described, along with a specific example of a method for removing the base substrate 78. However, the method for fabricating the vertical transistor 70 is not limited to the example described below. (Semiconductor element manufacturing process)

[0232] The Fig. Figures 28A to 28D are vertical cross-sectional views showing an exemplary process of manufacturing the vertical transistor 70 in the seventh embodiment.

[0233] As in Fig. As shown in Figure 28A, the epitaxial layer 72 is first formed on the base substrate 78.

[0234] The base substrate 78 is the same substrate as the base substrate 11 in the first embodiment and has a thickness of, for example, 600 µm before polishing. The base substrate 78 cannot contain an n-doping agent. The process for forming the epitaxial layer 72 is the same as the process for forming the epitaxial layer 22 in the second embodiment.

[0235] As in Fig. As shown in Figure 28B, the highly thermally conductive substrate 71 is subsequently bonded to the upper surface of the epitaxial layer 72. For example, direct bonding, such as surface-activated bonding, is used to bond the highly conductive substrate 71 to the epitaxial layer 72. The epitaxial layer 72 and the highly thermally conductive substrate 71, which are bonded by surface-activated bonding, are in ohmic contact with each other at a bonding interface between them.

[0236] As in Fig. As shown in Figure 28C, the thickness of the base substrate 78, which is supported by the highly thermally conductive substrate 71, is subsequently reduced by polishing and finally removed by further continuous polishing.

[0237] Polishing can be combined with another process such as etching, or a different process can be used instead of polishing.

[0238] As in Fig. As shown in 28D, the following components are subsequently placed in the epitaxial layer 72 in this order: the gate electrode 73, the gate insulating film 74, the contact areas 75 and the p + -areas 79 are formed and subsequently the source electrode 76 is formed on the epitaxial layer 72. Furthermore, an electrode termination structure or a passivation film may be provided on the epitaxial layer 72.

[0239] The processes for forming the gate electrode 73, the gate insulating film 74, the contact areas 75, the p + -areas 79 and the source electrode 76 are, in this order, the same as the processes for forming the gate electrode 23, the gate insulating film 24, the contact areas 25, the p + -areas 28 and the source electrode 26 in the second embodiment.

[0240] As in Fig. As shown in Figure 29, the drain electrode 77 is subsequently formed on a surface of the highly thermally conductive substrate 71 on the side opposite the epitaxial layer 72.

[0241] The process for forming the drain electrode 77 is the same as the process for forming the drain electrode 27 in the second embodiment. [Eighth embodiment]

[0242] The eighth embodiment is a vertical semiconductor element implemented as a vertical transistor having a MISFET structure. (Structure of the semiconductor element)

[0243] Fig. Figure 30 is a vertical cross-sectional view showing a vertical transistor 80 in the eighth embodiment. The vertical transistor 80 has an epitaxial layer 82 formed on a substrate 81, two source electrodes 86 formed on the epitaxial layer 82, a gate electrode 83 formed over a gate insulating film 84 in a region between the two source electrodes 86 on the epitaxial layer 82, n-contact regions 85 formed under each of the two source electrodes 86 in the epitaxial layer 82, and p-body regions 88 surrounding each of the two contact regions 85. + -areas 89, which are formed on the outer sides of the two contact areas 85, and are provided with a drain electrode 87, which is formed on a surface of the base substrate 81 on the side opposite the epitaxial layer 82.

[0244] When a voltage not less than the threshold value is applied to the gate electrode 83 in the vertical transistor 80, channels are formed in the p-body regions 88 under the gate electrode 83, which allow a current to flow from the source electrode 86 to the drain electrode 87.

[0245] The base substrate 81 and the epitaxial layer 82 are formed from a Ga2O3-based crystal and contain an n-type dopant. Preferably, the n-type dopant is a group IV element such as Si or Sn.

[0246] The thickness of the base substrate 81 is the same as the thickness of the base substrate 11 in the first embodiment. Since the base substrate 81 is thin, the heat generated in the vertical transistor 80 can be effectively dissipated through the base substrate 81. Thus, the vertical transistor 80 exhibits excellent heat dissipation.

[0247] Alternatively, in the fourth embodiment, an ion-implanted layer can be formed in the same way as in the Schottky diode 40 by implanting impurity ions of group IV into the lower surface of the epitaxial layer 82 after complete removal of the base substrate 81, which is to be in ohmic contact with the drain electrode 27.

[0248] The epitaxial layer 82 is formed from a Ga2O3-based crystal, which exhibits a high breakdown field strength. This allows for a smaller thickness than elements formed using other semiconductor materials, while simultaneously preventing a reduction in the voltage withstand capability of the vertical transistor 80. As a result, the overall thickness of the vertical transistor 80 can be reduced, and heat dissipation can be further improved. Thus, the vertical transistor 80 exhibits both high heat dissipation and high voltage withstand capability.

[0249] The plane orientation of the main surface of the base substrate 81 is also the same as that of the base substrate 11 in the first embodiment, wherein (010) is particularly preferred. The thickness of the epitaxial layer 82 is, for example, 0.4 to 30 µm.

[0250] The gate electrode 83, the gate insulating film 84, the source electrode 86 and the drain electrode 87 are, for example, made of the same materials as the gate electrode 23, the gate insulating film 24, the source electrode 26 and the drain electrode 27 in the second embodiment.

[0251] The contact areas 85 are regions with a high concentration of the n-doping agent, which are formed in the epitaxial layer 82 and are connected to the source electrodes 86. Preferably, the n-doping agent is an element of group IV such as Si or Sn.

[0252] Body region 88 and the p + Area 89 contains a p-dopant. The concentration of the p-dopant of the p + The value of area 89 is higher than that of body region 88. Preferably, the p-doping agent is Fe or an element of group II such as Be, Mg, or Zn. Alternatively, body region 88 can be an i-region formed by carrier compensation.

[0253] The vertical transistor 80 can be manufactured using the method for manufacturing the vertical transistor 20 in the second embodiment.

[0254] In the process of forming the gate electrode 23, the gate insulating film 24, and the contact area 25 of the vertical transistor 20, the body areas 88 and the contact area 85 are formed instead. Subsequently, in the process of forming the source electrode 26, the gate insulating film 84, the gate electrode 83, and the source electrode 86 are formed instead.

[0255] Body region 88, the p + -Area 89 and the contact area 85 are formed, for example, by implanting a doping agent into the epitaxial layer 82 using the ion implantation method.

[0256] The procedures for forming the base substrate 81, the epitaxial layer 82 and the drain electrode 87 are in this order the same as the procedures for forming the base substrate 21, the epitaxial layer 22 and the drain electrode 27 of the vertical transistor 20. [Ninth embodiment]

[0257] The ninth embodiment is a vertical semiconductor element implemented as a Schottky diode. (Structure of the semiconductor element)

[0258] Fig. Figure 31 is a vertical cross-sectional view showing a Schottky diode 90 in the ninth embodiment. The Schottky diode 90 is provided with the support substrate 15, with the base substrate 11 attached to the support substrate, with the epitaxial layer 12, which has been formed on an upper surface of the base substrate 11 (a surface opposite the surface in contact with the support substrate 15) by epitaxial growth, with the cathode electrode 13, which is formed on a lower surface of the support substrate 15 (a surface opposite the surface in contact with the base substrate 11) and in ohmic contact with the support substrate 15, and with the anode electrode 14, which is formed on the upper surface of the epitaxial layer 12 (a surface opposite the surface in contact with the base substrate 11) and in Schottky contact with the epitaxial layer 12.

[0259] In the Schottky diode 90, the height of the Schottky barrier at the interface between the anode electrode 14 and the epitaxial layer 12 is lowered by applying a forward bias between the anode electrode 14 and the cathode electrode 13, whereby a current flows from the anode electrode 14 to the cathode electrode 13. Conversely, the height of the Schottky barrier at the interface between the anode electrode 14 and the epitaxial layer 12 is increased, and no current flows, when a reverse bias is applied between the anode electrode 14 and the cathode electrode 13.

[0260] The base substrate 11 is the same as that used in the first embodiment. However, the concentration of the n-doping agent in the base substrate 11 can be, for example, at a similar level to that of the epitaxial layer 12, since in the ninth embodiment the base substrate 11 is not in ohmic contact with the cathode electrode.

[0261] The support substrate 15 is the same as that used in the first embodiment. However, in the ninth embodiment, the support substrate 15 is in ohmic contact with the cathode electrode and is thus formed from a conductor or from a semiconductor containing a high concentration of an n-doping agent.

[0262] Since the base substrate 11 is thin, heat generated in the Schottky diode 90 can be effectively released through the base substrate 11 via the support substrate 15. Thus, the Schottky diode 90 exhibits excellent heat dissipation properties.

[0263] The epitaxial layer 12, the cathode electrode 13 and the anode electrode 14 are the same as those used in the first embodiment.

[0264] The epitaxial layer 12 is formed from a Ga2O3-based crystal, which exhibits a high breakdown field strength. This allows for a smaller thickness than elements formed using other semiconductor materials, while simultaneously preventing a reduction in the dielectric strength of the Schottky diode 90. As a result, the overall thickness of the Schottky diode 90 can be reduced, and heat dissipation can be further improved. Thus, the Schottky diode 90 exhibits both high heat dissipation and high dielectric strength.

[0265] In the following, a method for manufacturing the Schottky diode 10 in the present embodiment is described together with a specific example. (Semiconductor element manufacturing process)

[0266] The Fig. Figures 32A to 32E are vertical cross-sectional views showing an exemplary process for the fabrication of the Schottky diode 90 in the ninth embodiment. In the Fig. In the example shown in Figures 32A to 32E, the thickness of the base layer 11 is reduced by polishing and an epitaxial layer is subsequently allowed to grow on the polished surface of the base substrate 11.

[0267] As in Fig. As shown in Figure 32A, the base substrate 11 is first attached to the support substrate 15. The method for attaching the base substrate 11 to the support substrate 15 is, for example, direct bonding such as surface-activated bonding or adhesion using a conductive adhesive.

[0268] As in Fig. As shown in Figure 32B, the thickness of the base substrate 11 supported by the support substrate 15 is subsequently reduced by polishing to not less than 10 µm and not more than 50 µm.

[0269] The polishing carried out in this base substrate 11 is the same as the polishing carried out on the base substrate 11 in the first embodiment.

[0270] The method for removing the base substrate 11 is not limited to polishing. Polishing can be combined with another process such as etching. The thickness of the base substrate 11 can be reduced to less than 10 µm by etching.

[0271] After reducing the thickness, the base substrate 11 can be separated from the support substrate 15. The separated base substrate 11 is a semiconductor substrate formed from a Ga₂O₃-based crystal with a thickness of not less than 0.05 µm and not more than 50 µm and can be used as a base substrate for epitaxy to fabricate another semiconductor device. Furthermore, the plane orientation of the main surface of the base substrate 11 is preferably the same as in the first embodiment (010) to increase the thermal conductivity of the base substrate 11 in the thickness direction.

[0272] As in Fig. As shown in 32C, the epitaxial layer 12 is subsequently formed on the base substrate 11.

[0273] The process for forming this epitaxial layer 12 is the same as the process for forming the epitaxial layer 12 in the first embodiment.

[0274] As in Fig. As shown in Figure 32D, the anode electrode 14 is subsequently formed on a surface of the epitaxial layer 12 on the side opposite the base substrate 11. The process for forming this anode electrode 14 is the same as the process for forming the anode electrode 14 in the first embodiment.

[0275] As in Fig. As shown in Figure 32E, the cathode electrode 13 is subsequently formed on a surface of the support substrate 15 on the side opposite the base substrate 11. The process for forming the cathode electrode 13 is the same as the process for forming the cathode electrode 13 in the first embodiment.

[0276] The method for manufacturing the semiconductor element in the ninth embodiment is applicable to a manufacturer of a semiconductor element having a dilute base substrate formed from a Ga2O3-based crystal, such as a vertical transistor or lateral transistor. [Tenth embodiment]

[0277] The tenth embodiment is a vertical semiconductor element implemented as a vertical transistor having a MISFET structure. (Structure of the semiconductor element)

[0278] Fig. Figure 33 is a vertical cross-sectional view showing a vertical transistor 100 in the tenth embodiment. The vertical transistor 100 is equipped with an ion-implanted layer 101 formed on a surface of the epitaxial layer 22, with the gate electrode 23 covered with the gate insulating film 24 and embedded in the epitaxial layer 22, with the contact areas 25 formed in the epitaxial layer 22 such that they are located on both sides of the gate electrode 23, with the p +-areas 28, which are formed on respective sides of the contact areas 25, are provided with the source electrode 26, which is formed on the epitaxial layer 22 and is connected to the contact areas 25, and with the drain electrode 27, which is formed on the lower surface of the epitaxial layer 22 (a surface on which the ion-implanted layer 101 is provided) and is in ohmic contact with the ion-implanted layer 101.

[0279] The vertical transistor 100 is a vertical semiconductor device in which the source electrode 26 and the drain electrode 27 are arranged on top of and below the device, respectively, and a current flows in a vertical direction. When a voltage not less than the threshold value is applied to the gate electrode 23, channels are formed in the epitaxial layer 22 in regions on both sides of the gate electrode 23, allowing a current to flow from the source electrode 26 to the drain electrode 27.

[0280] The epitaxial layer 22, the gate electrode 23, the gate insulating film 24, the contact area 25, the source electrode 26, the drain electrode 27 and the p + -Area 28 are the same as those used in the second embodiment.

[0281] The ion-implanted layer 101 is a layer formed by implanting a high dose of an n-doping agent into layer 22a of the epitaxial layer 22 and has a higher concentration of the n-doping agent than layer 22a. Preferably, the n-doping agent is a group IV element such as Si or Sn. To reduce the conduction loss of the Schottky diode, it is particularly preferred to use Si as an n-doping agent, since the activation rate of Si, when implanted with a high dose, is higher than that of Sn.

[0282] In the vertical transistor 100, a base substrate, which serves as a foundation for the epitaxy of the epitaxial layer 22 (e.g., the base substrate 21 described later), is removed, and the ion-implanted layer 101 is used as the layer intended to be in ohmic contact with the drain electrode 27. Thus, a heat dissipation path to the ion-implanted layer 101 does not pass through the base substrate, and the heat is efficiently dissipated. Therefore, the vertical transistor 100 exhibits excellent heat dissipation. Furthermore, the use of the ion implantation technique can achieve a higher donor concentration than a method in which impurities are added during substrate growth, resulting in a reduction of the conduction loss of the Schottky diode.

[0283] Since the epitaxial layer 22 is formed from a Ga2O3-based crystal exhibiting a high breakdown field strength, a reduction in the voltage withstand capability of the vertical transistor 100 can be prevented even after the removal of the base substrate 21. Thus, the vertical transistor 100 exhibits both high heat dissipation and high voltage withstand capability.

[0284] The following describes, along with a specific example, a method for manufacturing the vertical transistor 100 in its tenth embodiment. However, the method for manufacturing the vertical transistor 100 is not limited to the example described below. (Semiconductor element manufacturing process)

[0285] The Fig. Figures 34A to 34D and 35A to 35D are vertical cross-sectional views showing an exemplary process of manufacturing the vertical transistor 100 in the tenth embodiment.

[0286] As in Fig. As shown in Figure 34A, the epitaxial layer 22 is first formed on the base substrate 21.

[0287] The base substrate 21 is the same substrate as the base substrate 11 in the first embodiment and has a thickness of, for example, 600 µm before polishing. The base substrate 21 may not contain an n-doping agent. The process for forming this epitaxial layer 22 is the same as the process for forming the epitaxial layer 22 in the second embodiment.

[0288] As in Fig. As shown in Figure 34B, layer 22a of the epitaxial layer 22 is subsequently attached to the support substrate 15 via the adhesive layer 16. The material used for the support substrate 15 here is, for example, metal, resin, or ceramic, etc., but is not limited to this. The adhesive layer 16 is the same as the one used in the first embodiment.

[0289] As in Fig. As shown in Figure 34C, the thickness of the base substrate 21 supported by the support substrate 15 is subsequently reduced by polishing and finally removed by further continuous polishing.

[0290] Polishing can be combined with another process such as etching, or a different process can be used instead of polishing.

[0291] As in Fig. As shown in Figure 34D, ions of an n-doping agent are subsequently implanted into the lower surface of layer 22a of the epitaxial layer 22.

[0292] As in Fig. As shown in Figure 35A, the n-doping agent implanted in layer 22a is subsequently activated by annealing, thereby forming the ion-implanted layer 101. The annealing is carried out, for example, for 30 minutes in an inert atmosphere at 800 to 1000 °C.

[0293] As in Fig. As shown in Figure 35B, a support substrate 102 is subsequently attached to the lower surface of layer 22a (a surface on which the ion-implanted layer 101 is formed). The material used for the support substrate 102 here is, for example, metal, resin, or ceramic, etc., but is not limited to these.

[0294] Layer 22a is attached to the support substrate 102 using a solder (e.g. Au-Sn, Sn-Ag-Cu or Si-Ge), an Ag paste, a resin or an inorganic material, etc.

[0295] As in Fig. As shown in Figure 35C, the epitaxial layer 22, supported by the support substrate 102, is subsequently separated from the support substrate 15 and the adhesive layer 16. Then, the gate electrode 23, the gate insulating film 24, the contact areas 25, and the p are inserted into the epitaxial layer 22. + -areas 28 are formed. Subsequently, the source electrode 26 is formed on the epitaxial layer 22. Furthermore, an electrode termination structure or a passivation film may be provided on the epitaxial layer 22.

[0296] The processes for forming the gate electrode 23, the gate insulating film 24, the contact areas 25, the p + -areas 28 and the source electrode 26 are, in this order, the same as the processes for forming the gate electrode 23, the gate insulating film 24, the contact areas 25, the p + -areas 28 and the source electrode 26 in the second embodiment.

[0297] As in Fig.As shown in Figure 35D, a support substrate 103, which has an electrode 104 on one side, is prepared, and the epitaxial layer 22 is attached to the support substrate 103 by bonding the source electrode 26 to the electrode 104. Subsequently, the epitaxial layer 22, supported by the support substrate 103, is separated from the support substrate 102, and the drain electrode 27 is formed on the lower surface of layer 22a. The material of the support substrate 103 is not specifically limited. However, if the support substrate 103 is retained as a support substrate for the vertical transistor 100 as described later, it is preferably made of a material that has a higher thermal conductivity than β-Ga₂O₃, e.g., β-Ga₂O₃. B. from a metal such as Al, from a nitride such as AlN, SiN or GaN, from an oxide such as SiO2 or Al2O3 or from SiC, Si, GaAs or from diamond, etc.

[0298] The process for forming this drain electrode 27 is the same as the process for forming the drain electrode 27 in the first embodiment.

[0299] The support substrate 103 can be retained as a support substrate for the completed vertical transistor 100. In this case, external power can be supplied to the source electrode 26 via the electrode 104 of the support substrate 103. If the support substrate 103 is electrically conductive, external power can be supplied to the source electrode 26 via the support substrate 103 and the electrode 104. Alternatively, the vertical transistor 100 can be separated from the support substrate 101 and then attached to a different support substrate. (Effects of the embodiments)

[0300] In the first to tenth embodiments, it is possible to effectively dissipate heat by reducing the thickness of the base substrate, by removing the base substrate and subsequently forming the ion-implanted layer, or by removing the base substrate and attaching the highly thermally conductive substrate. As a result, the heat dissipation properties of the semiconductor element are improved. [List of reference symbols] 10, 40, 60, 90 SCHOTTKY DIODE 11, 21, 31, 81 BASIC SUBSTANCE 12, 22, 32, 42, 62, 72, 82 EPITAXIC LAYER 20, 70, 80, 100 VERTICAL TRANSISTOR 30 LATERAL TRANSISTOR 41, 101 ION IMPLANTED LAYER 15, 46, 51, 52 SUPPORT SUBSTRATE 61, 71 HIGHLY THERMALLY CONDUCTIVITATE

Claims

[1] Semiconductor element (10, 20, 30) comprising: a base substrate (11, 21, 31) comprising a Ga2O3-based crystal having a thickness of not less than 0.05 µm and not more than 50 µm; an epitaxial layer (12, 22, 32) comprising a Ga2O3-based crystal formed on the substrate (11, 21, 31), and a support substrate (17, 37, 52) formed from a material with higher thermal conductivity than the Ga2O3-based crystal and attached to a lower surface of the base substrate (11, 21, 31), and / or a support substrate (15, 51) formed from a material with higher thermal conductivity than the Ga2O3-based crystal and attached to an upper surface of the epitaxial layer (12, 22, 32). [2] Semiconductor element according to claim 1, wherein the thickness of the base substrate (11, 21, 31) is less than 10 µm. [3] Semiconductor element according to claim 1 or 2, wherein a plane orientation of a main surface of the base substrate (11, 21, 31) is (010). [4] Semiconductor element according to claim 1 or 2, wherein the semiconductor element is a vertical element (10, 20) in which the base substrate (11, 21) and the epitaxial layer (12, 22) provide a current path. [5] Semiconductor element according to claim 1 or 2, wherein the semiconductor element is a lateral element (30) in which the base substrate (31) does not provide a current path. [6] Semiconductor element according to claim 1 or 2, wherein the base substrate (11, 21, 31) and the epitaxial layer (12, 22, 32) are each attached to the support substrates (51, 52). [7] Semiconductor element (40) comprising: an epitaxial layer (42) comprising a Ga2O3-based crystal containing an n-doping agent; an ion implantation layer (41) formed on a surface of the epitaxial layer (42) and containing a higher concentration of the n-doping agent than the epitaxial layer (42); an anode electrode (44) which is connected to the epitaxial layer (42); a cathode electrode (43) connected to the ion implantation layer (41); and a support substrate (47, 52) formed from a material with higher thermal conductivity than the Ga2O3-based crystal and attached to a lower surface of the ion implantation layer (41) by the cathode electrode (43). [8] Semiconductor element according to claim 7, wherein the epitaxial layer (42) anode electrode (44) is attached to a further supporting substrate (51) via the [9] Method for manufacturing a semiconductor device (10, 20, 30), the method comprising: Formation of an epitaxial layer (12, 22, 32) by epitaxial growth of a Ga2O3-based crystal on a substrate (11, 21, 31) comprising a Ga2O3-based crystal; and Reducing the thickness of the base substrate (11, 21, 31) to not less than 0.05 µm and not more than 50 µm, wherein the thickness of the base substrate (11, 21, 31) is reduced while the epitaxial layer is attached to a support substrate (15). [10] Method for producing a semiconductor element according to claim 9, wherein the thickness of the base substrate (11, 21, 31) is reduced to less than 10 µm. [11] Method for producing a semiconductor element according to claim 9, wherein the thickness of the base substrate (11, 21, 31) is reduced by polishing. [12] Method for producing a semiconductor element according to claim 9 or 10, wherein the thickness of the base substrate (11, 21, 31) is reduced by polishing and etching after polishing. [13] Method for producing a semiconductor element (40), comprising: Formation of an epitaxial layer (42) including an n-doping agent by epitaxial growth of a Ga2O3-based crystal on a substrate (45); and Reducing the thickness of the base substrate (45) while the epitaxial layer is attached to a support substrate (15), wherein ions of an n-doping agent are implanted into a surface of the epitaxial layer (42) on one side on which the base substrate (45) is located, after the thickness of the base substrate has been reduced and it has finally been removed, so that an ion implantation layer (41) is formed on the surface which contains a higher concentration of the n-doping agent than the epitaxial layer (42). [14] Semiconductor substrate (11, 21, 31) comprising a Ga2O3-based crystal, wherein the semiconductor substrate (11, 21, 31) has a thickness of not less than 0.05 µm and not more than 50 µm, and wherein the semiconductor substrate (11, 21, 31) is attached to a support substrate (17, 37) having a higher thermal conductivity than the Ga2O3-based crystal. [15] Semiconductor substrate according to claim 14, wherein a plane orientation of a major surface thereof is (010). [16] . Crystal layer structure comprising: a base substrate (11, 21, 31) comprising a Ga2O3-based crystal having a thickness of not less than 0.05 µm and not more than 50 µm; an epitaxial layer (12, 22, 32) comprising a Ga2O3-based crystal formed on the substrate (11, 21, 31), and a support substrate (17, 37, 52) formed from a material with higher thermal conductivity than the Ga2O3-based crystal and attached to a lower surface of the base substrate (11, 21, 31), and / or a support substrate (15, 51) formed from a material with higher thermal conductivity than the Ga2O3-based crystal and attached to an upper surface of the epitaxial layer (12, 22, 32). [17] Crystal layer structure according to claim 16, wherein the thickness of the base substrate (11, 21, 31) is less than 10 µm. [18] Crystal layer structure according to claim 16 or 17, wherein a plane orientation of a main surface of the base substrate (11, 21, 31) is (010).

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