Display plate and display device

Abstract

Display panel, including: a plurality of pixel driver circuits (10) arranged in an array; a plurality of first scanning signal lines (11), wherein the plurality of first scanning signal lines (11) are electrically connected to the plurality of pixel driver circuits (10) and are configured to provide first scanning signals (scan1) to the plurality of pixel driver circuits (10); a plurality of shift register units (12), wherein the plurality of shift register units (12) are cascaded, each electrically connected to the plurality of first sampling signal lines (11) and configured to output the first sampling signals (scan1) to the plurality of first sampling signal lines (11), wherein voltages of a first sampling signal (scan1) of the first sampling signals (scan1) comprise a turn-on voltage (V11) and a turn-off voltage (V12); a plurality of modulation transistors (13), wherein a first terminal (131) of a modulation transistor (13) of the plurality of modulation transistors (13) is electrically connected to a first sampling signal line (11) of the plurality of first sampling signal lines (11); a plurality of modulation voltage signal lines (14), wherein one modulation voltage signal line (14) of the plurality of Modulation voltage signal lines (14) are electrically connected to a second terminal (132) of the modulation transistor (13) and are configured to provide a modulation voltage to the second terminal (132) of the modulation transistor (13); and a plurality of modulation control signal lines (15), wherein a The modulation control signal line (15) of the plurality of modulation control signal lines (15) is electrically connected to a gate of the modulation transistor (13) and is configured, to provide a modulation control signal (K0) to the gate of the modulation transistor (13), and the modulation control signal (K0) includes a valid pulse, and the valid pulse is configured to control the modulation transistor (13) to turn on, wherein a switching stage (T0) between the turn-on voltage (V11) of the first sampling signal (scan1) and the turn-off voltage (V12) of the first sampling signal (scan1) overlaps with the valid pulse (K01) of the modulation control signal (K0).

Description

TECHNICAL AREA

[0001] The present disclosure relates to the field of display technologies and in particular to a display plate and a display device. BACKGROUND

[0002] With the continuous development of display technologies, consumers have placed higher demands on the visual experience of display panels. High resolution, large size, and high refresh rates have become important development trends for modern display panels.

[0003] However, as the size and resolution of the display panels increase, uneven display brightness is more likely to occur, which negatively affects the display quality. SUMMARY

[0004] The present disclosure provides a display plate and a display device.

[0005] According to one aspect of the present disclosure, a display board is provided. The display board comprises several pixel driver circuits, several first sampling signal lines, several shift register units, several modulation transistors, several modulation voltage signal lines, and several modulation control signal lines.

[0006] The multiple pixel driver circuits are arranged in an array.

[0007] The multiple first sampling signal lines are electrically connected to the multiple pixel driver circuits and configured to provide first sampling signals to the multiple pixel driver circuits.

[0008] The multiple shift register units are cascaded, each electrically connected to the multiple first sampling signal lines and configured to output the first sampling signals to the multiple first sampling signal lines, wherein the voltages of a first sampling signal of the first sampling signals include a turn-on voltage and a turn-off voltage.

[0009] The first terminal of one of several modulation transistors is electrically connected to the first of several first sampling signal lines.

[0010] One of the multiple modulation voltage signal lines is electrically connected to a second terminal of the modulation transistor and is configured to provide a modulation voltage to the second terminal of the modulation transistor.

[0011] One of the multiple modulation control signal lines is electrically connected to a gate of the modulation transistor and is configured to provide a modulation control signal to the gate of the modulation transistor, wherein the modulation control signal includes a valid pulse, and the valid pulse is configured to control the modulation transistor to turn on.

[0012] A switching stage between the turn-on voltage of the first sampling signal and the turn-off voltage of the first sampling signal overlaps with the valid pulse of the modulation control signal.

[0013] In one or more embodiments, the switch-on voltage is higher than the switch-off voltage; and The modulation voltage is lower than the turn-on voltage.

[0014] In one or more embodiments, the switch-on voltage is lower than the switch-off voltage; and The modulation voltage is higher than the turn-on voltage.

[0015] In one or more embodiments, the display plate further comprises a first voltage signal line and a second voltage signal line; A shift register unit of several shift register units comprises a first transistor and a second transistor; A first terminal of the first transistor is electrically connected to the first voltage signal line, a second terminal of the first transistor is electrically connected to the first sampling signal line, and the first transistor is configured to provide a first voltage on the first voltage signal line of the first sampling signal line; a first terminal of the second transistor is electrically connected to the second voltage signal line, a second terminal of the second transistor is electrically connected to the first sampling signal line, and the second transistor is configured to provide a second voltage on the second voltage signal line of the first sampling signal line; The first voltage is higher than the second voltage; The multiple modulation voltage signal lines include a first modulation voltage signal line; The first modulation voltage signal line is electrically connected to the first voltage signal line, and the modulation voltage is identical to the first voltage; or The first modulation voltage signal line is electrically connected to the second voltage signal line, and the modulation voltage is identical to the second voltage.

[0016] In one or more embodiments, the display plate further comprises several light-emitting elements arranged in an array, and the several light-emitting elements are electrically connected to the several pixel driver circuits;

[0017] The display plate also includes several first power voltage signal lines and several second power voltage signal lines; A pixel driver circuit of the multiple pixel driver circuits comprises a driver transistor, and the driver transistor and a light-emitting element of the multiple light-emitting elements are connected in series between a first power voltage signal line of the multiple first power voltage signal lines and a second power voltage signal line of the multiple second power voltage signal lines; A first power voltage transmitted through the first power voltage signal line is higher than a second power voltage transmitted through the second power voltage signal line; The multiple modulation voltage signal lines include a second modulation voltage signal line; The second modulation voltage signal line is the same signal line as the first power voltage signal line, and the modulation voltage is identical to the first power voltage; or The second modulation voltage signal line is the same signal line as the second power voltage signal line, and the modulation voltage is identical to the second power voltage.

[0018] In one or more embodiments, the display plate further comprises several light-emitting elements arranged in an array, and the several light-emitting elements are electrically connected to the several pixel driver circuits; A pixel driver circuit of the multiple pixel driver circuits comprises a driver transistor, a first switching transistor and a second switching transistor, and the driver transistor and a light-emitting element of the multiple light-emitting elements are connected in series between a first power voltage signal line of the multiple first power voltage signal lines and a second power voltage signal line of the multiple second power voltage signal lines; A gate of the driver transistor is electrically connected to a first terminal of the first switch transistor, a second terminal of the first switch transistor is electrically connected to one of the data signal lines, and a gate of the first switch transistor is electrically connected to the first sample signal line; A first terminal of the second switching transistor is electrically connected to a first terminal of the driver transistor, a second terminal of the second switching transistor is electrically connected to one of the reference voltage signal lines, and a gate of the second switching transistor is electrically connected to one of the second of the several second sample signal lines; and The multiple modulation voltage signal lines include multiple third modulation voltage signal lines, and one third modulation voltage signal line of the multiple third modulation voltage signal lines is the same signal line as the reference voltage signal line to provide the modulation voltage to the modulation transistor via the reference voltage signal line.

[0019] In one or more embodiments, the pixel driver circuit has a light emission stage in which the first switching transistor and the second switching transistor are switched off; In a control stage of the second switch transistor, a reference voltage is transmitted on the reference voltage signal line; In the light emission stage, the modulation voltage is transmitted on the reference voltage signal line; and The reference voltage differs from the modulation voltage.

[0020] In one or more embodiments, the display plate further comprises a first clock signal line and a second clock signal line; The first clock signal line is electrically connected to the multiple shift register units and is configured to provide a first clock signal to the multiple shift register units; The second clock signal line is electrically connected to the multiple shift register units and is configured to provide a second clock signal to the multiple shift register units; The first clock signal and the second clock signal are inverted relative to each other; The multiple modulation control signal lines include a first modulation control signal line; The first modulation control signal line is electrically connected to the first clock signal line, and the modulation control signal is identical to the first clock signal; or The first modulation control signal line is electrically connected to the second clock signal line, and the modulation control signal is identical to the second clock signal.

[0021] In one or more embodiments, the display plate includes a display area; The multiple modulation control signal lines further include multiple secondary modulation control signal lines, which are located at least partially within the display area; and The direction of extension of the multiple second modulation control signal lines is the same as the direction of extension of the multiple first sampling signal lines.

[0022] In one or more embodiments, the display plate further comprises several modulation control signal generation units; An input terminal of one of the multiple modulation control signal generation units is electrically connected to the first sampling signal line to receive the first sampling signal; An output terminal of the modulation control signal generation unit is electrically connected to one of the several second modulation control signal lines; and The modulation control signal generation unit is set up to provide the modulation control signal to the second modulation control signal line.

[0023] In one or more embodiments, the display plate further comprises a non-display area located on at least one side of the display area; The non-display area comprises a first non-display area and a second non-display area, each located on two opposite sides of the display area; The display plate also includes several modulation control signal generation units; An output terminal of one of several modulation control signal generation units is electrically connected to a second modulation control signal line of the several second modulation control signal lines; The modulation control signal generation unit is set up to provide the modulation control signal to the second modulation control signal line; The multiple shift register units are arranged in the first non-display area; and The multiple modulation control signal generation units are located in the second non-display area.

[0024] In one or more embodiments, the start time of the valid pulse of the modulation control signal is identical to the start time of the switching stage of the first sampling signal.

[0025] In one or more embodiments, the pulse width of the valid pulse of the modulation control signal is shorter than the duration of the switch-off voltage of the first sampling signal.

[0026] In one or more embodiments, the display plate further comprises several light-emitting elements arranged in an array, and the several light-emitting elements are electrically connected to the several pixel driver circuits; A pixel driver circuit of the multiple pixel driver circuits comprises a driver transistor, a first switching transistor and a second switching transistor, and the driver transistor and a light-emitting element of the multiple light-emitting elements are connected in series between a first power voltage signal line of the multiple first power voltage signal lines and a second power voltage signal line of the multiple second power voltage signal lines; A gate of the driver transistor is electrically connected to a first terminal of the first switch transistor, a second terminal of the first switch transistor is electrically connected to one of the data signal lines, and a gate of the first switch transistor is electrically connected to the first sample signal line; A first terminal of the second switching transistor is electrically connected to a first terminal of the driver transistor, a second terminal of the second switching transistor is electrically connected to one of the reference voltage signal lines, and a gate of the second switching transistor is electrically connected to one of the second of the several second sample signal lines; and The pixel driver circuit has a light emission stage in which the first switch transistor and the second switch transistor are switched off; and The pulse width of the valid pulse of the modulation control signal is shorter than the duration of the light emission stage.

[0027] In one or more embodiments, the display plate further comprises a display area and a non-display area located on at least one side of the display area; The multiple modulation transistors comprise multiple first modulation transistors, and the multiple first modulation transistors are arranged within the non-display area; and One shift register unit of the multiple shift register units is connected to a first end of the first sampling signal line, and one first modulation transistor of the multiple first modulation transistors is connected to a second end of the first sampling signal line.

[0028] In one or more embodiments, the display plate further comprises several light-emitting elements arranged in an array, and the several light-emitting elements are electrically connected to the several pixel driver circuits; A pixel driver circuit of the multiple pixel driver circuits comprises a driver transistor and a first switching transistor, and the driver transistor and a light-emitting element of the multiple light-emitting elements are connected in series between a first power voltage signal line of the multiple first power voltage signal lines and a second power voltage signal line of the multiple second power voltage signal lines; A gate of the driver transistor is electrically connected to a first terminal of the first switch transistor, a second terminal of the first switch transistor is electrically connected to one of the data signal lines, and a gate of the first switch transistor is electrically connected to the first sample signal line; and The channel width-to-channel length ratio of the first modulation transistor is greater than or equal to the channel width-to-channel length ratio of the first switching transistor.

[0029] In one or more embodiments, the display plate further comprises a display area; and The multiple modulation transistors include multiple second modulation transistors, and the multiple second modulation transistors are arranged in the display area.

[0030] In one or more embodiments, the first sampling signal line is connected to a second modulation transistor or several second modulation transistors; One of the multiple shift register units is connected to a first end of the first sampling signal line; and The length of the first sampling signal line is L1, and the distance between the second modulation transistor and a second end of the first sampling signal line is D1, where D1 ≤ L1 / 3.

[0031] In one or more embodiments, the first sampling signal line is connected to N second modulation transistors of the multiple second modulation transistors, where N ≥ 2; One of the multiple shift register units is connected to a first end of the first sampling signal line; and The length of the first sampling signal line is L1, and the distance between a second end of the first sampling signal line and a second modulation transistor of the N second modulation transistors that is closest to the second end of the first sampling signal line is D2, where D2 ≤ L1 / (N + 1).

[0032] In one or more embodiments, the first sampling signal line is connected to N second modulation transistors of the multiple second modulation transistors, where N ≥ 2, and the N second modulation transistors are arranged uniformly along one extension direction of the first sampling signal line.

[0033] In one or more embodiments, the display plate further comprises a non-display area located on at least one side of the display area; The non-display area comprises a first non-display area located on one side of the display area, and the multiple shift register units are arranged in the first non-display area; The display area comprises a first display area and a second display area, wherein the first display area and the second display area are arranged along a direction of extension of the first scanning signal line, and the first display area is located on a side of the second display area that faces the first non-display area; and The first sampling signal line is connected to N second modulation transistors of the multiple second modulation transistors, where N ≥ 2, and among the N second modulation transistors, the distribution density of second modulation transistors in the first display area is less than the distribution density of second modulation transistors in the second display area.

[0034] In one or more embodiments, the display plate further comprises a non-display area located on at least one side of the display area; The non-display area comprises a first non-display area and a second non-display area, each located on two opposite sides of the display area; The multiple shift register units comprise multiple cascaded first shift register units and multiple cascaded second shift register units; The multiple first shift register units are arranged in the first non-display area, and the multiple second shift register units are arranged in the second non-display area; The display area comprises a first display area, a second display area and a third display area, wherein the first display area, the second display area and the third display area are arranged along an extension direction of the first scanning signal line and the second display area is arranged between the first display area and the third display area; the first sampling signal line is connected to N of the multiple second modulation transistors, where N ≥ 2; and Among the N second modulation transistors, the distribution density of second modulation transistors in the second display area is greater than the distribution density of second modulation transistors in the first display area and the distribution density of second modulation transistors in the third display area.

[0035] In one or more embodiments, the number of pixel driver circuits of the multiple pixel driver circuits connected to the first sampling signal line is equal to the number of second modulation transistors of the multiple second modulation transistors connected to the first sampling signal line.

[0036] In one or more embodiments, the display plate further comprises several light-emitting elements arranged in an array, and the several light-emitting elements are electrically connected to the several pixel driver circuits; A pixel driver circuit of the multiple pixel driver circuits comprises a driver transistor and a first switching transistor, and the driver transistor and a light-emitting element of the multiple light-emitting elements are connected in series between a first power voltage signal line of the multiple first power voltage signal lines and a second power voltage signal line of the multiple second power voltage signal lines.

[0037] A gate of the driver transistor is electrically connected to a first terminal of the first switch transistor, a second terminal of the first switch transistor is electrically connected to one of the data signal lines, and a gate of the first switch transistor is electrically connected to the first sample signal line; and The channel width-to-channel length ratio of a second modulation transistor of the multiple second modulation transistors is less than or equal to the channel width-to-channel length ratio of the first switching transistor.

[0038] In one or more embodiments, the first sampling signal line is connected to at least two of the second modulation transistors of the multiple second modulation transistors; at least two second modulation transistors connected to the same first sampling signal line of the multiple first sampling signal lines comprise a second nearby modulation transistor and a second distant modulation transistor; The distance between the second nearest modulation transistor and a shift register unit of the multiple shift register units is smaller than the distance between the second furthest modulation transistor and the shift register unit; and The channel width-to-channel length ratio of the second nearby modulation transistor is smaller than the channel width-to-channel length ratio of the second distant modulation transistor.

[0039] In one or more embodiments, the display plate further comprises a base substrate and several light-emitting elements located on one side of the base substrate, and drive electrodes of the several light-emitting elements are electrically connected to the several pixel driver circuits; and Perpendicular projections of the multiple second modulation transistors onto the base substrate do not overlap with perpendicular projections of the drive electrodes of the multiple light-emitting elements onto the base substrate.

[0040] In one or more embodiments, the display plate further comprises a display area and a non-display area located on at least one side of the display area; The multiple modulation transistors include multiple first modulation transistors and multiple second modulation transistors; The several first modulation transistors are arranged within the non-display area, and the several second modulation transistors are arranged within the display area; and A channel width-to-channel length ratio of a first modulation transistor of the several first modulation transistors is greater than or equal to a channel width-to-channel length ratio of a second modulation transistor of the several second modulation transistors.

[0041] In one or more embodiments, the multiple modulation transistors and the transistors in the multiple pixel driver circuits are all n-type transistors or p-type transistors.

[0042] In one or more embodiments, the display plate further comprises several light-emitting elements arranged in an array, and the several light-emitting elements are electrically connected to the several pixel driver circuits; A pixel driver circuit of the multiple pixel driver circuits comprises a driver transistor, and the driver transistor and a light-emitting element of the multiple light-emitting elements are connected in series between a first power voltage signal line of the multiple first power voltage signal lines and a second power voltage signal line of the multiple second power voltage signal lines; and At least one of the modulation transistor or the driver transistor is a dual-port transistor.

[0043] In one or more embodiments, the multiple pixel driver circuits arranged in an array further comprise multiple pixel driver circuit rows arranged in a column direction; A pixel driver circuit line of several pixel driver circuit lines comprises several pixel driver circuit groups arranged in the line direction; A pixel driver circuit group of several pixel driver circuit groups comprises two adjacent pixel driver circuits along the row direction, which are referred to as the first pixel driver circuit and the second pixel driver circuit; and In the same pixel driver circuit group of the multiple pixel driver circuit groups, the first pixel driver circuit and the second pixel driver circuit are connected to the same data signal line of the multiple data signal lines and to different first sampling signal lines of the multiple first sampling signal lines.

[0044] In one or more embodiments, the display plate further comprises several light-emitting elements arranged in an array, and the several light-emitting elements are electrically connected to the several pixel driver circuits; A pixel driver circuit of the multiple pixel driver circuits comprises a driver transistor, a first switching transistor and a second switching transistor, and the driver transistor and a light-emitting element of the multiple light-emitting elements are connected in series between a first power voltage signal line of the multiple first power voltage signal lines and a second power voltage signal line of the multiple second power voltage signal lines; A gate of the driver transistor is electrically connected to a first terminal of the first switch transistor, a second terminal of the first switch transistor is electrically connected to one of the data signal lines, and a gate of the first switch transistor is electrically connected to the first sample signal line; A first terminal of the second switching transistor is electrically connected to a first terminal of the driver transistor, a second terminal of the second switching transistor is electrically connected to one of the reference voltage signal lines, and a gate of the second switching transistor is electrically connected to one of the second of the several second sample signal lines; and The first sampling signal line is the same line as, or a different line than, the second sampling signal line.

[0045] According to another aspect of the present disclosure, a display device is provided. The display device comprises the display plate according to the first aspect.

[0046] It should be understood that the content described in this section is neither intended to identify essential or decisive features of the embodiments of the present disclosure, nor is it intended to limit the scope of protection of the present disclosure. Further features of the present disclosure will be readily understood from the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] To more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings used in the description of the embodiments are briefly described below. Obviously, the drawings described below show some embodiments of the present disclosure, and those skilled in the art can obtain further drawings based on the drawings described below, provided that no inventive step is required. Fig. Figure 1 is a diagram illustrating the structure of a display plate according to an embodiment of the present disclosure. Fig. 2 is a cross-sectional view along AA' of Fig. 1. Fig. Figure 3 is a diagram illustrating the structure of a pixel driver circuit according to an embodiment of the present disclosure. Fig. Figure 4 is a diagram of a first sampling signal according to an embodiment of the present disclosure. Fig. Figure 5 is another diagram of a first sampling signal according to an embodiment of the present disclosure. Fig. Figure 6 is another diagram of a first sampling signal according to an embodiment of the present disclosure. Fig. Figure 7 is another diagram of a first sampling signal according to an embodiment of the present disclosure. Fig. Figure 8 is another diagram of a first sampling signal according to an embodiment of the present disclosure. Fig. Figure 9 is a diagram illustrating the structure of a shift register unit according to an embodiment of the present disclosure. Fig. Figure 10 is another diagram illustrating the structure of a display plate according to an embodiment of the present disclosure. Fig. Figure 11 is another diagram illustrating the structure of a display plate according to an embodiment of the present disclosure. Fig. Figure 12 is another diagram illustrating the structure of a display plate according to an embodiment of the present disclosure. Fig. Figure 13 is another diagram illustrating the structure of a display plate according to an embodiment of the present disclosure. Fig. Figure 14 is an operating timing diagram of a pixel driver circuit according to an embodiment of the present disclosure. Fig. Figure 15 is another diagram illustrating the structure of a display plate according to an embodiment of the present disclosure. Fig. Figure 16 is an operating timing diagram of a shift register unit according to an embodiment of the present disclosure. Fig. Figure 17 is another diagram illustrating the structure of a display plate according to an embodiment of the present disclosure. Fig. Figure 18 is another diagram illustrating the structure of a display plate according to an embodiment of the present disclosure. Fig. Figure 19 is another diagram illustrating the structure of a display plate according to an embodiment of the present disclosure. Fig. Figure 20 is another diagram illustrating the structure of a display plate according to an embodiment of the present disclosure. Fig. Figure 21 is another diagram illustrating the structure of a display plate according to an embodiment of the present disclosure. Fig. Figure 22 is another operating timing diagram of a pixel driver circuit according to an embodiment of the present disclosure. Fig. Figure 23 is another diagram illustrating the structure of a display plate according to an embodiment of the present disclosure. Fig. Figure 24 is another diagram illustrating the structure of a display plate according to an embodiment of the present disclosure. Fig. Figure 25 is another diagram illustrating the structure of a display plate according to an embodiment of the present disclosure. Fig. Figure 26 is another diagram illustrating the structure of a display plate according to an embodiment of the present disclosure. Fig. Figure 27 is another diagram illustrating the structure of a display plate according to an embodiment of the present disclosure. Fig. Figure 28 is another diagram illustrating the structure of a display plate according to an embodiment of the present disclosure. Fig. Figure 29 is another diagram illustrating the structure of a display plate according to an embodiment of the present disclosure. Fig. Figure 30 is another diagram illustrating the structure of a display plate according to an embodiment of the present disclosure. Fig. Figure 31 is a partial cross-sectional diagram of a display plate according to an embodiment of the present disclosure. Fig. Figure 32 is another diagram illustrating the structure of a display plate according to an embodiment of the present disclosure. Fig. Figure 33 is a partial cross-sectional diagram of a display plate according to an embodiment of the present disclosure. Fig. Figure 34 is another diagram illustrating the structure of a pixel driver circuit according to an embodiment of the present disclosure. Fig. Figure 35 is another operating timing diagram of a pixel driver circuit according to an embodiment of the present disclosure. Fig. Figure 36 is a diagram illustrating the layer structure of a pixel driver circuit in a display panel according to an embodiment of the present disclosure. Fig. 37 is a diagram showing the structure of a first metal layer in the Fig. 36 pixel driver circuits are illustrated. Fig. 38 is a diagram showing the structure of a second metal layer in the Fig. 36 pixel driver circuits are illustrated. Fig. 39 is a diagram showing the structure of a third metal layer in the Fig. 36 pixel driver circuits are illustrated. Fig. 40 is a diagram showing the structure of a semiconductor layer in the Fig. 36 pixel driver circuits are illustrated. Fig. 41 is a diagram showing the structure of a fourth metal layer in the Fig. 36 pixel driver circuits are illustrated. Fig. 42 is a diagram showing the structure of a fifth metal layer in the Fig. 36 pixel driver circuits are illustrated. Fig. 43 is a diagram showing the structure of a sixth metal layer in the Fig. 36 pixel driver circuits are illustrated. Fig. 44 is a diagram that shows the stacked structure of layers in the Fig. 36 pixel driver circuits are illustrated. Fig. Figure 45 is a diagram illustrating the structure of a display device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0048] To make the technical solutions of this disclosure more understandable to those skilled in the art, the technical solutions in the embodiments of this disclosure are described clearly and completely below with reference to the drawings in those embodiments. Obviously, the embodiments described below represent some, but not all, embodiments of this disclosure. Based on the embodiments of this disclosure, all further embodiments that arise from the invention by those skilled in the art, provided that no inventive step is required, fall within the scope of protection of this disclosure.

[0049] It should be noted that terms such as "first" and "second" in the description, claims, and foregoing drawings of this disclosure serve to distinguish between similar objects and are not necessarily used to describe a particular order or sequence. It is to be understood that data used in this manner may be interchangeable, so that the embodiments of this disclosure described herein may be implemented in an order not illustrated or described here. Furthermore, the terms "comprehensive," "comprising," or any variations thereof are to be understood as constituting a non-exhaustive list.For example, a process, procedure, system, product or device comprising a series of steps or units may include not only the steps or units expressly listed, but also other steps or units that are not expressly listed or are inherent in such processes, procedures, products or devices.

[0050] Fig. Figure 1 is a diagram illustrating the structure of a display plate according to an embodiment of the present disclosure. Fig. 2 is a cross-sectional view along AA' of Fig. 1. As in Fig. 1 and Fig. As shown in Figure 2, the display plate provided in the embodiment of the present disclosure comprises several pixel driver circuits 10, several first sampling signal lines 11, several shift register units 12, several modulation transistors 13, several modulation voltage signal lines 14 and several modulation control signal lines 15.

[0051] The multiple pixel driver circuits 10 are arranged in an array.

[0052] The multiple first scanning signal lines 11 are electrically connected to the multiple pixel driver circuits 10 and configured to provide first scanning signals scan1 to the multiple pixel driver circuits 10.

[0053] The multiple shift register units 12 are cascaded, each electrically connected to the multiple first sampling signal lines 11 and configured to output the first sampling signals scan1 to the multiple first sampling signal lines 11, wherein voltages of a first sampling signal scan1 include a turn-on voltage V11 and a turn-off voltage V12.

[0054] A first terminal 131 of a modulation transistor 13 is electrically connected to a first sampling signal line 11.

[0055] A modulation voltage signal line 14 is electrically connected to a second terminal 132 of the modulation transistor 13 and is configured to provide a modulation voltage to the second terminal 132 of the modulation transistor 13.

[0056] A modulation control signal line 15 is electrically connected to a gate of the modulation transistor 13 and is configured to provide a modulation control signal K0 to the gate of the modulation transistor, wherein the modulation control signal K0 includes a valid pulse K01, and the valid pulse K01 is configured to control the modulation transistor 13 to turn on.

[0057] A switching stage T0 between the turn-on voltage V11 of the first sampling signal scan1 and the turn-off voltage V12 of the first sampling signal scan1 overlaps with the valid pulse K01 of the modulation control signal K0.

[0058] In one embodiment as in Fig. 1 and Fig. As shown in Figure 2, the multiple pixel driver circuits 10 are arranged in rows and columns and are formed within a display area AA of the display plate. Each pixel driver circuit 10 can be connected to at least one light-emitting element 20, thus forming a sub-pixel of the display plate. The pixel driver circuit 10 is configured to transmit a light-emitting driver current to the at least one light-emitting element 20 under the influence of signals on signal lines (such as scanning signal lines, data signal lines, and power voltage signal lines) of the display plate, thereby exciting this at least one light-emitting element 20 to emit light.

[0059] In some embodiments, the light-emitting element 20 can be, but is not limited to, an organic light-emitting diode (OLED), a micro light-emitting diode (Micro LED), or a mini light-emitting diode (Mini LED).

[0060] In one or more embodiments, as in Fig. As shown in Figure 2, the light-emitting element 20, using the organic light-emitting diode as an example, can comprise an anode 201, a light-emitting layer 202, and a cathode 203, which are stacked. When electrons and holes from the cathode 203 and the anode 201, respectively, are injected into the light-emitting layer 202, excitons are formed in the light-emitting layer 202. These excites light-emitting molecules and causes the light-emitting layer 202 to emit visible light. The light-emitting layer 202 can be made of different materials, so that visible light can be emitted in different colors.

[0061] In some embodiments, the at least one light-emitting element 20 can comprise a red-emitting element, a green-emitting element, and a blue-emitting element to display a colored image. In some further embodiments, the at least one light-emitting element 20 can additionally comprise a white-emitting element and other elements. This is not particularly limited in the embodiments of the present disclosure.

[0062] In some embodiments, such as in Fig. As shown in Figure 2, the pixel driver circuit 10 comprises at least one transistor T. A transistor T can comprise an active layer 1, a gate 2, and source and drain electrodes 3 stacked on one side of a base substrate 100.

[0063] Fig. Figure 3 is a diagram illustrating the structure of a pixel driver circuit according to an embodiment of the present disclosure. As in Fig. As shown in Figure 3, the at least one transistor T comprises, for example, a driver transistor T3. In the pixel driver circuit 10, a light-emitting element 20 and the driver transistor T3 are connected in series between a first power voltage signal line 31 and a second power voltage signal line 32. The first power voltage signal line 31 is configured to transmit a first power voltage PVDD, and the second power voltage signal line 32 is configured to transmit a second power voltage PVEE, where the first power voltage PVDD is greater than the second power voltage PVEE.

[0064] The driver transistor T3 can be switched on according to the potential of its gate, and a driver current generated by switching on the driver transistor T3 is configured to excite the light-emitting element 20 to emit light. The gate potential of the driver transistor T3 can determine the magnitude of the inrush current, so that the brightness of the light-emitting element 20 can be adjusted by controlling the gate voltage of the driver transistor T3, thus achieving grayscale control.

[0065] In some embodiments, such as in Fig. As shown in Figure 1, the multiple first sampling signal lines 11 run parallel in the display plate, for example along the line direction. Each first sampling signal line 11 is connected to a respective row of pixel driver circuits 10, whereby each row of pixel driver circuits 10 can be connected to one or two independent first sampling signal lines 11. Fig. Figure 1 schematically shows an example in which each row of pixel driver circuits 10 is connected to two respective independent first sampling signal lines 11, but this is not limited to this.

[0066] In some embodiments, such as in Fig. As shown in Figure 3, the pixel driver circuit 10 further comprises a first switching transistor T1. The first switching transistor T1 is connected in series between the gate of the driver transistor T3 and a data signal line 16, and a gate of the first switching transistor T1 is electrically connected to the first sampling signal line 11. Based on this, as shown in Figure 3, the following applies: Fig. Figure 1 shows that the gates of the first switching transistors T1 of the same row of pixel driver circuits 10 are all connected to a first sampling signal line 11 corresponding to the respective row of pixel driver circuits 10, so that at least a part of the same row of pixel driver circuits 10 receives a uniform first sampling signal scan1.

[0067] In the pixel driver circuit 10, the first switch transistor T1 serves as a data write switch, and the line state of the first switch transistor T1 is controlled by the first sampling signal scan1, which is transmitted on the first sampling signal line 11.

[0068] The first sampling signal scan1 is a pulse signal generated by a shift register unit 12. As in Fig. As shown in Figure 1, the multiple cascaded shift register units 12 form a gate driver circuit of the display disk, that is, a gate driver-on-array (GOA) circuit, which is arranged in a non-display area NAA along one or two sides of the edge region of the display disk and is configured to generate the first sampling signals scan1 and output them to the multiple first sampling signal lines 11. Each first sampling signal line 11 is connected to a respective shift register unit 12, thereby implementing line-wise sampling control.

[0069] Fig. Figure 4 is a diagram of a first sampling signal according to an embodiment of the present disclosure. As in Fig. As shown in Figure 4, the voltage of the first sampling signal scan1 switches periodically between the switch-on voltage V11 (for example, a high level) and the switch-off voltage V12 (for example, a low level).

[0070] The turn-on voltage V11 refers to a voltage level of the first sampling signal scan1, which is used to turn on a switching transistor (for example, the first switching transistor T1) in the pixel driver circuit 10.

[0071] As in Fig. As shown in Figure 3, when the on-voltage voltage V11 is applied, the first switching transistor T1 is switched on, so that a data signal can be written from the data signal line 16 to the gate of the driver transistor T3 in order to control the conductance of the driver transistor T3 and to determine the magnitude of the driver current flowing to the light-emitting element 20, thereby realizing a grayscale display.

[0072] Furthermore, the turn-off voltage V12 denotes a voltage level of the first sampling signal scan1, which is used to turn off a switching transistor (for example, the first switching transistor T1) in the pixel driver circuit 10.

[0073] As in Fig. As shown in Figure 3, when the switch-off voltage V12 is applied, the first switch transistor T1 is switched off, so that the written data signal is held at the gate of the driver transistor T3 and protected against disturbances that could be caused by subsequent data signal changes on the data signal line 16.

[0074] In practical applications, when the first scanning signal scan1 switches from the turn-on voltage V11 to the turn-off voltage V12, the first switching transistor T1 in the pixel driver circuit 10 must be turned off quickly and reliably. However, through investigations, the inventors discovered that in a large-format display panel (especially one with a single-sided driver architecture), the first scanning signal line 11 typically runs across the entire display area AA along the line direction and thus has a relatively large physical length. The resistance of the first scanning signal line 11 and parasitic capacitances between the first scanning signal line 11 and other lines form a resistive-capacitant (RC) load.This RC load causes the first sampled signal scan1 to experience a significant signal propagation delay and waveform distortion during transmission from the near end (aligned towards the shift register unit 12) of the pixel driver circuit 10 to the far end (aligned away from the shift register unit 12) of the pixel driver circuit 10.

[0075] Fig. Figure 5 is another diagram of a first sampling signal according to an embodiment of the present disclosure. As in Fig. As shown in Figure 5, with increasing transmission distance of the first sample signal, the time required for a distant first sample signal scan1 to decay from the turn-on voltage V11 to the turn-off voltage V12 increases. The switching stage T0 between the turn-on voltage V11 and the turn-off voltage V12 has a slower decay edge and an extended decay time (i.e., the duration of the switching stage T0), which results in the turn-off time of a distant first switch transistor T1 occurring later than that of a nearby first switch transistor T1. This causes a non-uniform spatial distribution of the effective pixel load time and thus a non-uniform display. In one embodiment, under a line-wise sample driver solution, the theoretical data signal write time (i.e., a load window) for each line of sub-pixels is fixed.Assuming that the turn-on voltage V11 is a high level and the turn-off voltage V12 is a low level, the theoretical data signal write time for each row of sub-pixels begins on the rising edge of the first sample signal of the current row and ends on the rising edge of the first sample signal of the next row. However, the actual effective end time of the data signal write for a row of sub-pixels should be determined by the time at which the first switching transistors T1 of the row are completely and reliably turned off. Because the fall-off edge of the furthest first sample signal scan1 is slowed down, the turn-off time of the first switching transistor T1 corresponding to the furthest first sample signal scan1 occurs later than that of the nearest first switching transistor T1.Therefore, for the same row of subpixels, the actual effective loading time of the more distant subpixels is shorter than that of the nearby subpixels. This difference in loading times directly results in a lower loading ratio for the more distant subpixels compared to the nearby ones. When displaying a static or dynamic image, this spatial difference in loading ratios is converted into brightness or grayscale gradations, resulting in visually perceptible uneven brightness and thus impairing display quality.

[0076] Furthermore, it can happen that the first switching transistors T1 of distant pixel driver circuits 10 of the current row are not yet completely switched off due to the delayed fall-off edge of the first scan signal scan1, while the data signal line 16 has already begun writing a new data signal to the next row of pixel driver circuits 10. In this case, the data signal of the next row is fed into the gates of driver transistors T3 of the current row via the first switching transistors T1, which are not yet completely switched off, thus interfering with the already stored data signal. This leads to data crosstalk, which causes a deviation of the sub-pixel display from the target grayscale value and thus grayscale distortion.

[0077] Furthermore, the timing must include a longer protection interval for scanning each line to ensure that even the first switching transistors T1 at the most distant positions have enough time to completely switch off and thus prevent data crosstalk. This reduces the effective line time available for writing data signals, which complicates applications with high frame rates or high resolution.

[0078] With regard to the technical problems described above, in the embodiment of the present disclosure, as described in Fig. Figure 1 shows the modulation transistors 13, the modulation voltage signal lines 14, and the modulation control signal lines 15. The first terminal 131 of the modulation transistor 13 is electrically connected to the first sampling signal line 11, and the second terminal 132 of the modulation transistor 13 is electrically connected to the modulation voltage signal line 14. The modulation voltage signal line 14 is configured to provide the modulation voltage. The potential of the modulation voltage is set to a level that ensures reliable switching off of the first switching transistor T1. For example, the modulation voltage can be a voltage with the same or a similar potential to the switch-off voltage V12.

[0079] Fig. Figure 6 is another diagram of a first sampling signal according to an embodiment of the present disclosure. As in Fig. 1 and Fig. As shown in Figure 6, the gate of the modulation transistor 13 is electrically connected to the modulation control signal line 15 and is controlled by the modulation control signal K0 on the modulation control signal line 15. When the valid pulse K01 of the modulation control signal K0 is applied to the gate of the modulation transistor 13, the modulation transistor 13 is switched on (conducting).

[0080] In the embodiment of the present disclosure, the switching stage T0 between the turn-on voltage V11 of the first sampling signal scan1 and the turn-off voltage V12 of the first sampling signal scan1 overlaps in time with the valid pulse K01 of the modulation control signal K0. When the first sampling signal scan1 has to switch from the turn-on voltage V11 to the turn-off voltage V12, that is, in the switching stage T0, the modulation control signal K0 simultaneously provides a valid control pulse (the valid pulse K01) to put the modulation transistor 13 into a conducting state. In this case, the modulation voltage on the modulation voltage signal line 14 is fed directly into the first sampling signal line 11 at low impedance via the first terminal 131 of the modulation transistor 13 through the switched-on modulation transistor 13.This can accelerate the switching of the first sample signal scan1, significantly shorten the duration of the switching stage T0, and speed up the turning off of the remote first switching transistors T1, thus ensuring that the switching stage T0 of the first sample signal scan1 occurs quickly and consistently at all positions along the entire first sample signal line 11. This effectively compensates for delay differences caused by the transmission distance.

[0081] In this way, the potentials at all positions of the first sample signal scan1 are quickly and synchronously pulled to the modulation voltage, and the first switching transistors T1 at all positions (including the most distant ones) are switched off synchronously and quickly. This can eliminate the differences in effective charging times caused by different switch-off times of the first switching transistors T1, so that the charging ratios of the nearby and distant sub-pixels within the same row tend to become consistent, thus suppressing uneven display brightness.

[0082] Furthermore, the rapid switching off of the first switching transistors T1 can shorten the time window in which the first switching transistors T1 are not completely switched off, thereby reducing the probability of data signal crosstalk during the data signal change and ensuring the accuracy of the data signals written into the sub-pixels.

[0083] Additionally, shortening the switching stage T0 can allow the first switching transistors T1 to be switched off earlier, which in timing control can facilitate increasing the effective data signal write time of each line, improve the load ratio and support higher resolution or higher frame rates.

[0084] In summary, in the display board provided in the embodiment of the present disclosure, the modulation transistor, controlled by the modulation control signal with a specific timing sequence, is arranged on the first sampling signal line. In the switching stage, where the first sampling signal switches from the turn-on voltage to the turn-off voltage, the valid pulse of the modulation control signal is used to turn on the modulation transistor and rapidly apply the modulation voltage to the first sampling signal line via the turned-on modulation transistor, thereby accelerating the switching of the first sampling signal. This significantly reduces the duration of the switching stage, ensuring that the switching of the first sampling signal occurs quickly and consistently at all positions along the entire first sampling signal line.This can effectively compensate for delay differences caused by transmission distance, thereby eliminating variations in effective load times. As a result, the load ratios of nearby and distant sub-pixels within the same row tend to become more consistent, thus suppressing uneven display brightness. Furthermore, the possibility of data signal crosstalk in the switching stage can be reduced, ensuring the accuracy of the data signals written to the sub-pixels. Additionally, timing control can facilitate increasing the effective data signal write time of each row, thereby improving the load ratio and supporting higher resolutions or higher refresh rates.

[0085] Fig. Figure 7 is another diagram of a first sampling signal according to an embodiment of the present disclosure. As in Fig. As shown in Figure 7, for example, the turn-on voltage V11 is higher than the turn-off voltage V12, and the modulation voltage is lower than the turn-on voltage V11.

[0086] In one embodiment, the first sampling signal scan1 uses high-level RMS logic, meaning that the turn-on voltage V11 is higher than the turn-off voltage V12. This configuration is applicable to a pixel driver circuit 10 in which an n-type transistor is used as the first switching transistor T1. Under this architecture, when the first sampling signal scan1 is at the high-level turn-on voltage V11, a sufficiently high level is applied to the gate of the first switching transistor T1 so that the channel of the first switching transistor T1 is turned on and the data signal from the data signal line 16 can be written to the gate of the driver transistor T3.Furthermore, when the first sampling signal scan1 switches to the low-level turn-off voltage V12, the gate-source voltage of the first switching transistor T1 is reduced below the threshold voltage of the first switching transistor T1, so that the first switching transistor T1 is reliably turned off and the potential of the gate of the driver transistor T3 remains stable.

[0087] Furthermore, the modulation voltage is set so that it is lower than the turn-on voltage V11. For example, the modulation voltage is equal to or lower than the turn-off voltage V12, so that when the modulation transistor 13 is switched on, the potential of the first sampling signal line 11 can be effectively pulled down.

[0088] As in Fig. As shown in Figure 6, during the fall-off edge where the first sample signal scan1 switches from the turn-on voltage V11 to the turn-off voltage V12 (i.e., in the switching stage T0), the modulation control signal K0 with the valid pulse K01 is output, thereby turning on the modulation transistor 13. Since the modulation voltage is lower than the turn-on voltage V11, the potential of the first sample signal line 11 can be rapidly reduced, thus accelerating the voltage drop of the first sample signal line 11, shortening the switching stage T0, and allowing the remote first switching transistor T1 to be turned off synchronously with the nearby first switching transistor T1. This avoids display degradation caused by a delayed turn-off of the remote first switching transistor T1.

[0089] Fig. Figure 8 is another diagram of a first sampling signal according to an embodiment of the present disclosure. As in Fig. As shown in Figure 8, for example, the turn-on voltage V11 is lower than the turn-off voltage V12, and the modulation voltage is higher than the turn-on voltage V11.

[0090] In one embodiment, the first sampling signal scan1 uses low-level RMS logic, meaning that the turn-on voltage V11 is lower than the turn-off voltage V12. This configuration is applicable to a pixel driver circuit 10 in which a p-type transistor is used as the first switching transistor T1. Under this architecture, when the first sampling signal scan1 is at the low-level turn-on voltage V11, a sufficiently low level is applied to the gate of the first switching transistor T1 such that the gate-source voltage of the first switching transistor T1 exceeds the threshold voltage, thereby turning on the channel of the first switching transistor T1 and allowing the data signal from the data signal line 16 to be written to the gate of the driver transistor T3.Furthermore, when the first sampling signal scan1 switches to the high-level turn-off voltage V12, the first switching transistor T1 is turned off due to the increased potential at the gate of the first switching transistor T1, so that the potential of the gate of the driver transistor T3 remains stable.

[0091] Accordingly, the modulation voltage is set so that it is higher than the turn-on voltage V11. For example, the modulation voltage is equal to or higher than the turn-off voltage V12. This ensures that when the modulation transistor 13 is switched on, the potential of the first sampling signal line 11 can be effectively pulled up.

[0092] In one embodiment, during the rising edge, when the first sample signal scan1 switches from the turn-on voltage V11 (low level) to the turn-off voltage V12 (high level), the modulation control signal K0 with the valid pulse K01 is output, thereby turning on the modulation transistor 13. Since the modulation voltage is higher than the turn-on voltage V11, the first sample signal line 11 can be quickly pulled high via the modulation transistor 13, thus accelerating the rise of the potential of the first sample signal scan1, shortening the switching stage T0, and allowing the remote first switching transistor T1 to turn off synchronously with the nearby first switching transistor T1. This avoids display degradation that would be caused by a delayed turn-off of the remote first switching transistor T1.

[0093] Fig. Figure 9 is a diagram illustrating the structure of a shift register unit according to an embodiment of the present disclosure. As in Fig. 1 and Fig. As shown in Figure 9, the display plate provided in the embodiment of the present disclosure further comprises a first voltage signal line 17 and a second voltage signal line 18. The shift register unit 12 comprises a first transistor M1 and a second transistor M2. A first terminal m11 of the first transistor M1 is electrically connected to the first voltage signal line 17, a second terminal m12 of the first transistor M1 is electrically connected to the first sampling signal line 11, and the first transistor M1 is configured to provide a first voltage VGH on the first voltage signal line 17 to the first sampling signal line 11.A first terminal m21 of the second transistor M2 is electrically connected to the second voltage signal line 18, a second terminal m22 of the second transistor M2 is electrically connected to the first sampling signal line 11, and the second transistor M2 is configured to provide a second voltage VGL on the second voltage signal line 18 to the first sampling signal line 11. The first voltage VGH is higher than the second voltage VGL.

[0094] The multiple modulation voltage signal lines 14 include a first modulation voltage signal line 14A; the first modulation voltage signal line 14A is electrically connected to the first voltage signal line 17, and the modulation voltage is identical to the first voltage VGH.

[0095] Alternatively, the first modulation voltage signal line 14A is electrically connected to the second voltage signal line 18, and the modulation voltage is identical to the second voltage VGL.

[0096] In one embodiment as in Fig. As shown in Figure 9, the first transistor M1 and the second transistor M2 are output transistors of the shift register unit 12. The first terminal m11 of the first transistor M1 is an input terminal, and the second terminal m12 of the first transistor M1 is an output terminal. When the first transistor M1 is switched on, the first voltage VGH on the first voltage signal line 17 is transferred to the first sampling signal line 11. The first terminal m21 of the second transistor M2 is an input terminal, and the second terminal m22 of the second transistor M2 is an output terminal. When the second transistor M2 is switched on, the second voltage VGL on the second voltage signal line 18 is transferred to the first sampling signal line 11.The first transistor M1 and the second transistor M2 output the first voltage VGH and the second voltage VGL to the first sampling signal line 11 with a time delay.

[0097] In the embodiment of the present disclosure, the first voltage VGH is a high-level power voltage and the second voltage VGL is a low-level power voltage. The first voltage VGH and the second voltage VGL each serve as two reference levels for the sampling drive and can be flexibly configured depending on the type of first switching transistor T1 used and the drive method.

[0098] In some embodiments, the first switching transistor T1 is an n-type transistor. In this case, the first voltage VGH serves as the turn-on voltage V11, and the second voltage VGL serves as the turn-off voltage V12. In this mode, when the shift register unit 12 outputs the first voltage VGH to the first sampling line 11, the first switching transistor T1 in the pixel driver circuit 10 is turned on because the gate potential of the first switching transistor T1 is higher than the source / drain electrode potential of the first switching transistor T1, allowing the data signal to be written. When the shift register unit 12 outputs the second voltage VGL to the first sampling line 11, the first switching transistor T1 is turned off, thus completing the data signal writing and stabilizing the gate potential of the driver transistor T3.

[0099] As in Fig. 1 and Fig. As shown in Figure 9, the first modulation voltage signal line 14A is electrically connected to the second voltage signal line 18, so that the modulation voltage is equal to the second voltage VGL. In this case, in the switching stage T0, when the first sample signal scan1 switches from the turn-on voltage V11 (e.g., the first voltage VGH) to the turn-off voltage V12 (e.g., the second voltage VGL), the modulation transistor 13 is turned on to quickly pull the first sample signal line 11 down to the second voltage VGL (i.e., the turn-off voltage V12). This can speed up the turn-off process of the first switching transistor T1, mitigate the problem of the slowed fall-off edge of the distant first sample signal scan1 due to RC delay, and ensure that the first switching transistor T1 turns off quickly and synchronously, thereby improving charging uniformity and display uniformity.

[0100] In some embodiments, the first switching transistor T1 is a p-type transistor. In this case, the first voltage VGH serves as the turn-off voltage V12, and the second voltage VGL serves as the turn-on voltage V11. In this mode, when the shift register unit 12 outputs the second voltage VGL to the first sampling line 11, the first switching transistor T1 in the pixel driver circuit 10 is turned on, allowing the data signal to be written. When the shift register unit 12 outputs the first voltage VGH to the first sampling line 11, the first switching transistor T1 is turned off, thus completing the writing of the data signal and stabilizing the potential of the gate of the driver transistor T3.

[0101] Fig. Figure 10 is another diagram illustrating the structure of a display plate according to an embodiment of the present disclosure. As in Fig. 9 and Fig. As shown in Figure 10, the first modulation voltage signal line 14A is electrically connected to the first voltage signal line 17, so that the modulation voltage is equal to the first voltage VGH. In this case, in the switching stage T0, when the first sample signal scan1 switches from the turn-on voltage V11 (e.g., the second voltage VGL) to the turn-off voltage V12 (e.g., the first voltage VGH), the modulation transistor 13 is turned on to quickly pull the first sample signal line 11 up to the first voltage VGH (i.e., the turn-off voltage V12). This can speed up the turn-off process of the first switching transistor T1, mitigate the problem of the slowed fall-off edge of the distant first sample signal scan1 due to RC delay, and ensure that the first switching transistor T1 turns off quickly and synchronously, thereby improving charging uniformity and display uniformity.

[0102] The first modulation voltage signal line 14A directly utilizes the first voltage signal line 17 or the second voltage signal line 18 used by the shift register unit 12, without requiring an additional independent power supply or signal line. This effectively reduces wiring density, facilitating high pixel density and narrow bezel designs.

[0103] Furthermore, this ensures that the modulation voltage matches the turn-off voltage V12, allowing the first sample signal scan1 to be fully pulled down to the specified turn-off voltage V12. This prevents incomplete turn-off of the first switching transistor T1 due to an insufficient pull-down potential, thus avoiding grayscale distortion caused by data crosstalk.

[0104] It should be noted that by configuring the first voltage VGH to be higher than the second voltage VGL, the shift register unit 12 can output the first sample signal scan1 with a well-defined logical state, thus ensuring the accuracy and reliability of the line-wise sampling. The amplitude range of the first voltage VGH and the amplitude range of the second voltage VGL can be adjusted according to the actual requirements. For example, when using the n-type transistor as the first switching transistor T1, the amplitude range of the first voltage VGH can be between +10 V and +18 V, which is sufficient to fully turn on the first switching transistor T1; the amplitude range of the second voltage VGL can be between -5 V and 0 V, which can effectively suppress the leakage current of the first switching transistor T1 and ensure its reliable turn-off.The voltage difference between the first voltage VGH and the second voltage VGL defines the effective oscillation range of the first sampling signal scan1, which can influence the conductivity and temporal stability of the first switching transistor T1. Experts can adjust this voltage difference according to the actual requirements.

[0105] Fig. Figure 11 is another diagram illustrating the structure of a display plate according to an embodiment of the present disclosure. As in Fig. 3 and Fig. As shown in Figure 11, the display plate includes, for example, several light-emitting elements 20 arranged in an array, and the several light-emitting elements 20 are electrically connected to the several pixel driver circuits 10. The display plate further includes several first power voltage signal lines 31 and several second power voltage signal lines 32. A pixel driver circuit 10 includes a driver transistor T3, and the driver transistor T3 and a light-emitting element 20 are connected in series between a first power voltage signal line 31 and a second power voltage signal line 32. A first power voltage PVDD, transmitted through the first power voltage signal line 31, is higher than a second power voltage PVEE, transmitted through the second power voltage signal line 32. The several modulation voltage signal lines 14 include a second modulation voltage signal line 14B.The second modulation voltage signal line 14B is the same signal line as the first power voltage signal line 31, and the modulation voltage is identical to the first power voltage PVDD. Alternatively, the second modulation voltage signal line 14B is the same signal line as the second power voltage signal line 32, and the modulation voltage is identical to the second power voltage PVEE.

[0106] The specific structure and function of the light-emitting element 20 may refer to one of the foregoing embodiments and is not explained again herein.

[0107] In this embodiment, the first power voltage signal lines 31 and the second power voltage signal lines 32 can be arranged within the display area AA. The driver transistor T3 of the pixel driver circuit 10 and the light-emitting element 20 are connected in series between the first power voltage signal line 31 and the second power voltage signal line 32, thus forming a basic current drive circuit. The first power voltage PVDD transmitted by the first power voltage signal line 31 is higher than the second power voltage PVEE transmitted by the second power voltage signal line 32 to ensure that the light-emitting element 20 (e.g., a light-emitting diode) emits normally under forward voltage.

[0108] In some embodiments, such as in Fig. As shown in Figure 11, the second modulation voltage signal line 14B is connected to the second power voltage signal line 32, so that both form the same physical signal line and the modulation voltage is equal to the second power voltage PVEE. This configuration is applicable to the pixel driver circuit 10, in which the first switching transistor T1 is an n-type transistor. In such an architecture, the turn-on voltage V11 is higher than the turn-off voltage V12, and the second power voltage PVEE can be the same or a similar voltage to the turn-off voltage V12. During operation, on the fall-off edge when the first scan signal scan1 switches from the turn-on voltage V11 to the turn-off voltage V12 (i.e., the switching stage T0), the valid pulse K01 is output through the modulation control signal line 15 to the gate of the modulation transistor 13, thus turning on the modulation transistor 13.Due to the shared use of the second modulation voltage signal line 14B and the second power voltage signal line 32, the second terminal 132 of the modulation transistor 13 is clamped to the second power voltage PVEE. Therefore, the first sample signal line 11 is rapidly discharged to the second power voltage PVEE (i.e., equivalent to the turn-off voltage V12) via the on modulation transistor 13, creating a low-impedance path. This can accelerate the turn-off process of the first switching transistor T1, mitigate the problem of the slowed fall-off edge of the distant first sample signal scan1 due to RC delay, and ensure that the first switching transistor T1 turns off quickly and synchronously, thus improving charging uniformity and display uniformity.

[0109] Fig. Figure 12 is another diagram illustrating the structure of a display plate according to an embodiment of the present disclosure. As in Fig. As shown in Figure 12, the second modulation voltage signal line 14B is connected to the first power voltage signal line 31, so that both form the same physical signal line and the modulation voltage is equal to the first power voltage PVDD. This configuration is applicable to the pixel driver circuit 10, in which the first switching transistor T1 is a p-type transistor. In such an architecture, the turn-on voltage V11 is lower than the turn-off voltage V12. During operation, on the fall-off edge when the first scan signal scan1 switches from the turn-on voltage V11 to the turn-off voltage V12 (i.e., the switching stage T0), the valid pulse K01 is output through the modulation control signal line 15 to the gate of the modulation transistor 13, thus turning on the modulation transistor 13.Due to the shared use of the second modulation voltage signal line 14B and the first power voltage signal line 31, the second terminal 132 of the modulation transistor 13 is set to the first power voltage PVDD. The first sample signal line 11 is rapidly charged to the first power voltage PVDD (i.e., equivalent to the turn-off voltage V12) via the switched-on modulation transistor 13, creating a low-impedance pull-up path. This can accelerate the turn-off of the first switch transistor T1, mitigate the slowed fall-off edge of the distant first sample signal scan1 caused by the RC delay, and ensure that the first switch transistor T1 turns off quickly and synchronously, thereby improving charging uniformity and display uniformity.

[0110] The second modulation voltage signal line 14B directly uses the first power voltage signal line 31 or the second power voltage signal line 32 used by the pixel driver circuit 10, without requiring an additional independent power supply or signal line. This effectively reduces wiring density, enabling high pixel density and narrow bezels.

[0111] Fig. Figure 13 is another diagram illustrating the structure of a display plate according to an embodiment of the present disclosure. As in Fig. 3 and Fig. As shown in Figure 13, the display plate comprises several light-emitting elements 20 arranged in an array, and the several light-emitting elements 20 are electrically connected to the several pixel driver circuits 10. A pixel driver circuit 10 comprises a driver transistor T3, a first switch transistor T1, and a second switch transistor T2, and the driver transistor T3 and a light-emitting element 20 are connected in series between a first power voltage signal line 31 and a second power voltage signal line 32. A gate of the driver transistor T3 is electrically connected to a first terminal t11 of the first switch transistor T1, a second terminal t12 of the first switch transistor T1 is electrically connected to a data signal line 16, and a gate of the first switch transistor T1 is electrically connected to the first sample signal line 11.A first terminal t21 of the second switching transistor T2 is electrically connected to a first terminal t31 of the driver transistor T3, a second terminal t22 of the second switching transistor T2 is electrically connected to a reference voltage signal line 33, and a gate of the second switching transistor T2 is electrically connected to a second sampling signal line 34. The multiple modulation voltage signal lines 14 include multiple third modulation voltage signal lines 14C, and a third modulation voltage signal line 14C is the same signal line as the reference voltage signal line 33, in order to provide the modulation voltage to the modulation transistor 13 via the reference voltage signal line 33.

[0112] The specific structures and functions of the light-emitting element 20, the driver transistor T3, the first power voltage signal line 31 and the second power voltage signal line 32 can refer to one of the preceding embodiments and are not explained again here.

[0113] In this embodiment, as in Fig. Figure 3 shows the first switching transistor T1 connected in series between the gate of the driver transistor T3 and the data signal line 16, and the gate of the first switching transistor T1 is connected to the first sampling signal line 11, so that under the control of the turn-on voltage V11 of the first sampling signal scan1 the data signal on the data signal line 16 can be written into the gate of the driver transistor T3.

[0114] The second switching transistor T2 is connected in series between the first terminal t31 of the driver transistor T3 and the reference voltage signal line 33, and the gate of the second switching transistor T2 is connected to the second sampling signal line 34, so that under the control of a second sampling signal scan2 on the second sampling signal line 34 a reference voltage on the reference voltage signal line 33 can be written to the first terminal t31 of the driver transistor T3 and thereby fulfills a compensation function of the threshold voltage (Vth) of the driver transistor T3.

[0115] In some embodiments, as in Fig. Figure 3 shows the first terminal t31 of the driver transistor T3 being connected to the light-emitting element 20, and a second terminal t32 of the driver transistor T3 being connected to the first power voltage signal line 31.

[0116] In some embodiments, the pixel driver circuit comprises 10, as shown in Fig. 3 shown, furthermore a first capacitor C1, which is connected in series between the gate of the driver transistor T3 and the first terminal t31 of the driver transistor T3.

[0117] Fig. Figure 14 is an operating timing diagram of a pixel driver circuit according to an embodiment of the present disclosure. As in Fig. 3 and Fig. As shown in Figure 14, the operating cycle of the pixel driver circuit 10 can, for example, include an initialization stage Ti, a measurement stage Ts and a light emission stage Te.

[0118] In the initialization stage Ti, the first sampling signal scan1, provided by the first sampling line 11, is held at the turn-on voltage V11, and the first switching transistor T1 is turned on due to the turn-on voltage V11, so that the data voltage (data) of the data signal DATA on data signal line 16 is applied to the gate of the driver transistor T3. Simultaneously, the second sampling signal scan2, provided by the second sampling line 34, is held at the turn-on voltage V21, and the second switching transistor T2 is turned on due to the turn-on voltage V21, so that the reference voltage vref of a reference voltage signal VREF on reference voltage signal line 33 is applied to the first terminal t31 of the driver transistor T3.

[0119] In the measurement stage Ts, the first sampling signal, scan1, is held at the turn-on voltage V11, and the first switching transistor, T1, remains switched on due to this voltage. Consequently, the gate voltage Vg of the driver transistor T3 is held at the data voltage (data). The second sampling signal, scan2, is held at the turn-off voltage V22, causing the second switching transistor, T2, to switch off. A current corresponding to the gate-source voltage Vgs of driver transistor T3, set in the initialization stage Ti, flows through driver transistor T3. Therefore, the source voltage Vs of driver transistor T3 rises towards the data voltage (data) applied to its gate, and the gate-source voltage Vgs of driver transistor T3 is adjusted to match a desired gray value.

[0120] The light emission stage Te can be a period during which the light-emitting element 20 emits light based on a drain-source current of the driver transistor T3. In the light emission stage Te, the first sampling signal scan1 is held at the turn-off voltage V12, so that the first switching transistor T1 is off. The second sampling signal scan2 is held at the turn-off voltage V22, so that the second switching transistor T2 is off.

[0121] The gate voltage Vg and the source voltage Vs of the driver transistor T3 increase due to the drain-source current of the driver transistor T3, while the gate-source voltage Vgs of the driver transistor T3, set in the measuring stage Ts, is maintained until the source voltage Vs reaches the operating point voltage of the light-emitting element 20. When the source voltage Vs reaches the operating point voltage of the light-emitting element 20, a driver current corresponding to the set gate-source voltage Vgs of the driver transistor T3 flows through the light-emitting element 20 and excites it to emit the desired gray value.

[0122] The display plate provided in the embodiment of the present disclosure can be a self-illuminating display plate, and the pixel driver circuit 10 can comprise a 3T1C circuit, a 7T1C circuit, an 8T1C circuit, or an 8T2C circuit. The 3T1C circuit means that the pixel driver circuit 10 comprises three transistors and one capacitor; the 7T1C circuit means seven transistors and one capacitor; the 8T1C circuit means eight transistors and one capacitor; the 8T2C circuit means eight transistors and two capacitors. The 3T1C circuit is described in Fig. 3 is shown only as an example and is not limited to it.

[0123] Furthermore, as in Fig. As shown in Figure 13, the third modulation voltage signal line 14C is connected to the reference voltage signal line 33, so that both form the same physical signal line and the required modulation voltage is supplied to the modulation transistor 13 via the reference voltage signal line 33. The third modulation voltage signal line 14C directly uses the reference voltage signal line 33 used by the pixel driver circuit 10, without the need for an additional independent power supply or signal line. This can effectively reduce wiring density and support high pixel density and narrow bezel designs.

[0124] In one or more embodiments, the pixel driver circuit 10, as shown in Fig. 3 and Fig. Figure 14 shows the light emission stage Te, in which the first switching transistor T1 and the second switching transistor T2 are switched off. In the control stage of the second switching transistor T2, the reference voltage vref is transmitted on the reference voltage signal line 33. In the light emission stage Te, the modulation voltage V0 is transmitted on the reference voltage signal line 33. The reference voltage vref differs from the modulation voltage V0.

[0125] The operating cycle of the pixel driver circuit 10 can refer to any of the foregoing embodiments and is not explained again herein.

[0126] In this embodiment, the operating cycle of the pixel driver circuit 10 includes the light emission stage Te. In the light emission stage Te, the first switching transistor T1 and the second switching transistor T2 are in the off state, and the driver transistor T3 controls the current flowing through the light-emitting element 20 based on the data voltage stored at the gate of the driver transistor T3, thus achieving stable light emission.

[0127] The reference voltage signal VREF transmitted on the reference voltage signal line 33 is dynamically switched in different operating stages.

[0128] In one embodiment, in the control stage of the second switching transistor T2 (e.g., the initialization stage Ti), the voltage of the reference voltage signal VREF on the reference voltage signal line 33 is the reference voltage vref, which serves to provide a reference potential for internal nodes of the sub-pixels (such as the first terminal t31 of the driver transistor T3) in order to support operations with respect to the threshold voltage Vth of the driver transistor T3 such as compensation, initialization, or pre-charging.

[0129] In the light emission stage Te, the voltage of the reference voltage signal VREF on the reference voltage signal line 33 is switched to the modulation voltage V0.

[0130] In one embodiment, after entering the light emission stage Te, the second switching transistor T2 is already switched off, so that there is no longer a direct electrical connection between the reference voltage signal line 33 and the internal nodes of the pixel driver circuit 10. In this case, the reference voltage signal line 33 can be reconfigured to output the modulation voltage V0. In this case, the modulation transistor 13 is connected to the reference voltage signal line 33. In the switching stage T0 between the turn-on voltage V11 of the first sample signal scan1 and the turn-off voltage V12 of the first sample signal scan1 (the switching stage T0 is already within the light emission stage Te), the modulation transistor 13 can output the modulation voltage V0 via the reference voltage signal line 33 to actively regulate the first sample signal line 11.

[0131] In some embodiments, the modulation voltage V0 differs from the reference voltage vref. For example, in the control stage of the second switching transistor T2 (such as the initialization stage Ti), the reference voltage vref may be an intermediate voltage (e.g., +2 V) used for precise compensation control. In the light-emitting stage Te, the modulation voltage V0 may be close to or equal to the turn-off voltage V12 of the first sampling signal scan1 to ensure effective turn-off capability. By switching the voltage of the reference voltage signal VREF on the reference voltage signal line 33 to the modulation voltage V0 in the light-emitting stage Te, a modulation voltage that meets the turn-off requirements can be provided without the need for additional wiring.

[0132] Fig. Figure 15 is another diagram illustrating the structure of a display plate according to an embodiment of the present disclosure. Fig. Figure 16 is an operating timing diagram of a shift register unit according to an embodiment of the present disclosure. As in Fig. 8, Fig. 15 and Fig. As shown in Figure 16, the display panel includes, for example, a first clock signal line 35 and a second clock signal line 36. The first clock signal line 35 is electrically connected to the multiple shift register units 12 and is configured to provide a first clock signal CK to the multiple shift register units 12. The second clock signal line 36 is electrically connected to the multiple shift register units 12 and is configured to provide a second clock signal XCK to the multiple shift register units 12. The first clock signal CK and the second clock signal XCK are inverted relative to each other. The multiple modulation control signal lines 15 include a first modulation control signal line 15A. The first modulation control signal line 15A is electrically connected to the first clock signal line 35, and the modulation control signal can be identical to the first clock signal CK.Alternatively, the first modulation control signal line 15A is electrically connected to the second clock signal line 36, and the modulation control signal can be identical to the second clock signal XCK.

[0133] As in Fig. 9, Fig. 15 and Fig. As shown in Figure 16, the first clock signal CK, provided by the first clock signal line 35, and the second clock signal XCK, provided by the second clock signal line 36, are inverted relative to each other. That is, when the first clock signal CK is at a high level, the second clock signal XCK is at a low level, and vice versa. This complementary clock signal pair serves as timing control signals for the stepwise shift operation of the shift register units 12.

[0134] In one or more embodiments, the shift register unit comprises 12, as shown in Fig. Figure 9 shows a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, a second capacitor C2, a third capacitor C3 and a fourth capacitor C4.

[0135] A gate of the third transistor M3 is connected to the first clock signal line 35, and a first electrode of the third transistor M3 is connected to an input node IN.

[0136] A gate of the fourth transistor M4 is connected to a second electrode of the third transistor M3, and a second electrode of the fourth transistor M4 is connected to a first node N1.

[0137] One gate of the fifth transistor M5 is connected to the first clock signal line 35, one first electrode of the fifth transistor M5 is connected to the second voltage signal line 18, and one second electrode of the fifth transistor M5 is connected to the first node N1.

[0138] A gate of the sixth transistor M6 is connected to the second clock signal line 36, and a first electrode of the sixth transistor M6 is connected to the gate of the fourth transistor M4.

[0139] A gate of the seventh transistor M7 is connected to the first node N1, a first electrode of the seventh transistor M7 is connected to the first voltage signal line 17, and a second electrode of the seventh transistor M7 is connected to a second electrode of the sixth transistor M6.

[0140] A gate of the eighth transistor M8 is connected to the first node N1, a first electrode of the eighth transistor M8 is connected to the second clock signal line 36, and a second electrode of the eighth transistor M8 is connected to a first electrode of the ninth transistor M9.

[0141] One gate of the ninth transistor M9 is connected to the second clock signal line 36, and a second electrode of the ninth transistor M9 is connected to a third node N3.

[0142] One terminal of the second capacitor C2 is connected to a second node N2, and the other terminal of the second capacitor C2 is connected to the second clock signal line 36.

[0143] One terminal of the third capacitor C3 is connected to the first node N1, and the other terminal of the third capacitor C3 is connected to the first electrode of the ninth transistor M9.

[0144] The second node N2 outputs a voltage value of the second node, and the third node N3 outputs a voltage value of the third node.

[0145] A gate of the tenth transistor M10 is connected to the second node N2, a first electrode of the tenth transistor M10 is connected to the first voltage signal line 17, and a second electrode of the tenth transistor M10 is connected to the second electrode of the ninth transistor M9.

[0146] A gate of the first transistor M1 is connected to the third node N3, a first electrode of the first transistor M1 is connected to the first voltage signal line 17, and a second electrode of the first transistor M1 is connected to the first sampling signal line 11.

[0147] A gate of the second transistor M2 is connected to the second node N2, a first electrode of the second transistor M2 is connected to the second voltage signal line 18, and a second electrode of the second transistor M2 is connected to the first sampling signal line 11.

[0148] One terminal of the fourth capacitor C4 is connected to the third node N3, and the other terminal of the fourth capacitor C4 is connected to the first voltage signal line 17.

[0149] A first electrode of the eleventh transistor M11 is connected to the first clock signal line 35, a gate of the eleventh transistor M11 is connected to a second electrode of the eleventh transistor M11, creating a diode structure, and the second electrode of the eleventh transistor M11 is connected to a first electrode of the fourth transistor M4.

[0150] In the embodiment of the present disclosure, the first transistor M1 to the eleventh transistor M11 are all p-type transistors, with the first electrodes serving as source electrodes and the second electrodes as drain electrodes. However, this is not limited in the present disclosure. In other embodiments, all transistors in the shift register unit 12 can also be n-type transistors.

[0151] The operational process of the in Fig. The shift register unit 12 shown in section 8 is described below with reference to the information in Fig. 16 shown operating timing diagram and explained using an example where a first level is a low level and a second level is a high level.

[0152] It is understood that the operating state of the shift register unit 12 in the preceding stage influences the operating state of the shift register unit 12 in the subsequent stage. Therefore, a description of the stage T00 preceding the first stage T01 is given before the description of the first stage T01.

[0153] As in Fig. As shown in Figure 16, in stage T00, a signal at input node IN and the first clock signal CK on the first clock signal line 35 remain at the first level, while the second clock signal XCK on the second clock signal line 36 remains at the second level. In this case, the gate of the third transistor M3 and the gate of the fifth transistor M5 are connected to the low level of the first clock signal CK, so the third transistor M3 and the fifth transistor M5 remain switched on in this stage. The low level coming from input node IN is passed to the second node N2 via the switched-on third transistor M3. Therefore, the fourth transistor M4, the tenth transistor M10, and the second transistor M2 are switched on. The second voltage VGL, provided by the second voltage signal line 18, is passed to the first node N1 via the switched-on fifth transistor M5.The first voltage VGH, transmitted on the first voltage signal line 17, is passed via the switched-on tenth transistor M10 to the third node N3, and the first transistor M1 is switched off. Therefore, in stage T00, the first node N1 and the second node N2 are at a low level, the third node N3 is at a high level, and the second voltage VGL is output to the first sampling signal line 11, that is, the first sampling signal scan1 is on the second voltage VGL.

[0154] In the first stage T01, the signal at input node IN and the second clock signal XCK on the second clock line 36 remain at the first level, while the first clock signal CK on the first clock line 35 is at the second level. In this case, the gate of the third transistor M3 and the gate of the fifth transistor M5 are connected to the high level of the first clock signal CK, so the third transistor M3 and the fifth transistor M5 are switched off. In this stage, the second clock signal XCK changes from the high level in stage T00 to a low level. Due to the coupling effect of the second capacitor C2, the voltage at the second node N2 decreases further. Since the second electrode of the eleventh transistor M11 is connected to the gate of the eleventh transistor M11, the eleventh transistor M11 acts as a diode in the entire circuit.In the first stage T01, one electrode of the diode-structured eleventh transistor M11 is connected to the high level of the first clock signal CK, while the other electrode of the diode-structured eleventh transistor M11 is connected to the first node N1 via the switched-on fourth transistor M4. Since the first node N1 was at a low level in the previous stage T00, the eleventh transistor M11 is switched on in this stage according to the forward conduction and reverse blocking characteristics of a diode. The high-level first clock signal CK is gradually transferred to the first node N1 via the switched-on eleventh transistor M11 and the switched-on fourth transistor M4, so that the potential of the first node N1 gradually rises from the low potential of stage T00.

[0155] In the first stage T01, the first voltage VGH, transmitted on the first voltage signal line 17, is passed via the switched-on tenth transistor M10 to the third node N3, and the first transistor M1 is switched off. Therefore, in the first stage T01, the first node N1 and the third node N3 are at a high level, the second node N2 is at a low level, and the second voltage VGL is output to the first sampling signal line 11, that is, the first sampling signal scan1 is present on the second voltage VGL.

[0156] In the second stage T02, the first clock signal CK is at the first level on the first clock signal line 35, while the signal at input node IN and the second clock signal XCK are at the second level on the second clock signal line 36. In this case, the gate of the third transistor M3 and the gate of the fifth transistor M5 are connected to the low level of the first clock signal CK, so the third transistor M3 and the fifth transistor M5 are switched on; the second voltage VGL, provided by the second voltage signal line 18, is passed to the first node N1 via the switched-on fifth transistor M5, and the eighth transistor M8 is switched on; the high-level signal coming from input node IN is passed to the second node N2 via the switched-on third transistor M3.Therefore, the fourth transistor M4, the tenth transistor M10, and the second transistor M2 are switched off, while the third node N3 remains at the high level of the preceding stage T01. Thus, in the second stage T02, the first node N1 is at a low level, the third node N3 and the second node N2 are at a high level, and the first sample signal scan1 remains at the second voltage VGL of the preceding stage.

[0157] In the third stage T03, the first clock signal CK on the first clock signal line 35 is at the second level, while the signal at input node IN and the second clock signal XCK on the second clock signal line 36 are at the first level. In this case, the gate of the third transistor M3 and the gate of the fifth transistor M5 are connected to the high-level first clock signal CK, so the third transistor M3 and the fifth transistor M5 are switched off. Therefore, the first node N1 remains at the low-level voltage of the previous second stage T02, and the seventh transistor M7 and the eighth transistor M8 are switched on. The gate of the sixth transistor M6 and the gate of the ninth transistor M9 are connected to the low-level second clock signal XCK, so the sixth transistor M6 and the ninth transistor M9 are switched on.Therefore, in the third stage T03, the first voltage VGH, transmitted on the first voltage signal line 17, is passed to the second node N2 via the switched-on sixth transistor M6 and the switched-on seventh transistor M7, while the tenth transistor M10 and the second transistor M2 are switched off; the low-level second clock signal XCK is passed to the third node N3 via the switched-on eighth transistor M8 and the switched-on ninth transistor M9. Thus, in the third stage T03, the first node N1 and the third node N3 are at a low-level voltage, the second node N2 is at a high-level voltage, and the first voltage VGH is output to the first sampling signal line 11, that is, the first sampling signal scan1 is present at the first voltage VGH.

[0158] In the fourth stage T04, the first clock signal CK is on the first clock signal line 35, and the signal at input node IN is at the first level, while the second clock signal XCK is on the second clock signal line 36 at the second level. In this case, the gate of the third transistor M3 and the gate of the fifth transistor M5 are connected to the low-level first clock signal CK, so the third transistor M3 and the fifth transistor M5 are switched on; the second voltage VGL, provided by the second voltage signal line 18, is passed through the switched-on fifth transistor M5 to the first node N1, and the eighth transistor M8 is switched on; the low-level signal coming from input node IN is passed through the switched-on third transistor M3 to the second node N2. Therefore, the fourth transistor M4, the tenth transistor M10, and the second transistor M2 are switched on.The first voltage VGH, transmitted on the first voltage signal line 17, is passed via the switched-on tenth transistor M10 to the third node N3, and the first transistor M1 is switched off. Thus, in the fourth stage T04, the first node N1 and the second node N2 are at a low-level voltage, the third node N3 is at a high-level voltage, and the second voltage VGL is output to the first sampling signal line 11, that is, the first sampling signal scan1 is on the second voltage VGL.

[0159] In the fifth stage T05, the signal at input node IN and the second clock signal XCK on the second clock signal line 36 are at the first level, while the first clock signal CK on the first clock signal line 35 is at the second level. In this case, the gate of the third transistor M3 and the gate of the fifth transistor M5 are connected to the high-level first clock signal CK, so the third transistor M3 and the fifth transistor M5 are switched off. In this stage, the second clock signal XCK changes from the high level in the fourth stage T04 to a low level. Due to the coupling effect of the second capacitor C2, the voltage of the second node N2 continues to decrease. The first voltage VGH, which is transmitted on the first voltage signal line 17, is passed to the third node N3 via the switched-on tenth transistor M10, and the first transistor M1 is switched off.Consequently, in the fifth stage T05, the first node N1 and the third node N3 are at a high-level voltage, the second node N2 is at a low-level voltage, and the second voltage VGL is output to the first sampling signal line 11, that is, the first sampling signal scan1 is on the second voltage VGL.

[0160] The preceding analysis shows that the fifth stage T05 begins to repeat the operation of the first stage T01. Therefore, the operating cycle of the shift register unit 12 extends from T01 to T04.

[0161] Furthermore, the first modulation control signal line 15A is optionally electrically connected to the first clock signal line 35 or the second clock signal line 36, thereby reusing an existing clock signal as a modulation control signal.

[0162] In some embodiments, as in Fig. Figure 15 shows the first modulation control signal line 15A electrically connected to the first clock signal line 35, so that the modulation control signal applied to the gate of the modulation transistor 13 is identical to the first clock signal CK.

[0163] Fig. Figure 17 is another diagram illustrating the structure of a display plate according to an embodiment of the present disclosure. As in Fig. As shown in Figure 17, the first modulation control signal line 15A is electrically connected to the second clock signal line 36, so that the modulation control signal is identical to the second clock signal XCK.

[0164] Since the first clock signal CK and the second clock signal XCK are inverted relative to each other, the two connections mentioned above can each correspond to different modulation trigger times. Using the first switching transistor T1 as an n-type transistor as an example: If the first sample signal scan1 needs to be pulled down quickly on the fall-off edge (i.e., in the switching stage T0), and the modulation transistor 13 is also an n-type transistor, a high-level control signal is required to turn on the modulation transistor 13. In this case, the first modulation control signal line 15A can be connected to the second clock signal line 36, since the second clock signal XCK on the second clock signal line 36 is at a high level on the fall-off edge of the first sample signal scan1.This can enable the modulation transistor 13 to be switched on at the appropriate time, thereby pulling the first sampling signal scan1 on the first sampling signal line 11 down to the modulation voltage.

[0165] In some embodiments, if the first switching transistor T1 is an n-type transistor and the modulation transistor 13 is a p-type transistor, the first modulation control signal line 15A can also optionally be connected to the first clock signal line 35, so that the modulation control signal reuses the first clock signal CK, which is not particularly limited in the embodiment of the present disclosure.

[0166] In this embodiment, the modulation control signal transmitted on the first modulation control signal line 15A directly uses the first clock signal CK or the second clock signal XCK used by the shift register unit 12. This eliminates the need for an additional logic circuit or wiring to generate a modulation pulse, effectively reducing wiring density and facilitating a high pixel density and narrow bezel design.

[0167] Furthermore, the first clock signal CK and the second clock signal XCK are the core clock signals derived from the first sample signal scan1, and their phases are closely related to the rise / fall edge of the first sample signal scan1. Therefore, reusing the first clock signal CK or the second clock signal XCK as a modulation control signal can ensure that the modulation transistor 13 is switched on precisely at the time a pull-down (or pull-up) is required, thus avoiding modulation errors due to additional delays.

[0168] Fig. Figure 18 is another diagram illustrating the structure of a display plate according to an embodiment of the present disclosure. As in Fig. As shown in Figure 18, the display plate comprises a display area AA. The multiple modulation control signal lines 15 further comprise multiple secondary modulation control signal lines 15B, which are located at least partially within the display area AA. The direction of extension of the multiple secondary modulation control signal lines 15B is the same as the direction of extension of the multiple first sampling signal lines 11.

[0169] In one embodiment, as in Fig. Figure 18 shows the display area AA as an area of ​​the display panel that is actually used to display images, text, or other visual content. The light-emitting elements 20 are arranged within the display area AA, and different images are displayed by controlling the brightness of the light-emitting elements 20.

[0170] A non-display area (NAA) is provided on at least one side of the display area (AA). The non-display area (NAA) is located at the edge of the display plate. This area does not participate in the image display but includes some necessary circuitry and lines, such as a driver IC (integrated circuit) and signal lines, that support the operation of the display area (AA).

[0171] As in Fig. As shown in Figure 18, the second modulation control signal lines 15B extend within the display area AA, and their direction of extension is the same as that of the first sampling signal lines 11, for example arranged along the line direction and parallel to the several first sampling signal lines 11.

[0172] In some embodiments, such as in Fig. As shown in Figure 18, the second modulation control signal lines 15B are used to transmit modulation control signals to modulation transistors 13 located in the non-display area NAA.

[0173] Fig. Figure 19 is another diagram illustrating the structure of a display plate according to an embodiment of the present disclosure. As in Fig. As shown in Figure 19, the second modulation control signal lines 15B are used, for example, to transmit the modulation control signals to the modulation transistors 13 located within the display area AA. The modulation control signals can be introduced from the non-display area NAA into the display area AA via the second modulation control signal lines 15B and travel along the line direction through the entire display area AA, thus enabling synchronous control of the modulation transistors 13 of an entire line or a local area.

[0174] In this embodiment, by extending the second modulation control signal lines 15B into the display area AA, the modulation transistors 13 located within the display area AA can be directly driven. This avoids a modulation response delay or attenuation that could occur if the modulation transistors 13 received the modulation voltages from only one side of the non-display area NAA. This can thus more effectively compensate for the RC delay of the first sampling signal lines 11 and improve the waveform of the first sampling signals scan1.

[0175] Furthermore, because the second modulation control signal lines 15B extend in the same direction as the first sampling signal lines 11 (e.g., along the line direction), multiple modulation transistors 13 can be distributed along the entire line of the first sampling signal line 11. This allows modulation transistors 13 at different positions to receive the modulation control signals almost simultaneously, ensuring that the auxiliary pull-down or pull-up operations at different positions are highly synchronized. This enables the first switching transistors T1 of the entire line of pixel driver circuits 10 to be switched off synchronously, improving the consistency of the load conditions.

[0176] Fig. Figure 20 is another diagram illustrating the structure of a display plate according to an embodiment of the present disclosure. As in Fig. As shown in Figure 20, the display panel includes, for example, several modulation control signal generation units 37. An input terminal of a modulation control signal generation unit 37 is electrically connected to the first sampling signal line 11 to receive the first sampling signal scan1, and an output terminal of the modulation control signal generation unit 37 is electrically connected to a second modulation control signal line 15B. The modulation control signal generation unit 37 is configured to provide the modulation control signal to the second modulation control signal line 15B.

[0177] In one embodiment, it receives, as in Fig. As shown in 20, the input terminal of the modulation control signal generation unit 37 receives the first sampled signal scan1 in real time from the first sampled signal line 11, and the output terminal of the modulation control signal generation unit 37 provides the modulation control signal to the modulation transistors 13 which are connected to the first sampled signal line 11.

[0178] The modulation control signal generation units 37 can be integrated in the non-display area NAA or distributed in the display area AA and serve to automatically generate the corresponding modulation control signals based on the received first sample signals scan1.

[0179] In some embodiments, the modulation control signal generation unit 37 can consist of one or more logic gate circuits (such as an inverter, a delay unit, or an edge detection circuit). For example, when the first sample signal scan1 transitions from the turn-on voltage V11 to the turn-off voltage V12, the modulation control signal generation unit 37 can detect the fall-off or rise-off edge and output a short valid pulse. This pulse serves to turn on the modulation transistor 13 during the fall-off or rise-off phase of the first sample signal scan1 (i.e., the switching stage T0), thereby accelerating the switching operation of the first sample signal line 11.

[0180] Since the modulation control signal is generated by the first sample signal scan1, the timing of the modulation control signal is highly synchronized to the first sample signal scan1, without requiring an external global clock (such as the first clock signal CK / the second clock signal XCK) or other independent control signals. This avoids timing deviations due to different signal paths.

[0181] Furthermore, modulation control signal generation units 37 can each be arranged in multiple rows or key areas, creating a distributed modulation network. Each modulation control signal generation unit 37 responds only to the first sample signal scan1 of the row in which the modulation control signal generation unit 37 is located, thus effectively compensating for differences in the RC loads of the first sample signals scan1 of different rows and improving display uniformity.

[0182] In some embodiments, the display plate includes, as in Fig. Figure 20 shows the non-display area NAA, which is located on at least one side of the display area AA. The non-display area NAA comprises a first non-display area NAA1, which is located on one side of the display area AA, and the shift register units 12 and the modulation control signal generation units 37 are arranged in the first non-display area NAA1.

[0183] In this arrangement, the shift register units 12 generate the first sampling signals scan1 stepwise based on a clock signal (such as the first clock signal CK / second clock signal XCK) and transmit the first sampling signals scan1 via the first sampling signal lines 11 to the lines of the pixel driver circuits 10 within the display area AA. Furthermore, the input terminal of the modulation control signal generation unit 37 is electrically connected to the first sampling signal line 11 to receive its signal in real time, and the output terminal of the modulation control signal generation unit 37 is electrically connected to the second modulation control signal line 15B to output the corresponding modulation control signal, which switches on the modulation transistor 13 in the switching stage T0 and thereby performs active pull-down or pull-up control of the first sampling signal line 11.

[0184] Since the shift register unit 12 and the modulation control signal generation unit 37 are located in the same non-display area NAA1, efficient signal interaction can be achieved through short-range and low-latency wiring. For example, when the first sample signal scan1 switches from the turn-on voltage V11 to the turn-off voltage V12 on the first sample signal line 11, the modulation control signal generation unit 37 can quickly generate the valid pulse K01 of the modulation control signal K0 based on the waveform of a nearby first sample signal scan1. This valid pulse K01 synchronously triggers several modulation transistors 13 (which may extend into the display area AA) via the second modulation control signal line 15B, thus providing auxiliary control of the entire line of the first sample signal scan1.

[0185] It is understood that the shift register unit 12 and the modulation control signal generation unit 37 are located in the same non-display area NAA1 and that the connection path between them is relatively short, thus avoiding parasitic effects and timing deviations that would arise from long cross-area wiring. This ensures that the valid pulse K01 of the modulation control signal K0 is closely correlated with the first sampled signal scan1, thereby improving response accuracy.

[0186] Furthermore, the arrangement of the shift register unit 12 and the modulation control signal generation unit 37 exclusively in the non-display area NAA on the same side of the display plate (e.g. in the first non-display area NAA1) can significantly reduce the frame width on the opposite side of the display plate and thereby enable a high screen-to-chassis ratio.

[0187] Fig. Figure 21 is another diagram illustrating the structure of a display plate according to an embodiment of the present disclosure. As in Fig. As shown in Figure 21, the display plate includes, for example, a non-display area NAA located on at least one side of the display area AA. The non-display area NAA comprises a first non-display area NAA1 and a second non-display area NAA2, each located on two opposite sides of the display area AA. The display plate further includes several modulation control signal generation units 37. An output terminal of a modulation control signal generation unit 37 is electrically connected to a second modulation control signal line 15B. The modulation control signal generation unit 37 is configured to provide the modulation control signal to the second modulation control signal line 15B. The several shift register units 12 are arranged in the first non-display area NAA1. The several modulation control signal generation units 37 are arranged in the second non-display area NAA2.

[0188] In this embodiment, the non-display area NAA is divided into the first non-display area NAA1 and the second non-display area NAA2, each of which is arranged on two opposite sides of the display area AA.

[0189] The shift register unit 12 is located in the first non-display area NAA1, ensuring that the arrangement of the sub-pixels in the display area AA is not affected and improving the aperture ratio. This allows for increased brightness, energy efficiency, and display uniformity.

[0190] The modulation control signal generation unit 37 is located in the second non-display area NAA2, and the output terminal of the modulation control signal generation unit 37 is directly electrically connected to the second modulation control signal line 15B, so that the modulation control signal can be generated and transmitted to the second modulation control signal line 15B.

[0191] The modulation control signal generation unit 37 outputs the valid pulse K01 of the modulation control signal K0 within a precise time window based on a specific input signal in order to control the modulation transistor 13 and actively (e.g. pull down or pull up) control the first sampled signal scan1 on the first sampled signal line 11, thereby improving the waveform of the first sampled signal scan1 and suppressing the influence of the RC delay.

[0192] An input terminal of the modulation control signal generation unit 37 can be flexibly configured as required. For example, the input terminal of the modulation control signal generation unit 37 can be electrically connected to the first sampling signal line 11 to respond to level changes of the first sampling signal scan1 in real time. The modulation control signal generation unit 37 can consist of a first-stage inverter, a delay unit, and a NAND gate to implement fall-edge or rise-edge detection.

[0193] In some embodiments, the input terminal of the modulation control signal generation unit 37 can also be connected to an internal node of the shift register unit 12 to obtain a steeper signal edge or lower noise.

[0194] In some embodiments, the input terminal of the modulation control signal generation unit 37 can also be connected to a clock signal line (such as the first clock signal line 35 or the second clock signal line 36). By logically combining a clock signal with the first sample signal scan1 or an enable signal, a modulation control signal can be generated that is valid only within a specific line cycle.

[0195] In some embodiments, the input terminal of the modulation control signal generation unit 37 can also be connected to a global enable signal or a picture synchronization signal (such as STV or OE). For example, the input terminal can receive a global control signal from a timing controller (TCON), ensuring that a modulation operation is only activated during the valid display period, thus reducing static power consumption.

[0196] In this embodiment, as in Fig. As shown in Figure 21, the modulation control signal generation unit 37 and the shift register unit 12 are each arranged in the non-display areas NAA on two opposite sides of the display area AA (such as the first non-display area NAA1 and the second non-display area NAA2). In this arrangement, the first sampling signal scan1 is output from the first non-display area NAA1 and transmitted via the first sampling signal line 11 to the entire display area AA; the modulation control signal is output from the second non-display area NAA2 and transmitted via the second modulation control signal line 15B in a direction opposite to the transmission direction of the first sampling signal scan1, thus creating a signal transmission path in which the first sampling signal scan1 and the modulation control signal move towards each other.

[0197] If the first sample signal scan1 experiences a slowed fall or rise edge at the far end (near the second non-display area NAA2) due to the RC delay, the modulation control signal starts from the far end and preferentially acts on a modulation transistor 13 in this area, thereby rapidly pulling the first sample signal scan1 down or up to the modulation voltage on the first sample signal line 11. This ensures that the pull-down or pull-up operation occurs particularly quickly and in a timely manner at the point where the RC delay is greatest, thus improving the consistency of the charging conditions and the uniformity of the display.

[0198] In one or more embodiments, as in Fig. 7 and Fig. Figure 8 shows that the start time of the valid pulse K01 of the modulation control signal K0 is identical to the start time of the switching stage T0 of the first sampling signal scan1.

[0199] In one embodiment, as in Fig. 7 and Fig. As shown in Figure 8, upon the entry of the first sample signal scan1 into the switching stage T0, the modulation control signal K0 is immediately output with the valid pulse K01 to switch on the modulation transistor 13. Since the start time of the valid pulse K01 coincides exactly with the start time of the switching stage T0, the modulation transistor 13 can be switched on precisely at the moment when the potential of the first sample signal scan1 begins to fall or rise. This allows the first sample signal scan1 to be quickly pulled down or up to the modulation voltage on the first sample signal line 11 via a low-impedance path, effectively suppressing any delay caused by the parasitic line resistance (R) and the line capacitance (C).This allows the first switching transistor T1, which is connected to the first sampling signal line 11, to be switched off almost simultaneously, thereby improving the display uniformity.

[0200] Fig. Figure 22 is another operating timing diagram of a pixel driver circuit according to an embodiment of the present disclosure. As in Fig. As shown in Figure 22, the pulse width of the valid pulse K01 of the modulation control signal K0 is shorter than the duration of the switch-off voltage V12 of the first sampling signal scan1.

[0201] In one embodiment, the first scanning signal scan1 provides the turn-on voltage V11 and the turn-off voltage V12 in each line cycle. The duration of the turn-off voltage V12 typically extends over the entire non-gate period from the end of the turn-on voltage V11 of the first scanning signal scan1 until the next line is again supplied with the turn-on voltage V11. The duration of the turn-off voltage V12 can depend on the resolution and refresh rate of the display.

[0202] In this embodiment, the valid pulse K01 is provided only in the initial stage, when the first sampling signal scan1 switches to the off-voltage V12 (as in the switching stage T0), and the pulse width of the valid pulse K01 is shorter than the total duration of the off-voltage V12. This prevents interference with the normal operation of other operating stages (such as the initialization stage Ti and the measurement stage Ts, which correspond to the switch-on voltage V11).

[0203] In some embodiments, the slowed fall or rise edge of the first sample signal scan1 caused by the RC delay occurs mainly in the switching stage T0, and the first sample signal scan1 is subsequently already stabilized. Therefore, the valid pulse K01 covers only the switching stage T0, thus avoiding an unnecessary line state during the stable phase of the first sample signal scan1, which reduces power consumption.

[0204] It is understandable that if the valid pulse K01 were to persist for the entire duration of the off-voltage V12, the modulation transistor 13 would remain switched on for a prolonged period. This would not only increase leakage currents but could also cause supply voltage noise or voltage fluctuations due to continuous discharge. Using a narrow valid pulse K01 can significantly reduce the conduction time of the modulation transistor 13, thereby effectively suppressing current consumption. Furthermore, this can also reduce the risk of coupling interference between the modulation control signal K0 and other signal lines, thus improving temporal robustness.

[0205] In one or more embodiments, the display plate comprises, as in Fig. 1, Fig. 3 and Fig. Figure 22 shows several light-emitting elements 20 arranged in an array, and these multiple light-emitting elements 20 are electrically connected to multiple pixel driver circuits 10. A pixel driver circuit 10 comprises a driver transistor T3, a first switch transistor T1, and a second switch transistor T2. The driver transistor T3 and a light-emitting element 20 are connected in series between a first power voltage signal line 31 and a second power voltage signal line 32. A gate of the driver transistor T3 is electrically connected to a first terminal t11 of the first switch transistor T1, a second terminal t12 of the first switch transistor T1 is electrically connected to a data signal line 16, and a gate of the first switch transistor T1 is connected to the first sample signal line 11.A first terminal t21 of the second switching transistor T2 is electrically connected to a first terminal t31 of the driver transistor T3, a second terminal t22 of the second switching transistor T2 is electrically connected to a reference voltage signal line 33, and a gate of the second switching transistor T2 is connected to a second sampling signal line 34. The pixel driver circuit 10 has a light emission stage Te in which the first switching transistor T1 and the second switching transistor T2 are switched off. The pulse width of the valid pulse K01 of the modulation control signal K0 is shorter than the duration of the light emission stage Te.

[0206] The specific structures and operating procedures of the light-emitting element 20 and the pixel driver circuit 10 can refer to one of the preceding embodiments and are not explained again here.

[0207] In this embodiment, the pixel driver circuit 10 passes through several operating stages during a normal operating cycle, including the light emission stage Te. In this stage, the first switching transistor T1 and the second switching transistor T2 are in the off state, and the driver transistor T3 maintains a constant driver current based on the data signal voltage stored at the gate of the driver transistor T3, so that the light-emitting element 20 can emit light stably without being affected by external signals.

[0208] Furthermore, the pulse width of the valid pulse K01 of the modulation control signal K0 is shorter than the duration of the light emission stage Te, so that the valid pulse K01 only occurs in the light emission stage Te and interference with the normal operation of other operating stages (such as the initialization stage Ti and the measurement stage Ts, which correspond to the switch-on voltage V11) is avoided.

[0209] In some embodiments, the valid pulse K01 of the modulation control signal K0 covers only the switching stage T0, thus ensuring that the modulation operation only takes effect in the initial stage, when the first sampling signal scan1 switches to the turn-off voltage V12 (as in the switching stage T0). During most of the light emission stage Te, the modulation transistor 13 remains off, so that no additional load or noise is introduced into the pixel driver circuit 10 and interference with the stable light emission process is avoided.

[0210] In one or more embodiments, the display plate comprises, as in Fig. Figure 1 shows a display area AA and a non-display area NAA, which is located on at least one side of the display area AA. The multiple modulation transistors 13 comprise multiple first modulation transistors 13A, and the multiple first modulation transistors 13A are arranged in the non-display area NAA. A shift register unit 12 is connected to a first end 111 of the first sampling signal line 11, and a first modulation transistor 13A is connected to a second end 112 of the first sampling signal line 11.

[0211] In one embodiment, the first scanning signal line 11 has the first end 111 and the second end 112 and extends along the line direction over the entire display area AA to transmit the first scanning signal scan1 to the gates of the first switching transistors T1 of a row of pixel driver circuits 10 that is associated with the first scanning signal line 11.

[0212] The shift register unit 12 is connected to the first end 111 of the first sampling signal line 11, so that the required first sampling signal scan1 is provided line by line to each line of a first sampling signal line 11. The shift register unit 12 can be located in the non-display area NAA on one side of the first end 111 of the first sampling signal line 11, so that the shift register unit 12 remains outside the display area AA, does not occupy any effective pixel area, and does not block the light emission path of the light-emitting element 20, thus avoiding any impairment of the display effect of the display area AA.

[0213] Furthermore, the arrangement of modulation transistors 13, i.e., the first modulation transistors 13A, in the non-display area NAA can reduce the effects of the first modulation transistors 13A on the display effect of the display area AA and facilitate a higher screen-to-chassis ratio.

[0214] The RC delay accumulates with the transmission distance, and the far end (an area facing away from the side of the shift register unit 12) is an area where the distortion of the first sample signal scan1 is more pronounced. In this embodiment, the first modulation transistor 13A is connected to the second end 112 of the first sample signal line 11, and the first modulation transistor 13A and the shift register unit 12 are each arranged on two opposite sides of the display area AA, such that the first modulation transistor 13A is located at the farthest position.Accordingly, in the switching stage T0 of the first sample signal scan1, the first modulation transistor 13A can be quickly switched on to pull the first sample signal line 11 down or up to the modulation voltage via a low-impedance path, effectively accelerating the potential switching at the remote end. This can ensure that the timing of the fall or rise edge of the first sample signal scan1 tends to be uniform along the entire first sample signal line 11, so that the first switching transistors T1 of the pixel driver circuits 10 are switched off almost simultaneously, improving the consistency of the load time and the uniformity of the display.

[0215] In some embodiments, as in Fig. 1 and Fig. As shown in Figure 10, the first voltage signal line 17 and the second voltage signal line 18 are located in the non-display area (NAA) and thus do not occupy the effective area of ​​the display area (AA), thereby avoiding any interference with the pixel arrangement and light emission performance. The first modulation transistor 13A is electrically connected to the first modulation voltage signal line 14A, and the first modulation voltage signal line 14A is electrically connected to either the first voltage signal line 17 or the second voltage signal line 18. In this way, all these connections are located in the non-display area (NAA), which avoids noise coupling caused by signal lines when crossing high-density sub-pixels and thus effectively reduces line voltage drop and parasitic effects.This ensures that the modulation voltage is applied stably and reliably to the first modulation transistor 13A without adversely affecting the display effect of the display area AA.

[0216] In some embodiments, as in Fig. 15 and Fig. As shown in Figure 17, the first clock signal line 35 and the second clock signal line 36 are located in the non-display area NAA and thus do not occupy the effective area of ​​the display area AA, thereby avoiding any impairment of the pixel arrangement and the light emission performance. The first modulation transistor 13A is electrically connected to the first modulation control signal line 15A, and the first modulation control signal line 15A is electrically connected to either the first clock signal line 35 or the second clock signal line 36.In this way, all these wiring connections are located in the non-display area NAA, thus avoiding noise coupling caused by signal lines when crossing high-density sub-pixels, effectively reducing line voltage drop and parasitic effects, and ensuring that the modulation control signal is applied stably and reliably to the first modulation transistor 13A without adversely affecting the display effect of the display area AA.

[0217] In one or more embodiments, the display plate comprises, as in Fig. 1 and Fig. Figure 3 shows several light-emitting elements 20 arranged in an array, and these elements are electrically connected to several pixel driver circuits 10. A pixel driver circuit 10 comprises a driver transistor T3, a first switching transistor T1, and a second switching transistor T2. The driver transistor T3 and a light-emitting element 20 are connected in series between a first power voltage signal line 31 and a second power voltage signal line 32. A gate of the driver transistor T3 is electrically connected to a first terminal t11 of the first switching transistor T1, a second terminal t12 of the first switching transistor T1 is electrically connected to a data signal line 16, and a gate of the first switching transistor T1 is electrically connected to the first sampling signal line 11.The channel width-to-channel length ratio of the first modulation transistor 13A is greater than or equal to the channel width-to-channel length ratio of the first switching transistor T1.

[0218] The specific structures and functions of the light-emitting element 20 and the pixel driver circuit 10 may refer to one of the foregoing embodiments and are not explained again herein.

[0219] It should be noted that during transmission on the first sampling line 11, the fall or rise edge of the first sampling signal scan1 at the remote end is gradually slowed down due to the RC delay. If the driving capability of the first modulation transistor 13A is insufficient to quickly pull the first sampling signal scan1 to the turn-off voltage V12, the first switching transistor T1 will be turned off with a delay, which impairs the loading accuracy of the sub-pixels at the remote end.

[0220] In this embodiment, the channel width-to-channel length ratio of the first modulation transistor 13A is greater than or equal to that of the first switching transistor T1. The channel width-to-channel length ratio denotes the ratio W / L of a transistor's channel width W to its channel length L, which directly determines the transistor's conductance (i.e., its transconductance and drive current capability). Therefore, a relatively large channel width-to-channel length ratio can impart a stronger pull-down or pull-up drive capability to the first modulation transistor 13A, enabling efficient and fast active pull-down or pull-up operation at the remote end and effectively eliminating signal propagation delay at the remote end.

[0221] In one or more embodiments, the multiple modulation transistors 13 comprise, as in Fig. 19, Fig. 20 to Fig. Figure 21 shows several second modulation transistors 13B, which are arranged in the display area AA.

[0222] Unlike the first modulation transistor 13A, which is located in the non-display area NAA, a second modulation transistor 13B is located in the display area AA, with its physical position close to or directly integrated into the pixel driver circuit 10. This arrangement allows the pull-down or pull-up operation of the second modulation transistor 13B to directly affect the first sample signal scan1 at the pixel driver circuit 10, enabling local fine modulation. This improves the response speed and consistency of the pixel driver circuits 10 across different areas, increases load time consistency, and thus enhances display uniformity.

[0223] In some embodiments, as in Fig. 19, Fig. 20 to Fig. Figure 21 shows the reference voltage signal line 33 in display area AA to provide the reference voltage vref to the second switching transistor T2 in the pixel driver circuits 10 within display area AA, thereby supporting operations such as initialization or threshold voltage compensation. The second modulation transistor 13B in display area AA is connected to the third modulation voltage signal line 14C, and the third modulation voltage signal line 14C is the same signal line as the reference voltage signal line 33, so the existing reference voltage signal line 33 is reused, no additional wiring is required, space is saved in display area AA, and a high-resolution integrated design is facilitated.

[0224] Fig. Figure 23 is another diagram illustrating the structure of a display plate according to an embodiment of the present disclosure. Fig. Figure 24 is another diagram illustrating the structure of a display plate according to an embodiment of the present disclosure. As in Fig. 23 and Fig. As shown in Figure 24, for example, the first power voltage signal line 31 and the second power voltage signal line 32 are also located in display area AA to provide the necessary power voltages to the pixel driver circuit 10 within display area AA. The second modulation transistor 13B is connected to the second modulation voltage signal line 14B, and the second modulation voltage signal line 14B is the same signal line as the first power voltage signal line 31 or the second power voltage signal line 32. By reusing the existing power voltage signal line, no additional wiring is required, thus saving space in display area AA and facilitating a high-resolution integrated design.

[0225] In some embodiments, as in Fig. 19, Fig. 20 to Fig. Figure 21 shows the second modulation control signal line 15B in the display area AA and is connected to the second modulation transistor 13B to provide the modulation control signal to the second modulation transistor 13B in the display area AA.

[0226] Fig. Figure 25 is another diagram illustrating the structure of a display plate according to an embodiment of the present disclosure. As in Fig. As shown in Figure 25, for example, the first sampling signal line 11 is connected to a second modulation transistor 13B. A shift register unit 12 is connected to a first end 111 of the first sampling signal line 11. The length of the first sampling signal line 11 is L1, and the distance between the second modulation transistor 13B and a second end 112 of the first sampling signal line 11 is D1, where D1 ≤ L1 / 3.

[0227] In one embodiment, the first sampling signal line 11 has a first end 111 and a second end 112 and extends along the line direction over the entire display area AA. The first sampling signal line 11 is connected to the second modulation transistor 13B, which can reduce the effect of the second modulation transistor 13B on the display effect of the display area AA and thus lower costs.

[0228] The shift register unit 12 is located in the non-display area NAA and is electrically connected to the first end 111 of the first sampling signal line 11 to generate and output the first sampling signal scan1, which drives the line of pixel driver circuits 10 that is associated with the first sampling signal line 11.

[0229] In this embodiment, the first sampling signal line 11 has a total length L1, where the total length L1 can be understood as the distance between the first end 111 of the first sampling signal line 11 and the second end 112 of the first sampling signal line 11.

[0230] The distance D1 between the second modulation transistor 13B and the second end 112 of the first sampling signal line 11 can be understood as the distance between the junction where the second modulation transistor 13B is connected to the first sampling signal line 11 and the second end 112 of the first sampling signal line 11.

[0231] D1 ≤ L1 / 3, such that the second modulation transistor 13B is located within one-third of the region closest to the far end (i.e., the second end 112) of the first sample signal line 11. This position is determined based on a comprehensive consideration of the RC delay distribution and the signal integrity requirements. Since signal attenuation and the slowed fall or rise edge accumulate with distance during the transmission of the first sample signal scan1 from the first end 111 of the first sample signal line 11 to the second end 112 of the first sample signal line 11, signal degradation occurs relatively strongly in the far region (especially in the last third). Therefore, by arranging the second modulation transistor 13B within the third closest to the far end (i.e.,The second end 112) of the first sampling signal line 11 ensures that the pull-down or pull-up effect covers a region where the first sampling signal scan1 tends to degrade. This allows the difference in effective loading times between the near end and the far end to be reduced, provided only the second modulation transistor 13B is provided, thus improving display uniformity.

[0232] Fig. Figure 26 is another diagram illustrating the structure of a display plate according to an embodiment of the present disclosure. As in Fig. As shown in Figure 26, for example, the first sampling signal line 11 is connected to N second modulation transistors 13B, where N ≥ 2. A shift register unit 12 is connected to a first end 111 of the first sampling signal line 11. The length of the first sampling signal line 11 is L1, and the distance between a second end 112 of the first sampling signal line 11 and a second modulation transistor 13B, which is closest to the second end 112 of the first sampling signal line 11, is D2, where D2 ≤ L1 / (N + 1).

[0233] In one embodiment, as in Fig. As shown in Figure 26, the first sampling signal line 11 is connected to the N second modulation transistors 13B, where N ≥ 2. That is, the first sampling signal line 11 is connected to at least two second modulation transistors 13B. The second modulation transistors 13B are all located in the display area AA, and the first terminals of the second modulation transistors 13B are each electrically connected to different positions of the first sampling signal line 11. During the valid pulse K01 of the modulation control signal K0, the first sampling signal scan1 can be actively pulled down or up at the different positions, thereby reducing differences in the effective load times of the pixel driver circuits 10 at the different positions and improving display uniformity.

[0234] Furthermore, the shift register unit 12 is located in the non-display area NAA and is electrically connected to the first end 111 of the first sampling signal line 11. The shift register unit 12 serves as the drive source of the first sampling signal scan1 and provides the first sampling signal scan1 for the entire first sampling signal line 11.

[0235] In this embodiment, the total length of the first sampling signal line 11 is L1, and the distance between the second end 112 of the first sampling signal line 11 and the second modulation transistor 13B, which is closest to the second end 112 of the first sampling signal line 11, is defined as D2, where D2 ≤ L1 / (N + 1). Here, the distance D2 denotes the length of a line between an electrical connection point of the second modulation transistor 13B with the first sampling signal line 11 and the second end 112.

[0236] If the above condition is met, the position of a second modulation transistor 13B, the one closest to the far end, is restricted to being within a range that does not exceed L1 / (N + 1) from the second end 112. This ensures that the pull-down or pull-up effect covers the far end where the first sample signal scan1 tends to degrade, thereby reducing the difference in effective load times between the near and far ends and improving display uniformity.

[0237] Fig. Figure 27 is another diagram illustrating the structure of a display plate according to an embodiment of the present disclosure. As in Fig. As shown in Figure 27, the first sampling signal line 11 is connected, for example, to N second modulation transistors 13B, where N ≥ 2, and the N second modulation transistors 13B are arranged uniformly along the extension direction of the first sampling signal line 11.

[0238] In one embodiment, the first sampling signal line 11 is connected to at least two second modulation transistors 13B. The second modulation transistors 13B are all arranged in the display area AA and are evenly distributed along the direction of extension of the first sampling signal line 11.

[0239] The uniform arrangement can be understood as follows: the connection points of the N second modulation transistors 13B on the first sampling signal line 11 essentially divide the signal line into N + 1 sub-segments of equal or approximately equal length. If the total length of the first sampling signal line 11 is L1, the distance between each pair of adjacent second modulation transistors 13B, as well as the distances between the first and last second modulation transistors 13B and the respective ends of the first sampling signal line 11, are each approximately equal.

[0240] This arrangement creates multiple equidistant active pull-down and pull-up nodes along the entire first sampling signal line 11, so that the pull-up or pull-down effect is evenly distributed over the entire length of the first sampling signal line 11. This effectively suppresses signal attenuation at different positions and ensures that the fall or rise edge remains steep and synchronous along the entire line direction, thereby improving timing accuracy.

[0241] Furthermore, a concentration of the second modulation transistors 13B in a specific area leads to a relatively high local transistor density, which reduces the open-circuit ratio in that area and can cause local brightness reduction or color shift, impairing display uniformity. Therefore, in this embodiment, the second modulation transistors 13B are arranged uniformly along the direction of extension of the first sampling signal line 11, thereby effectively distributing the density of the second modulation transistors 13B, avoiding the aforementioned problem, and improving a uniform display effect across the entire screen.

[0242] Fig. Figure 28 is another diagram illustrating the structure of a display plate according to an embodiment of the present disclosure. As in Fig. As shown in Figure 28, the display plate includes, for example, a non-display area NAA located on at least one side of the display area AA. The non-display area NAA includes a first non-display area NAA1 located on one side of the display area AA, and the multiple shift register units 12 are arranged in the first non-display area NAA1. The display area AA includes a first display area AA1 and a second display area AA2, wherein the first display area AA1 and the second display area AA2 are arranged along the extension direction of the first sampling signal line 11, and the first display area AA1 is located on a side of the second display area AA2 facing the first non-display area NAA1.The first sampling signal line 11 is connected to N second modulation transistors 13B, where N ≥ 2, and the distribution density of the second modulation transistors 13B in the first display area AA1 is less than the distribution density of the second modulation transistors 13B in the second display area AA2.

[0243] In one embodiment, as in Fig. Figure 28 shows the shift register units 12 arranged and set up in the first non-display area NAA1 on the side of the display area AA to generate and output the first scanning signals scan1.

[0244] The display area AA is divided into the first display area AA1 and the second display area AA2. The first display area AA1 is located on the side facing the first non-display area NAA1 and serves as the near area of ​​the transmission path for the first scan signals scan1. The second display area AA2 is located on the side facing away from the first non-display area NAA1 and serves as the far area of ​​the transmission path for the first scan signals scan1.

[0245] Furthermore, the first sampling signal line 11 is connected to at least two second modulation transistors 13B. The second modulation transistors 13B are all located in the display area AA, and the distribution density of the second modulation transistors 13B in the first display area AA1 is lower than the distribution density of the second modulation transistors 13B in the second display area AA2.

[0246] The distribution density can be understood as the number of second modulation transistors 13B connected per unit length of the first sampling signal line 11. For example, within the same length interval, three second modulation transistors 13B may be provided in the second display area AA2, while only two or fewer second modulation transistors 13B may be provided in the first display area AA1.

[0247] It is understood that when the first sample signal scan1 is transmitted via the first sample signal line 11 from the first non-display area NAA1 towards the far end, the RC delay accumulates with distance. As a farther area, the second display area AA2 experiences greater signal degradation than the first display area AA1. Therefore, by increasing the distribution density of the second modulation transistors 13B in the far area (e.g., in the second display area AA2), a stronger active pull-down or pull-up capability can be provided at a location where the first sample signal scan1 is significantly degraded. In the near area (e.g., near the first non-display area NAA1), the number of second modulation transistors 13B can be appropriately reduced to lower costs.

[0248] Fig. Figure 29 is another diagram illustrating the structure of a display plate according to an embodiment of the present disclosure. As in Fig. As shown in Figure 29, the display plate includes, for example, a non-display area NAA located on at least one side of the display area AA. The non-display area NAA comprises a first non-display area NAA1 and a second non-display area NAA2, each located on two opposite sides of the display area AA. The multiple shift register units 12 comprise multiple cascaded first shift register units 121 and multiple cascaded second shift register units 122. The multiple first shift register units 121 are arranged in the first non-display area NAA1, and the multiple second shift register units 122 are arranged in the second non-display area NAA2.The display area AA comprises a first display area AA1, a second display area AA2, and a third display area AA3, wherein the first display area AA1, the second display area AA2, and the third display area AA3 are arranged along the extension direction of the first sampling signal line 11, and the second display area AA2 is arranged between the first display area AA1 and the third display area AA3. The first sampling signal line 11 is connected to N second modulation transistors 13B, where N ≥ 2. The distribution density of the second modulation transistors 13B in the second display area AA2 is greater than the distribution density of the second modulation transistors 13B in the first display area AA1 and the distribution density of the second modulation transistors 13B in the third display area AA3.

[0249] In one embodiment, as in Fig. As shown in Figure 29, the non-display area NAA is further subdivided into the first non-display area NAA1 and the second non-display area NAA2, each arranged on two opposite sides of the display area AA. The multiple cascaded first shift register units 121 are arranged in the first non-display area NAA1, and the multiple cascaded second shift register units 122 are arranged in the second non-display area NAA2, thus enabling bidirectional transmission of the first sampling signals scan1.

[0250] It should be noted that in this embodiment, as in Fig. As shown in Figure 29, the display panel uses a two-sided scanning drive method. That is, a first shift register unit 121 and a second shift register unit 122 output the first scanning signals scan1 synchronously from the two ends of the first scanning signal line 11 (the first end 111 and the second end 112) towards a central area. This two-sided driver architecture can effectively shorten the transmission path of a one-sided first scanning signal scan1, reduce the RC delay effects, and is better suited for large-sized or high-resolution display panels.

[0251] Although the two-sided scanning operation has improved the overall integrity of the first scan signal scan1, waveform distortions and signal degradation may still occur in the central area due to superposition, phase deviation or load imbalance of the two first scan signals scan1.

[0252] In this embodiment, the display area AA is subdivided along the extension direction of the first sampling signal line 11 into the first display area AA1, the second display area AA2, and the third display area AA3, with the first display area AA1 and the third display area AA3 each being arranged on opposite sides of the second display area AA2. The first sampling signal line 11 is connected to at least two second modulation transistors 13B. The distribution density of the second modulation transistors 13B in the second display area AA2 is greater than the distribution density of the second modulation transistors 13B in the first display area AA1 and the distribution density of the second modulation transistors 13B in the third display area AA3.

[0253] Increasing the number of second modulation transistors 13B in the central area (i.e., in the second display area AA2) provides stronger active pull-down or pull-up capability at positions where the first sample signals scan1 are significantly degraded, thereby improving the overall display quality. However, the number of second modulation transistors 13B in the two side areas (e.g., in the first display area AA1 and the third display area AA3) can be appropriately reduced to lower costs.

[0254] In other embodiments, a one-sided scanning drive method can also be used. For example, as in Fig. As shown in Figure 1, the shift register unit 12 is arranged only in the first non-display region NAA1 to drive the entire first sampling signal line 11 from one end. In this case, the degradation of the first sampling signal scan1 increases monotonically along the first sampling signal line 11, and the arrangement of modulation transistors 13 at the far end (i.e., in a region facing away from the shift register unit 12) can, in particular, provide compensation for the RC delay of the first sampling signal scan1 in one-sided operation. Details are not repeated here.

[0255] In one or more embodiments, as in Fig. 19, Fig. 20 to Fig. Figure 21 shows that the number of pixel driver circuits 10 connected to the first sampling signal line 11 is equal to the number of second modulation transistors 13B connected to the first sampling signal line 11.

[0256] In one embodiment, if the first sampling signal line 11 is connected to M pixel driver circuits 10, correspondingly M second modulation transistors 13B are connected to the first sampling signal line 11, and each second modulation transistor 13B can correspond to a respective pixel driver circuit 10 in terms of its spatial arrangement or be directly adjacent to it.

[0257] For example, each pixel driver circuit 10 can be further integrated with its own second modulation transistor 13B, in addition to the driver transistor T3, the first switch transistor T1 and the second switch transistor T2.

[0258] Since a slight delay of the first sampled signal scan1 can occur at the position of each pixel driver circuit 10 due to differences in parasitic parameters, relying on only a small number of second modulation transistors 13B may be insufficient to achieve highly accurate, uniform compensation. In this embodiment, configuring an independent second modulation transistor 13B for each pixel driver circuit 10 enables pixel-level pull-down or pull-up capability, thereby significantly improving the control accuracy of the first sampled signal scan1 at the different positions.

[0259] In some embodiments, the second modulation transistor 13B can be used as part of the pixel driver circuit 10. Utilizing an existing transistor layout space in the pixel driver circuit 10 to integrate the second modulation transistor 13B does not require any additional area from another non-light-emitting region, which is advantageous for maintaining a high aperture ratio and improves the manufacturing yield.

[0260] In one or more embodiments, the display plate comprises, as in Fig. 3 and Fig. Figure 19 shows several light-emitting elements 20 arranged in an array, and the several light-emitting elements 20 are electrically connected to the several pixel driver circuits 10. A pixel driver circuit 10 comprises a driver transistor T3 and a first switching transistor T1, and the driver transistor T3 and a light-emitting element 20 are connected in series between a first power voltage signal line 31 and a second power voltage signal line 32. A gate of the driver transistor T3 is electrically connected to a first terminal t11 of the first switching transistor T1, a second terminal t12 of the first switching transistor T1 is electrically connected to a data signal line 16, and a gate of the first switching transistor T1 is electrically connected to the first sampling signal line 11.The channel width-to-channel length ratio of a second modulation transistor 13B is less than or equal to the channel width-to-channel length ratio of the first switching transistor T1.

[0261] The specific structures and operating procedures of the light-emitting element 20 and the pixel driver circuit 10 can refer to one of the preceding embodiments and are not explained again here.

[0262] In this embodiment, the second modulation transistor 13B is located in the display area AA, and the channel width-to-channel length ratio of the second modulation transistor 13B is no greater than that of the first switching transistor T1. This can result in the second modulation transistor 13B having a relatively low static leakage current and a relatively small physical size, which not only reduces the overall current consumption but also minimizes the occupancy of the limited space in the display area AA, thus contributing to an increase in the on-ratio and an improvement in the manufacturing yield.

[0263] Fig. Figure 30 is another diagram illustrating the structure of a display plate according to an embodiment of the present disclosure. As in Fig. As shown in Figure 30, the first sampling signal line 11 is connected to at least two second modulation transistors 13B. At least two second modulation transistors 13B connected to the same first sampling signal line 11 comprise a second nearby modulation transistor 13B1 and a second distant modulation transistor 13B2. The distance between the second nearby modulation transistor 13B1 and a shift register unit 12 is smaller than the distance between the second distant modulation transistor 13B2 and the shift register unit 12. The channel width-to-channel length ratio of the second nearby modulation transistor 13B1 is smaller than the channel width-to-channel length ratio of the second distant modulation transistor 13B2.

[0264] In one embodiment, the first sampling signal line 11 is connected to the at least two second modulation transistors 13B, and any two second modulation transistors 13B can be designated as the second nearby modulation transistor 13B1, which is closer to the shift register unit 12, and the second distant modulation transistor 13B2, which is further away from the shift register unit 12.

[0265] The second nearby modulation transistor 13B1 is located close to the shift register unit 12, where the integrity of the first sampled signal scan1 is relatively good. Therefore, the second nearby modulation transistor 13B1 has a relatively small channel width-to-channel length ratio, which can reduce power consumption and minimize the occupancy of the limited space in the display area AA, thereby increasing the open-circuit ratio and improving manufacturing yield.

[0266] The second remote modulation transistor 13B2 is located on a side where the transmission path of the first sample signal scan1 is particularly long. Due to RC delay effects, the waveform of the first sample signal scan1 is significantly degraded. By increasing the channel width-to-channel length ratio of the second remote modulation transistor 13B2, a stronger active pull-down or pull-up capability can be provided, allowing the voltage of the first sample signal line 11 to be quickly pulled up to the modulation voltage and ensuring that a first switch transistor T1 at this position is turned off in a timely manner.

[0267] Fig. Figure 31 is a partial cross-sectional diagram of a display plate according to an embodiment of the present disclosure. As in Fig. As shown in Figure 31, the display plate further comprises, for example, a base substrate 100 and several light-emitting elements 20 located on one side of the base substrate 100, and drive electrodes 204 of the several light-emitting elements 20 are electrically connected to the several pixel driver circuits 10. Perpendicular projections of the several second modulation transistors 13B onto the base substrate 100 do not overlap with perpendicular projections of the drive electrodes 204 of the several light-emitting elements 20 onto the base substrate 100.

[0268] In one embodiment, each light-emitting element 20 comprises a drive electrode 204, and the drive electrode 204 is an electrode that serves to provide a drive current to the light-emitting element 20. The drive electrodes 204 are electrically connected to the pixel driver circuits 10 arranged on the base substrate 100 and can receive drive currents output by driver transistors T3, thereby controlling the brightness of the light-emitting elements 20.

[0269] The design of the drive electrode 204 depends specifically on the component structure of the light-emitting element 20. For example, if the light-emitting element 20 is an organic light-emitting diode (OLED), the drive electrode 204 is an anode 201 of the light-emitting element 20. If the light-emitting element 20 is a micro-light-emitting diode (micro-LED), the drive electrode 204 can be a p-electrode of the light-emitting element 20. The design of the drive electrode 204 is not limited in this respect.

[0270] Furthermore, when the multiple second modulation transistors 13B are arranged within the display area AA, the perpendicular projections of the multiple second modulation transistors 13B onto the base substrate 100 do not overlap with the perpendicular projections of the drive electrodes 204 of the multiple light-emitting elements 20 onto the base substrate 100. In the case of a second modulation transistor 13B, an active layer 1, a gate 2, source and drain electrodes 3, and other components completely avoid the area occupied by the drive electrode 204 in the plane, so that the second modulation transistor 13B and the drive electrode 204 do not overlap in their spatial arrangement.

[0271] This arrangement prevents the second modulation transistor 13B from influencing the potential of the drive electrode 204 due to parasitic capacitance, thus avoiding brightness fluctuations or flickering and improving display stability.

[0272] Furthermore, by avoiding the placement of the second modulation transistor 13B below the drive electrode 204, the flatness of the layers located below the drive electrode 204 can be improved, thereby reducing the risk of short circuits or open circuits that could be caused by insufficient step coverage during the manufacture of the drive electrode 204, and thus improving the manufacturing yield.

[0273] Fig. Figure 32 is another diagram illustrating the structure of a display plate according to an embodiment of the present disclosure. As in Fig. As shown in Figure 32, the display plate further comprises, for example, a display area AA and a non-display area NAA, which is located on at least one side of the display area AA. The multiple modulation transistors 13 comprise multiple first modulation transistors 13A and multiple second modulation transistors 13B. The multiple first modulation transistors 13A are arranged in the non-display area NAA, and the multiple second modulation transistors 13B are arranged in the display area AA. The channel width-to-channel length ratio of a first modulation transistor 13A is greater than or equal to the channel width-to-channel length ratio of a second modulation transistor 13B.

[0274] In one embodiment, as in Fig. Figure 32 shows the first modulation transistors 13A arranged in the non-display area NAA, while the second modulation transistors 13B are arranged in the display area AA, which can improve the response speed and consistency of the pixel driver circuits 10 in different areas, increase the consistency of loading times and thereby improve display uniformity.

[0275] Since the wiring space in the non-display area NAA is relatively generous and can accommodate relatively large transistors, the first modulation transistor 13A is designed with a relatively large channel width to channel length ratio to provide stronger pull-down or pull-up driving capability, thus effectively addressing signal propagation delay.

[0276] Furthermore, due to the high-density pixel arrangement and the requirements for the aperture ratio in the display area AA, the second modulation transistor 13B is designed with a relatively small channel width-to-channel length ratio in order to reduce the size of the second modulation transistor 13B, minimize the shading of a light-emitting area by the second modulation transistor 13B, ensure a relatively high aperture ratio, and also reduce static current consumption and parasitic capacitances, thereby improving the overall circuit efficiency.

[0277] In some embodiments, the first modulation transistor 13A and the second modulation transistor 13B can be, as in Fig. As shown in Figure 32, the transistors can be connected to different modulation voltage signal lines 14. For example, the first modulation transistor 13A is connected to the first modulation voltage signal line 14A, and the first modulation voltage signal line 14A is electrically connected to the first voltage signal line 17. The second modulation transistor 13B is connected to the third modulation voltage signal line 14C, and the third modulation voltage signal line 14C is the same signal line as the reference voltage signal line 33. In this way, the wiring path can be kept short, which facilitates a low-impedance, high-reliability connection. However, this configuration is not limited in this respect.

[0278] In some embodiments, the first modulation transistor 13A and the second modulation transistor 13B can also be connected to the same modulation voltage signal line 14. In this case, the first modulation transistor 13A and the second modulation transistor 13B are electrically connected by the same physical wiring, which ensures the consistency of the modulation voltage signal and avoids non-uniform turn-off delays that would be caused by multi-voltage level drift or timing mismatch, thus improving display uniformity.

[0279] In some embodiments, the first modulation transistor 13A and the second modulation transistor 13B can be, as in Fig. Figure 32 shows that the transistors can be connected to different modulation control signal lines 15. For example, the first modulation transistor 13A is connected to the first modulation control signal line 15A, and the first modulation control signal line 15A is electrically connected to either the first clock signal line 35 or the second clock signal line 36; the second modulation transistor 13B is connected to the second modulation control signal line 15B, and the propagation direction of the second modulation control signal line 15B is the same as that of the first sample signal line 11. In this way, the wiring path can be kept short, which facilitates a low-impedance, high-reliability connection. However, this configuration is not limited in this respect.

[0280] In some embodiments, the first modulation transistor 13A and the second modulation transistor 13B can also be connected to the same modulation control signal line 15. In this case, the first modulation transistor 13A and the second modulation transistor 13B are electrically connected by the same physical wiring, so that the same modulation control signal source and the same wiring path are shared. This configuration can eliminate potential problems such as clock offset or uneven driving capability between multiple modulation control signals, enable synchronous pull-up or pull-down operations, and thus contribute to improved display uniformity.

[0281] In some embodiments, the modulation transistors 13, as in Fig. Figure 1 shows only the first modulation transistors 13A, that is, the display board has the first modulation transistors 13A exclusively in the non-display area NAA.

[0282] In some embodiments, the modulation transistors 13, as in Fig. As shown in Figure 19, only the second modulation transistors 13B are included; that is, the display plate has the second modulation transistors 13B exclusively in the display area AA. This is not particularly limited in the embodiment of the present disclosure.

[0283] In some embodiments, the modulation transistors 13 can include both the first modulation transistors 13A and the second modulation transistors 13B. That is, the display board has the first modulation transistors 13A in the non-display area NAA and the second modulation transistors 13B in the display area AA. A suitable configuration can be selected according to the specific application requirements.

[0284] In one or more embodiments, as in Fig. 1 and Fig. Figure 3 shows the multiple modulation transistors 13 and the transistors in the multiple pixel driver circuits 10, all n-type transistors or p-type transistors.

[0285] In one embodiment, the modulation transistors 13 and the transistors in the pixel driver circuits 10 (including, but not limited to, driver transistors T3, first switch transistors T1, and second switch transistors T2) are of the same transistor type, i.e., they are all n-type or all p-type transistors. With this arrangement, the modulation transistors 13 and the transistors in the pixel driver circuits 10 can be manufactured using the same process, which can simplify the process steps and reduce manufacturing costs. Furthermore, transistors of the same type exhibit the same trend in the event of process variations (such as non-uniform layer thickness or changes in the interface density of states), thereby reducing the variation in electrical parameters between sub-pixels or modulation points and thus improving display uniformity and long-term operational stability.

[0286] In some embodiments, as in Fig. 1 and Fig. Figure 3 shows that the modulation transistors 13 and the transistors in the pixel driver circuits 10 are all n-type transistors, for example indium gallium zinc oxide (IGZO) transistors, which have advantages such as low leakage current.

[0287] In some embodiments, the modulation transistors 13 and the transistors in the pixel driver circuits 10 are all p-type transistors, for example low-temperature polycrystalline silicon (LTPS) transistors, which have advantages such as high switching speed, high charge carrier mobility and low power consumption.

[0288] Fig. Figure 33 is a partial cross-sectional diagram of a display plate according to an embodiment of the present disclosure. As in Fig. As shown in Figure 33, the display plate further comprises, for example, several light-emitting elements 20 arranged in an array, and the several light-emitting elements 20 are electrically connected to the several pixel driver circuits 10. A pixel driver circuit 10 comprises a driver transistor T3, and the driver transistor T3 and a light-emitting element 20 are connected in series between a first power voltage signal line 31 and a second power voltage signal line 32. At least one of the modulation transistor 13 or the driver transistor T3 is a dual-port transistor.

[0289] The specific structures and operating procedures of the light-emitting element 20 and the pixel driver circuit 10 can refer to one of the preceding embodiments and are not explained again here.

[0290] In this embodiment, at least one of the modulation transistor 13 or the driver transistor T3 is a dual-port transistor. A dual-port transistor is a thin-film transistor with a gate structure having two independent or common electrodes. In the dual-port transistor, an active layer 1 is arranged between an upper gate 2 and a lower gate 2 (top-gate and bottom-gate structure, as shown in...). Fig. 33), or two gates connected in parallel or in series are arranged on the same side (for example, segmented gates), which can reduce the leakage current of the transistor.

[0291] In some embodiments, the driver transistor T3 features a dual-gate structure. By applying identical or complementary bias potentials to the upper and lower gates, the drain-induced barrier lowering effect (DIBL) and off-state leakage current (Ioff) can be effectively suppressed, thereby improving the stability of the current driving capability and maintaining brightness consistency.

[0292] In some embodiments, the modulation transistor 13 features a dual-port structure, which improves the blocking capability of the modulation transistor 13 in the off state and prevents unintentional pull-down or pull-up caused by the first sampling signal line 11 being at a floating potential during a non-modulation period. Furthermore, in the on state, the dual-port structure can cooperatively increase the transconductance, thereby providing stronger pull-down or pull-up capability and improving the waveform of the first sampling signal scan1 on the first sampling signal line 11.

[0293] It should be noted that, as in Fig. Figure 19 shows that the display plate uses a single-gate line-driving (SGLD) architecture. A key feature of this architecture is that each column of pixel driver circuits 10 exclusively shares a data signal line 16, and each row of pixel driver circuits 10 is controlled only by a first sampling signal line 11.

[0294] However, through investigations, the inventors discovered that when applying the SGLD architecture to higher-resolution and larger-format applications (such as large-format OLED televisions), the number of data signal lines 16 increases significantly, resulting in a large number of required source IC channels. This considerably increases chip costs, packaging costs, and the difficulty and cost of bonding the source IC channels to the display board. Furthermore, numerous data signal lines 16 require more wiring space in a fan-out area at the edge of the display board, severely limiting the narrow bezel design of the bottom (or top) edge of the display board. It is understandable that with increasing resolution and pixel density, the number of data signal lines 16 continues to increase, further exacerbating the aforementioned cost and bezel problems.

[0295] Based on the technical problems described above, for example, the majority of pixel driver circuits arranged in an array comprise 10, as in Fig. 1, Fig. 2, Fig. 3, Fig. 4, Fig. 5, Fig. 6, Fig. 7, Fig. 8, Fig. 9, Fig. 10, Fig. 11, Fig. 12, Fig. 13, Fig. 14, Fig. 15, Fig. 16, Fig. 17 to Fig. Figure 18 shows several pixel driver circuit rows 101 arranged in the column direction Y. A pixel driver circuit row 101 comprises several pixel driver circuit groups 1011 arranged in the row direction X. A pixel driver circuit group 1011 comprises two adjacent pixel driver circuits 10 along the row direction X, which are designated as the first pixel driver circuit 10A and the second pixel driver circuit 10B. In the same pixel driver circuit group 1011, a first pixel driver circuit 10A and a second pixel driver circuit 10B are connected to the same data signal line 16 and to different first sampling signal lines 11.

[0296] As in Fig. 1, Fig. 2, Fig. 3, Fig. 4, Fig. 5, Fig. 6, Fig. 7, Fig. 8, Fig. 9, Fig. 10, Fig. 11, Fig. 12, Fig. 13, Fig. 14, Fig. 15, Fig. 16, Fig. 17 to Fig. As shown in Figure 18, this embodiment uses a dual-gate line-driving (DGLD) architecture. A key feature of this architecture is that, in the same pixel driver circuit group 1011, the first pixel driver circuit 10A and the second pixel driver circuit 10B share the same data signal line 16, but are each connected to two different first sampling signal lines 11.

[0297] Furthermore, the data signal line 16 extends along the column direction Y and provides a data signal for the same column of several pixel driver circuit groups 1011.

[0298] The two first sampling signal lines 11 extend along the row direction X. In the same pixel driver circuit group 1011, the first pixel driver circuit 10A and the second pixel driver circuit 10B are each controlled by the two independent first sampling signal lines 11 (for example, an nth row-first sampling signal line 11 controls the first pixel driver circuit 10A and an (n + 1)th first sampling signal line 11 controls the second pixel driver circuit 10B).

[0299] In the row direction X, one data signal line 16 is arranged for each pair of pixel driver circuits 10; in the column direction Y, each row of pixel driver circuits 10 corresponds to two independent first sampling signal lines 11. This arrangement can reduce the number of data signal lines 16 to half that of a conventional RGB arrangement (in which each column of pixel driver circuits 10 is assigned one data signal line 16).

[0300] With this arrangement, in the same image frame cycle, a first scanning signal scan1, which controls the first pixel driver circuit 10A, and a first scanning signal scan1, which controls the second pixel driver circuit 10B, are designed such that their switch-on voltages V11 occur at different times.

[0301] When the first sampling signal scan1, which controls the first pixel driver circuit 10A, is at the turn-on voltage V11, a first switching transistor T1 of the first pixel driver circuit 10A is turned on. In this case, a data signal DATA, corresponding to the first pixel driver circuit 10A, is transmitted on the data signal line 16 and written to a gate of a driver transistor T3 of the first pixel driver circuit 10A.

[0302] Subsequently, when the first sampling signal scan1, which controls the first pixel driver circuit 10A, is at the off voltage V12, and the first sampling signal scan1, which controls the second pixel driver circuit 10B, is at the on voltage V11, a first switching transistor T1 of the second pixel driver circuit 10B is turned on. In this case, a data signal DATA, corresponding to the second pixel driver circuit 10B, is transmitted on the data signal line 16 and written to a gate of a driver transistor T3 of the second pixel driver circuit 10B.

[0303] Therefore, the same data signal line 16 writes the data signals DATA successively to the first pixel driver circuit 10A and the second pixel driver circuit 10B within the same pixel driver circuit group 1011 by temporal reuse.

[0304] In this embodiment, since two columns of pixel driver circuits 10 share a data signal line 16, the total number of data signal lines 16 required for the entire display plate can be reduced by almost 50%. This allows the required number of source IC channels to be halved, significantly reducing chip costs, packaging costs, and the difficulty and cost of bonding the source IC channels to the display plate. Furthermore, the wiring space required for the data signal line 16 in the output area can be reduced, which helps to narrow the bottom bezel and achieve a slim bezel design.

[0305] It should be noted that the inventors discovered through further investigations that in the DGLD architecture, two data signal write operations must be completed within a single line sampling period (1H) by temporal reuse (for example, the first pixel driver circuit 10A and the second pixel driver circuit 10B in the same pixel driver circuit group 1011 must each be written with data signals). Therefore, each first sampling signal line 11 must switch the first sampling signal scan1 between the turn-on voltage V11 and the turn-off voltage V12 faster and more accurately.

[0306] In one embodiment, if the fall-off edge of a first scan signal scan1, which controls a specific row of pixel driver circuits 10, is slowed down, the first switching transistors T1 corresponding to that row of pixel driver circuits 10 cannot be fully switched off in time. If a data signal on a data signal line 16 subsequently switches to a data signal for the next row, the data signal for the next row is erroneously written to the current row of pixel driver circuits 10 due to the first switching transistors T1 of the current row not yet being fully switched off, resulting in significant data crosstalk. In the DGLD architecture, the probability of data crosstalk is significantly increased because two columns of pixel driver circuits 10 share the same data signal line 16.

[0307] Therefore, a delay of the rise / fall edge or a waveform degradation of a first sampling signal scan1 on any first sampling signal line 11 affects the data signal write operation of the current row of pixel driver circuits 10 and can, moreover, directly interfere with the precise data signal write operation of adjacent rows / columns of pixel driver circuits 10 via the shared data signal line 16, causing complex display anomalies.

[0308] Furthermore, the requirements for high resolution and high frame rates continuously compress the line sampling period (1H). Therefore, under the DGLD architecture, it is necessary to further shorten the duration of the switching stage T0 between the turn-on voltage V11 and the turn-off voltage V12 of the first sampling signal scan1 in order to provide a sufficiently effective time window for two data signal writes of the same line by pixel driver circuits 10 and to ensure that each pixel driver circuit 10 receives sufficient loading time within the limited line sampling period (1H).

[0309] It should be noted that the solution of arranging a modulation transistor 13 in the foregoing embodiment of the present disclosure can effectively satisfy the aforementioned requirements of the DGLD architecture. In one embodiment, by configuring a separate modulation transistor 13 for each first sampling signal line 11 in the switching stage T0, where the first sampling signal scan1 must switch from the turn-on voltage V11 to the turn-off voltage V12, a strong active pull-down or pull-up function can be provided, thereby accelerating the switching of the first sampling signal scan1 and significantly reducing the duration of the switching stage T0. This can reduce the time window in which the first switching transistors T1 are not completely turned off, decrease the possibility of data crosstalk, and ensure the accuracy of the data signal written to the pixel driver circuits 10.In this way, while simultaneously reducing costs through the DGLD architecture, clearer data signal write boundaries can be achieved, the risk of data crosstalk is eliminated and the impairment of display quality is reduced, thus facilitating the stable application of the DGLD architecture in high-performance and high-resolution display products.

[0310] In one or more embodiments, the display plate comprises, as in Fig. Figure 3 shows several light-emitting elements 20 arranged in an array, and these elements are electrically connected to several pixel driver circuits 10. A pixel driver circuit 10 comprises a driver transistor T3, a first switching transistor T1, and a second switching transistor T2. The driver transistor T3 and a light-emitting element 20 are connected in series between a first power voltage signal line 31 and a second power voltage signal line 32. A gate of the driver transistor T3 is electrically connected to a first terminal t11 of the first switching transistor T1, a second terminal t12 of the first switching transistor T1 is electrically connected to a data signal line 16, and a gate of the first switching transistor T1 is electrically connected to the first sampling signal line 11.A first terminal t21 of the second switching transistor T2 is electrically connected to a first terminal t31 of the driver transistor T3, a second terminal t22 of the second switching transistor T2 is electrically connected to a reference voltage signal line 33, and a gate of the second switching transistor T2 is electrically connected to a second sampling signal line 34. The first sampling signal line 11 is the same line as, or different from, the second sampling signal line 34.

[0311] The specific structures of the light-emitting element 20 and the pixel driver circuit 10 can refer to one of the preceding embodiments and are not explained again here.

[0312] In some embodiments, as in Fig. 3 and Fig. Figure 14 shows that the first sampling signal line 11 may be a different line than the second sampling signal line 34, and its operating procedures may refer to the foregoing embodiments and are not explained again here.

[0313] Fig. Figure 34 is another diagram illustrating the structure of a pixel driver circuit according to an embodiment of the present disclosure. Fig. Figure 35 is another operating timing diagram of a pixel driver circuit according to an embodiment of the present disclosure. As in Fig. 34 and Fig. As shown in Figure 35, for example, the first sampling signal line 11 is the same signal line as the second sampling signal line 34. In this case, the operating cycle of the pixel driver circuit 10 can include a data write stage Tw and the light emitting stage Te.

[0314] In the data write stage Tw, the first sample signal scan1, provided by the first sample signal line 11, is held at the turn-on voltage V11, and the first switching transistor T1 is turned on due to the turn-on voltage V11, so that the data voltage (data) of the data signal DATA on data signal line 16 is applied to the gate of the driver transistor T3. The second switching transistor T2 is turned on due to the turn-on voltage V11, so that the reference voltage vref of the reference voltage signal VREF on reference voltage signal line 33 is applied to the first terminal t31 of the driver transistor T3.

[0315] In the light emission stage Te, the first sampling signal scan1, provided by the first sampling signal line 11, is held at the turn-off voltage V12, thus turning off the first switching transistor T1 and the second switching transistor T2. The first power voltage PVDD charges the source of driver transistor T3 via driver transistor T3, causing the source voltage to gradually increase. Due to the coupling effect of the first capacitor C1, the gate voltage of driver transistor T3 is also increased accordingly, and the gate-source voltage of driver transistor T3 is essentially held at the voltage value (data - vref) stored in the data write stage Tw. When the source voltage rises above the operating point voltage of the light-emitting element 20, a driver current flows through the light-emitting element 20, exciting it to emit light.The magnitude of the driver current is determined by the gate-source voltage of the driver transistor T3, thereby achieving the desired grayscale display.

[0316] In this embodiment, combining the first sampling signal line 11 and the second sampling signal line 34 into the same signal line can reduce the wiring of a sampling signal line, which can reduce layout complexity, increase the aperture ratio and decrease coupling capacitances between signal lines, thereby improving display uniformity.

[0317] Fig. Figure 36 is a diagram illustrating the layer structure of a pixel driver circuit in a display panel according to an embodiment of the present disclosure. Fig. 37 is a diagram showing the structure of a first metal layer in the Fig. 36 pixel driver circuits are illustrated. Fig. 38 is a diagram showing the structure of a second metal layer in the Fig. 36 pixel driver circuits are illustrated. Fig. 39 is a diagram showing the structure of a third metal layer in the Fig. 36 pixel driver circuits are illustrated. Fig. 40 is a diagram showing the structure of a semiconductor layer in the Fig. 36 pixel driver circuits are illustrated. Fig. 41 is a diagram showing the structure of a fourth metal layer in the Fig. 36 pixel driver circuits are illustrated. Fig. 42 is a diagram showing the structure of a fifth metal layer in the Fig. 36 pixel driver circuits are illustrated. Fig. 43 is a diagram showing the structure of a sixth metal layer in the Fig. 36 pixel driver circuits are illustrated. Fig. 44 is a diagram that shows the stacked structure of layers in the Fig. 36 pixel driver circuits are illustrated. As shown in Fig. 36, Fig. 37, Fig. 38, Fig. 39, Fig. 40, Fig. 41, Fig. 42, Fig. 43 to Fig. As shown in Figure 44, for example, a first metal layer Gate1, a second metal layer Gate2, a third metal layer Gate3, a semiconductor layer 31, a fourth metal layer MG, a fifth metal layer SD1, and a sixth metal layer SD2 are stacked sequentially on one side of the base substrate 100. Fig. 2, Fig. 31, Fig. 33 and Fig. As shown in Figure 36, an insulating layer 30 can be provided between any two adjacent conductive layers to prevent a short circuit between the two adjacent conductive layers.

[0318] It should be noted that the in Fig. 36, Fig. 37, Fig. 38, Fig. 39, Fig. 40, Fig. 41, Fig. 42, Fig. 43 to Fig. 44 layer structure shown in Fig. 34 can correspond to the pixel driver circuit 10 shown, in which the first switching transistor T1, the second switching transistor T2 and the driver transistor T3 are all indium gallium zinc oxide (IGZO) transistors, but this is not limited here.

[0319] In one or more embodiments, as in Fig. 37, Fig. 38, Fig. 39, Fig. 40, Fig. 41, Fig. 42, Fig. 43 to Fig. Figure 44 shows a first plate c11 of the first capacitor C1 arranged in the first metal layer Gate1, and a second plate c12 of the first capacitor C1 arranged in the second metal layer Gate2.

[0320] A lower gate 21 of the driver transistor T3 is located in the third metal layer Gate3.

[0321] The active layers of the first switching transistor T1, the second switching transistor T2, and the driver transistor T3 are arranged in the semiconductor layer 31. The semiconductor layer 31 can consist of indium gallium zinc oxide (IGZO), but this is not the limit.

[0322] An upper gate 22 of the driver transistor T3, the gate 2 of the first switch transistor T1 and the gate 2 of the second switch transistor T2 are arranged in the fourth metal layer MG.

[0323] The first sampling signal line 11, which extends along the line direction, lateral auxiliary lines of the second power voltage signal line 32 and lateral auxiliary lines of the reference voltage signal line 33 are arranged in the fifth metal layer SD1.

[0324] The data signal line 16, which extends along the column direction, the first power voltage signal line 31 and the second power voltage signal line 32 are arranged in the sixth metal layer SD2.

[0325] It should be noted that adaptive adjustments can be made to the specific layer arrangement of the display plate according to actual requirements, such as adding or removing certain layers, which is not specifically limited in this embodiment.

[0326] Based on the same inventive concept, an embodiment of the present disclosure further provides a display device. Fig. Figure 45 is a diagram illustrating the structure of a display device according to an embodiment of the present disclosure. As in Fig. As shown in Figure 45, the display device 40 comprises the display plate 41 according to any embodiment of the present disclosure. Therefore, the display device 40 provided in this embodiment exhibits the technical effects of the technical solutions according to any foregoing embodiment, and structures corresponding to or similar to the structures in the foregoing embodiments, as well as the explanation of the terms, are not described again herein.

[0327] The display device 40 provided in this embodiment can be a mobile phone, as shown in Fig.45 shown, or any other electronic product with a display function. The electronic product includes, but is not limited to, a television, a laptop, a desktop monitor, a tablet, a digital camera, a smart bracelet, smart glasses, an in-vehicle display, a medical device, an industrial control unit, or an interactive touch terminal. The display device 40 is not specifically limited in the embodiment of the present disclosure.

[0328] It is understood that various of the above-described process variants can be adopted, whereby steps are rearranged, added, or removed. For example, the steps described in this disclosure can be carried out in parallel, sequentially, or in different orders, as long as the desired results of the technical solutions of this disclosure are achieved. No restriction is imposed here.

[0329] The foregoing embodiments do not limit the scope of protection of the present disclosure. Those skilled in the art can understand that various modifications, combinations, sub-combinations, and substitutions may be made according to design requirements and other factors. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present disclosure fall within the scope of protection of the present disclosure.

Claims

[1] Display plate, comprising: a plurality of pixel driver circuits (10) arranged in an array; a plurality of first scanning signal lines (11), wherein the plurality of first scanning signal lines (11) are electrically connected to the plurality of pixel driver circuits (10) and are configured to provide first scanning signals (scan1) to the plurality of pixel driver circuits (10); a plurality of shift register units (12), wherein the plurality of shift register units (12) are cascaded, each electrically connected to the plurality of first sampling signal lines (11) and configured to output the first sampling signals (scan1) to the plurality of first sampling signal lines (11), wherein voltages of a first sampling signal (scan1) of the first sampling signals (scan1) comprise a turn-on voltage (V11) and a turn-off voltage (V12); a plurality of modulation transistors (13), wherein a first terminal (131) of a modulation transistor (13) of the plurality of modulation transistors (13) is electrically connected to a first sampling signal line (11) of the plurality of first sampling signal lines (11); a plurality of modulation voltage signal lines (14), wherein one modulation voltage signal line (14) of the plurality of Modulation voltage signal lines (14) are electrically connected to a second terminal (132) of the modulation transistor (13) and are configured to provide a modulation voltage to the second terminal (132) of the modulation transistor (13); and a plurality of modulation control signal lines (15), wherein a The modulation control signal line (15) of the plurality of modulation control signal lines (15) is electrically connected to a gate of the modulation transistor (13) and is configured, to provide a modulation control signal (K0) to the gate of the modulation transistor (13), and the modulation control signal (K0) includes a valid pulse, and the valid pulse is configured to control the modulation transistor (13) to turn on, wherein a switching stage (T0) between the turn-on voltage (V11) of the first sampling signal (scan1) and the turn-off voltage (V12) of the first sampling signal (scan1) overlaps with the valid pulse (K01) of the modulation control signal (K0). [2] Display plate according to claim 1, wherein the switch-on voltage (V11) is higher than the switch-off voltage (V12); and the modulation voltage is lower than the turn-on voltage (V11). [3] Display plate according to claim 1, wherein the switch-on voltage (V11) is lower than the switch-off voltage (V12); and the modulation voltage is higher than the turn-on voltage (V11). [4] The display plate according to claim 1, wherein the display plate further comprises a first voltage signal line (17) and a second voltage signal line (18); a shift register unit (12) of the plurality of shift register units (12) comprises a first transistor (M1) and a second transistor (M2); a first terminal (m11) of the first transistor (M1) is electrically connected to the first voltage signal line (17), a second terminal of the first transistor (M1) is electrically connected to the first sampling signal line (11), and the first transistor (M1) is configured to provide a first voltage (VGH) on the first voltage signal line (17) of the first sampling signal line (11); a first terminal (m21) of the second transistor (M2) is electrically connected to the second voltage signal line (18), a second terminal (m22) of the second transistor (M2) is electrically connected to the first sampling signal line (11), and the second transistor (M2) is configured to provide a second voltage (VGL) on the second voltage signal line (18) of the first sampling signal line (11); the first voltage (VGH) is higher than the second voltage (VGL); the plurality of modulation voltage signal lines (14) includes a first modulation voltage signal line (14); and the first modulation voltage signal line (14) is electrically connected to the first voltage signal line (17) and the modulation voltage is identical to the first voltage (VGH); or the first modulation voltage signal line (14) is electrically connected to the second voltage signal line (18) and the modulation voltage is identical to the second voltage (VGL). [5] The display plate according to claim 1, wherein the display plate further comprises a plurality of light-emitting elements (20) arranged in an array, and the plurality of light-emitting elements (20) is electrically connected to the plurality of pixel driver circuits (10); the display plate further comprises a plurality of first power voltage signal lines (31) and a plurality of second power voltage signal lines (32); a pixel driver circuit (10) of the plurality of pixel driver circuits (10) comprises a driver transistor (T3), and the driver transistor (T3) and a light-emitting element (20) of the plurality of light-emitting elements (20) are connected in series between a first power voltage signal line (31) of the plurality of first power voltage signal lines (31) and a second power voltage signal line (32) of the plurality of second power voltage signal lines (32); a first power voltage transmitted through the first power voltage signal line (31) is higher than a second power voltage transmitted through the second power voltage signal line (32); the plurality of modulation voltage signal lines (14) includes a second modulation voltage signal line (14); and the second modulation voltage signal line (14) is the same signal line as the first power voltage signal line (31) and the modulation voltage is identical to the first power voltage; or the second modulation voltage signal line (14) is the same signal line as the second power voltage signal line (32) and the modulation voltage is identical to the second power voltage. [6] The display plate according to claim 1, further comprising a plurality of light-emitting elements (20) arranged in an array, wherein the plurality of light-emitting elements (20) is electrically connected to the plurality of pixel driver circuits (10); a pixel driver circuit (10) of the plurality of pixel driver circuits (10) comprises a driver transistor (T3), a first switching transistor (T1) and a second switching transistor (T2), and the driver transistor (T3) and a light-emitting element (20) of the plurality of light-emitting elements (20) are connected in series between a first power voltage signal line (31) of a plurality of first power voltage signal lines (31) and a second power voltage signal line (32) of a plurality of second power voltage signal lines (32); a gate of the driver transistor (T3) is electrically connected to a first terminal (t11) of the first switch transistor (T1), a second terminal (t12) of the first switch transistor (T1) is electrically connected to a data signal line (16) of a plurality of data signal lines (16), and a gate of the first switch transistor (T1) is electrically connected to the first sampling signal line (11); a first terminal (t21) of the second switching transistor (T2) is electrically connected to a first terminal (t31) of the driver transistor (T3), a second terminal (t22) of the second switching transistor (T2) is electrically connected to a reference voltage signal line (33) of a plurality of reference voltage signal lines (33), and a gate of the second switching transistor (T2) is electrically connected to a second sampling signal line (34) of a plurality of second sampling signal lines (34); and the plurality of modulation voltage signal lines (14) includes a plurality of third modulation voltage signal lines (14), and a third modulation voltage signal line (14) of the plurality of third modulation voltage signal lines (14) is the same signal line as the reference voltage signal line (33) to provide the modulation voltage via the reference voltage signal line (33) to the modulation transistor (13). [7] The display plate according to claim 6, wherein the pixel driver circuit (10) has a light emission stage (Te) in which the first switching transistor (T1) and the second switching transistor (T2) are switched off; in a control stage of the second switch transistor (T2) a reference voltage is transmitted on the reference voltage signal line (33); in the light emission stage (Te) the modulation voltage is transmitted on the reference voltage signal line (33); and the reference voltage differs from the modulation voltage. [8] The display plate according to claim 1, wherein the display plate further comprises a first clock signal line (35) and a second clock signal line (36); the first clock signal line (35) is electrically connected to the plurality of shift register units (12) and is configured to provide a first clock signal to the plurality of shift register units (12); the second clock signal line (36) is electrically connected to the plurality of shift register units (12) and is configured to provide a second clock signal to the plurality of shift register units (12); the first clock signal and the second clock signal are inverted relative to each other; the plurality of modulation control signal lines (15) includes a first modulation control signal line (15); and the first modulation control signal line (15) is electrically connected to the first clock signal line (35) and the modulation control signal (K0) is identical to the first clock signal (CK); or the first modulation control signal line (15) is electrically connected to the second clock signal line (36) and the modulation control signal (K0) is identical to the second clock signal (XCK). [9] The display plate according to claim 1, comprising a display area (AA), wherein the plurality of modulation control signal lines (15) further comprises a plurality of second modulation control signal lines (15) which are located at least partially in the display area (AA); and wherein a direction of extension of the plurality of second modulation control signal lines (15) is the same as a direction of extension of the plurality of first sampling signal lines (11). [10] The display plate according to claim 9, further comprising a plurality of modulation control signal generation units (37), wherein an input terminal of a modulation control signal generation unit (37) of the plurality of modulation control signal generation units (37) is electrically connected to the first sampling signal line (11) to receive the first sampling signal (scan1); wherein an output terminal of the modulation control signal generation unit (37) is electrically connected to a second modulation control signal line (15) of the plurality of second modulation control signal lines (15); and wherein the modulation control signal generation unit (37) is configured to provide the modulation control signal (K0) to the second modulation control signal line (15). [11] The display plate according to claim 9, further comprising a non-display area (NAA) located on at least one side of the display area (AA), wherein the non-display area (NAA) comprises a first non-display area (NAA1) and a second non-display area (NAA2), each located on two opposite sides of the display area (AA); and the display plate further comprises a variety of modulation control signal generation units (37), wherein an output terminal of a modulation control signal generation unit (37) of the plurality of modulation control signal generation units (37) is electrically connected to a second modulation control signal line (15) of the plurality of second modulation control signal lines (15); wherein the modulation control signal generation unit (37) is configured to provide the modulation control signal (K0) to the second modulation control signal line (15); wherein the plurality of shift register units (12) is arranged in the first non-display area (NAA1); and wherein the plurality of modulation control signal generation units (37) is arranged in the second non-display area (NAA2). [12] The display plate according to claim 1, wherein a start time of the valid pulse (K01) of the modulation control signal (K0) is identical to a start time of the switching stage of the first sample signal (scan1). [13] The display plate according to claim 1, wherein a pulse width of the valid pulse (K01) of the modulation control signal (K0) is shorter than a duration of the off-voltage (V12) of the first sampling signal (scan1). [14] The display plate according to claim 1, further comprising a plurality of light-emitting elements (20) arranged in an array, wherein the plurality of light-emitting elements (20) is electrically connected to the plurality of pixel driver circuits (10); a pixel driver circuit (10) of the plurality of pixel driver circuits (10) comprises a driver transistor (T3), a first switching transistor (T1) and a second switching transistor (T2), and the driver transistor (T3) and a light-emitting element (20) of the plurality of light-emitting elements (20) are connected in series between a first power voltage signal line (31) of a plurality of first power voltage signal lines (31) and a second power voltage signal line (32) of a plurality of second power voltage signal lines (32); a gate of the driver transistor (T3) is electrically connected to a first terminal (t11) of the first switch transistor (T1), a second terminal (t12) of the first switch transistor (T1) is electrically connected to a data signal line (16) of a plurality of data signal lines (16), and a gate of the first switch transistor (T1) is electrically connected to the first sampling signal line (11); a first terminal (t21) of the second switching transistor (T2) is electrically connected to a first terminal of the driver transistor (T3), a second terminal (t22) of the second switching transistor (T2) is electrically connected to a reference voltage signal line (33) of a plurality of reference voltage signal lines (33), and a gate of the second switching transistor (T2) is electrically connected to a second sampling signal line (34) of a plurality of second sampling signal lines (34); the pixel driver circuit (10) has a light emission stage (Te) in which the first switching transistor (T1) and the second switching transistor (T2) are switched off; and a pulse width of the valid pulse (K01) of the modulation control signal (K0) is shorter than a duration of the light emission stage (Te). [15] The display plate according to claim 1, further comprising a display area (AA) and a non-display area (NAA) located on at least one side of the display area (AA), wherein the plurality of modulation transistors (13) comprises a plurality of first modulation transistors (13) and the plurality of first modulation transistors (13) is arranged in the non-display area (NAA); and wherein a shift register unit (12) of the plurality of shift register units (12) is connected to a first end (111) of the first sampling signal line (11) and a first modulation transistor (13) of the plurality of first modulation transistors (13) is connected to a second end (112) of the first sampling signal line (11). [16] The display plate according to claim 15, further comprising a plurality of light-emitting elements (20) arranged in an array, wherein the plurality of light-emitting elements (20) is electrically connected to the plurality of pixel driver circuits (10); a pixel driver circuit (10) of the plurality of pixel driver circuits (10) comprises a driver transistor (T3) and a first switching transistor (T1), and the driver transistor (T3) and a light-emitting element (20) of the plurality of light-emitting elements (20) are connected in series between a first power voltage signal line (31) of a plurality of first power voltage signal lines (31) and a second power voltage signal line (32) of a plurality of second power voltage signal lines (32); a gate of the driver transistor (T3) is electrically connected to a first terminal (t11) of the first switch transistor (T1), a second terminal (t12) of the first switch transistor (T1) is electrically connected to a data signal line (16) of a plurality of data signal lines (16), and a gate of the first switch transistor (T1) is electrically connected to the first sampling signal line (11); and a channel width-to-channel length ratio of the first modulation transistor (13) is greater than or equal to a channel width-to-channel length ratio of the first switching transistor (T1). [17] The display plate according to claim 1, further comprising a display area (AA), wherein the plurality of modulation transistors (13) comprises a plurality of second modulation transistors (13) and the plurality of second modulation transistors (13) is arranged in the display area (AA). [18] The display plate according to claim 17, wherein the first sampling signal line (11) is connected to a second modulation transistor (13) of the plurality of second modulation transistors (13); a shift register unit (12) of the plurality of shift register units (12) is connected to a first end (111) of the first sampling signal line (11); and a length of the first sampling signal line (11) L1 is and a distance between the second modulation transistor (13) and a second end (112) of the first sampling signal line (11) D1 is, where D1 ≤ L1 / 3. [19] The display plate according to claim 17, wherein the first sampling signal line (11) is connected to N second modulation transistors (13) of the plurality of second modulation transistors (13), where N ≥ 2; a shift register unit (12) of the plurality of shift register units (12) is connected to a first end (111) of the first sampling signal line (11); and a length of the first sampling signal line (11) L1 and a distance between a second end (112) of the first sampling signal line (11) and a second modulation transistor (13) of the N second modulation transistors (13) that is closest to the second end (112) of the first sampling signal line (11) is D2, where D2 ≤ L1 / (N + 1). [20] The display plate according to claim 17, wherein the first sampling signal line (11) is connected to N second modulation transistors (13) of the plurality of second modulation transistors (13), wherein N ≥ 2, and the N second modulation transistors (13) are arranged uniformly along one extension direction of the first sampling signal line (11). [21] The display plate according to claim 17, further comprising a non-display area (NAA) located on at least one side of the display area (AA), wherein the non-display area (NAA) comprises a first non-display area (NAA1) located on one side of the display area (AA), and the plurality of shift register units (12) are arranged in the first non-display area (NAA1); wherein the display area (AA) comprises a first display area (AA1) and a second display area (AA2), wherein the first display area (AA1) and the second display area (AA2) are arranged along a direction of extension of the first scanning signal line (11) and the first display area (AA1) is located on a side of the second display area (AA2) facing the first non-display area (NAA1); and wherein the first sampling signal line (11) is connected to N second modulation transistors (13) of the plurality of second modulation transistors (13), where N ≥ 2, and among the N second modulation transistors (13) a distribution density of second modulation transistors (13) in the first display area (AA1) is less than a distribution density of second modulation transistors (13) in the second display area (AA2). [22] The display plate according to claim 17, further comprising a non-display area (NAA) located on at least one side of the display area (AA), wherein the non-display area (NAA) comprises a first non-display area (NAA1) and a second non-display area (NAA2), each located on two opposite sides of the display area (AA); wherein the plurality of shift register units (12) comprises a plurality of cascaded first shift register units (12) and a plurality of cascaded second shift register units (12); wherein the plurality of first shift register units (12) is arranged in the first non-display area (NAA1) and the plurality of second shift register units (12) is arranged in the second non-display area (NAA2); wherein the display area (AA) comprises a first display area (AA1), a second display area (AA2) and a third display area (AA3), wherein the first display area (AA1), the second display area (AA2) and the third display area (AA3) are arranged along a direction of extension of the first scanning signal line (11) and the second display area (AA2) is arranged between the first display area (AA1) and the third display area (AA3); wherein the first sampling signal line (11) is connected to N second modulation transistors (13) of the plurality of second modulation transistors (13), where N ≥ 2; and where among the N second modulation transistors (13) a distribution density of second modulation transistors (13) in the second display area (AA2) is greater than a distribution density of second modulation transistors (13) in the first display area (AA1) and a distribution density of second modulation transistors (13) in the third display area (AA3). [23] The display plate according to claim 17, wherein a number of pixel driver circuits (10) of the plurality of pixel driver circuits (10) connected to the first sampling signal line (11) is equal to a number of second modulation transistors (13) of the plurality of second modulation transistors (13) connected to the first sampling signal line (11). [24] The display plate according to claim 17, further comprising a plurality of light-emitting elements (20) arranged in an array, wherein the plurality of light-emitting elements (20) is electrically connected to the plurality of pixel driver circuits (10); a pixel driver circuit (10) of the plurality of pixel driver circuits (10) comprises a driver transistor (T3) and a first switching transistor (T1), and the driver transistor (T3) and a light-emitting element (20) of the plurality of light-emitting elements (20) are connected in series between a first power voltage signal line (31) of a plurality of first power voltage signal lines (31) and a second power voltage signal line (32) of a plurality of second power voltage signal lines (32); a gate of the driver transistor (T3) is electrically connected to a first terminal (t11) of the first switch transistor (T1), a second terminal (t12) of the first switch transistor (T1) is electrically connected to a data signal line (16) of a plurality of data signal lines (16), and a gate of the first switch transistor (T1) is electrically connected to the first sampling signal line (11); and a channel width-to-channel length ratio of a second modulation transistor (13) of the plurality of second modulation transistors (13) is less than or equal to a channel width-to-channel length ratio of the first switching transistor (T1). [25] The display plate according to claim 17, wherein the first sampling signal line (11) is connected to at least two second modulation transistors (13) of the plurality of second modulation transistors (13); comprising at least two second modulation transistors (13) connected to the same first sampling signal line (11) of the plurality of first sampling signal lines (11), a second nearby modulation transistor (13) and a second remote modulation transistor (13); a distance between the second nearby modulation transistor (13) and a shift register unit (12) of the plurality of shift register units (12) is smaller than a distance between the second most distant modulation transistor (13) and the shift register unit; and a channel width-to-channel length ratio of the second nearby modulation transistor (13) is smaller than a channel width-to-channel length ratio of the second distant modulation transistor (13). [26] The display plate according to claim 17, further comprising a base substrate and a plurality of light-emitting elements (20) located on one side of the base substrate, wherein drive electrodes of the plurality of light-emitting elements (20) are electrically connected to the plurality of pixel driver circuits (10); and perpendicular projections of the plurality of second modulation transistors (13) onto the base substrate do not overlap with perpendicular projections of the drive electrodes of the plurality of light-emitting elements (20) onto the base substrate. [27] The display plate according to claim 1, further comprising a display area (AA) and a non-display area (NAA) located on at least one side of the display area (AA), wherein the plurality of modulation transistors (13) comprises a plurality of first modulation transistors (13) and a plurality of second modulation transistors (13); wherein the plurality of first modulation transistors (13) is arranged in the non-display area (NAA) and the plurality of second modulation transistors (13) is arranged in the display area (AA); and wherein a channel width-to-channel length ratio of a first modulation transistor (13) of the plurality of first modulation transistors (13) is greater than or equal to a channel width-to-channel length ratio of a second modulation transistor (13) of the plurality of second modulation transistors (13). [28] The display plate according to claim 1, wherein the plurality of modulation transistors (13) and transistors in the plurality of pixel driver circuits (10) are all n-type transistors or p-type transistors. [29] The display plate according to claim 1, further comprising a plurality of light-emitting elements (20) arranged in an array, wherein the plurality of light-emitting elements (20) is electrically connected to the plurality of pixel driver circuits (10); a pixel driver circuit (10) of the plurality of pixel driver circuits (10) comprises a driver transistor (T3), and the driver transistor (T3) and a light-emitting element (20) of the plurality of light-emitting elements (20) are connected in series between a first power voltage signal line (31) of a plurality of first power voltage signal lines (31) and a second power voltage signal line (32) of a plurality of second power voltage signal lines (32); and at least one of the modulation transistor (13) or the driver transistor (T3) is a double-port transistor. [30] The display plate according to claim 1, wherein the plurality of pixel driver circuits (10) arranged in an array further comprises a plurality of pixel driver circuit rows arranged in a column direction; a pixel driver circuit row of the plurality of pixel driver circuit rows comprises a plurality of pixel driver circuit groups (1011) arranged in a row direction; a pixel driver circuit group (1011) of the plurality of pixel driver circuit groups (1011) comprises two adjacent pixel driver circuits (10) along the row direction, which are referred to as the first pixel driver circuit (10) and the second pixel driver circuit (10); and in the same pixel driver circuit group (1011) of the plurality of pixel driver circuit groups (1011) the first pixel driver circuit (10) and the second pixel driver circuit (10) are connected to the same data signal line (16) of the plurality of data signal lines (16) and to different first sampling signal lines (11) of the plurality of first sampling signal lines (11). [31] The display plate according to claim 30, wherein the display plate further comprises a plurality of light-emitting elements (20) arranged in an array, and the plurality of light-emitting elements (20) is electrically connected to the plurality of pixel driver circuits (10); a pixel driver circuit (10) of the plurality of pixel driver circuits (10) comprises a driver transistor (T3), a first switching transistor (T1) and a second switching transistor (T2), and the driver transistor (T3) and a light-emitting element (20) of the plurality of light-emitting elements (20) are connected in series between a first power voltage signal line (31) of a plurality of first power voltage signal lines (31) and a second power voltage signal line (32) of a plurality of second power voltage signal lines (32); a gate of the driver transistor (T3) is electrically connected to a first terminal (t11) of the first switch transistor (T1), a second terminal (t12) of the first switch transistor (T1) is electrically connected to a data signal line (16) of the plurality of data signal lines (16), and a gate of the first switch transistor (T1) is electrically connected to the first sampling signal line (11); a first terminal (t21) of the second switching transistor (T2) is electrically connected to a first terminal of the driver transistor (T3), a second terminal (t22) of the second switching transistor (T2) is electrically connected to a reference voltage signal line (33) of a plurality of reference voltage signal lines (33), and a gate of the second switching transistor (T2) is electrically connected to a second sampling signal line (34) of a plurality of second sampling signal lines (34); and the first sampling signal line (11) is the same signal line as or a different signal line than the second sampling signal line (34). [32] Display device comprising the display plate according to any one of claims 1 to 31.

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