NON-VOLATILE TRANSISTOR, NON-VOLATILE TRANSISTOR ASSEMBLY, AND NON-VOLATILE TRANSISTOR MATRIX

Abstract

NON-VOLATILE TRANSISTOR, ASSEMBLY OF NON-VOLATILE TRANSISTORS AND MATRIX OF NON-VOLATILE TRANSISTORS The invention relates to a non-volatile transistor (10) comprising a ferroelectric semiconductor layer (11) comprising a ferroelectric domain (12) exhibiting a spontaneous electrical bias (13) capable of taking a plurality of distinct states, a source (14), a gate (15) and a drain (16).The source (14), gate (15), and drain (16) are spaced apart and arranged such that an electrical potential applied between the source (14) and the gate (15) applies an electric field to the ferroelectric domain (12). The drain (16) is in electrical contact with the ferroelectric layer (11). The source (14) forms, with the ferroelectric layer (11), a Schottky barrier (17) at an interface between the source (14) and the ferroelectric layer (11). This barrier has an electrical resistance that is a function of the electrical bias (13). The transistor is such that the ferroelectric semiconductor layer (11) is degenerate at the interface between the source (14) and the ferroelectric layer (11), and the ferroelectric semiconductor layer (11) has an electrical conductivity independent of the spontaneous bias (13). Figure to be published with the abbreviation: Figure 1.

Description

Title of the invention: NON-VOLATILE TRANSISTOR, ASSEMBLY OF NON-VOLATILE TRANSISTORS AND NON-VOLATILE TRANSISTOR MATRIX TECHNICAL FIELD OF THE INVENTION

[0001] The technical field of the invention is that of memory and logic computing devices, and in particular of non-volatile transistors. It also relates to assemblies and matrices formed from such transistors. TECHNOLOGICAL BACKGROUND OF THE INVENTION

[0002] The main interest of the microelectronics and semiconductor industry is to continuously increase the computing power and storage capacity of digital devices. To achieve this, one solution used until now was to reduce the size of transistors in order to increase their number on the same surface area.

[0003] Currently, transistors have reached sizes at which quantum effects come into play. These currents increase the overall operating power consumption of the transistors and therefore prevent their size from being reduced.

[0004] To reduce the energy consumption of the computing and memory units and to allow their capacities to be increased further, it has become necessary to find an alternative to conventional logic transistors (such as so-called "CMOS", "DRAM", "SRAM", and "NAND flash" transistors) through the use of new physical phenomena.

[0005] An electronic circuit architecture used for several decades is called the "von Neumann architecture." It physically separates information storage areas, such as non-volatile and volatile memory (also called "RAM" for "Random Access Memory"), from processing units (also called "CPUs" for "Central Processing Unit"). This physical separation can be several centimeters in a computer. The information stored in memory must then be transferred to the processing unit, and the result of the calculation must be transferred back to memory. These transfers consume both time and energy.

[0006] To reduce the energy consumption of electronic circuit architectures and increase their performance, it has become necessary to find an alternative to the von Neumann architecture.

[0007] New architectures are proposed for, for example, performing calculations directly in memory, known as "in-memory computing", or for performing Calculations are performed using a model similar to that of the human brain, also known as "neuromorphic computing." To implement these new architectures, new devices are required. These devices must, among other things, store information in a non-volatile manner, consume little energy, be durable, and be fast.

[0008] A new type of two-terminal device, called "memristors" (or "memristors"), comprises passive electronic components whose electrical resistance can be modified non-volatilely (also called "permanently") by the application of currents or voltages. Non-volatile information can then be stored in these devices and read via a conventional resistance measurement.

[0009] These memristors can, initially, be used as mass storage or as RAM thanks to their non-volatility.

[0010] They can also be assembled to form the same logic functions as CMOS (or "Complementary Metal Oxide Semiconductor") transistors and thus be used for computation. Being non-volatile, it is then no longer necessary to use the von Neumann architecture, as the information is already stored in the computational elements. This is referred to as in-memory computation.

[0011] They can also be assembled to form matrices that perform multiplication and addition operations ("multiply accumulate" or "MAC" in English). This type of operation is particularly useful for neuromorphic computing.

[0012] Among the best-known memristors are PCRAM (Phase Change Random Access Memory), in which information is stored using the crystalline or amorphous phase of a phase-change material, and ReRAM (Resistive Random Access Memory), in which information is stored using the movement of vacancies (e.g., oxygen vacancies) or metal ions within a material. These memristors exhibit high ON / OFF resistance ratios but have endurance and reliability issues. The ON / OFF ratio of a device is the ratio of the resistance of the highest component to the resistance of the lowest component.

[0013] Also found are memories called "MRAM" for "Magnetoresistive Random Access Memory," in which information is stored using the direction of magnetization of a ferromagnetic material. These memristors exhibit good endurance and reliability characteristics but have low ON / OFF resistance ratios.

[0014] There are also "FRAM" memories, short for "Ferroelectric Random Access Memory," in which information is stored by means of the electrical polarization of a ferroelectric material. These memories exhibit good endurance and reliability characteristics as well as strong ON / OFF ratios but whose reading is destructive.

[0015] Furthermore, these two-terminal memories must necessarily use the same path for writing and reading information.

[0016] Modifying the information contained in an order parameter (for example, a crystalline arrangement of an active layer) may require different physical constraints than those desired along a read path. To optimize the writing and reading of a memristor, separating the read and write paths can be advantageous.

[0017] There is therefore a need to provide a memristor device exhibiting good endurance and reliability characteristics, a large ON / OFF resistance ratio, non-destructive reading, and distinct read and write paths. This device can be described as a transistor.

[0018] Similar to the requirements, ferroelectric transistors have been proposed. The ferroelectric field-effect transistor, also called an Fe-FET, is based on the same principle as the conventional field-effect transistor, with the addition of a ferroelectric element to introduce non-volatility. As a reminder, a field-effect transistor, or FET, comprises a semiconductor layer, called the "channel," connecting two conductive electrodes called the "source" and "drain." A third conductive electrode, called the "gate," separated from the channel by an insulator, allows an electric field to be applied to the channel to modulate its conduction. In an Fe-FET, the electric field applied to the channel is generated by a layer of ferroelectric material located near the channel.This layer maintains the electric field on the channel even when it is not powered. Furthermore, the information does not need to be refreshed periodically. As a result, the Fe-FET consumes little energy in static mode. In addition, the state stored in the ferroelectric layer can be read non-destructively.

[0019] The ferroelectric layer of an Fe-FET is, however, difficult to integrate into the current semiconductor industry because it is made from perovskite oxide. The use of materials compatible with the current semiconductor industry, for example hafnium-based materials, does not, however, show sufficient results in terms of endurance or aging.

[0020] A ferroelectric semiconductor FET, also called a "FeS-FET" for "Ferroelectric Semiconductor FET" in English, is also known, which comprises a ferroelectric semiconductor channel in which information is stored. The document [Si et al. "A Ferroelectric Semiconductor Field-Effect"] [Transistor], Nat Electron 2, 580-586 (2019) https: / / doi.org / 10.1038 / s41928-019-0338-7] discloses an example of a ferroelectric semiconductor FeS-FET. In this example, the transistor comprises a ferroelectric semiconductor layer and three conducting electrodes arranged to form a source and drain in contact with the ferroelectric semiconductor layer, and a gate, insulated from the ferroelectric semiconductor layer. The electrical bias of the ferroelectric semiconductor layer can influence the conduction and valence bands of the ferroelectric semiconductor layer in such a way as to create, for one bias state, a conductive surface between the source and drain. The transistor is in a forward-biased state. For another bias state, the conductive surface is absent, and the transistor is reverse-biased.

[0021] To achieve this behavior, however, the ferroelectric semiconductor channel must be non-degenerate and therefore a poor conductor (the Fermi level must be within the channel's band gap), which limits the applications of such a transistor. The bias of the ferroelectric material must also be reversed across the entire channel, even though the potential difference for its control is applied only between the source and the gate. This is because the conductive surface must extend between the source and the drain to achieve conduction. An area of ​​the ferroelectric semiconductor layer that is not properly biased can interrupt the conductive surface. As a result, controlling the ferroelectric state of the channel can be difficult, with significant variability from one device to another.

[0022] Both Fe-FET and FeS-FET modulate the channel conductivity according to a ferroelectric state. This modulation restricts the transistor geometry to a three-terminal device and thus limits the assembly possibilities for forming different logic functions.

[0023] There is therefore a need to provide a non-volatile transistor or memristor exhibiting good endurance and reliability characteristics, a large ON / OFF resistance ratio, whose reading is not destructive, whose read and write paths are different and whose channel conductivity does not depend on the encoded information. Summary of the invention

[0024] The invention offers a solution to the aforementioned problems by splitting charging current paths to achieve writing and reading the state stored in a transistor.

[0025] To this end, the invention relates to a non-volatile transistor comprising: • a ferroelectric semiconductor layer comprising at least one ferroelectric domain, the ferroelectric domain exhibiting a spontaneous electrical polarization that can take on a plurality of distinct states; • a first conductive electrode, forming a “source”; • a second conductive electrode, forming a "grid"; and • a third conductive electrode, forming a “drain”, the source, the gate and the drain being separated from each other and arranged such that an electrical potential applied between the source and the gate applies an electric field to the ferroelectric domain, the drain being in electrical contact with the ferroelectric semiconductor layer, the source forming, with the ferroelectric semiconductor layer, a Schottky barrier at an interface between the source and the ferroelectric semiconductor layer, the Schottky barrier having an electrical resistance that is a function of the electrical bias, said transistor being such that: • the ferroelectric semiconductor layer is degenerate at least at the interface between the source and the ferroelectric semiconductor layer; and • the ferroelectric semiconductor layer exhibits electrical conductivity independent of spontaneous electrical polarization.

[0026] By “ferroelectric”, we mean a material or an object (for example a domain) carrying a configuration of dielectric moments and capable of exhibiting a configuration of dielectric moments (for example an alignment of these dielectric moments) forming a macroscopic dielectric moment also called “spontaneous electric polarization”.

[0027] The term "spontaneous electrical polarization" also refers to "ferroelectric polarization," "electrical polarization," or simply "polarization." The term "polarization state" refers to a particular and stable configuration of the dielectric moments that constitute the spontaneous electrical polarization. This could be, for example, an orientation that the dielectric moments can assume.

[0028] By "ferroelectric domain" is meant a region of the ferroelectric layer comprising dipole moments whose orientation is uniform.

[0029] By "electrical contact" is meant a contact between two elements allowing the passage of an electric current when certain conditions are met. This is for example a direct contact (for example forming, at least under certain conditions, an ohmic contact) or a contact made via a thin layer (forming for example a diffusion barrier, a protective layer, a layer promoting a certain type of growth or an insulating layer allowing the passage of a current by tunneling).

[0030] By "Schottky barrier" is meant a potential energy barrier for electric charges formed at a metal-semiconductor junction.

[0031] By "non-volatile," we mean that the states of the electrical bias are stable. The bias thus maintains its state for a sufficiently long period for the intended application. For example, it is greater than or equal to a few microseconds at the intended operating temperatures, and advantageously much longer than one second. The electrical bias thus allows information to be stored in a non-volatile manner. Applying a potential between the source and the gate allows an electric field to be applied to the electrical bias to switch it into one of its different bias states. Applying a potential between the source and the gate therefore allows a state to be written to the transistor. Since only an electric field is necessary to switch the bias, it is not necessary for the electrical conduction between the source and the drain to be high.In other words, the path used to perform a write operation for the transistor (called the "write path") can have a resistance as high as necessary. The write path can therefore be dimensioned and the materials chosen in such a way that the electrical current flowing through the transistor during writing is low, or even zero.

[0032] By "degenerate," we mean a material whose Fermi level is not in the band gap of the ferroelectric layer, or a material whose Fermi level is in the band gap of the ferroelectric layer but near the valence band or near the conduction band. By "near a band," we mean within 50 meV of said band. In other words, the Fermi level can be at most 50 meV above the valence band or at least 50 meV below the conduction band. Thus, the material is conductive at room temperature (for example, at 300 K).

[0033] By "degenerate at least at the interface," it is meant that the ferroelectric layer is locally degenerate, the rest of the ferroelectric layer remaining non-degenerate. Local degeneracy is obtained, for example, by local doping of the ferroelectric layer.

[0034] The polarization state of the ferroelectric semiconductor layer can be read by measuring the resistance of the Schottky barrier formed between the ferroelectric semiconductor layer and the source. For example, the so-called "reading path" between the source and the drain can be used to measure the resistance of the Schottky barrier.

[0035] Thus, using a different write path (between the source and the gate) and a different read path (between the source and the drain) makes it possible to offer a transistor whose risk of destroying information during reading is reduced, while exhibiting good performance.

[0036] It may happen that the ferroelectric layer comprises several ferroelectric domains, each of them carrying a different electrical polarization. The bias influencing the Schottky barrier can be attached to only one of these ferroelectric domains. Since only this bias modulates the Schottky barrier, it is not necessary to switch the other ferroelectric domains that do not interact with the Schottky barrier. Therefore, it is not necessary to switch the entire ferroelectric layer. The single domain carrying the bias coupled to the Schottky barrier is sufficient. Consequently, the energy required to operate the transistor can be reduced. The transistor can thus exhibit good switching performance.

[0037] Furthermore, there is no significant difference whether only one domain switches or several other domains, not interacting with the Schottky barrier, also switch. Once the domain coupled to the Schottky barrier has switched, it is irrelevant whether other domains have followed suit. The transistor switching therefore offers good reproducibility.

[0038] Applying an electrical potential between the source and the gate allows the resistance of the Schottky barrier to be modulated. Thus, the conductivity between the source and the drain can be controlled by applying a voltage between the source and the gate, in the same way as a conventional transistor. Therefore, the transistor can be used like a conventional transistor, for example in a computing architecture.

[0039] It is interesting to note that the transistor is not a field-effect transistor (FET). Indeed, it does not have a channel in the strict sense. In a FET, the channel conduction is modulated by applying an electric field in the vicinity of the channel. In the transistor according to the invention, the conduction of the semiconductor layer remains unchanged. Only the resistance of an interface between an electrode and the ferroelectric layer is modulated. In other words, the resistance between the gate and the drain remains unchanged. Since the transistor is not a field-effect transistor, it avoids the physical limitations of FETs, which make it difficult to reduce the channel size or the operating voltages.

[0040] The transistor according to the invention is also not comparable to a ferroelectric semiconductor FET, also known as an "FeS-FET." In an FeS-FET, the conductivity of the semiconductor layer forming the channel is modulated according to the electrical bias. The transistor according to the invention therefore differs from an FeS-FET in that the electrical conductivity of the ferroelectric semiconductor layer does not depend on the electrical bias and remains constant regardless of the bias state.

[0041] In one embodiment, the ferroelectric semiconductor layer is entirely degenerate. It therefore exhibits good electrical conductivity. The read path thus exhibits, when the transistor is conducting, a very low resistance. Moreover, the variation in the resistance of the Schottky barrier can be relatively significant compared to the total resistance of the reading path.

[0042] Furthermore, since the read path has low resistance, a low electrical potential can be applied to perform this reading. Therefore, reading the transistor's state is easier. The power consumption for such a reading is thus reduced. Moreover, a low electrical potential is less likely to disturb the transistor's electrical biasing.

[0043] In addition to the characteristics mentioned in the preceding paragraphs, the transistor according to the invention may have one or more additional characteristics from among the following, considered individually or in all technically possible combinations:

[0044] The grid is electrically isolated from the ferroelectric semiconductor layer.

[0045] The ferroelectric semiconductor layer comprises a first ferroelectric semiconductor sublayer and a second ferroelectric sublayer, the source forming the Schottky barrier with the first ferroelectric semiconductor sublayer, the second ferroelectric sublayer being disposed between the first ferroelectric semiconductor sublayer and the grid, the second ferroelectric sublayer having a lower electrical conductivity than the first ferroelectric semiconductor sublayer.

[0046] The grid and drain are arranged so that an electric potential applied between the grid and drain applies an electric field to the ferroelectric domain.

[0047] The drain forms, with the ferroelectric semiconductor layer, an additional Schottky barrier, at an interface between the drain and the ferroelectric semiconductor layer, the ferroelectric semiconductor layer also being degenerate at least at the interface between the drain and the ferroelectric semiconductor layer, the additional Schottky barrier having an electrical resistance that is a function of the electrical polarization.

[0048] The ferroelectric semiconductor layer includes an additional ferroelectric domain, exhibiting a spontaneous electrical polarization that can take a plurality of distinct states, the drain forming, with the ferroelectric semiconductor layer, an additional Schottky barrier, at an interface between the drain and the ferroelectric semiconductor layer, the ferroelectric semiconductor layer also being degenerate at least at the interface between the drain and the ferroelectric semiconductor layer, the additional Schottky barrier exhibiting an electrical resistance that is a function of the electrical polarization of the additional ferroelectric domain.

[0049] The drain and the grid are arranged so that an applied electric potential between the drain and the grid applies an electric field to the additional ferroelectric domain.

[0050] The transistor according to the invention comprises a conductive and non-ferroelectric spacer, the ferroelectric layer being separated into two distinct portions by the spacer, the spacer forming an ohmic contact with each of the two portions of the ferroelectric layer, one of the portions of the ferroelectric layer comprising the ferroelectric domain and the other portion of the ferroelectric layer comprising the additional ferroelectric domain.

[0051] The grid comprises a first portion and a second portion, the first portion of the grid being arranged so that an electric potential applied between the source and the first portion of the grid applies an electric field on the ferroelectric domain, the second portion of the grid being arranged so that an electric potential applied between the drain and the second portion of the grid applies an electric field on the additional ferroelectric domain.

[0052] The invention also relates to an assembly of non-volatile transistors comprising a plurality of non-volatile transistors according to the invention for which the ferroelectric semiconductor layers are common and form a single ferroelectric semiconductor layer and for which the drains are common and form a single common drain, to each non-volatile transistor corresponds at least one ferroelectric domain, the ferroelectric domain having a spontaneous electrical polarization that can take a plurality of distinct states.

[0053] In addition to the characteristics mentioned in the preceding paragraphs, the assembly of non-volatile transistors according to the invention may have one or more additional characteristics from among the following, considered individually or in all technically possible combinations:

[0054] The sources are electrically connected to each other, or even the sources are common and form a single source, and the grids are separate.

[0055] The grids are common and form a single grid in which the sources are distinct.

[0056] The assembly according to the invention comprises a nanowire and a nanotube surrounding the nanowire, the nanotube forming the ferroelectric semiconductor layer of the transistors, the nanowire forming the gates of the transistors, the common drain being in electrical contact with the nanotube.

[0057] The invention further relates to a matrix of non-volatile transistors comprising: • a first plurality of conducting lines, called "source lines"; • a second plurality of guiding lines, called “word lines”; • a third plurality of conducting lines, called "data lines"; and • a plurality of non-volatile transistors according to the invention, the source of each transistor being connected to one of the source lines, the gate of each transistor being connected to one of the word lines and the drain of each transistor being connected to one of the data lines.

[0058] According to one embodiment, the transistors of the matrix according to the invention are connected to the same row of words belonging to said at least one assembly.

[0059] The invention and its various applications will be better understood by reading the following description and examining the accompanying figures. BRIEF DESCRIPTION OF THE FIGURES

[0060] The figures are shown for illustrative purposes only and are not intended to limit the invention. Unless otherwise specified, the same element appearing in different figures has a unique reference numeral.

[0061] Figures [Fig. 1] and [Fig. 2] present a first embodiment of a non-volatile transistor according to the invention in two different usage configurations.

[0062] Figures [Fig.3], [Fig.4], [Fig.5], [Fig.6], [Fig.7] and [Fig.8] present six additional embodiments of the transistor according to the invention.

[0063] Figures [Fig.9], [Fig.10], [Fig.11] and [Fig.12] present three embodiments of an assembly of non-volatile transistors according to the invention.

[0064] Figures 13 and 14 present two embodiments of a non-volatile transistor matrix according to the invention. DETAILED DESCRIPTION

[0065] The invention aims to provide a means of storing information in a non-volatile manner, which can be used in a computing architecture. Figures 1 to 7 show several embodiments of a transistor 10 according to the invention offering such properties.

[0066] Figures 1 and 2 illustrate a first embodiment of transistor 10 in two different configurations and a band diagram {E ; z] associated with each configuration.

[0067] In these figures, the transistor 10 includes, in particular, a ferroelectric semiconductor layer 11 (also called the "ferroelectric layer") extending in a plane. The ferroelectric layer has a first face called the "top face" and a second face called the "bottom face," opposite the top face. The top face is above the bottom face along the z-axis of Figures 1 and 2. Alternatively, the ferroelectric layer 11 can be a hollow cylinder in a core / shell type system (as illustrated in Figures 11 and 12). The top face of the layer 11 then corresponds to an outer face of the cylinder and the lower face of layer 11 corresponds to the inner face of the cylinder.

[0068] The transistor 10 of Figures 1 and 2 also includes first, second, and third conducting electrodes 14, 15, and 16. These form, respectively, a source 14 (also represented by the terminal "S"), a gate 15 (also represented by the terminal "G"), and a drain 16 (also represented by the terminal "D"). The source and drain 14, 16 extend against the upper face of the ferroelectric layer 11. The gate 15 extends against the lower face of the ferroelectric layer 11. Thus, the ferroelectric layer 11 is arranged between, on the one hand, the source and drain 14, 16, and, on the other hand, the gate 15.

[0069] To enable effective control of a ferroelectric polarization 13 of the ferroelectric semiconductor layer 11, the grid 15 is preferably arranged opposite the source 14. In one embodiment, the grid 15 extends only opposite the source 14. To offer a minimum lateral footprint, they are preferably of the same dimension and aligned with each other (along the z-axis of Figures 1 and 2). In another embodiment, corresponding to figures 1 and 2, simplifying the construction of the transistor, the gate 15 extends over a surface of the lower face of the ferroelectric layer 11 corresponding to that of the source 14 and the drain 16. The gate 15 is arranged to be opposite the source 14 and the drain 16. In particular, the gate 15 extends opposite the electrodes 14 and 16.Applying an electric potential between the source 14 and the drain 15 creates an electric field between the source 14 and the grid 15. The ferroelectric layer 11, located between these electrodes 14 and 15, is then immersed in this electric field. Similarly, applying an electric potential between the drain 16 and the grid 15 also creates an electric field between these two electrodes 16 and 15, in which the ferroelectric layer 11 is immersed.

[0070] The ferroelectric layer 11 comprises at least one ferroelectric domain 12. This domain 12 exhibits an electrical polarization 13, which arises spontaneously. It results, for example, from the vector sum of dipole moments present in the first domain 12. The dipole moments are, for example, all parallel to each other (a configuration comparable to the magnetic moments of a ferromagnetic domain). The dipole moments can also be oriented with different orientations, for example, antiparallel but with different magnitudes (a configuration comparable to the magnetic moments of a ferrimagnetic domain) or perpendicular. The ferroelectric domain has, for example, a lateral dimension of a few nanometers to a few tens of nanometers.

[0071] The ferroelectric layer 11 may comprise several ferroelectric domains, each carrying a spontaneous electrical polarization. These multiple ferroelectric domains may interact and behave as a single ferroelectric domain (i.e., the spontaneous electrical polarizations are uniformly oriented), except that it is larger (this larger domain may be called the "large ferroelectric domain"). The electrical polarization 13 thus corresponds to the vector sum of the electrical polarizations of the multiple interacting domains. Alternatively, the multiple ferroelectric domains may be decoupled from each other but interact in the same way with the other elements of the transistor 10. For example, a plurality of electrical domains may be arranged under the source electrode 14 or the drain electrode 15.Therefore, these multiple decoupled domains can be considered as a single large ferroelectric domain (that is, the different spontaneous electric polarizations, undergoing the same transformations, have a uniform final orientation). The electric polarization 13 thus corresponds to the vector sum of the electric polarizations of the multiple decoupled domains.

[0072] A ferroelectric domain may have a characteristic surface (for example a cross-sectional area) less than or equal to half the contact area between the source 14 and the ferroelectric layer 11. This characteristic surface is for example between 5 nm and 50 nm.

[0073] The ferroelectric bias 13 has at least two distinct and stable states. By "states," we mean specific directions and amplitudes of the bias 13. By "stable state," we mean a state that the bias 13 can adopt for a sufficiently long time, for example, with regard to the intended use of the transistor 10 (for example, on the order of nanoseconds for computing to tens of years for information storage). In Figures 1 and 2, the two stable states of the bias 13 are perpendicular to the plane in which the ferroelectric layer 11 extends. They have the same amplitude (the arrow shown is the same length); however, they are oriented differently. The bias 13 is oriented upwards in [Fig. 1] and downwards in [Fig. 2].

[0074] The ferroelectric biasing 13 can also exhibit a plurality of stable intermediate states. These may be intermediate states with the same direction (for example, perpendicular to the plane of the ferroelectric layer 11) and different amplitudes. They may also be states with different directions and the same amplitude. They may also be a combination of these two types of stable states. What may be important for the transistor 10 (discussed below) is the out-of-plane component of the electric biasing 13. By The "out-of-plane component" refers to a component perpendicular to the interface between the ferroelectric layer 11 and the electrode 14. The out-of-plane component of the electrical polarization 13 can take several values ​​and manifest in different ways. The dipole moments giving rise to the electrical polarization 13 can be oriented out of the plane of the ferroelectric layer 11, but they can also exhibit configurations for which the vector sums are different. For example, the dipole moments can change from an antiparallel to a parallel configuration (comparable to the transformation of a ferromagnetic material into a ferrimagnetic material) or from perpendicular to parallel. The dipole moments can remain parallel (or antiparallel or perpendicular) but exhibit different orientations relative to the plane of the ferroelectric layer 11.In this case, the out-of-plane component is zero when the dipole moments are parallel to the plane of the ferroelectric layer 11, and maximum when they are perpendicular to the plane of the ferroelectric layer 11.

[0075] Information can be stored in the transistor 10 and can correspond to one of the states of the bias 13. When the bias 13 can take two distinct states, it can then store binary information. When the bias 13 can take a plurality of distinct states, it can then store non-binary information, but comprising at most as many states as the bias 13 can adopt. In a development, the bias 13 can exhibit a significant number of stable intermediate states so as to form a continuous range of stable states. The bias 13 can therefore take a plurality of distinct states within this continuous range of stable states. Thus, the bias 13 can be used to store analog information, such as a synaptic weight. Obtaining intermediate states for the bias 13 can be facilitated by implementing a domain 12 comprising a plurality of small domains.

[0076] The source, grid and drain 14, 15, 16 are arranged so as to apply an electric field on the ferroelectric domain 12, in order to be able to act on the electric polarization 13. Thus, the application of a potential between the source 14 and the drain 15 and / or between the grid 15 and the drain 16 makes it possible to apply an electric field on the ferroelectric domain 12 and thus put the polarization 13 into one of its stable states. The source 14 and the grid 15 are advantageously arranged so that the field applied to the ferroelectric layer 11 is along a ferroelectric polarization axis of the ferroelectric domain 12. In this way, the electric field is more likely to effect a switching of the ferroelectric polarization of the domain 12. The same is true for the arrangement of the drain 16 and the grid 15 when these electrodes are intended to also control the ferroelectric polarization.

[0077] In order to avoid the flow of an electric current when the electric field is applied to the ferroelectric layer 11, the grid 15 can be electrically isolated from the ferroelectric layer 11. It is, for example, isolated by means of an insulating layer (such as a layer made of SiO2 or HfO2 type oxide, or Si3 N4 type nitride, or their combination) separating the grid 15 and the ferroelectric layer 11.

[0078] In general, bringing a metal into contact with a semiconductor material can distort the valence and conduction bands of the semiconductor material and induce the formation of a potential barrier at the interface between the two materials, called a "Schottky barrier".

[0079] In the transistor 10 according to the invention, the source 14 forms, with the ferroelectric layer 11, a Schottky barrier 17. The Schottky barrier 17 is located at the interface between the two materials. The source 14 is, for example, metallic and is in direct contact with the ferroelectric layer 11 in order to form the Schottky barrier 17. Generally, a person skilled in the art knows how to choose a combination of materials to obtain a Schottky barrier.

[0080] The band diagrams in Figures 1 and 2 show an example of energy E as a function of a height z in the transistor 10 for the conduction band of the source 14 and the valence and conduction bands of the ferroelectric layer 11. The Fermi level EF of the materials is indicated by dashed lines. Far from the interface, the valence and conduction bands of the ferroelectric layer 11 are not distorted. At the interface with the metal of the source 14, the bands of the ferroelectric layer 11 are distorted such that the Fermi level moves out of the conduction band. In the band diagram of [Fig. 1], a portion C of the band gap then forms a barrier to the passage of charges (in particular electrons) from the metal of the source 14 to the semiconductor of the ferroelectric layer 11. This portion C then forms the Schottky barrier 17.

[0081] The deformation of the bands giving rise to the Schottky barrier 17 can depend on an electric field at the interface between the two materials. A sufficiently strong and close electric field can reduce the deformation of the bands and reduce, or even eliminate, the Schottky barrier 17. The band diagram in [Fig. 2] shows an example where the Fermi level remains within the conduction band, although the bands are deformed. Thus, modulating the electric field at the metal / semiconductor interface allows for modulation of the height and / or width of the Schottky barrier 17, which is equivalent to modulating the electrical resistance of the Schottky barrier 17. In a particular case, when the Schottky barrier 17 is completely eliminated (case in Figure 2), the resistance of the Schottky barrier 17 is minimal. It corresponds, for example, to an ohmic contact resistance between the two materials.

[0082] The transistor 10 of the invention provides that the electric field used to modulate the resistance of the Schottky barrier 17 is induced by the ferroelectric bias 13. By using a semiconductor and ferroelectric material, the electric field near the interface is sufficiently high to effectively modulate the height and / or width of the Schottky barrier 17. Thus, placing the bias 13 in its different states is equivalent to modulating the electric field at the Schottky barrier 17. The modulation of the electric field then results in a modulation of the resistance of the Schottky barrier 17. Therefore, measuring the resistance of the Schottky barrier 17 makes it possible to determine the state in which the bias 13 is located.

[0083] The materials suitable for forming the source 14 can be chosen according to the type of doping of the material forming the ferroelectric semiconductor layer 11. Each material is chosen to adjust the height of the Schottky barrier according to its work function. If the semiconductor is, for example, n-type, the work function of the source 14 is chosen to be greater than the electronic affinity of the semiconductor. Conversely, if the semiconductor is p-doped, the work function of the conducting electrode is chosen to be less than the electronic affinity of the semiconductor. However, the materials suitable for forming the source 14 are preferably chosen so that the amplitude of the Schottky barrier 17 varies measurably as a function of the polarization 13 of the ferroelectric layer 11.To choose a suitable material pair, one step involves selecting a material to form the ferroelectric semiconductor layer 11 of the transistor 10. A second step involves forming a test layer with the same dimensions as the ferroelectric semiconductor layer. A third step involves measuring the electric field variation at the surface of the test layer for different bias states of the test layer. Finally, a fourth step involves selecting a material to form the source 14, based on its work function, the amplitude of the electric field variation measured on the test layer, and the electron affinity of the semiconductor material used to form the test layer.The material intended to form the source 14, for example, exhibits a work function such that the height of the Schottky barrier that can be formed is modulated by more than 5%, and preferably by more than 10%, and even more preferably by more than 80%, for two distinct polarization states. When the ferroelectric layer is made of n-type doped silicon, the source 14 is, for example, made of platinum.

[0084] As a consequence of the preceding paragraph, it is possible to imagine a non-degenerate ferroelectric semiconductor material that is locally doped to make it degenerate, either of the n-type or p-type. By carefully selecting the appropriate metallic electrodes for each case, one can thus obtain characteristics analogous to the complementarity of CMOS transistors. For the same voltage by applying writing to a p-doped or n-doped device, we thus obtain opposite resistance states.

[0085] The ferroelectric layer 11 has a thickness of a few atomic layers (for example greater than 2 Â) to a few hundred nanometers (for example less than 500 nm), and advantageously on the order of tens of nanometers (for example between 5 nm and 50 nm).

[0086] The resistance of the Schottky barrier 17 varies preferentially according to a strictly monotonic function of the out-of-plane component of the polarization 13 (i.e., the component of the polarization 11 that is orthogonal to the plane of the ferroelectric layer 11). Thus, the correspondence between the resistance of the Schottky barrier 17 and the state of the polarization 13 is bijective.

[0087] By "monotonous," we mean a function whose derivative is positive or zero (or respectively negative or zero). By "strictly monotonic," we mean a function whose derivative is strictly positive (or strictly negative).

[0088] In the case where the out-of-plane component of the biasing 13 exhibits a continuous range of stable states, the Schottky barrier 17 can show a continuous range of associated resistance values. The transistor 10 then allows for the storage and retrieval of analog rather than digital information.

[0089] The ferroelectric domain 12 can comprise a plurality of ferroelectric domains. The interaction of the out-of-plane component of the dipole moments of these domains with the Schottky barrier 17 is then integrated over the entire surface of the Schottky barrier 17, that is to say over the contact surface between the source 14 and the ferroelectric layer 11.

[0090] To efficiently measure the resistance of the Schottky barrier 17, the resistance variation between the source 14 and the drain 16 can be measured. This electrical path can be considered a "reading path." To measure the resistance variation of the Schottky barrier 17 with the best possible accuracy, the drain 16 is in electrical contact with the ferroelectric layer 11. In one scenario, the electrical contact between the drain 16 and the ferroelectric layer 11 may have a resistance independent of the polarization 13. For example, the drain 16 forms an ohmic contact with the ferroelectric layer. The contact can also be made through a thin layer, forming, for example, a diffusion barrier, a protective layer, a layer promoting a certain type of growth, or an insulating layer allowing current to pass through by tunneling.In a second scenario, for example presented with reference to [Fig.4], the electrical contact between the drain 16 and the ferroelectric layer 11 exhibits an electrical resistance which is also a function of the ferroelectric polarization 13. The contact. forms for example a second Schottky barrier, whose equivalent resistance is also a function of the polarization 13.

[0091] Transistor 10 can be used to: • control the state of the bias 13 by applying a potential between the source 14 and the grid 15 (the electrical path between the source 14 and the grid 15 forming a so-called "writing path"); and • read the state of the polarization 13 by measuring the resistance of the Schottky barrier 17, i.e. by measuring the total resistance between the source 14 and the drain 16 (i.e. along the reading path).

[0092] In order that the bias 13 is not disturbed during the reading of the resistance of the Schottky barrier 17, the drain 16 is preferentially arranged so that the field applied to the ferroelectric domain 12 during the reading (i.e. when a potential is applied between the source 14 and the gate 15) is not along an axis of ferroelectric bias (i.e. along an axis corresponding to a stable state of the bias 13). Advantageously, the source 14 and the drain 16 are arranged so that the ferroelectric layer 11 is not located between these electrodes 14, 16. In the example of Figures 1 and 2, the source 14 and the drain 16 are arranged on the same face (in this case the upper face) of the ferroelectric layer 11. Thus, there is no part of the ferroelectric layer 11 which is located between these electrodes 14, 16.The electric field thus created between electrodes 14 and 16 is mostly along the plane and has little or no effect on the out-of-plane component of the ferroelectric bias 13. The reading of the state of transistor 10 can be carried out without risk of unintentionally switching the bias 13.

[0093] However, it is possible to arrange the drain 16 differently, provided that it is in electrical contact with the ferroelectric layer 11. For example, the drain 16 can be positioned against the underside of the ferroelectric layer 11, near the grid 15 (but without electrical contact with it). It can also be positioned on a side or edge of the ferroelectric layer 11 (but without contact with the source 14 or the grid 15). To avoid disturbing the bias 13, it may be sufficient to use a low-amplitude readout voltage.

[0094] In order to improve the reading of the resistance of the Schottky barrier 17, it is advantageous for the total resistance between the source 14 and the drain 16 to be as low as possible, preferably less than 10 kΩ. One way to achieve this is to dope the ferroelectric layer 11 to increase its conductivity. Preferably, the ferroelectric layer 11 is conductive at room temperature. It can be degenerate, either intrinsically or by appropriate doping. In this way, the ferroelectric layer 11 can exhibit an electrical conductivity close to the conductivity of a metal, for example at room temperature, and it is not necessary for this conductivity to depend, as in an FeS-FET or a FEFET, on the polarization state 13. The band diagrams in Figures 1 and 2 illustrate a degenerate ferroelectric layer 11 where the Fermi level is in the conduction band. The ferroelectric material α-GeTe is intrinsically degenerate (that is, naturally degenerate) and is remarkably well suited to the invention. The ferroelectric layer 11 can also be made from α-In2Se3 sufficiently doped to make the ferroelectric layer 11 degenerate.

[0095] Moreover, these two materials (degenerate a-GeTe and degenerate a-In2Se3), although they exhibit a ferroelectric polarization, also exhibit an electrical conductivity independent of their polarization.

[0096] The transistor 10 illustrated in Figures 1 and 2 can be used as a conventional transistor, thanks to its configuration employing three conductive electrodes. Thus, the electrical conductivity between the source 14 and the drain 16 can be modulated by modifying the resistance of the Schottky barrier 17. However, the transistor 10 of the invention has the advantage of maintaining the same level of conductivity between the source 14 and the drain 16 even when the transistor 10 is no longer powered. In other words, the transistor 10 according to the invention is non-volatile.

[0097] To form the source 14 and the drain 16, it is preferable that there be no contamination between the source and / or the drain and the ferroelectric layer. Ideally, the deposition of the layer (e.g., metallic) intended to form the source and / or the drain is carried out immediately after the deposition of the ferroelectric layer 11, preferably without re-exposing the ferroelectric layer 11 to air between the two steps. In an alternative embodiment, a thin layer (e.g., a diffusion barrier, an insulating layer, or a layer promoting a particular growth) can be deposited on the ferroelectric layer 11 before the deposition of the layer intended to form the source and / or the drain. The layer intended to form the source and / or the drain can then be deposited on this thin layer. This thin layer can optionally prevent contamination of the ferroelectric layer if re-exposure to air is necessary before the deposition of the layer intended to form the source and / or the drain.

[0098] By "thin layer" is meant a layer whose thickness is sufficiently small so as not to prevent the formation of a Schottky barrier or an ohmic contact. This thickness is, for example, less than the Thomas-Fermi length of the ferroelectric layer 11 and / or of the material forming the layer intended to form the source and / or the drain.

[0099] Figure 3 presents an embodiment of the transistor which differs from the embodiment of Figures 1 and 2 in that the ferroelectric layer 11 comprises a first ferroelectric semiconductor sublayer 21 and a second sublayer 22. In this embodiment, the source 14 and the drain 16 are in electrical contact with the first ferroelectric sublayer 21. Thus, the source 14 forms a Schottky barrier 17 with the first sublayer 21. The grid 15 extends against the second sublayer 22.

[0100] Reversing the polarization of a degenerate ferroelectric can be difficult due to the leakage current that flows when a voltage is applied to the ferroelectric. In the case where the ferroelectric layer 11 comprises two sublayers 21, 22, it is advantageous for the conductivities of these two sublayers 21, 22 to be different. Preferably, the second sublayer 22 has a lower electrical conductivity than the first ferroelectric sublayer 21, for example, less than 10% of the electrical conductivity of the first ferroelectric sublayer 21. Thus, when the resistance of the Schottky barrier 17 is read or when it is exposed to an electric field, the leakage current flowing to the gate 15 is reduced.Conversely, the low electrical conductivity of the second subshell 22 facilitates the application of an electric field to the ferroelectric layer 11 (for example, to switch its polarization). Thus, the polarization 13 can be switched with a low voltage. When the electrical conductivity of the second subshell 22 is sufficiently low (for example, less than 10% of the electrical conductivity of the first ferroelectric subshell 21, or even less), it can act as an insulating layer between the ferroelectric layer 11 and the grid 15. In one embodiment, the second subshell 22 is simply insulating.

[0101] The second subshell 22 can also be ferroelectric. Thus, in addition to limiting the leakage current that could flow to the gate 15, it facilitates the switching of the electric polarization of the first ferroelectric subshell 21. Indeed, applying an electric field to the second ferroelectric subshell 22 allows the switching of ferroelectric domains (which can be vertical) which in turn induce a switching of the ferroelectric domains of the first ferroelectric subshell 21. In a final state, the two subshells 21, 22 can have the same polarization directions.

[0102] The resistance of the Schottky barrier 17 is influenced by the polarization of the ferroelectric sublayer with which the source 14 is in contact. In this example, this is the first ferroelectric sublayer 21. It is irrelevant, from the point of view of its influence on the resistance of the Schottky barrier 17, whether the polarization 13 is carried solely by the first sublayer 21 or by both sublayers 21 and 22. In other words, the ferroelectric domain 12 can belong to the first sublayer 21 or to both sublayers 21 and 22. The second ferroelectric sublayer 22 facilitates the switching of the first sub- layer 21. The second sublayer can be sized to switch at lower voltage and drive the switching of the ferroelectric domains of the first sublayer by vertical propagation of the ferroelectric domains.

[0103] The embodiment of [Fig. 4] differs from the embodiment of Figures 1 and 2 in that the transistor 10 includes an additional Schottky barrier 30. In other words, the transistor 10 includes two Schottky barriers 17, 30. The first Schottky barrier 17 is located at the interface between the ferroelectric layer 11 and the source 14 (this is the Schottky barrier described previously). The second Schottky barrier 30 (also called the additional Schottky barrier) is located at the interface between the ferroelectric layer 11 and the drain 16. In this case, the drain 16 is, for example, made of metal and in direct contact with the ferroelectric layer 11 (it can be dimensioned as described previously, with reference to the first Schottky barrier 17).

[0104] In this embodiment, the resistance of the second barrier 30 is a function of the bias 13. Thus, the measurement of the total resistance between the source 14 and the drain 16 includes the sum of the resistances of the first and second barriers 17, 30. The variation in the total resistance associated with the modulation of the bias 13 is therefore increased, thereby improving the reading. Of course, it is preferable that the second barrier 30 be a monotonic function of the bias 13 and follow the same trend as the first Schottky barrier 17 (i.e., both increasing with the bias 13 or both decreasing with the bias 13).

[0105] Figures 5 to 7 show three embodiments of transistor 10 allowing two distinct pieces of information to be stored.

[0106] Unlike the embodiments shown in Figures 1 to 4, in which the ferroelectric layer 11 comprises only one ferroelectric domain, the transistor 10 in Figures 5 to 7 therefore has two distinct ferroelectric domains 12, 41. The first ferroelectric domain 12 corresponds, for example, to the ferroelectric domain shown previously, with reference to Figures 1 to 4. The transistor 10 has a second ferroelectric domain 41, distinct from the first ferroelectric domain 12. The second ferroelectric domain 41 has a second spontaneous electrical bias 42, distinct from the first bias 12 (in other words, decoupled from the latter). The second spontaneous electrical bias 42 can take on a plurality of bias states. The transistor 10 therefore comprises a plurality of distinct biases 13, 42, allowing it to store a plurality of distinct information.

[0107] In embodiments of Figures 5 to 7, the first and second ferroelectric domains 12, 41 may be separate ferroelectric domains or sets of ferroelectric domains (coupled or not) and forming large ferroelectric domains as described above.

[0108] The source 14 and the drain 16 are preferentially sufficiently far apart that the interaction between the first and second domains 12, 41 is negligible. The distance separating the source 14 and the drain 16 is, for example, greater than the thickness of a domain wall separating the two ferroelectric domains 12, 4L. In one development, the two ferroelectric domains 12, 41 can be separated by at least one third ferroelectric domain. The source 14 and the drain 16 are then separated from each other by a distance corresponding to the third domain.

[0109] Alternatively, and as illustrated in [Fig. 6], the ferroelectric layer 11 is separated into two distinct portions by a third conductive but non-ferroelectric portion 43, called the "spacer". The spacer 43 reduces the interaction between the first and second ferroelectric domains 12, 4L. The spacer 43 is preferentially in ohmic contact with each of the two portions of the ferroelectric semiconductor layer 11. In this way, it allows an electric current to flow from the first portion to the second portion and vice versa. The spacer 43 is, for example, metallic. It may be important to avoid any direct contact between the spacer 43 and the source 14, the gate 15, or the drain 16, in order to prevent any short circuit.

[0110] In the embodiments of Figures 5 and 6, applying a voltage between the source 14 and the gate 15 and between the drain 16 and the gate 15 allows an electric field to be applied to, respectively, the first and second domains 12, 4L. The first and second polarizations 13, 42 of these domains can thus be controlled independently of each other. The source 14 and the drain 16 are preferentially arranged, with respect to the first and second domains 12, 41 and the gate 15, so that the generated electric fields are not aligned with a polarization axis of a domain that they are not intended to control. For example, no portion of the first ferroelectric domain 12 is located between the drain 16 and the grid 15. Thus, no electric field generated between the drain 16 and the grid 15 is aligned with a polarization axis of the first ferroelectric domain 12.

[0111] In order to enhance the independence in the control of the polarizations 13, 42, the grid 15 may comprise two distinct portions 15a, 15b, as illustrated in [Fig. 7]. The two grid portions 15a, 15b are separated from each other and from the source 14 and the drain 16. The two grid portions 15a, 15b extend against the underside of the ferroelectric layer 11 and are directly above, respectively, the source 14 and the drain 16. The first domain 12 is thus arranged between the source 16 and the first grid portion 15a. And the second domain 41 is arranged between the drain 16 and the second grid portion 15b. Thus, the two grid portions 15a, 15b are arranged such that: • the source 14 and the first portion of grid 15a can apply an electric field to the first ferroelectric domain 12; • the drain 16 and the second portion of grid 15b can apply an electric field on the second ferroelectric domain 41.

[0112] The electric field applied between the drain 16 and the second portion of the grid 15b remains localized at the level of the second domain 41, carrying the second polarization 42, with a reduced or even negligible influence on the first domain 12. Similarly, the first portion of the grid 15a does not extend against the entire lower face of the ferroelectric layer 11. Thus, the electric field applied between the source 14 and the first portion of the grid 15b remains localized at the level of the first domain 12, carrying the first polarization 13, with a reduced or even negligible influence on the second domain 41.

[0113] The two grid portions 15a, 15b are preferably electrically isolated from the ferroelectric layer 11, for example by an insulating layer. This may be the same layer that insulates the monolithic grid 15 of Figures 1 to 4.

[0114] The embodiments shown in Figures 5 to 7 are particularly well suited to operation according to an "AND" logic principle. This is referred to as an "AND logic gate" or an "AND function." In these embodiments, the transistor comprises two Schottky barriers 17, 30. The source 14 is in electrical contact with the first ferroelectric domain 12, with which it forms the first Schottky barrier 17. The drain 16 is in electrical contact with the second ferroelectric domain 41, with which it forms the second Schottky barrier 30. Thus, the resistance of the second Schottky barrier 30 is not a function of the first bias 13, as is the case in [Fig. 4]. It is a function of the second bias 42, carried by the second ferroelectric domain 4L. The second Schottky barrier 30 therefore allows the state of the second bias 42 of the second ferroelectric domain 4L to be determined.

[0115] The total resistance between the source 14 and the drain 16 also includes the sum of the resistances of the first and second Schottky barriers 17, 30. Therefore, it is sufficient for one or both of these two barriers 17, 30, to be in a state of high resistance for the total resistance between the source 14 and the drain 16 to also be high. Only when both barriers 17, 30 simultaneously exhibit low resistance is the total resistance between the source 14 and the drain 16 low.

[0116] The table below summarizes the operation of the transistors in Figures 5 to 7. For this example, the first and second biases 13, 42, denoted PI and P2, can take two distinct states "0" or "1" for which the Schottky barrier resistors RBi, RB2 can respectively take the values ​​"high" and "low". The total resistance between the source 14 and the drain 16 is indicated by Rnet; the associated final state is indicated in the last column. Pi Rbi P2 Rb2 R13 Final state 0 high 0 high high 0 0 high 1 low high 0 1 low 0 high high 0 1 low 1 low low 1

[0117] Figures 8 to 10 show three embodiments of an assembly 60 of transistors 10, taking advantage of a remarkable property of the transistors 10. Indeed, for each transistor 10, the electrical conductivity in the ferroelectric layer 11 is not modified by the different states that the different biasings of said layer 11 can assume. The only change in conductivity occurs at the interface between the ferroelectric layer 11 and the source 14 (and the drain 16 when there is another Schottky barrier). Therefore, apart from these interfaces, the ferroelectric layer 11 can be used as a conduction track. A single ferroelectric layer 11 can, for example, be shared between several transistors 10.

[0118] The assemblies 60 of Figures 8 to 9 comprise a ferroelectric layer 11 comprising a plurality of ferroelectric domains 12. Each domain 12 carries a spontaneous polarization 13. The domains 12 are electrically connected to each other but sufficiently distant so as not to influence each other. The assemblies 60 also include a plurality of sources 14 extending against the ferroelectric layer 11, at the level of each domain 12 and forming a Schottky barrier 17 with the ferroelectric layer 11. A grid 15, single or having portions thereof, extends against the ferroelectric layer 11 and is arranged opposite the sources 14. The sources 14 are, for example, arranged against the upper face of the ferroelectric layer 11 and the grid 15 (or each portion of the grid) extends against the lower face of the ferroelectric layer 11, opposite the upper layer. Finally, a drain 16, unique and common to all sources 14, extends against the ferroelectric layer 11.In these examples, the common drain 16 extends over the upper face of the ferroelectric layer 11, on the same face as the sources 14. The ferroelectric layer 11 can be locally degenerate, particularly at its interfaces with the different sources 14. However, it is advantageous for the entire ferroelectric layer 11 to be degenerate, so as to provide a high ON / OFF ratio for each Schottky barrier 17.

[0119] Each source 14 / Schottky barrier 17 / drain 16 pair then forms a transistor 10 according to the invention. The assembly 60 therefore corresponds to a plurality of transistors 10 according to the invention, of which the ferroelectric layer 11 is common and of which the drain 16 is common.

[0120] Remarkably, the ferroelectric domains 12 are then part of the same ferroelectric layer 11. Since the conductivity in the ferroelectric layer 11 is not influenced by the state of each bias 13, it does not matter whether there is one or more domains between the Schottky barrier 17 and the common drain 16; each transistor 10 can therefore be operated in the same way as the transistor 10 in Figures 1 and 2. To determine the bias state of one of the biases, the resistance of the associated Schottky barrier 17 is measured by measuring the total resistance between the corresponding source 14 and the common drain 16. The assembly 60 makes it possible to store several pieces of information in distinct ferroelectric domains 12 while using only a single ferroelectric layer 11. The footprint per unit of information is therefore reduced.

[0121] In the example of [Fig. 8], the assembly 60 comprises two transistors 10. In addition, the sources 14 are electrically connected to each other. This embodiment is particular in that it is adapted to operation according to an "OR" logic principle. This is then referred to as an "OR logic gate" or an "OR function". Unlike the transistor of [Fig. 7], the assembly of [Fig. 8] includes a fifth electrode 62 in electrical contact with the two sources 14 of the two transistors 10 and a common drain 16.

[0122] To function as an OR logic gate, it is necessary that the assembly 60 be able to independently control the biases 13. In this embodiment, this control is ensured by the different portions of the gate 15. Thus, applying an electrical potential to the sources 14 and a single portion of the gate 15 allows each bias 13 to be switched independently.

[0123] In this embodiment, the Schottky barriers 17 are connected in parallel. Thus, it is sufficient for one of the two barriers 17 to be conducting (i.e., to have a state of low resistance) for the total resistance (between the electrode 62 and the drain 16) to be low.

[0124] The table below summarizes the operation of the assembly in [Fig. 8]. In this example, the biases 13, labeled Pi and P2, can take two distinct states, "0" or "1", for which the Schottky barrier resistors RBi and RB2 can respectively take the values ​​"high" and "low". The total resistance (between electrode 61 and drain 16) is indicated by RT0T, and the associated final state is shown in the last column. Pi Rbi P2 Rb2 Rtot Final state 0 High 0 High High 0 0 High 1 Low Low 1 1 Low 0 High Low 1 1 Low 1 Low Low 1

[0125] In the example of [Fig. 9], the assembly 60 comprises four transistors 10 according to the invention, similar to the transistor in Figures 1 and 2, connected in a star configuration with a common drain 16 and independent gates and sources 14. The electrical potential to be applied to control one of the biases 13 is then applied between one of the sources 14 and the corresponding gate 15. Thus, the electric field applied at each domain 12 is spatially restricted.

[0126] Assembly 60 of [Fig. 10] differs from assembly [Fig. 9] in that it includes a common grid 15. In this example, the grid 15 is arranged opposite all the sources 14. This embodiment simplifies the manufacture of the grid 15.

[0127] Figures 11 and 12 illustrate an embodiment of the assembly 60. This embodiment represents a particular variant of the embodiment of [Fig. 10]. In this case, it can be referred to as a "3D assembly," with reference to the three dimensions of space. In this particular example, the assembly 60 comprises a nanowire 71 and a nanotube 72, the nanotube 72 surrounding the nanowire 71. The nanowire 71 is conductive and forms the common gate 15 of the assembly 60 (and therefore of each associated transistor 10, as in [Fig. 10]). The nanotube 72 is made of ferroelectric semiconductor material, preferably fully degenerate, and forms the common ferroelectric layer 11 (and therefore of each transistor). In a 3D assembly, the ferroelectric layer 11 and the gate 15 are therefore cylindrical.The nanowire 71 and the nanotube 72 can be separated by an insulating layer, for example in oxide, or by a diffusion barrier or a protective layer, or a ferroelectric layer 22 of lower conductivity (as in [Fig.3]).

[0128] In the embodiment shown in Figures 11 and 12, a common drain 16 extends perpendicularly to the nanotube / nanowire assembly 71, 72 and makes contact with the nanotube 71 on one edge thereof. A plurality of sources 14, in the form of planar conducting electrodes, extend perpendicularly to the nanowire / nanotube assembly 71, 72. The sources 14 make contact with the nanotube 72 at various points so as to form the transistors 10. They may partially or completely surround the nanotube 72.

[0129] In a variant of the 3D assembly, based on the principle of [Fig. 8], the transistors 10 may have a common source 14, formed for example by the nanowire 72. Each transistor then has a distinct gate 15, formed by one of the flat conducting electrodes surrounding, at least partially, the nanotube 72. In this In the variant, the nanowire 71 is preferentially in contact with the nanotube 72 while the flat electrodes are preferentially isolated from the nanotube 71.

[0130] Figures 13 and 14 present two embodiments of a non-volatile storage matrix integrating the transistors 10 described in Figures 1 to 4.

[0131] Figure 13 includes, as an inset, a simplified representation of a transistor 10 according to the invention. In particular, the source, gate and drain 14, 15, 16 are shown there.

[0132] Figure 13 shows a matrix 70 implementing these transistors 10. In particular, the matrix 70 comprises: • a first plurality of BL conductive lines, called "data line"; • a second plurality of WL conductive lines, called "word lines"; and • a third plurality of conducting lines SL, called the "source line".

[0133] For each transistor 10: • Source 14 is connected to one of the SL source lines; • Grid 15 is connected to one of the WL word rows; and • Drain 16 is connected to one of the BL data lines.

[0134] The transistors 10 connected to the same WL word line can be part of an assembly 60 as described previously, for example with reference to Figures 9 and 10. In [Fig. 13], four transistors 10 connected to the same WL word line are outlined with dashed lines. They can be part of an assembly 60 such as that shown in [Fig. 9] or 10. For example, following the example of the assembly 60 in [Fig. 10], the transistors 10 connected to the same WL word line would have a common gate 15.

[0135] Figure 14 shows an embodiment of the matrix comprising a plurality of transistors 10, where each transistor 10 is part of an assembly 60 as illustrated in Figures 11 and 12. An example of an assembly 60, referred to as a "3D assembly," is outlined by a dashed line. A transistor 10 within this assembly is surrounded by a solid circle. These assemblies 60 allow for the easy connection of a plurality of transistors 10, which can be operated independently of each other, to form the matrix 70. In particular, each assembly 60 is connected to only one row of WL words.

Claims

Demands

1. Non-volatile transistor (10) comprising: - a ferroelectric semiconductor layer (11) comprising at least one ferroelectric domain (12), the ferroelectric domain having a spontaneous electrical polarization (13) capable of taking a plurality of distinct states; - a first conducting electrode (14), forming a "source"; - a second conducting electrode (15), forming a "gate";and - a third conducting electrode (16), forming a "drain", the source (14), the gate (15) and the drain (16) being spaced apart and arranged such that an electrical potential applied between the source (14) and the gate (15) applies an electric field to the ferroelectric domain (12), the drain (16) being in electrical contact with the ferroelectric semiconductor layer (11), the source (14) forming, with the ferroelectric semiconductor layer (11), a Schottky barrier (17) at an interface between the source (14) and the ferroelectric semiconductor layer (11), the Schottky barrier (17) having an electrical resistance that is a function of the electrical bias (13), the transistor being characterized in that: - the ferroelectric semiconductor layer (11) is degenerate at least at the interface between the source (14) and the ferroelectric semiconductor layer (11);and in that - the ferroelectric semiconductor layer (11) exhibits an electrical conductivity independent of the spontaneous electrical polarization (13).;

2. Transistor (10) according to claim 1, wherein the gate (15) is electrically isolated from the ferroelectric semiconductor layer (H).

3. Transistor (10) according to claim 1 or 2, wherein the ferroelectric semiconductor layer (11) comprises a first ferroelectric semiconducting sublayer (21) and a second ferroelectric sublayer (22), the source (14) forming the Schottky barrier (17) with the first ferroelectric semiconducting sublayer (21), the second ferroelectric sublayer (22) being disposed between the first ferroelectric semiconducting sublayer (21) and the grid (15), the second ferroelectric sublayer (22) having a lower electrical conductivity than the first ferroelectric semiconducting sublayer (21).

4. Transistor (10) according to any one of claims 1 to 3, wherein the gate (15) and the drain (16) are arranged such that an electric potential applied between the gate (15) and the drain (16) applies an electric field to the ferroelectric domain (12).

5. Transistor (10) according to any one of claims 1 to 4, wherein the drain (16) forms, with the ferroelectric semiconductor layer (11), an additional Schottky barrier (30), at an interface between the drain (16) and the ferroelectric semiconductor layer (11), the ferroelectric semiconductor layer (11) also being degenerate at least at the interface between the drain (16) and the ferroelectric semiconductor layer (11), the additional Schottky barrier (30) having an electrical resistance that is a function of the electrical polarization (13).

6. Transistor (10) according to any one of claims 1 to 3, wherein the ferroelectric semiconductor layer (11) comprises an additional ferroelectric domain (41), having a spontaneous electrical polarization (42) capable of taking a plurality of distinct states, the drain (16) forming, with the ferroelectric semiconductor layer (11), an additional Schottky barrier (30), at an interface between the drain (16) and the ferroelectric semiconductor layer (11), the ferroelectric semiconductor layer (11) also being degenerate at least at the interface between the drain (16) and the ferroelectric semiconductor layer (11), the additional Schottky barrier (30) having an electrical resistance as a function of the electrical polarization (42) of the additional ferroelectric domain (41).

7. Transistor (10) according to claim 6, wherein the drain (16) and the gate (15) are arranged such that an electric potential applied between the drain (16) and the gate (15) applies an electric field to the additional ferroelectric domain (41).

8. Transistor (10) according to any one of claims 6 to 7, comprising a conductive and non-ferroelectric spacer (43), the ferroelectric layer (11) being separated into two distinct portions by the spacer (43), the spacer (43) forming an ohmic contact with each of the two portions of the ferroelectric layer (11), one of the portions of the ferroelectric layer (11) comprising the ferroelectric domain (12) and the other portion of the ferroelectric layer (11) comprising the additional ferroelectric domain (41).

9. Transistor (10) according to any one of claims 6 to 8, wherein the gate (15) comprises a first portion (15a) and a second portion (15b), the first gate portion (15a) being arranged such that an electric potential applied between the source (14) and the first gate portion (15a) applies an electric field to the ferroelectric domain (12), the second gate portion (15b) being arranged such that an electric potential applied between the drain (16) and the second gate portion (15b) applies an electric field to the additional ferroelectric domain (41).

10. Assembly (60) of non-volatile transistors comprising a plurality of non-volatile transistors (10) according to any one of claims 1 to 5 wherein the ferroelectric semiconductor layers (11) are common and form a single ferroelectric semiconductor layer and wherein the drains (16) are common and form a single common drain, to each non-volatile transistor (10) corresponds at least one ferroelectric domain (12), the ferroelectric domain having a spontaneous electrical bias (13) capable of taking a plurality of distinct states.

11. Assembly (60) according to claim 10, wherein the sources (16) are electrically connected to each other, or even the sources (16) are common and form a single source, and wherein the grids (15) are separate.

12. Assembly (60) according to claim 10, wherein the grids (15) are common and form a single grid and wherein the sources (16) are distinct.

13. Assembly (60) according to any one of claims 10 to 12, comprising a nanowire (71) and a nanotube (72) surrounding the nanowire, the nanotube forming the ferroelectric semiconducting layer (11) of the transistors (10), the nanowire forming the gates (15) of the transistors, the common drain (16) being in electrical contact with the nanotube (71).

14. Matrix (70) of non-volatile transistors comprising: - a first plurality of conducting lines (SL), called "source lines"; - a second plurality of conductive lines (WL), called "word lines"; - a third plurality of conducting lines (CLs), called "data lines"; and - a plurality of non-volatile transistors (10) according to any one of claims 1 to 5, the source (14) of each transistor being connected to one of the source lines (SL), the gate (15) of each transistor being connected to one of the word lines (WL) and the drain (16) of each transistor being connected to one of the data lines (BL).

15. Matrix (70) according to claim 14, comprising at least one assembly (60) of non-volatile transistors according to any one of claims 10 to 13, the transistors (10) of the matrix (70) connected to the same word line (WL) belonging to said at least one assembly (60).

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