Method for fast turn off and recovery of regulated outputs

Abstract

The invention discloses a bias circuit system for an amplifier. The bias circuit system (10) includes: a bias generator (12) having a bias generator output terminal (14); and a switch having a bias input terminal (28), an amplifier bias output terminal (24), a bias shunt terminal, and a switch control terminal. The switch is configured to switch a bias generated by the bias generator to the amplifier bias output terminal in response to a connection bias signal received at the switch control terminal, and to switch from the amplifier bias output terminal to the bias shunt terminal in response to a disconnection bias signal. An overvoltage detector (38) is configured to monitor a supply voltage to the amplifier and, in response, generate the off bias signal when the supply voltage exceeds a reference voltage and generate the connection bias signal when a supply voltage level is less than the reference voltage.

Description

(19) State Intellectual Property Office (12) Invention Patent Application (10) Application Publication Number (43) Application Publication Date (21) Application Number 202480062181.2 (22) Application Date 2024.08.29 (30) Priority Data 63 / 543,197 2023.10.09 US 63 / 569,764 2024.03.26 US (85) PCT International Application Entering National Phase Date 2026.03.27 (86) PCT International Application Application Data PCT / US2024 / 044321 2024.08.29 (87) PCT International Application Publication Data WO2025 / 080351 EN 2025.04.17 (71) Applicant: QORVO, Inc., USA (72) Inventor: M.Z. Westergaard (74) Patent Agency: China Council for the Promotion of International Trade Patent & Trademark Office Co., Ltd., 11038 Patent Attorney: Zhang Dan (51) Int.Cl. H03F 1 / 30 (2006.01) (54) Invention Title: Method for Rapidly Turning Off and Resuming Regulated Output (57) Abstract: This invention discloses a bias circuit system for an amplifier. The bias circuit system (10) comprises: a bias generator (12) having a bias generator output terminal (14); and a switch having a bias input terminal (28), an amplifier bias output terminal (24), a bias shunt terminal, and a switch control terminal. The switch is configured to switch the bias generated by the bias generator to the amplifier bias output terminal in response to a connection bias signal received at the switch control terminal, and to switch from the amplifier bias output terminal to the bias shunt terminal in response to a disconnect bias signal. An overvoltage detector (38) is configured to monitor the supply voltage of the amplifier and, in response, generate the disconnect bias signal when the supply voltage exceeds a reference voltage, and generate the connection bias signal when the supply voltage level is less than the reference voltage. Claims 2 pages Description 5 pages Drawings 4 pages CN 121925783 A 2026.04.24 CN 1 21 92 57 83 A 1. A bias circuit system (10) for an amplifier, comprising: ● a bias generator (12) having a bias generator output terminal (14); and ● a switch having a bias input terminal (28), an amplifier bias output terminal (24), a bias shunt terminal, and a switch control terminal, wherein the switch is configured to switch the bias generated by the bias generator to the amplifier bias output terminal in response to a connection bias signal received at the switch control terminal, and to switch from the amplifier bias output terminal to the bias shunt terminal in response to a disconnect bias signal.2. The bias circuit system of claim 1, further comprising an overvoltage detector (38) configured to monitor the supply voltage of the amplifier and, in response, generate the disconnect bias signal when the supply voltage exceeds a reference voltage, and generate the connection bias signal when the supply voltage level is less than the reference voltage. 3. The bias circuit system of claim 1, further comprising a parallel load coupled between the bias shunt terminal and ground. 4. The bias circuit system of claim 3, wherein the parallel load is a resistor. 5. The bias circuit system of claim 3, wherein the parallel load is a capacitor. 6. The bias circuit system of claim 3, wherein the parallel load is a resistor coupled in parallel with a capacitor. 7. The bias circuit system of claim 3, wherein the bias generator has a closed feedback loop configured to remain closed when the bias is shunt to the bias shunt terminal. 8. A method for protecting an amplifier having a bias circuit system (10), the bias circuit system comprising a bias generator (12) having a bias generator output terminal (14), and a switch having a bias input terminal (28), an amplifier bias output terminal (24), a bias shunt terminal, and a switch control terminal, the method comprising switching a bias generated by the bias generator to the amplifier bias output terminal in response to a connection bias signal received at the switch control terminal, and switching from the amplifier bias output terminal to the bias shunt terminal in response to a disconnect bias signal. 9. The method for protecting the amplifier according to claim 8, further comprising monitoring the supply voltage of the amplifier by means of an overvoltage detector (38), and generating the disconnect bias signal in response to the supply voltage exceeding a reference voltage, and generating the connection bias signal when the supply voltage level is less than the reference voltage. 10. The method of protecting the amplifier according to claim 8, further comprising shunting the bias voltage to a parallel load coupled between the bias shunt terminal and ground in response to the disconnect bias signal, such that the load is maintained on the bias generator. 11. The method of protecting the amplifier according to claim 10, wherein the parallel load is a resistor. 12. The method of protecting the amplifier according to claim 10, wherein the parallel load is a capacitor. 13. The method of protecting the amplifier according to claim 10, wherein the parallel load is a resistor coupled in parallel with a capacitor.14. A wireless communication device (66) comprising: ● a baseband processor (70); ● a transmitting circuit system (72) configured to receive encoded data from the baseband processor and modulate a carrier signal with the encoded data, wherein the transmitting circuit system comprises: ● an amplifier configured to amplify the carrier signal; and ● a bias circuit system (10) for the amplifier, comprising: ● a bias generator (12) having a bias generator output terminal (14); and ● a switch having a bias input terminal (28), an amplifier bias output terminal (24), a bias shunt terminal, and a switch control terminal, wherein the switch is configured to switch the bias generated by the bias generator to the amplifier bias output terminal in response to a connection bias signal received at the switch control terminal, and to switch from the amplifier bias output terminal to the bias shunt terminal in response to a disconnect bias signal. 15. The wireless communication device of claim 14, wherein the bias circuit system further includes an overvoltage detector (38) configured to monitor the supply voltage of the amplifier and, in response, generate the disconnect bias signal when the supply voltage exceeds a reference voltage, and generate the connection bias signal when the supply voltage level is less than the reference voltage. 16. The wireless communication device of claim 14, further including a parallel load coupled between the bias shunt terminal and ground. 17. The wireless communication device of claim 16, wherein the parallel load is a resistor. 18. The wireless communication device of claim 16, wherein the parallel load is a capacitor. 19. The wireless communication device of claim 16, wherein the parallel load is a resistor coupled in parallel with a capacitor. 20. The wireless communication device of claim 16, wherein the bias generator has a closed feedback loop configured to remain closed when the bias is shunt to the bias shunt terminal. Claims 2 / 2 Page 3 CN 121925783 A Method for rapidly shutting down and restoring regulated output

[0001] Related Applications

[0002] This application claims the benefit of Provisional Patent Application No. 63 / 569,764, filed March 26, 2024, and Provisional Patent Application No. 63 / 543,197, filed October 9, 2023, the disclosures of which are hereby incorporated herein by reference in their entirety. Technical Field

[0003] This disclosure relates to power amplifiers having protection circuitry systems, and more particularly, to radio frequency power amplifiers having overvoltage protection circuitry systems.Background Art

[0004] In cellular networks, power amplifiers are used to transmit data from mobile phones to base stations. However, power amplifiers may experience voltages higher than they are designed for. Therefore, overvoltage protection is used to protect power amplifiers. Current solutions for protecting power amplifiers from overvoltage work by turning off the bias voltage of the power amplifier. This is currently achieved by turning off the bias circuit. However, this solution has a challenge, namely, a slow response time, especially a slow release time. This slow release time can lead to unwanted data loss when the bias circuit resumes applying bias to the power amplifier, resulting in less data being transmitted. Summary of the Invention

[0005] A bias circuit is disclosed that is designed to improve the release time from the time the bias output is low to the time the bias output is ready again, resulting in lower data loss after an overvoltage occurs. The bias circuit according to this disclosure is as fast or faster than the bias circuits in existing solutions when turning off the output. The disclosed circuit is much faster than existing solutions when turning the output back on. Furthermore, the disclosed circuit keeps the bias circuit loop connected when the output is cut off.

[0006] In another aspect, any of the foregoing aspects, individually or together, and / or the various individual aspects and features as described herein, may be combined to obtain additional advantages. Unless otherwise stated herein, any of the various features and elements disclosed herein may be combined with one or more other disclosed features and elements.

[0007] Those skilled in the art will understand the scope of this disclosure and realize its additional aspects after reading the following preferred embodiments in conjunction with the accompanying drawings. Brief Description of the Drawings

[0008] The accompanying drawings (which are incorporated in and form a part of this specification) illustrate several aspects of this disclosure and, together with the description, assist in explaining the principles of this disclosure.

[0009] FIG1 is a generalized diagram depicting an embodiment of a bias circuit system operating nominally according to this disclosure, wherein the generated bias voltage and / or current switches to the bias output terminal.

[0010] FIG2 is a generalized diagram depicting an embodiment of a bias circuit system operating under protection conditions, wherein the generated bias voltage and / or current switches to the protection load during an overvoltage event.

[0011] FIG3 is a diagram of an exemplary detailed embodiment of the bias circuit system of FIG1 and 2. Specification 1 / 5 pages 4 CN 121925783 A

[0012] FIG4 is a schematic diagram of an exemplary communication device in which a bias circuit system may be employed. Detailed Description

[0013] The various embodiments described below represent the information required to enable those skilled in the art to practice the various embodiments and illustrate the best mode for practicing the various embodiments. After reading the following description with reference to the accompanying drawings, those skilled in the art will understand the concepts of this disclosure and will realize the application of these concepts not specifically set forth herein.It should be understood that these concepts and applications fall within the scope of this disclosure and the appended claims.

[0014] It will be understood that although terms such as first, second, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish different elements. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element, without departing from the scope of this disclosure. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0015] It will be understood that when an element (e.g., a layer, region, or substrate) is referred to as being “on” or extending “on” another element, the element may be directly on or directly extending to the other element, or there may also be an intermediary element. Conversely, when an element is referred to as being “directly” on or “directly” extending to the other element, there is no intermediary element. Similarly, it will be understood that when an element (e.g., a layer, region, or substrate) is referred to as being "above" or extending "above" another element, the element may be directly above or extending directly above the other element, or there may be an intermediary element present. Conversely, when an element is referred to as being "directly" above or extending "directly" above another element, there is no intermediary element present. It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, the element may be directly connected or coupled to the other element, or there may be an intermediary element present. Conversely, when an element is referred to as being "directly connected" or "directly coupled" to another element, there is no intermediary element present.

[0016] As illustrated in the schematic, relative terms (e.g., "below" or "above" or "top" or "bottom" or "horizontal" or "vertical") may be used herein to describe the relationship between an element, layer, or region and another element, layer, or region. It will be understood that, in addition to the orientations depicted in the figures, these terms and the above-discussed terms are intended to cover different orientations of the device.

[0017] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the disclosure. As used herein, unless clearly indicated otherwise, the single forms “a,” “an,” and “described” are intended to include multiple forms. It will also be understood that, when used herein, the terms “comprising” and / or “including” expressly indicate the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0018] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art.It will also be understood that the terms used herein should be interpreted in a meaning consistent with the context of this specification and related prior art, and should not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0019] Embodiments are described herein with reference to illustrative illustrations of embodiments of this disclosure. Therefore, the actual dimensions of layers and elements may vary, and deviations in illustrated shapes are expected due to, for example, manufacturing techniques and / or tolerances. For example, areas drawn or described as square or rectangular may have circular or curved features, and areas shown as straight lines may have some irregularities. Therefore, the areas illustrated in the figures are illustrative and their shapes are not intended to show the precise shapes of areas of the device, nor are they intended to limit the scope of this disclosure. Furthermore, the size of structures or areas may be particularly exaggerated relative to other structures or areas for illustrative purposes, and therefore, provided to illustrate the general structure of the subject matter of the invention, may or may not be drawn to scale. Common elements between the figures may be shown herein using common element symbols, and may not be described again thereafter on page 2 / 5 of the specification, CN 121925783 A.

[0020] FIG1 is a generalized diagram depicting an embodiment of a bias circuit system 10 in normal operation, wherein a bias generator 12 is configured to generate a bias level, which may be a bias voltage or bias current output via a bias generator output terminal 14. The bias generator 12 is configured to maintain the bias level by means of an regulated feedback loop 16 coupled between the bias generator output terminal 14 and the feedback terminal 18. In this exemplary embodiment, the bias level is maintained as proportional to a first reference voltage VREF1 input at a first reference terminal 20. A switching circuit system 22 is configured to switch the bias level at the bias generator output terminal 14 to the amplifier bias output terminal 24 via a first switch SW1 during normal operation. The first switch SW1 is symbolically depicted as a single-pole double-throw switch in FIG1. ​​However, the first switch SW1 is typically composed of a transistor.

[0021] As shown in FIG1, a bias level can be used to bias the radio frequency (RF) amplifier 26. The bias level is received at the bias input terminal 28. In normal operation, the RF amplifier 26 receives an RF signal at the RF input terminal 30 labeled RFIN and outputs an amplified version of the RF signal via the RF output terminal 32 labeled RFOUT. The RF amplifier 26 is powered via the supply terminal 34 and the fixed node terminal 36. In this exemplary embodiment, the supply voltage VCC is applied to the supply terminal 34 and grounded (GND) coupled to the fixed voltage node 36. Other embodiments may couple a negative DC voltage to the fixed node terminal 36.

[0022] For example, the RF amplifier of the RF amplifier 26 may be damaged or destroyed by temporary spikes in the supply voltage VCC.To mitigate the possibility of overvoltage damage, the bias circuit system 10 includes an overvoltage detector 38 configured to generate a disconnect signal DIS_OUT, which switches the bias level output from the bias generator 12 to a protective load 40 coupled between the load terminal 42 and the fixed voltage terminal 36. The protective load 40 may be a load resistor RLD and / or a load capacitor CLD. In the exemplary embodiment of FIG1, the protective load 46 is a parallel combination of the load resistor RLD and the load capacitor CLD. In embodiments where only the load capacitor CLD constitutes the protective load 40, the charge stored by the load capacitor will be substantially dissipated before a subsequent charging event occurs.

[0023] The control terminal 44 of the first switch SW1 is coupled to the overvoltage signal terminal 46 of the overvoltage detector 38. The logic state of the disconnect signal DIS_OUT determines whether the bias level generator 12 applies to the bias input terminal 28 or the protective load 40. The overvoltage detector 38 has a voltage sensing terminal 48 that senses the instantaneous voltage level of the supply voltage VCC. The overvoltage detector 38 also has a second reference voltage terminal 50, where a second reference voltage VREF2 is applied. The overvoltage detector 38 is configured to compare the instantaneous voltage level of the supply voltage VCC with the second reference voltage VREF2, and in response generates a logic state of a disconnect signal DIS_OUT. The first logic state of the disconnect signal DIS_OUT is a connected state, which connects the bias generated by the bias generator to the amplifier bias output terminal 24 coupled to the bias input 28 of the RF amplifier 26. FIG1 depicts the bias level applied to the bias input terminal 28 via the first switch SW1, as the overvoltage detector 38 shows that the detected supply voltage is less than the second reference voltage VREF2.

[0024] FIG2 depicts the bias circuit system 10 in response to the overvoltage detector 38 generating a second logic state of the disconnect signal DIS_OUT, in which case the logic state is a disconnect state in response to an overvoltage event. The disconnect state of the disconnect signal DIS_OUT disconnects the bias generated by the bias generator 12 from the amplifier bias output terminal 24 by means of the first switch SW1. The first switch SW1 then connects the bias level to the protected load 40 for the duration of the overvoltage event. Figure 2 depicts the bias level applied to the load terminal 42 via the first switch SW1, as the overvoltage detector 38 shows that the detected supply voltage is greater than the second reference voltage VREF2. The advantage of the bias circuit system 10 over conventional circuit systems with similar functionality is that the bias circuit system 10 is configured to maintain the regulation feedback loop 16 closed while the resulting bias level switches to the protected load 40, ensuring a lower release time / reconnection time.

[0025] Figure 3 is a diagram of an exemplary detailed embodiment of the bias circuit system 10 of Figures 1 and 2.An exemplary version of the bias generator 12 includes a bias amplifier 52 coupled between the bias generator output terminal 14, the feedback terminal 18, and the first reference terminal (page 3 / 5, CN 121925783 A 20). A first feedback resistor RF1 is coupled within a feedback loop 16 between the bias generator output terminal 14 and the feedback terminal 18. A second feedback resistor RF2 is coupled between the feedback terminal and ground.

[0026] An exemplary embodiment of the switching circuit system 22 is also depicted in FIG3. In this exemplary embodiment, the first switch SW1 is composed of a first transistor M1, a second transistor M2, and a third transistor M3. The first transistor M1 is a P-channel field-effect transistor (PFET) having a first source S1 coupled to the bias generator output terminal 14, a first drain D1 coupled to the amplifier bias output terminal 24, and a first gate G1 coupled to the control terminal 44. The second transistor M2 is an N-channel FET (NFET) having a second drain D2 coupled to the first drain D1, a second source S2 coupled to ground, and a second gate G2 coupled to the control terminal 44. The third transistor M3 is a PFET having a third source S3 coupled to the bias generator output terminal 14, a third drain D3 coupled to the load terminal 42, and a third gate G3 coupled to the control terminal 44 via an inverter logic gate 54.

[0027] FIG3 also depicts an exemplary embodiment of the overvoltage detector 38. In this exemplary embodiment, the operational transconductance amplifier (OTA) 56 is configured as a comparator to compare the supply voltage VCC with the second reference voltage VREF2. The OTA 56 is coupled between the voltage sensing terminal 48, the second reference voltage terminal 50, and the OTA output terminal 58. The Schmitt trigger 60 has a trigger input 62 coupled to the OTA output terminal 58 and a trigger output terminal 64 coupled to the overvoltage signal terminal 46.

[0028] The method according to this disclosure offers advantages in reconnection / release time because it does not de-energize any part of the circuitry in the bias generator and does not pull down the feedback point. The differences in release time are shown in Table 1. The feedback loop is similar to a conventional amplifier configuration of an operational transconductance amplifier or operational amplifier as shown in Figure 3. The advantage of not cutting off the feedback is evident from the structure of the bias circuitry 10, making the possible response and release times of the disclosed method readily apparent.

[0029]

[0030] Table 1

[0031] The disclosed bias circuitry 10 and operating method use a first switch SW1 and a protective load 40 to maintain regulator operation only when the bias level output to the RF amplifier 26 is deactivated for a short period of time or reactivated within a short time.

[0032] The disclosed method can also be implemented with other types of loads; for example, a regulator capacitor can be constantly connected to the regulated voltage to act as another load to maintain regulator operation when the output is deactivated.This demonstrates how the disclosed method maintains regulation loop operation even when the bias output is turned off, resulting in a much faster recovery time.

[0033] Figure 4 is a schematic diagram of an exemplary communication device 66 that may employ the bias circuit system 10. In this document, the communication device 66 may be, for example, a mobile terminal, smartwatch, tablet computer, computer, navigation device, access point, base station (e.g., eNB or gNB), and any other type of wireless communication device that supports wireless communication, such as cellular, wireless local area network (WLAN), Bluetooth, ultra-wideband (UWB), and near-field communication. The communication device 66 typically includes a control system 68, a baseband processor 70, a transmitting circuit system 72, a receiving circuit system 74, an antenna switching circuit system 76, multiple antennas 78, and a user interface circuit system 80. In a non-limiting example, for example, the control system 68 may be a field-programmable gate array (FPGA). In this regard, the control system 68 may include at least one or more of a microprocessor, embedded memory circuitry, and a communication bus interface. The receiving circuitry 74 receives radio frequency signals from one or more base stations via antenna 78 and antenna switching circuitry 76. Low-noise amplifiers and filters cooperate to amplify and remove broadband interference from the received signals for processing. A down-conversion and digitization circuitry (not shown) then down-converts the filtered received signal into an intermediate frequency (IF) or baseband signal, which is then digitized into one or more digital streams using one or more analog-to-digital converters (ADCs).

[0034] The baseband processor 70 processes the digitized received signal to retrieve information or data bits conveyed in the received signal. This processing typically includes demodulation, decoding, and error correction operations, as will be discussed in more detail below. The baseband processor 70 is typically implemented using one or more digital signal processors (DSPs) and application-specific integrated circuits (ASICs).

[0035] For transmission, the baseband processor 70 receives digitized data representing voice, data, or control information, encoded by the control system 68, for transmission. The encoded data is output to the transmitting circuitry system 72, where a digital-to-analog converter (DAC) converts the digitally encoded data into an analog signal, and a modulator modulates the analog signal onto a carrier signal at one or more desired transmission frequencies. For example, the power amplifier of RF amplifier 26 (Figures 1-3) amplifies the modulated carrier signal to a level suitable for transmission and delivers the modulated carrier signal to antenna 78 via antenna switching circuitry system 76. Multiple antennas 78 and replicated transmitting circuitry system 72 and receiving circuitry system 74 provide spatial versatility. Those skilled in the art will understand the modulation and processing details.

[0036] In one embodiment, the bias circuit system 10 may be provided in any one or more of the circuit systems in the communication device 66, such as the transmitting circuit system 72 and / or the receiving circuit system 74.

[0037] Additional advantages may be obtained by combining any of the foregoing aspects and / or various individual aspects and features described herein. Unless otherwise indicated herein, any of the various embodiments disclosed herein may be combined with one or more other disclosed embodiments.

[0038] Those skilled in the art will understand improvements and modifications to the preferred embodiments of this disclosure. All such improvements and modifications are considered to be within the scope of the concepts disclosed herein and the appended claims. Instruction manual, page 5 / 5; CN 121925783 A, Figure 1; Instruction manual, Figure 1 / 4, page 9; CN 121925783 A, Figure 2; Instruction manual, Figure 2 / 4, page 10; CN 121925783 A, Figure 3; Instruction manual, Figure 3 / 4, page 11; CN 121925783 A, Figure 4; Instruction manual, Figure 4 / 4, page 12; CN 121925783 A.

Claims

1. A bias circuit system (10) for an amplifier, comprising: ● Bias generator (12), which has a bias generator output terminal (14); and ● A switch having a bias input terminal (28), an amplifier bias output terminal (24), a bias shunt terminal and a switch control terminal, wherein the switch is configured to switch the bias generated by the bias generator to the amplifier bias output terminal in response to a connection bias signal received at the switch control terminal, and to switch from the amplifier bias output terminal to the bias shunt terminal in response to a disconnect bias signal.

2. The bias circuit system of claim 1, wherein the bias circuit system further comprises an overvoltage detector (38) configured to monitor the supply voltage of the amplifier and, in response, generate the disconnect bias signal when the supply voltage exceeds a reference voltage and generate the connection bias signal when the supply voltage level is less than the reference voltage.

3. The bias circuit system according to claim 1, further comprising a parallel load coupled between the bias shunt terminal and ground.

4. The bias circuit system according to claim 3, wherein the parallel load is a resistor.

5. The bias circuit system according to claim 3, wherein the parallel load is a capacitor.

6. The bias circuit system according to claim 3, wherein the parallel load is a resistor coupled in parallel with the capacitor.

7. The bias circuit system of claim 3, wherein the bias generator has a closed feedback loop configured to remain closed when the bias is shunt to the bias shunt terminal.

8. A method for protecting an amplifier having a bias circuit system (10), the bias circuit system comprising a bias generator (12) having a bias generator output terminal (14), and a switch having a bias input terminal (28), an amplifier bias output terminal (24), a bias shunt terminal, and a switch control terminal, the method comprising switching a bias generated by the bias generator to the amplifier bias output terminal in response to a connection bias signal received at the switch control terminal, and switching from the amplifier bias output terminal to the bias shunt terminal in response to a disconnect bias signal.

9. The method of protecting the amplifier according to claim 8, further comprising monitoring the supply voltage of the amplifier by means of an overvoltage detector (38), and generating the disconnect bias signal in response to the supply voltage exceeding a reference voltage, and generating the connection bias signal when the supply voltage level is less than the reference voltage.

10. The method of protecting the amplifier according to claim 8, further comprising shunting the bias voltage to a parallel load coupled between the bias shunt terminal and ground in response to the disconnect bias signal, such that the load is maintained on the bias generator.

11. The method for protecting the amplifier according to claim 10, wherein the parallel load is a resistor.

12. The method for protecting the amplifier according to claim 10, wherein the parallel load is a capacitor.

13. The method for protecting the amplifier according to claim 10, wherein the parallel load is a resistor coupled in parallel with the capacitor.

14. A wireless communication device (66), comprising: ●Baseband processor (70); ● A transmitting circuit system (72) configured to receive encoded data from the baseband processor and modulate a carrier signal with the encoded data, wherein the transmitting circuit system includes: ● An amplifier configured to amplify the carrier signal; and ● The bias circuit system (10) for the amplifier includes: ● Bias generator (12), which has a bias generator output terminal (14); and ● A switch having a bias input terminal (28), an amplifier bias output terminal (24), a bias shunt terminal and a switch control terminal, wherein the switch is configured to switch the bias generated by the bias generator to the amplifier bias output terminal in response to a connection bias signal received at the switch control terminal, and to switch from the amplifier bias output terminal to the bias shunt terminal in response to a disconnect bias signal.

15. The wireless communication device of claim 14, wherein the bias circuit system further includes an overvoltage detector (38) configured to monitor the supply voltage of the amplifier and, in response, generate the disconnect bias signal when the supply voltage exceeds a reference voltage and generate the connection bias signal when the supply voltage level is less than the reference voltage.

16. The wireless communication device of claim 14, further comprising a parallel load coupled between the bias shunt terminal and ground.

17. The wireless communication device of claim 16, wherein the parallel load is a resistor.

18. The wireless communication device of claim 16, wherein the parallel load is a capacitor.

19. The wireless communication device of claim 16, wherein the parallel load is a resistor coupled in parallel with the capacitor.

20. The wireless communication device of claim 16, wherein the bias generator has a closed feedback loop configured to remain closed when the bias is shunt to the bias shunt terminal.

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