Fourier transformation device and radio communication device

Abstract

To reduce the storage capacity that a Fourier transformation device requires to store a twiddle factor.SOLUTION: A Fourier transformation device which performs fast Fourier transformation or inverse fast Fourier transformation of N points comprises a rotor 222 which performs a rotational operation and a rotation memory 28 which stores a twiddle factor. The rotation memory 28 includes a first rotation memory 43 which stores a plurality of first twiddle factors corresponding to rotation positions obtained by equally dividing 2π by N1 (where n1 is an integer equal to or larger than 3, and N1 is an integer of 2 raised to the power of n1), and a second rotation memory 44 which stores a plurality of second twiddle factors corresponding to rotation positions obtained by equally dividing 2π / N1 by N2, where N / N1 is N2 (n2 is an integer equal to or larger than 1, and N2 is an integer of 2 raised to the power of n2. The rotor 222 comprises a first complex multiplier 41 which has one of the plurality of first twiddle factors selectively set, and a second complex multiplier 42 which is connected to the first complex multiplier 41 in series, and has one of the plurality of second twiddle factors selectively set.SELECTED DRAWING: Figure 5

Description

Technical Field

[0001] The present invention relates to a Fourier transform device that performs a fast Fourier transform (including an inverse fast Fourier transform) and a communication device.

Background Art

[0002] Conventionally, fast Fourier transform (hereinafter also referred to as "FFT") has been used in various fields. When hardware-implementing FFT, various studies have been made for the purpose of speeding up processing, improving efficiency, reducing the memory used, etc., as shown in Non-Patent Document 1. As one of the architectures for efficiently executing FFT, one called "Radix-2 k " is known (Non-Patent Document 2). The k in Radix-2 k represents an integer of 2 or more. For example, as one that proposed the Radix-2 4 algorithm, there is Non-Patent Document 3. By adopting the Radix-2 k algorithm, simplification of the calculation of the rotation factor in FFT is realized. Note that the "k" in Radix-2 k is not related to the variable k in the Fourier transform described later.

[0003] On the other hand, a method for reducing the area for storing the rotation factor in FFT has also been proposed. For example, in Patent Document 1, paying attention to the phase shift between the cosine function and the sine function with respect to the rotation factor, and the positive-negative symmetry thereof, a technique for reducing the memory usage amount by storing only the positive values of the trigonometric functions in the memory without duplicating the rotation factor is disclosed. Further, in Patent Document 2, a technique for realizing speeding up of the calculation and reduction of the capacity of the memory for storing data by using fixed-point arithmetic using integer arithmetic instead of double-precision floating-point arithmetic in the FFT calculation is disclosed.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Patent Document 2

Non-Patent Document

[0005]

Non-Patent Document 1

Non-Patent Document 2

Non-Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0006] By the way, in the FFT, a rotation matrix corresponding to the rotation positions that divide the unit circle on the complex plane, called rotation factors, into N equal parts is used. The rotation factors are combinations of the values of the cosine function and the sine function, and in order to achieve high frequency resolution in the FFT, it is necessary to store a large number of rotation factors. Therefore, a storage device with a large storage capacity is required, increasing the manufacturing cost of the Fourier transform device. However, simply using the symmetry of the cosine function and the sine function as in Patent Document 1 has limitations in reducing the storage capacity required to store the rotation factors.

[0007] Reduction of the storage capacity for storing the rotation factors is particularly important when implementing the FFT (Fast Fourier Transform) on an FPGA (Field Programmable Gate Array) or the like where the path for reading the rotation factors is hardware-limited. Note that the reduction of the storage capacity for storing the rotation factors is the same in the inverse fast Fourier transform (IFFT).

[0008] The present invention has been made in view of the above problems, and an object thereof is to reduce the storage capacity required for storing rotation factors in a Fourier transform device.

Means for Solving the Problems

[0009] Aspect 1 of the present invention is a Fourier transform device that performs a fast Fourier transform or an inverse fast Fourier transform of N points (where N is a power of 2 and n is an integer of 5 or more), including a rotator that performs a rotation operation and a rotation memory that stores rotation factors. The rotation memory includes a first rotation memory that stores a plurality of first rotation factors corresponding to rotation positions obtained by equally dividing 2π into N1 parts (where N1 is an integer that is a power of 2 with n1 being an integer of 3 or more), and a second rotation memory that stores a plurality of second rotation factors corresponding to rotation positions obtained by equally dividing 2π / N1 into N2 parts with N / N1 being N2 (where N2 is an integer that is a power of 2 with n2 being an integer of 1 or more). The rotator performs a rotation operation by combining a first rotation factor selected from the plurality of first rotation factors and a second rotation factor selected from the plurality of second rotation factors.

[0010] Aspect 2 of the present invention is the Fourier transform device according to Aspect 1, including a Radix-2 k circuit that executes operations using the Radix-2 k algorithm, and the rotator is connected to the Radix-2 k circuit or is included in the Radix-2 k circuit.

[0011] Aspect 3 of the present invention is the Fourier transform device of Aspect 2, which is a circuit that performs Fourier transform or inverse Fourier transform with single input and output respectively, and further includes a plurality of small Fourier transform circuits arranged in parallel. A Radix-2 k circuit is arranged on the downstream side of the plurality of small Fourier transform circuits, and a plurality of rotators including the rotator are arranged between the plurality of small Fourier transform circuits and the Radix-2 k circuit, and it is a multi-path-delay-feedback type.

[0012] Aspect 4 of the present invention is the Fourier transform device of Aspect 3, wherein the number of the plurality of small Fourier transform circuits is P (where P is a power of 2 and p is an integer of 2 or more), and (P - 1) rotators including the rotator are arranged between the plurality of small Fourier transform circuits and the Radix-2 k circuit, and it is a multi-path-delay-feedback type.

[0013] Aspect 5 of the present invention is the Fourier transform device of Aspect 2, which is a circuit that performs Fourier transform or inverse Fourier transform with single input and output respectively, and further includes 16 small Fourier transform circuits arranged in parallel. A Radix-2 k circuit, that is, a Radix-2 4 circuit is arranged on the downstream side of the plurality of small Fourier transform circuits, and 15 rotators including the rotator are arranged between the 16 small Fourier transform circuits and the Radix-2 4 circuit, and it is a multi-path-delay-feedback type.

[0014] Aspect 6 of the present invention is the Fourier transform device of Aspect 1 (which may be any one of Aspects 1 to 5). A digital signal obtained by digitally converting an analog signal with a bandwidth of 4 GHz or more is input, and the frequency resolution at the output is 100 kHz or less, or the frequency resolution in the input frequency information is 100 kHz or less, and the bandwidth of the analog signal obtained by analog-converting the output digital signal is 4 GHz or more.

[0015] Aspect 7 of the present invention is the Fourier transform device of Aspect 6, wherein the frequency resolution in the output is 50 kHz or less, or the frequency resolution in the input frequency information is 50 kHz or less.

[0016] Aspect 8 of the present invention is a device for frequency analyzing a digital signal converted from a high-frequency analog signal of 300 MHz or more and 300 GHz or less, which is any one of the Fourier transform devices of Aspects 1 to 7 that perform the fast Fourier transform.

[0017] Aspect 9 of the present invention is a wireless communication device, comprising an analog-digital converter or digital-analog converter connected to an antenna, and any one of the Fourier transform devices according to any one of Aspects 1 to 7 that Fourier-transforms the digital signal output from the analog-digital converter or inverse Fourier-transforms digital information and sends it to the digital-analog converter.

Advantages of the Invention

[0018] According to the present invention, it is possible to reduce the storage capacity required for storing rotation factors in a Fourier transform device.

Brief Description of the Drawings

[0019]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Mode for Carrying Out the Invention

[0020] FIG. 1 is a diagram showing a schematic configuration of a frequency analysis device 10 including a Fourier transform device 12 according to an embodiment of the present invention. The frequency analysis device 10 includes an A / D (analog-digital) converter 11, a Fourier transform device 12, an analysis processing unit 13, and a display unit 14. The A / D converter 11 is electrically connected to an antenna 15. The antenna 15 may be regarded as a part of the frequency analysis device 10. Conversely, the A / D converter 11 may be regarded as not being included in the frequency analysis device 10. What inputs a signal to the A / D converter 11 is not limited to the antenna 15, and a high-frequency analog signal such as a high-frequency signal generation circuit or a noise component generated in an electric circuit may be input to the A / D converter 11. That is, the frequency analysis device 10 may be used for measurement of a high-frequency signal (RF) circuit.

[0021] The antenna 15 converts an electromagnetic wave into an electrical analog signal and outputs it to the A / D converter 11. The A / D converter 11 samples the analog signal at high speed and at regular intervals and converts it into a digital signal, that is, an array of time-series numerical values. Note that the analog signal may be input to the A / D converter 11 after the frequency band of the analog signal is shifted to the low-frequency side by a mixer.

[0022] An array of numerical values (hereinafter, also referred to as "input data") from the A / D converter 11 is input to the Fourier transform device 12, and the input data is converted into an array of numerical values indicating the amplitude for each frequency (hereinafter, also referred to as "output data") and output. That is, a fast Fourier transform (FFT) is performed on the input data indicating a value that changes with time, and the input data is converted into output data indicating the magnitude of components in the frequency domain.

[0023] The analysis processing unit 13 converts the output data from the Fourier transform device 12 into information suitable for display by the display unit 14. For example, the output data repeatedly output from the Fourier transform device 12 at high speed is averaged for each frequency at regular time intervals and output. As a result, the person observing the display unit 14 can appropriately grasp the analysis result in real time.

[0024] The frequency analysis device 10 can be used for various applications, and is particularly suitable when wideband and continuous measurement are required. The frequency analysis device 10 can be applied to, for example, frequency measurement in radio astronomy observations, multiplexed readout technology for superconducting detectors, communication technology, etc. For the details of the antenna 15 and the frequency analysis device 10, configurations according to the application are appropriately adopted. For example, as the antenna 15, an antenna for receiving radio waves from space, an antenna used for wireless communication, etc. are appropriately adopted. Of course, the frequency analysis device 10 can be used in various other frequency analysis fields.

[0025] As will be described later, in the Fourier transform device 12 provided in the frequency analysis device 10, the storage capacity for storing the rotation factors can be reduced, so that the manufacturing cost of the analysis device can be reduced. This effect is particularly obtained when the Fourier transform device 12 is implemented in hardware. Also, the power consumption is reduced.

[0026] For example, in the field of radio astronomy observations, it is necessary to perform real-time frequency analysis of radio waves from space in the observation of dark matter in outer space. Therefore, it is necessary to implement the fast calculation of FFT as hardware using electric circuits such as FPGA and ASIC (Application Specific Integrated Circuit). However, to execute FFT at high speed and with high frequency resolution, an enormous storage capacity for rotation factors is required, and it is impossible to achieve with commercially available hardware such as FPGA. In the Fourier transform device 12 described below, while suppressing the decrease in the calculation speed, the storage capacity required for storing the rotation factors can be significantly reduced, and the circuit scale on the hardware including the memory can be reduced, making it possible to be mounted on commercially available hardware.

[0027] Figure 2 is a diagram showing the configuration of the FFT circuit 2 included in the Fourier transform device 12. In Figure 2, the left side is the input side of the FFT circuit 2, and the right side is the output side. The FFT circuit 2 includes, in order from the input side to the output side, a small FFT circuit group 211, a first rotator group 212, a first butterfly arithmetic unit group 213, a second rotator group 214, a second butterfly arithmetic unit group 215, a third rotator group 216, a third butterfly arithmetic unit group 217, a fourth rotator group 218, and a fourth butterfly arithmetic unit group 219. Note that the "group" means a set of one or more identical or similar elements. The small FFT circuit group 211 includes 16 small FFT circuits 221, each of which performs an FFT operation. As will be described later, each small FFT circuit 221 is a single input / output, that is, a 1-input 1-output type FFT circuit.

[0028] The first rotator group 212 includes 15 first rotators 222, and it is possible to set a selected rotation factor for each of them as will be described later. A "rotator" is a circuit that performs a rotation operation of multiplying a rotation matrix. The second rotator group 214 includes four second rotators 224, and the rotation by the second rotator 224 is fixed to a 90° rotation operation. In Figure 2, a rotator that performs a 90° rotation operation is represented by "-i" (the same applies hereinafter). The fourth rotator group 218 is the same as the second rotator group 214 and includes four first rotators 228 that perform a 90° rotation operation. The third rotator group 216 includes nine third rotators 226. These perform rotation operations with various rotation angles, but the rotation angle in each third rotator 226 is fixed.

[0029] The first butterfly arithmetic unit group 213 has eight first butterfly arithmetic units 223. The second butterfly arithmetic unit group 215 has eight second butterfly arithmetic units 225. The third butterfly arithmetic unit group 217 has eight third butterfly arithmetic units 227. The fourth butterfly arithmetic unit group 219 has eight fourth butterfly arithmetic units 229. In FIG. 2, the butterfly arithmetic units are denoted by "R2" (the same applies hereinafter). FIG. 3 is a diagram showing one butterfly arithmetic unit 30 (corresponding to the first to fourth butterfly arithmetic units 223, 225, 227, 229). When values A and B are input to the butterfly arithmetic unit 30, the butterfly arithmetic unit 30 outputs the values (A + B) and (A - B).

[0030] Next, the operations corresponding to the configuration of the FFT circuit 2 will be described. Equation 1 is an equation showing the discrete Fourier transform of size N, that is, an equation for performing Fourier transform on N-point samples. However, N is a power of 2, and in the present embodiment, n is an integer of 5 or more. By the Fourier transform, a function x(t) with time t as a variable is transformed into a function x tilde (k) with frequency k as a variable (hereinafter, x tilde with a ~ above x is also expressed as "x~"). In other words, by the Fourier transform, time-series data x(t) is transformed into spectral data x~(k).

[0031]

Equation

[0032] Here, the right side shows the sum of the expressions within Σ when t changes from 0 to (N - 1). However, when Equation 1 is divided by the remainder t' obtained by dividing t by 16 with t = t' + 16t", Equation 2 is obtained.

[0033]

Equation

[0034] In Equation 2, the left Σ of the two Σs indicates a 16-fold division, and the right Σ part indicates the terms of the remainder t' extracted. The size of the right Σ part is N / 16.

[0035] Here, if we set \(k = (\frac{N}{16})k'+k''\), Equation (2) becomes Equation (3). Furthermore, since \((-2\pi i)\) - th power of \(e\) represents a rotation of \(2\pi\), that is, 1, and the \((-2\pi i)\) - th power of an integer multiple of \(e\) is also 1, the right - hand side of Equation (3) becomes Equation (4).

[0036]

Number

[0037]

Number

[0038] In Equation (4), the right - most \(x(t'+16t'')\) with the subscript \((4 - 1)\) represents the input value. The \(\sum\) part with the subscript \((4 - 2)\) on its left represents an \(N / 16\) - point discrete Fourier transform that Fourier - transforms a function of \(t''\) into a function of \(k''\). The \((-2\pi i(k''t' / N))\) - th power of \(e\) with the subscript \((4 - 3)\) represents a rotation factor.

[0039] Regarding the \(\sum\) part with the subscript \((4 - 4)\) on the left - most side, set \(k'=8k'_0 + 4k'_1+2k'_2 + k'_3\) (where \(k'_0,k'_1,k'_2,k'_3\) are 0 or 1) and \(t'=t'_0 + 2t'_1+4t'_2 + 8t'_3\) (where \(t'_0,t'_1,t'_2,t'_3\) are 0 or 1). Then, the part of Equation (4) with the subscript \((4 - 4)\) becomes Equation (5). Here, the fact that the \((-2\pi i)\) - th power of an integer multiple of \(e\) is 1 is also utilized. Equation (5) shows the (main) operation part to which the Radix - 2 4 algorithm is applied.

[0040]

Number

[0041] Next, the correspondence between the FFT circuit 2 in FIG. 2, Equation (4), and Equation (5) will be described.

[0042] The leftmost input in Figure 2 corresponds to (4 - 1) of the number 4. The small FFT circuit group 211 corresponds to (4 - 2) of the number 4. That is, each small FFT circuit 221 performs a discrete fast Fourier transform of N / 16 points and converts a function of t” into a function of k”.

[0043] Figure 4 is a diagram illustrating one small FFT circuit 221. The small FFT circuit 221 in Figure 4 is a one-input one-output type Fourier transform circuit. Various forms different from Figure 4 can be adopted as the small FFT circuit 221. The small FFT circuit 221 in Figure 4 has a plurality of butterfly calculators 31. Each butterfly calculator 31 performs the same calculation as the butterfly calculator 30 shown in Figure 3. A delay memory 32 is connected to each butterfly calculator 31, and it can appropriately store the values input to the butterfly calculator 31 and the values output from the butterfly calculator 31, and output them at a desired timing. Between the butterfly calculators 31 connected in series, a rotator 33 and a rotator 35 fixed to a 90° rotation (illustrated by “-i”) are provided as necessary. One of the plurality of rotation factors stored in the rotation memory 34 is selected and set for the rotator 33. The rotation memory 34 stores the rotation factors for performing the N / 16-point FFT calculation.

[0044] The first rotator group 212 in Figure 2 corresponds to the part indicated by (4 - 3) of the number 4 and represents the rotation of 2π·(m / N) by W N m and is expressed as. Each m of W N m is k”t’. The rotation factor of W N m is set for each calculation for each first rotator 222.

[0045] The first butterfly calculator group 213 corresponds to the rightmost Σ part indicated by (5 - 1) of number 5. Between the first rotator group 212 and the first butterfly calculator group 213, connections are made such that for each first butterfly calculator 223, those with the same values for t’2, t’1, and t’0 and with t’3 being 0 and 1 are input. For example, to the topmost first butterfly calculator 223, the value from the topmost small FFT circuit 221 and the value derived from the 9th small FFT circuit 221 from the top are input. The 9th input differs from the 1st input only in the value of t’3. By the first butterfly calculator group 213, t’3 is converted to k’3 (precisely, the function with t’3 as a variable is converted to the function with k’3 as a variable. The same expression will be used hereinafter).

[0046] The second rotator group 214 corresponds to the part indicated by (5 - 2) of number 5. Here, since k’3t’2 is 0 or 1, at the second rotator group 214 (position), a rotation operation of 0 (i.e., no rotation) or 2π / 4 (= 90°) is performed. Only 4 second rotators 224 are provided as the second rotator group 214, and each second rotator 224 performs a fixed operation.

[0047] The second butterfly calculator group 215 corresponds to the second Σ part from the right indicated by (5 - 3) of number 5. Between the second rotator group 214 and the second butterfly calculator group 215, connections are made such that for each second butterfly calculator 225, those with the same values for k’3, t’1, and t’0 and with t’2 being 0 and 1 are input. By the second butterfly calculator group 215, t’2 is converted to k’2.

[0048] The third rotator group 216 corresponds to the part indicated by (5 - 4) in Equation 5. Here, since (2k’2 + k’3)·(t’0 + 2t’1) / 16 is 0, 1, 2, 3, 4, 6, or 9, rotation operations of 0 (i.e., no rotation), 2π / 16 (= 22.5°), 2π / 8 (= 45°), 2π·3 / 16 (= 67.5°), 2π / 4 (= 90°), 2π·3 / 8 (= 135°), and 2π·9 / 16 (= 202.5°) are performed at the third rotator group 216. Only nine third rotators 226 are provided as the third rotator group 216, and each third rotator 226 performs a fixed operation.

[0049] The third butterfly calculator group 217 corresponds to the third Σ part from the right indicated by (5 - 5) in Equation 5. The third rotator group 216 and the third butterfly calculator group 217 are connected such that for each third butterfly calculator 227, those with the same values of k’3, k’2, and t’0 and with t’1 being 0 and 1 are input. The third butterfly calculator group 217 converts t’1 to k’1.

[0050] The fourth rotator group 218 corresponds to the part indicated by (5 - 6) in Equation 5. Here, since k’1t’0 is 0 or 1, rotation operations of 0 (i.e., no rotation) or 2π / 4 (= 90°) are performed at the fourth rotator group 218. Only four fourth rotators 228 are provided as the fourth rotator group 218, and each fourth rotator 228 performs a fixed operation.

[0051] The fourth butterfly calculator group 219 corresponds to the fourth Σ part from the right indicated by (5 - 7) in Equation 5. The fourth rotator group 218 and the fourth butterfly calculator group 219 are connected such that for each fourth butterfly calculator 229, those with the same values of k’3, k’2, and k’1 and with t’0 being 0 and 1 are input. The fourth butterfly calculator group 219 converts t’0 to k’0.

[0052] Through the above processing, when the inputs x(16t”), x(16t” + 1), x(16t” + 2), ···, x(16t” + 15) are sequentially input in parallel, x~(k”), x~(k”+(1 / 16)N), x~(k”+(2 / 16)N), ···, x~(k”+(15 / 16)N) (where the order of output is as shown on the right side (Output) of Figure 2.) are sequentially output in parallel.

[0053] Next, the first rotator group 212 will be described. Figure 5 is a diagram showing the configuration of one first rotator 222 and the rotation memory 28 connected thereto. The rotation memory 28 stores rotation factors. The rotation memory 28 is commonly used for each first rotator 222 in the first rotator group 212. That is, one rotation memory 28 (specifically, a set of first complex multipliers 41 and second complex multipliers 42 described later) is provided for the first rotator group 212. The first rotator 222 includes a first complex multiplier 41 and a second complex multiplier 42. The first complex multiplier 41 and the second complex multiplier 42 are connected in series. Each of the first complex multiplier 41 and the second complex multiplier 42 is an arithmetic unit that multiplies a rotation matrix, and each is a rotator. That is, the first rotator 222 is formed by connecting two rotators in series. The rotation memory 28 includes a first rotation memory 43 and a second rotation memory 44. The first rotation memory 43 is connected to the first complex multiplier 41. The second rotation memory 44 is connected to the second complex multiplier 42.

[0054] In the first rotation memory 43, N1 first rotation factors corresponding to rotation positions obtained by equally dividing 2π into N1 parts (which are rotation positions on the unit circle centered at the origin and can also be expressed as the rotation angle or rotation amount from the 0° position) are stored. Here, N1 is an integer that is a power of 2 with n1 being an integer of 3 or more. The "rotation factor corresponding to the rotation position" means a rotation factor that rotates by the rotation angle from the 0° position to the rotation position being focused on on the unit circle in the complex plane. On the other hand, setting N2 = N / N1 (that is, N = N1·N2), the second rotation memory 44 stores N2 second rotation factors corresponding to rotation positions obtained by equally dividing 2π / N1 into N2 parts. Here, N2 is an integer that is a power of 2 with n2 being an integer of 1 or more. n is n1 + n2 and is 5 or more.

[0055] In other words, the first rotation memory 43 stores a first rotation factor that rotates by (2π / N1)·a (where a is an integer and 0 ≤ a < N1), and the second rotation memory 44 stores a second rotation factor that rotates by (2π / N)·b (where b is an integer and 0 ≤ b < N2). In this way, the second rotation factor corresponds to a precise rotation angle that interpolates between the rough rotation positions corresponding to a plurality of first rotation factors. Then, any one of the plurality of first rotation factors is selectively set in the first complex multiplier 41, and any one of the plurality of second rotation factors is selectively set in the second complex multiplier 42. By connecting the first complex multiplier 41 and the second complex multiplier 42 in series, multiplication of the rotation matrices that are the first rotation factor and the second rotation factor is performed, and a rotation operation of the rotation angle obtained by adding the rotation angles indicated by both rotation factors is performed.

[0056] In the actually fabricated FFT circuit 2, N is 2 to the 17th power (2 17 ) and N1 is 2 to the 10th power (2 10 ), and N2 is 2 to the 7th power (2 7 ). That is, the first rotation memory 43 stores (substantially) 2 10 complex numbers, and 2 11 real numbers are stored. The second rotation memory 44 stores 2 7 complex numbers, and 2 8are stored. However, in reality, due to the symmetry every π / 2 rotation, the number of complex numbers stored in the first rotation memory 43 can be reduced to 1 / 4. Furthermore, based on the symmetry between the sin function and the cos function, the number of real numbers to be stored can be further reduced to 1 / 2. That is, the number of real numbers required to store the first rotation factor in the first rotation memory 43 is 2 10 ×2 / 8 (= 2 8 ).

[0057] If the first rotator 222 is realized by one complex arithmetic unit (hereinafter, this case is referred to as "comparative example"), the number of real numbers required to store the rotation factor is 2 15 (= 2 17 ·2 / 8). However, in the case of the first rotator 222 in FIG. 5, the number of real numbers to be stored in the first rotation memory 43 and the second rotation memory 44 is 2 9 (= 2 8 + 2 8 ), and is reduced to 1 / 2 6 of the original.

[0058] Note that the small FFT circuit 221 is also constructed as a single-input and single-output circuit to which the Radix-2 k algorithm (hereinafter, simply referred to as "Radix-2 k ") is applied. By doing so, the number of rotators with N / 16 rotation factors to be applied can be set to one for each small FFT circuit 221. Such rotators exist in parallel in 16 small FFT circuits 221. To reference the rotation memories storing the rotation factors set for the rotators at the same timing, the rotation memories can be shared among multiple rotators. By applying Radix-2 k , the number of rotation factors set for other rotators in each small FFT circuit 221 can be, for example, N / 64 or less depending on the hardware implementation method. For the entire small FFT circuit group 211, the number of (complex) rotation factors to be stored can be N / 8 to N / 16. As described above, the actual number of real numbers stored is 1 / 4 of the number of complex numbers. When N is 2 17 , the number of real numbers stored is 2 12 to 2 11 .

[0059] On the one hand, when dividing the first rotator 222 into the first complex multiplier 41 and the second complex multiplier 42, the number of real numbers to be stored in the rotation memory 28 is reduced from N = 2 17 to 2 15 to 2 9 even in the entire FFT circuit 2 considering the small FFT circuit group 211, the effect of reducing the storage capacity by the structure of FIG. 5 is high.

[0060] Next, considering the increase in the amount of computation, the multiplication in the first rotator 222 of the comparative example (exactly, the multiplication of a rotation matrix having real numbers as elements, the same applies hereinafter) is once, but in the first rotator 222 of FIG. 5, the multiplication is twice. In the small FFT circuit 221, when N = 2 17 N / 16 is 2 13 and assuming that the number of rotators 33 in FIG. 4 is 6, the multiplication is performed 6 times in the small FFT circuit 221. In the 90° rotator 35, only the sign is swapped, so no multiplication is performed. Also, downstream from the first rotator group 212 in FIG. 2, real number multiplication is performed only by the third rotator group 216. Therefore, when the first rotator 222 is composed of one complex multiplier, the multiplication is 8 times, but when composed of the first complex multiplier 41 and the second complex multiplier 42, it is 9 times, and the amount of computation only increases by about 1.1 times.

[0061] In this way, in the FFT circuit 2, it is possible to significantly reduce the storage capacity required to store the rotation factor while suppressing the increase in the amount of computation. Also, thereby, it becomes possible to realize the FFT circuit 2 at low cost using hardware such as a commercially available FPGA.

[0062] Next, with reference to FIG. 6, another configuration example of the FFT circuit 2 will be described. In the FFT circuit 2 of FIG. 6, in order from the input side to the output side, there are a small FFT circuit group 231, a first rotator group 232, a first butterfly arithmetic unit group 233, a second rotator group 234, and a second butterfly arithmetic unit group 235. The small FFT circuit group 231 consists of four small FFT circuits 241, each of which performs an FFT operation. Each small FFT circuit 241 is a one-input one-output type Fourier transform circuit.

[0063] The first rotator group 232 consists of three rotators 242, and it is possible to set the rotation factors selected as described later for each of them. The second rotator group 234 has one second rotator 244, but the rotation by the second rotator 244 is fixed to a 90° rotation operation. The first butterfly arithmetic unit group 233 has two first butterfly arithmetic units 243. The second butterfly arithmetic unit group 235 has two second butterfly arithmetic units 245.

[0064] Next, the operations corresponding to the configuration of the FFT circuit 2 in FIG. 6 will be described. Equation 6 represents a discrete Fourier transform of size N, and the part of the transform is shown as Equation 1. However, N is a power of 2, and in this embodiment, n is an integer of 5 or more. By the Fourier transform, a function x(t) with the variable time t to be transformed is transformed into a function x~(k) with the variable frequency k (refer to the input (Input) on the left side and the output (Output) on the right side of FIG. 6).

[0065]

Equation

[0066] Here, assuming k = (N / 4)k’ + k” and t = t’ + 4t”, when the discrete Fourier transform of size N is divided into the discrete Fourier transforms of size (N / 4) and size 4, it becomes Equation 7.

[0067]

Equation

[0068] In Equation (7), the left Σ part shown in (7 - 3) represents a 4 - way split, and the right Σ part shown in (7 - 1) represents an N / 4 - point discrete Fourier transform that Fourier - transforms a function of t” into a function of k”. The e to the power of (-2πi(k”t’ / N)) with (7 - 2) attached represents a rotation factor.

[0069] For the left - most Σ part with (7 - 3) attached, let k’ = 2k’0 + k’1 (where k’0 and k’1 are 0 or 1), and let t’ = t’0 + 2t’1 (where t’0 and t’1 are 0 or 1). Then the part of Equation (7) with (7 - 3) attached becomes Equation (8). Equation (8) shows the (main) operation part to which Radix - 2 2 is applied.

[0070]

Equation

[0071] Next, the correspondence between the FFT circuit 2 in Figure 6 and Equations (7) and (8) will be described.

[0072] The left - most input in Figure 6 is x(t), that is, x(4t” + t’). The small FFT circuit group 231 corresponds to the part shown in (7 - 1) of Equation (7). That is, each small FFT circuit 241 performs an N / 4 - point discrete fast Fourier transform, converting a function of t” into a function of k”. As specific configurations of the single - input - single - output small FFT circuit 241, various ones can be adopted.

[0073] The first rotator group 232 corresponds to (7 - 2) of Equation (7). Each W N m with m being k”t’. Each first rotator 242 has a rotation factor of W N m set for each operation.

[0074] The first butterfly arithmetic unit group 233 corresponds to the rightmost Σ part indicated by (8 - 1) of number 8. By the first butterfly arithmetic unit group 233, t’1 is converted into k’1. The second rotator group 234 corresponds to the part indicated by (8 - 2) of number 8. Here, since k’1t’0 is 0 or 1, a rotation operation of 0 (i.e., no rotation) or 2πi / 4 (= 90°) is performed at the position of the second rotator group 234. As described above, only one second rotator 244 is provided as the second rotator group 234.

[0075] The second butterfly arithmetic unit group 235 corresponds to the rightmost Σ part indicated by (8 - 3) of number 8. By the second butterfly arithmetic unit group 235, t’0 is converted into k’0.

[0076] By the above processing, when the inputs x(4t”), x(4t” + 1), x(4t” + 2), x(4t” + 3) are sequentially input in parallel, x~(k”), x~(k”+(1 / 4)N), x~(k”+(2 / 4)N), x~(k”+(3 / 4)N) (however, the output order is as shown in FIG. 6.) are sequentially output in parallel.

[0077] The configuration of FIG. 5 is also adopted for each first rotator 242 in FIG. 6. That is, the first rotator 242 includes a first complex multiplier 41 and a second complex multiplier 42, each of which is a rotator. The first complex multiplier 41 and the second complex multiplier 42 are connected in series. A first rotation memory 43 is connected to the first complex multiplier 41, and a second rotation memory 44 is connected to the second complex multiplier 42. And, N1 first rotation factors corresponding to the rotation positions obtained by equally dividing 2π into N1 parts are stored in the first rotation memory 43. However, N1 is an integer of 2 to the power of n1, where n1 is an integer of 3 or more. On the other hand, setting N2 = N / N1 (i.e., N = N1·N2), the second rotation memory 44 stores N2 second rotation factors corresponding to the rotation positions obtained by equally dividing 2π / N1 into N2 parts. However, N2 is an integer of 2 to the power of n2, where n2 is an integer of 1 or more. Note that n is n1 + n2 and is 5 or more. Any one of a plurality of first rotation factors is selectively set in the first complex multiplier 41, and any one of a plurality of second rotation factors is selectively set in the second complex multiplier 42.

[0078] By storing the rotation factors set for the first rotator 242 separately in a first rotation memory 43 that stores the first rotation factors corresponding to the rough rotation positions and a second rotation memory 44 that stores the second rotation factors corresponding to the rotation angles for interpolating between the rough rotation positions, the storage capacity required for storing the rotation factors can be significantly reduced. That is, for example, when N = 2 17 In the case of, similar to the case of FIG. 2, the number of real numbers to be stored in the first rotation memory 43 and the second rotation memory 44 is 2 6 times less than the case where the rotation factors are not stored separately for the rough rotation positions and the rotation angles for interpolation.

[0079] Note that the small FFT circuit 241 is also constructed as a single-input and single-output circuit to which Radix-2 k is applied, so that the number of rotators to which the number of rotation factors to be applied is N / 4 can be made one. Also, since such rotators exist in parallel in four small FFT circuits 221, the rotation memories for storing the rotation factors set for the rotators can be shared. When Radix-2 k is also applied in the small FFT circuit 241, the storage capacity required for storing the rotators in the small FFT circuit group 231 is reduced, so that the storage capacity required for the entire FFT circuit 2 becomes smaller. Therefore, the reduction ratio of the storage capacity for the entire FFT circuit 2 when the structure of FIG. 5 is provided becomes larger.

[0080] Furthermore, by configuring the rotator to which the number of rotation factors to be applied in the small FFT circuit 241 is N / 4 as the structure of FIG. 5, the required storage capacity can be further reduced.

[0081] Next, considering the increase in the amount of computation, in the small FFT circuit 241, when N = 2 17 in the case of, N / 4 is 2 15Assuming that the number of rotators 33 in FIG. 4 is 7, the small FFT circuit 241 performs multiplication 7 times. Note that in the 90° rotator 35, only sign swapping is performed, so no multiplication is done. Also, substantially no multiplication is performed downstream of the first rotator group 232 in FIG. 6. Therefore, when the first rotator 242 is configured with one complex multiplier, the number of multiplications is 8, but when configured with the first complex multiplier 41 and the second complex multiplier 42, it becomes 9, and the amount of computation only increases by about 1.1 times. Even if the configuration of FIG. 5 is further adopted for the rotator to which the maximum number of twiddle factors is applied within the small FFT circuit 241, the amount of computation only increases by about 1.25 times.

[0082] Thus, also in the FFT circuit 2 of FIG. 6, while suppressing an increase in the amount of computation, it is possible to significantly reduce the storage capacity required to store the twiddle factors. As a result, it becomes possible to implement the FFT circuit 2 at low cost using hardware such as a commercially available FPGA.

[0083] Next, with reference to FIG. 7, yet another configuration example of the FFT circuit 2 will be described. In the FFT circuit 2 of FIG. 7, in order from the input side to the output side, there are a small FFT circuit group 251, a first rotator group 252, a first butterfly arithmetic unit group 253, a second rotator group 254, a second butterfly arithmetic unit group 255, a third rotator group 256, a third butterfly arithmetic unit group 257, a fourth rotator group 258, and a fourth butterfly arithmetic unit group 259. The small FFT circuit group 251 consists of 16 small FFT circuits 261, each of which performs an FFT operation. Each small FFT circuit 261 is a single-input / single-output type Fourier transform circuit.

[0084] The first rotator group 252 consists of 12 first rotators 262, and it is possible to set selected rotation factors for each of them. The second rotator group 254 has 4 second rotators 264, but the rotation by the second rotator 264 is fixed to a 90° rotation operation. The third rotator group 256 consists of 12 third rotators 266, and it is possible to set selected rotation factors for each of them. The fourth rotator group 258 has 4 fourth rotators 268, but the rotation by the fourth rotator 268 is fixed to a 90° rotation operation.

[0085] The first butterfly calculator group 253 has 8 first butterfly calculators 263. The second butterfly calculator group 255 has 8 second butterfly calculators 265. The third butterfly calculator group 257 has 8 third butterfly calculators 267. The fourth butterfly calculator group 259 has 8 fourth butterfly calculators 269.

[0086] Next, the operations corresponding to the configuration of the FFT circuit 2 in FIG. 7 will be described. First, let k = (N / 16)k’ + k”, t = t’ + 16”. Further, let k’ = 8k’0 + 4k’1 + 2k’2 + k’3 (where k’0, k’1, k’2, k’3 are 0 or 1), and let t’ = t’0 + 2t’1 + 4t’2 + 8t’3 (where t’0, t’1, t’2, t’3 are 0 or 1). Divide the discrete Fourier transform of size N in Equation 6 into a discrete Fourier transform of size (N / 16) and a discrete Fourier transform of size 4 to obtain Equation 9.

[0087]

Equation

[0088] In Equation 9, the left Σ part indicated by (9 - 3) shows a four-way split, and the right Σ part indicated by (9 - 1) shows a discrete Fourier transform of N / 4 points. The exponent of e with (9 - 2) attached indicates the rotation factor.

[0089] Dividing the rightmost Σ part with (9 - 1) into a discrete Fourier transform of size (N / 16) and size 4 gives Equation 10. In Equation 10, the rightmost part with (10 - 1) represents a discrete Fourier transform of N / 16 points. The part with (10 - 2) represents a rotation factor. The parts from (10 - 3) to (10 - 5) are where Radix-2 2 indicates the (main) operation part to which it is applied.

[0090]

Number

[0091] On the other hand, (9 - 3) of Equation 9 can be transformed into Equation 11 similar to Equation 8, and Equation 11 is where Radix-2 2 indicates the (main) operation part to which it is applied.

[0092]

Number

[0093] Next, the correspondence between the FFT circuit 2 in FIG. 7 and Equations 9 to 11 will be described.

[0094] The leftmost input in FIG. 6 is x(t), that is, x(16t” + t’). The small FFT circuit group 251 corresponds to (10 - 1) of Equation 10. That is, each small FFT circuit 261 performs a discrete fast Fourier transform of N / 16 points and converts a function of t” into a function of k”. As specific configurations of the small FFT circuit 261, various ones can be adopted.

[0095] The first rotator group 252 corresponds to the part indicated by (10 - 2) of Equation 10. Each W N / 4 m has m of k”(t’2 + 2t’3). Each first rotator 262 is set with a rotation factor of W N / 4 m for each operation. Therefore, the rotation memory connected to the first rotator 262 stores information necessary to set N / 4 rotation factors corresponding to rotations of 2π / (N / 4) points in the first rotator 262.

[0096] The first butterfly arithmetic unit group 253 corresponds to the Σ part indicated by (10 - 3) of number 10. By the first butterfly arithmetic unit group 253, t'3 is converted to k'3. The second rotator group 254 corresponds to the part indicated by (10 - 4) of number 10. Here, since k'3t'2 is 0 or 1, at the position of the second rotator group 254, a rotation operation of 0 (i.e., no rotation) or 2πi / 4 (= 90°) is performed. Only 4 second rotators 264 are provided as the second rotator group 254. The second butterfly arithmetic unit group 255 corresponds to the rightmost Σ part indicated by (10 - 5) of number 10. By the second butterfly arithmetic unit group 255, t'2 is converted to k'2.

[0097] The third rotator group 256 corresponds to the part indicated by (9 - 2) of number 9. For each third rotator 266, a rotation factor of W N m is set for each operation.

[0098] The third butterfly arithmetic unit group 257 corresponds to the Σ part indicated by (11 - 1) of number 11. By the third butterfly arithmetic unit group 257, t'1 is converted to k'1. The fourth rotator group 258 corresponds to the part indicated by (11 - 2) of number 11. Here, since k'1t'0 is 0 or 1, at the position of the fourth rotator group 258, a rotation operation of 0 (i.e., no rotation) or 2πi / 4 (= 90°) is performed. Only 4 third rotators 268 are provided as the fourth rotator group 258. The fourth butterfly arithmetic unit group 259 corresponds to the rightmost Σ part indicated by (11 - 3) of number 11. By the fourth butterfly arithmetic unit group 259, t'0 is converted to k'0.

[0099] By the above processing, in the same way as in the case of FIG. 2, when the inputs x(16t”), x(16t” + 1), x(16t” + 2), ···, x(16t” + 15) are sequentially input in parallel, x~(k”), x~(k”+(1 / 16)N), x~(k”+(2 / 16)N), ···, x~(k”+(15 / 16)N) (however, the output order is as shown in FIG. 7.) are sequentially output in parallel.

[0100] In each of the third rotators 266 in FIG. 7, the configuration of FIG. 5 is also adopted. That is, the third rotator 266 includes a first complex multiplier 41 and a second complex multiplier 42, each of which is a rotator. The first complex multiplier 41 and the second complex multiplier 42 are connected in series. A first rotation memory 43 is connected to the first complex multiplier 41, and a second rotation memory 44 is connected to the second complex multiplier 42. And, the first rotation memory 43 stores N1 first rotation factors corresponding to rotation positions obtained by equally dividing 2π into N1 parts. However, N1 is an integer of 2 to the power of n1, where n1 is an integer of 3 or more. On the other hand, assuming N2 = N / N1 (that is, N = N1·N2), the second rotation memory 44 stores N2 second rotation factors corresponding to rotation positions obtained by equally dividing 2π / N1 into N2 parts. However, N2 is an integer of 2 to the power of n2, where n2 is an integer of 1 or more. Note that n is n1 + n2 and is 5 or more. Any one of a plurality of first rotation factors is selectively set in the first complex multiplier 41, and any one of a plurality of second rotation factors is selectively set in the second complex multiplier 42.

[0101] By separately storing the rotation factors set in the third rotator 266 in the first rotation memory 43 that stores the first rotation factors corresponding to the coarse rotation positions and the second rotation memory 44 that stores the second rotation factors corresponding to the rotation angles for interpolating between the coarse rotation positions, similar to the case of FIG. 2, the storage capacity required for storing the rotation factors can be significantly reduced. In particular, when Radix-2 k is applied even in the small FFT circuit 261, the storage capacity required for storing the rotators in the small FFT circuit group 251 is reduced, so that the storage capacity of the entire FFT circuit 2 becomes smaller. Therefore, the reduction ratio of the storage capacity of the entire FFT circuit 2 when the structure of FIG. 5 is provided becomes larger. Also, similar to the case of FIG. 2, the amount of computation does not increase so much even when the structure of FIG. 5 is adopted.

[0102] Note that in the case of the example of FIG. 7, the configuration of FIG. 5 may also be adopted for each of the first rotators 262. Thereby, the capacity for storing the rotation factors required for the first rotator group 252 and the third rotator group 256 can be reduced.

[0103] Thus, also in the FFT circuit 2 of FIG. 7, by adopting the rotator having the structure of FIG. 5, it is possible to significantly reduce the storage capacity required for storing the rotation factor while suppressing an increase in the amount of calculation. Further, this makes it possible to realize the FFT circuit 2 at low cost using hardware such as a commercially available FPGA.

[0104] FIG. 8 is a diagram illustrating a configuration of a communication system 5 including a Fourier transform apparatus having the FFT circuit 2 illustrated in FIGS. 2, 6, and 7. The communication system 5 of FIG. 8 includes a transmission apparatus 51 that transmits information by electromagnetic waves, and a reception apparatus 52 that receives electromagnetic waves and acquires information. The transmission apparatus 51 and the reception apparatus 52 are both wireless communication apparatuses.

[0105] The transmission apparatus 51 includes an input unit 511, an encoding unit 512, a D / A (digital - analog) converter 513, and an antenna 514. The encoding unit 512 includes an information conversion unit 611 and an inverse Fourier transform apparatus 612. The input unit 511 receives an input of information from an information source. The encoding unit 512 encodes the information and sends it to the D / A converter 513. The D / A converter 513 converts the encoded information into an analog signal. The antenna 514 is connected to the D / A converter 513. The antenna 514 converts the analog signal from the D / A converter 513 into electromagnetic waves and transmits them.

[0106] The information conversion unit 611 of the encoding unit 512 converts the information from the input unit 511 into a form suitable for inverse Fourier transform. For example, when the OFDM (orthogonal frequency - division multiplexing) communication method is adopted, the information conversion unit 611 maps the bit stream of the information on the complex plane. Then, the inverse Fourier transform apparatus 612 performs an inverse Fourier transform on the mapped digital information and sends it to the D / A converter 513. That is, the inverse Fourier transform apparatus 612 encodes the mapped information by converting it into information having time as a parameter.

[0107] Note that, as the inverse Fourier transform device 612, a circuit in which the sign of the rotation factor is inverted in the above-exemplified FFT circuit 2 is used. Therefore, in the description of the present embodiment, the inverse Fourier transform device is regarded as a kind of Fourier transform device, and in FIG. 8, it is denoted as "(inverse) Fourier transform device 612". The Fourier transform device including the FFT circuit 2 exemplified in FIGS. 2, 6, and 7 can be used as a Fourier transform device that performs an N-point fast Fourier transform, and can also be used as a Fourier transform device that performs an N-point inverse fast Fourier transform.

[0108] The receiving device 52 includes an output unit 521, a decoding unit 522, an A / D (analog-digital) converter 523, and an antenna 524. The decoding unit 522 includes an information acquisition unit 621 and a Fourier transform device 622. The antenna 524 is connected to the A / D converter 523. The antenna 524 receives an electromagnetic wave from the transmitting device 51 and guides an electrical analog signal to the A / D converter 523. The A / D converter 523 converts the analog signal into a digital signal. That is, the analog signal is sampled. The decoding unit 522 decodes the digital signal and acquires information. The output unit 521 outputs the information from the decoding unit 522 to a desired device.

[0109] The Fourier transform device 622 of the decoding unit 522 converts the digital signal output from the A / D converter 523 into information on a complex plane indicating, for example, a plurality of frequencies and their amplitudes by performing a Fourier transform. The information acquisition unit 621 converts the information from the Fourier transform device 622 into a format suitable for output. As the Fourier transform device 622, the above-exemplified FFT circuit 2 is used. Of course, the inverse Fourier transform device 612 and the Fourier transform device 622 may adopt various other configurations as long as they are provided with a structure having a first complex multiplier 41, a second complex multiplier 42, a first rotation memory 43, and a second rotation memory 44 shown in FIG. 5 to reduce the capacity required for storing the rotation factor. As a result, in the transmitting device 51 and the receiving device 52, it is possible to reduce the required storage capacity while suppressing an increase in the amount of calculation, and to reduce the manufacturing cost of the device. Also, the power consumption is reduced.

[0110] The communication system 5 can be adopted for various applications, and can be used not only for communication using electromagnetic waves propagating in the atmosphere or in vacuum, but also for communication for transmitting and receiving high-frequency signals transmitted through a coaxial cable. In the transmitting device 51 and the receiving device 52 which are communication devices, various other communication methods can be adopted.

[0111] The Fourier transform device having a rotator and a rotation memory having the configuration of FIG. 5 (hereinafter, also referred to as "the Fourier transform device according to the present invention", including an inverse Fourier transform device) is not limited to the FFT circuit 2 having the configuration described in the above embodiment, and is applicable to any Fourier transform device that performs Fourier transform or inverse Fourier transform. In the Fourier transform device, the number of combinations of the rotator and the rotation memory having the configuration of FIG. 5 may be only one, or may be two or more. With the configuration of FIG. 5, it is possible to reduce the storage capacity required for storing the rotation factor while suppressing an increase in the amount of calculation. That is, it is possible to secure the bandwidth and improve the frequency resolution while reducing the required storage capacity. As a result, the manufacturing cost of the Fourier transform device can be reduced.

[0112] In particular, in a hardware FFT circuit that performs high-speed calculation, since the arrangement and read timing of the read lines from the rotation memory are restricted, it is not possible to reduce the storage capacity by sharing the rotation memory between rotators whose calculation timings are before and after. Therefore, the reduction of the storage capacity by the configuration of FIG. 5 is effective in the hardware FFT circuit.

[0113] Also, when the Fourier transform device includes a Radix-2 k circuit that executes calculations using an algorithm, the number of rotator groups (hereinafter, referred to as "general rotator groups") that need to perform rotation calculations at rotation angles that are integer multiples of 2π / N (that is, each of 0 to (N - 1) times) can be only one. Therefore, by applying the rotator and the rotation memory of FIG. 5 to the general rotator group, a large reduction effect of the required storage capacity can be obtained. Radix-2 k circuit, the number of rotator groups (hereinafter, referred to as "general rotator groups") that need to perform rotation calculations at rotation angles that are integer multiples of 2π / N (that is, each of 0 to (N - 1) times) can be only one. Therefore, by applying the rotator and the rotation memory of FIG. 5 to the general rotator group, a large reduction effect of the required storage capacity can be obtained. Radix-2 kDepending on which part of the FFT circuit the circuit is regarded as, when the general rotator group to which the configuration of FIG. 5 is applied is regarded as a part separate from the Radix-2 k circuit (main part), the general rotator group is connected before or after the Radix-2 k circuit. When the entire FFT circuit is regarded as a Radix-2 k circuit, the general rotator group to which the configuration of FIG. 5 is applied is included in the Radix-2 k circuit.

[0114] Note that the above expression "Radix-2 k circuit (main part)" is intended to regard the circuit characterizing the Radix-2 k algorithm as a Radix-2 k circuit. In the case of FIG. 2, the parts labeled with reference numerals 213 to 219, in the case of FIG. 6, the parts labeled with reference numerals 232 to 235, in the case of FIG. 7, the parts labeled with reference numerals 253 to 255 and the parts labeled with reference numerals 257 to 259 correspond to the Radix-2 k circuit. In other words, the Radix-2 k circuit (main part) refers to the arithmetic part in which the rotation operation is fixed by the Radix-2 k algorithm. Note that when performing an operation with the Radix-2 k algorithm, N is subject to the constraint of being a power of 2 k or more.

[0115] Furthermore, in order to perform operations at high speed while using the Radix-2 k circuit, it is preferable to use a multi-path-delay-feedback type Fourier transform device exemplified in FIGS. 2, 7, and 8. Generally speaking, in the Fourier transform device, a plurality of small Fourier transform circuits (small FFT circuits) are arranged in parallel on the input side. Each small Fourier transform circuit is a circuit that performs a single-input / single-output Fourier transform or inverse Fourier transform. Also, a Radix-2 k circuit is arranged on the downstream side (output side) of the plurality of small Fourier transform circuits. And a rotator group to which the configuration of FIG. 5 is applied is arranged between the plurality of small Fourier transform circuits and the Radix-2 k circuit.

[0116] When expressing the circuit with the number of the plurality of small Fourier transform circuits being P, (P - 1) rotators are arranged between the plurality of small Fourier transform circuits and the Radix-2 k circuit. However, P is a power of 2, and p is an integer of 2 or more. p has the same value as k in the expression of "Radix-2 k ". When applying the above expression to the FFT circuit 2 in FIG. 2, 16 small Fourier transform circuits (small FFT circuits 221) are arranged in parallel, and a Radix-2 4 circuit is arranged on the downstream side of the 16 small Fourier transform circuits, and 15 rotators (first rotators 222) are arranged between the 16 small Fourier transform circuits and the Radix-2 4 circuit.

[0117] As is clear from comparing FIG. 2 and FIG. 6, the smaller the value of p, the larger the storage capacity required to store the rotation factor in the parallel small Fourier transform circuits. Therefore, it is preferable that the configuration of FIG. 5 is applied as the value of k (that is, the value of p) in the Radix-2 k circuit is larger. The value of p is preferably 4 or more, more preferably 5 or more, and even more preferably 6 or more.

[0118] Also, a Radix-2 k circuit may be adopted in the small Fourier transform circuit, or the configuration of FIG. 5 may be adopted.

[0119] Next, the reduction of the storage capacity required for storing the rotation factor will be further described. Let N be 2 n , the number of the first rotation factors be 2 n1 , and the number of the second rotation factors be 2 n2 (However, n, n1, and n2 are positive integers, and n = n1 + n2). When considering only the number of rotation factors, by dividing the rotation factors into the first rotation factors and the second rotation factors, the number is reduced from 2 n1+n2 to 2 n1 + 2 n2 .

[0120] For example, when the number of the first rotation factors is 24 (=16), and the number of second rotation factors is 2 4 (=16), if these are not separated, the number of rotation factors is 2 8 (=256), so by separating the rotation factors, the required memory capacity can be reduced by about 12 percent with simple calculations. Let N be 2 n (where n is an even number of 6 or more), and the number of first rotation factors is 2 n / 2 and the number of second rotation factors is 2 n / 2 Then, the number of rotation factors is reduced from N to 2·N 1 / 2 .

[0121] When considering the capacity required for storing rotation factors as the number of real numbers, if the number of first rotation factors is 2 n1 and the number of second rotation factors is 2 n2 then the number of real numbers is reduced from 2·2 n1+n2 to 2·(2 n1 +2 n2 ). Here, considering the symmetry of the sin function and cos function, since the number of real numbers to be stored as the original rotation factor and the first rotation factor can be reduced to 1 / 8, it is reduced from 2 n1+n2-2 (=2·2 n1+n2 / 8) to 2 n1-2 +2·2 n2 (=2·(2 n1 / 8+2 n2 )) in the example where the above N is 2 17 , with n1 = 10 and n2 = 7, the number of real numbers to be stored is reduced from 2 15 to 2 9 .

[0122] As described above, the number of real numbers actually stored as the first rotation factor may be twice the number of first rotation factors, or may not be twice considering symmetry. In the above description, "the first rotation memory 43 stores the first rotation factor" means that it stores the first rotation factor in a state where it can be quickly read out, and the first rotation memory 43 does not necessarily need to store a plurality of the first rotation factors themselves.

[0123] From the viewpoint of reducing the required memory capacity, that is, reducing the circuit scale (including memory) to be implemented, it is preferable that n2 is 3 or more, and more preferably n2 is 5 or more. It is also preferable that n1 is 3 or more, and more preferably n1 is 5 or more. Further, preferably n is 10 or more, and more preferably n is 15 or more. Although there is no need to define the upper limit of n, from a technical viewpoint, for example, it is 30 or less. The real numbers stored as rotation factors may be floating-point numbers or fixed-point numbers, and may be single-precision or double-precision.

[0124] Considering the symmetry of the sin function and the cos function, the required memory capacity can be reduced by making at least one of n1 and n2 larger than the combination of n1 = 3 and n2 = 1 (the number of first rotation factors is 8 and the number of second rotation factors is 2). That is, n1 is an integer of 3 or more, n2 is an integer of 1 or more, and n is an integer of 5 or more.

[0125] Next, the preferred performance of the Fourier transform device to which the present invention is applied will be described. In a conventional device for performing Fourier transform at high speed, for example, the bandwidth was 2 GHz and the frequency resolution was about 80 kHz. On the other hand, the inventors achieved a bandwidth of 4 GHz and a frequency resolution of 32 kHz by realizing a Fourier transform device having the FFT circuit 2 shown in FIG. 2. Specifically, the above performance was realized by operating 16 parallel small FFT circuits 221 at an operating clock of 300 MHz in the FPGA. As a result, the performance was improved by about four times compared with the conventional device while reducing the required memory capacity.

[0126] As described above, in the Fourier transform device according to the present invention, it is preferable that a digital signal obtained by digitally converting an analog signal having a bandwidth of 4 GHz or more is input, and the frequency resolution at the output is 100 kHz or less. Further preferably, the frequency resolution at the output is 50 kHz or less. When the Fourier transform device performs an inverse Fourier transform, it is preferable that the frequency resolution in the input frequency information is 100 kHz or less, and the bandwidth of the analog signal obtained by analog-converting the output digital signal is 4 GHz or more. More preferably, the frequency resolution in the input frequency information is 50 kHz or less. Further, when the Fourier transform device according to the present invention is applied to a frequency analysis device, it is preferable that the frequency analysis device analyzes a digital signal converted from a high-frequency analog signal of 300 MHz or more and 300 GHz or less.

[0127] The configuration of the rotator (the first rotator 222) (and the rotation memory 28) shown in FIG. 5 may be variously changed as long as a rotation operation of a rotation angle obtained by adding the rotation angles indicated by the first rotation factor and the second rotation factor is performed. For example, in FIG. 5, the positions of the combination of the first complex multiplier 41 and the first rotation memory 43 and the positions of the combination of the second complex multiplier 42 and the second rotation memory 44 may be interchanged. Further, as shown in FIG. 9, a complex multiplier 45 is provided to which a first rotation factor selected from a plurality of first rotation factors stored in the first rotation memory 43 and a second rotation factor selected from a plurality of second rotation factors stored in the second rotation memory 44 are input, and the complex multiplier 45 obtains a combined rotation factor corresponding to the rotation angle obtained by adding the rotation angles indicated by both rotation factors, and then, a rotation operation by the combined rotation factor may be performed by the complex multiplier 46. That is, as the rotator and the rotation memory shown in FIG. 5, various configurations can be adopted as long as a rotation operation combining a first rotation factor selected from a plurality of first rotation factors and a second rotation factor selected from a plurality of second rotation factors is performed.

[0128] In the above embodiment, the one-dimensional Fourier transform has been described. However, the first rotation factor corresponding to the rough rotation position in FIG. 5 and the second rotation factor corresponding to the precise rotation angle for interpolating the rough rotation position are applicable to the rotator and rotation memory of the two-dimensional or higher-dimensional Fourier transform (including the inverse Fourier transform).

[0129] The configurations in the above embodiment and each modification example may be appropriately combined as long as they do not conflict with each other.

Explanation of Signs

[0130] 12,612,622 Fourier transform device 28 Rotation memory 41 First complex multiplier 42 Second complex multiplier 43 First rotation memory 44 Second rotation memory 45,46 Complex multipliers 51 Transmitter 52 Receiver 211,231,251 Small FFT circuit groups 212,232,252 First rotator groups 213,233,253 First butterfly arithmetic unit groups 214,234,254 Second rotator groups 215,235,255 Second butterfly arithmetic unit groups 216,256 Third rotator groups 217,257 Third butterfly arithmetic unit groups 218,258 Third rotator groups 219,259 Third butterfly arithmetic unit groups 221,241,261 Small FFT circuits (small Fourier transform circuits) 222,242 First rotators 266 Third rotator 513 D / A (digital - analog) converter 514,525 Antennas 523 A / D (analog - digital) converter

Claims

1. A Fourier transform device that performs a fast Fourier transform or an inverse fast Fourier transform of N points (where N is a power of 2 and n is an integer of 5 or more), a rotator that performs a rotation operation, a rotation memory that stores rotation factors, comprising: wherein the rotation memory a first rotation memory that stores a plurality of first rotation factors corresponding to rotation positions obtained by dividing 2π into N1 equal parts (where N1 is an integer that is a power of 2 with n1 being an integer of 3 or more), defining N / N1 as N2 (where N2 is an integer that is a power of 2 with n2 being an integer of 1 or more), and a second rotation memory that stores a plurality of second rotation factors corresponding to rotation positions obtained by dividing 2π / N1 into N2 equal parts, including: a Fourier transform device in which the rotator performs a rotation operation combining a first rotation factor selected from the plurality of first rotation factors and a second rotation factor selected from the plurality of second rotation factors.

2. The Fourier transform device according to claim 1, Radix-2 ｋ Radix-2 that executes operations using an algorithm ｋ and includes a circuit The rotator is the Radix-2 ｋ connected to the circuit or included in the Radix-2 ｋ circuit Fourier transform device.

3. The Fourier transform device according to claim 2, each being a circuit that performs a single-input and single-output Fourier transform or inverse Fourier transform, and further comprising a plurality of small Fourier transform circuits arranged in parallel, The Radix-2 circuit is arranged on the downstream side of the plurality of small Fourier transform circuits ｋ and A plurality of rotators including the rotator are arranged between the plurality of small Fourier transform circuits and the Radix-2 ｋ circuit, and a multi-path-delay-feedback type Fourier transform device.

4. The Fourier transform device according to claim 3, wherein the number of the plurality of small Fourier transform circuits is P (where P is a power of 2 and p is an integer of 2 or more), (P-1) rotators including the rotator are arranged between the plurality of small Fourier transform circuits and the Radix-2 ｋ circuit, which is a multi-path-delay-feedback type Fourier transform device.

5. The Fourier transform device according to claim 2, each being a circuit that performs a single-input and single-output Fourier transform or inverse Fourier transform, and further comprising 16 small Fourier transform circuits arranged in parallel, On the downstream side of the plurality of small Fourier transform circuits, the Radix-2 ｋ circuit, the Radix-2 ４ circuit is arranged, Fifteen rotators including the said rotator are arranged between the said 16 small Fourier transform circuits and the Radix-2 ４ circuit, which is a multi-path-delay-feedback type Fourier transform device.

6. The Fourier transform device according to claim 1, wherein a digital signal obtained by digitally converting an analog signal with a bandwidth of 4 GHz or more is input, and the frequency resolution at the output is 100 kHz or less, or the frequency resolution in the input frequency information is 100 kHz or less, and the bandwidth of the analog signal obtained by analog-converting the output digital signal is 4 GHz or more.

7. The Fourier transform device according to claim 6, wherein the frequency resolution at the output is 50 kHz or less, or the frequency resolution in the input frequency information is 50 kHz or less.

8. In an apparatus for frequency-analyzing a digital signal converted from a high-frequency analog signal of 300 MHz or higher and 300 GHz or lower, the Fourier transform apparatus according to any one of claims 1 to 7 that performs the fast Fourier transform.

9. A wireless communication device, an analog-digital converter or digital-analog converter connected to an antenna, the Fourier transform apparatus according to any one of claims 1 to 7 that Fourier-transforms a digital signal output from the analog-digital converter or inverse Fourier-transforms digital information and sends it to the digital-analog converter, A wireless communication device comprising the same.

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