Methods, apparatuses, and computing devices for performing FFT computations

Abstract

The embodiment of the application discloses a method, device and computing equipment for performing FFT calculation, and belongs to the technical field of computers. The method comprises the following steps: dividing the FFT calculation into multiple calculation stages based on the length of a data sequence to be calculated; for at least one target calculation stage in the multiple calculation stages, determining a merging matrix corresponding to the target calculation stage based on a base corresponding to each of the multiple calculation stages, and the execution order of the target calculation stage in the multiple calculation stages, wherein the merging matrix is the product of a discrete Fourier transform (DFT) coefficient matrix in the target calculation stage and a rotation factor; and determining the product of the input sequence of the target calculation stage and the merging matrix as the output sequence of the target calculation stage when the target calculation stage is executed. According to the application, the calculation amount corresponding to the calculation stage can be reduced, and the execution efficiency of the FFT calculation can be improved.

Description

[0001] This application is a divisional application, the original application number is 202311638516.4, the original application date is November 30, 2023, and the entire contents of the original application are incorporated herein by reference. TECHNICAL FIELD

[0002] The present disclosure relates to the field of computer technology, and particularly relates to a method and device for performing FFT calculation and a computing device. BACKGROUND

[0003] Fast Fourier Transform (FFT) is a high-efficiency algorithm for implementing Discrete Fourier Transform (DFT).

[0004] In the current FFT calculation process, a large number of multiplication calculations of rotation factors are involved. In order to improve the efficiency of FFT calculation, the multiplication calculation of rotation factors can be implemented through vector multiplication or matrix multiplication in related technologies. However, since the multiplication calculation of rotation factors accounts for a large proportion in the entire FFT calculation, even if the multiplication calculation of rotation factors is implemented through vector multiplication or matrix multiplication, a large amount of calculation is still required, resulting in that the current efficiency of performing FFT calculation is still not high. SUMMARY

[0005] Embodiments of the present application provide a method, device and computing device for performing FFT calculation, which can improve the efficiency of performing FFT calculation. The corresponding technical solutions are as follows:

[0006] In a first aspect, a method for performing FFT calculation is provided, which can be executed by a processor, and the method comprises:

[0007] The processor acquires a data sequence to be executed for FFT calculation in response to an FFT calculation request. The FFT calculation is divided into a plurality of calculation stages based on the length of the data sequence. For at least one target calculation stage in the plurality of calculation stages, a merging matrix corresponding to the target calculation stage is determined based on the bases corresponding to the plurality of calculation stages respectively and the execution order of the target calculation stage in the plurality of calculation stages, wherein the merging matrix is the product of the Discrete Fourier Transform (DFT) coefficient matrix in the target calculation stage and the rotation factor. The plurality of calculation stages are sequentially executed, wherein the product of the input sequence of the target calculation stage and the merging matrix is determined as the output sequence of the target calculation stage when the target calculation stage is executed. The calculation result of performing FFT calculation on the data sequence is determined based on the output sequence of the last calculation stage in the plurality of calculation stages.

[0008] In the scheme shown in the present application, in the target calculation stage of performing the FFT calculation, the combined matrix after the DFT coefficient matrix is multiplied by the rotation factor can be obtained, and then the calculation of the target calculation stage is realized through the combined matrix. Wherein, the target calculation stage can be any calculation stage in the FFT calculation process, and the input data matrix composed of the combined matrix and the input sequence is subjected to one matrix operation, instead of DFT calculation and rotation factor calculation, thereby improving the execution efficiency of the FFT.

[0009] In an implementable manner, in the case that the extraction manner corresponding to the FFT calculation is time domain extraction, the input sequence of the first calculation stage in the plurality of calculation stages is changed to the data sequence. In the case that the extraction manner corresponding to the FFT calculation is frequency domain extraction, the input sequence of the first calculation stage is changed to the sequence after the rearrangement processing of the data sequence, wherein the rearrangement processing refers to determining the data sequence as a first multi-dimensional array with the dimensions of the plurality of calculation stages corresponding to the bases in turn, transposing the first multi-dimensional array to obtain a second multi-dimensional array, and the order of the dimensions corresponding to the second multi-dimensional array is opposite to the order of the dimensions corresponding to the first multi-dimensional array.

[0010] In the scheme shown in the present application, by changing the input sequence of the first calculation stage, the elements corresponding to the same rotation factor in the input sequence of each calculation stage in the FFT calculation can be arranged continuously, thereby avoiding the non-continuous reading of the elements in the input sequence in the FFT calculation process, and thereby improving the execution efficiency of the FFT.

[0011] In an implementable manner, based on the bases corresponding to the plurality of calculation stages respectively, and the execution order of the target calculation stage in the plurality of calculation stages, the merging matrix corresponding to the target calculation stage is determined, including: determining the rearrangement number corresponding to each block included in the target calculation stage, wherein the rearrangement number is used to indicate the arrangement order of each block in the target calculation stage in the case that the input sequence of the first calculation stage is not changed. Based on the rearrangement number of each block in the target calculation stage, the merging matrix corresponding to each block is determined.

[0012] In an implementable manner, in the case that the extraction manner of the FFT calculation is frequency domain extraction, the rearrangement number corresponding to each block included in the target calculation stage is determined, including: obtaining a third multi-dimensional array, the order of the dimensions of the third multi-dimensional array is opposite to the order of the dimensions of a fourth multi-dimensional array, the elements in the fourth multi-dimensional array are sequentially arranged from 0 and the length is the number of blocks included in the target calculation stage, and the dimensions of the fourth multi-dimensional array are the bases corresponding to the calculation stages after the target calculation stage in turn. The elements in the third multi-dimensional array are sequentially determined as the rearrangement number corresponding to each block included in the target calculation stage.

[0013] In an implementable manner, in the case that the decimation manner of the FFT calculation is time domain decimation, the determining of the rearrangement number corresponding to each block included in the target calculation stage comprises: obtaining a fifth multi-dimensional array, the order of each level dimension of the fifth multi-dimensional array being opposite to the order of each level dimension of a sixth multi-dimensional array, the elements in the sixth multi-dimensional array being sequentially arranged from 0 and having a length of the number of blocks included in the target calculation stage, and the dimensions of the sixth multi-dimensional array being the bases corresponding to the calculation stages before the target calculation stage in sequence. The elements in the fifth multi-dimensional array are sequentially determined as the rearrangement numbers corresponding to each block included in the target calculation stage.

[0014] In an implementable manner, in the case that the decimation manner of the FFT calculation is time domain decimation, the determining of the rearrangement number corresponding to each block included in the target calculation stage comprises: obtaining a first sequence matrix, the first sequence matrix being a transpose matrix of a second sequence matrix, the second sequence matrix being sequentially arranged from 0 in a row-major manner, the column number of the second sequence matrix being equal to the base of the calculation stage before the target calculation stage, and the row number of the second sequence matrix being equal to the product of the bases corresponding to the calculation stages before the calculation stage before the target calculation stage. The elements in the first sequence matrix are sequentially determined as the rearrangement numbers corresponding to each block included in the target calculation stage.

[0015] In an implementable manner, the method further comprises: for each calculation stage between the second calculation stage and the penultimate calculation stage of the plurality of calculation stages, obtaining a seventh multi-dimensional array, the order of each dimension of the seventh multi-dimensional array after the first level dimension being the same as the order of each dimension of an eighth multi-dimensional array before the last level dimension, the dimension of the first level of the seventh multi-dimensional array being equal to the dimension of the last level of the eighth multi-dimensional array, the elements in the eighth multi-dimensional array being sequentially arranged from 0 and having a length of the number of blocks included in the calculation stage, the dimension of the last level being the base corresponding to the calculation stage before the target calculation stage, and the dimensions before the last level being the bases corresponding to the calculation stages before the calculation stage before the target calculation stage in sequence. The seventh multi-dimensional array is determined as the storage order of each block in each calculation stage; and the calculation results of each block in each calculation stage are stored based on the storage order.

[0016] In an implementable manner, based on the rearrangement number of each block in the target calculation stage, the determining of the merging matrix corresponding to each block comprises: based on the rearrangement number of each block in the target calculation stage and the position information of each element in the merging matrix, the imaginary part data and the real part data of each element in the merging matrix corresponding to each block are determined, wherein the rearrangement number, the position information and the imaginary part data and the real part data of each element satisfy the following formula:

[0017] k = (Alp + Bpq) mod N;

[0018]

[0019] wherein, l is a rearrangement number, A, B are preset coefficients, N is the length of the data sequence, p, q are the row number and column number of the element in the merging matrix respectively, the real part data corresponding to the element in the pth row and qth column of the merging matrix corresponding to the lth block in the nth calculation stage, the imaginary part data corresponding to the element in the pth row and qth column of the merging matrix corresponding to the lth block in the nth calculation stage.

[0020] In the scheme shown in the present application, by substituting the rearrangement number of each block in each calculation stage into the corresponding formula, the corresponding combination matrix can be obtained. Compared with the prior art, the combination matrix is obtained by first determining the twiddle factor matrix and the DFT matrix, and then performing matrix multiplication operation of the twiddle factor matrix and the DFT matrix, the calculation amount of obtaining the combination matrix can be reduced, and the efficiency of performing FFT calculation can be improved.

[0021] In an implementable manner, the product of the input sequence of the target calculation stage and the merging matrix is determined as the output sequence of the target calculation stage, including: arranging each odd row in the merging matrix to each even row, or arranging each even row in the merging matrix to each odd row, to obtain a rearranged merging matrix. The product of the input sequence of the target calculation stage and the rearranged merging matrix is determined as the output sequence of the target calculation stage.

[0022] In the scheme shown in the present application, the odd rows and even rows of the merging matrix are rearranged first, and then the calculation is performed according to the rearranged merging matrix and the input data matrix, so that the real part data of the complex numbers in the result matrix is continuously arranged, and the imaginary part data of the complex numbers is continuously arranged, which can avoid the non-continuous reading of the real part data and the imaginary part data in the result matrix when converting the result matrix into the output sequence, and can improve the efficiency of obtaining the output sequence and further improve the efficiency of performing FFT calculation.

[0023] In an implementable manner, based on the length of the data sequence, the FFT calculation is divided into multiple calculation stages, including: based on the length of the data sequence and the priority of the multiple candidate bases, the FFT calculation is divided into multiple calculation stages, and the base corresponding to each calculation stage is determined, wherein the candidate base is less than or equal to one half of the calculation size of the matrix multiplication unit for performing the FFT calculation, and the priority of the candidate base is proportional to the numerical size of the candidate base. In this way, the size of the base corresponding to each calculation stage is set according to the calculation size of the matrix multiplication unit, which can improve the utilization rate of the matrix multiplication unit and further improve the efficiency of performing the FFT calculation.

[0024] In an implementable manner, the at least one target calculation stage is a calculation stage other than the first calculation stage and the last calculation stage among the plurality of calculation stages.

[0025] In a second aspect, an apparatus for performing FFT calculation is provided, and the apparatus comprises:

[0026] An obtaining module is configured to, in response to a fast Fourier transform (FFT) calculation request, obtain a data sequence to be subjected to FFT calculation.

[0027] A dividing module is configured to divide the FFT calculation into a plurality of calculation stages based on a length of the data sequence.

[0028] A determining module is configured to, for at least one target calculation stage among the plurality of calculation stages, determine a merging matrix corresponding to the target calculation stage based on a base corresponding to each of the plurality of calculation stages, and an execution order of the target calculation stage among the plurality of calculation stages, wherein the merging matrix is a product of a discrete Fourier transform (DFT) coefficient matrix in the target calculation stage and a rotation factor.

[0029] An executing module is configured to sequentially execute the plurality of calculation stages, wherein, when the target calculation stage is executed, a product of an input sequence of the target calculation stage and the merging matrix is determined as an output sequence of the target calculation stage.

[0030] The determining module is configured to determine a calculation result of the FFT calculation on the data sequence based on the output sequence of the last calculation stage among the plurality of calculation stages.

[0031] In an implementable manner, when an extraction manner corresponding to the FFT calculation is time domain extraction, the input sequence of the first calculation stage among the plurality of calculation stages is changed to the data sequence; when the extraction manner corresponding to the FFT calculation is frequency domain extraction, the input sequence of the first calculation stage is changed to a sequence subjected to rearrangement processing on the data sequence, wherein the rearrangement processing refers to determining the data sequence as a first multi-dimensional array with dimensions at each level being the base corresponding to the plurality of calculation stages in sequence, and performing transpose processing on the first multi-dimensional array to obtain a second multi-dimensional array, wherein the order of the dimensions at each level corresponding to the second multi-dimensional array is opposite to the order of the dimensions at each level corresponding to the first multi-dimensional array.

[0032] In an implementable manner, the determining module is configured to determine a rearrangement number corresponding to each block included in the target calculation stage, wherein the rearrangement number is used to indicate an arrangement order of each block in the target calculation stage when the input sequence of the first calculation stage is not changed; and determine a merging matrix corresponding to each block based on the rearrangement number of each block in the target calculation stage.

[0033] In an implementable manner, in the case that the decimation manner of the FFT calculation is frequency domain decimation, the determining module is configured to: obtain a third multi-dimensional array, the order of each level of dimensions of the third multi-dimensional array being opposite to the order of each level of dimensions of a fourth multi-dimensional array, the elements in the fourth multi-dimensional array being sequentially arranged from 0 and having a length of the number of blocks included in the target calculation stage, and the dimensions of the fourth multi-dimensional array being the bases corresponding to the calculation stages after the target calculation stage in sequence; and determine the elements in the third multi-dimensional array as the rearrangement numbers corresponding to each block included in the target calculation stage in sequence.

[0034] In an implementable manner, in the case that the decimation manner of the FFT calculation is time domain decimation, the determining module is configured to: obtain a fifth multi-dimensional array, the order of each level of dimensions of the fifth multi-dimensional array being opposite to the order of each level of dimensions of a sixth multi-dimensional array, the elements in the sixth multi-dimensional array being sequentially arranged from 0 and having a length of the number of blocks included in the target calculation stage, and the dimensions of the sixth multi-dimensional array being the bases corresponding to the calculation stages before the target calculation stage in sequence; and determine the elements in the fifth multi-dimensional array as the rearrangement numbers corresponding to each block included in the target calculation stage in sequence.

[0035] In an implementable manner, in the case that the decimation manner of the FFT calculation is time domain decimation, the determining module is configured to: obtain a first sequence matrix, the first sequence matrix being a transpose matrix of a second sequence matrix, the second sequence matrix being sequentially arranged from 0 in a row-major manner, the column number of the second sequence matrix being equal to the base of the calculation stage before the target calculation stage, and the row number of the second sequence matrix being equal to the product of the bases corresponding to the calculation stages before the preceding calculation stage; and determine the elements in the first sequence matrix as the rearrangement numbers corresponding to each block included in the target calculation stage in sequence.

[0036] In an implementable manner, the apparatus further includes a storage module configured to: for each calculation stage between the second calculation stage and the second-to-last calculation stage in the plurality of calculation stages, obtain a seventh multi-dimensional array, the order of each level of dimensions of the seventh multi-dimensional array after the first level of dimensions being the same as the order of each level of dimensions of an eighth multi-dimensional array before the last level of dimensions, the dimension of the first level of the seventh multi-dimensional array being equal to the dimension of the last level of the eighth multi-dimensional array, the elements in the eighth multi-dimensional array being sequentially arranged from 0 and having a length of the number of blocks included in the calculation stage, the dimension of the last level being the base corresponding to the preceding calculation stage of the calculation stage, and the dimensions before the last level being the bases corresponding to the calculation stages before the preceding calculation stage in sequence; determine the seventh multi-dimensional array as the storage order of the blocks in each calculation stage; and store the calculation results of the blocks in each calculation stage based on the storage order.

[0037] In an implementable manner, the determining module is configured to determine, based on the rearrangement number of each block in the target calculation stage and the position information of each element in the merging matrix, the imaginary part data and the real part data of each element in the merging matrix corresponding to each block, wherein the rearrangement number, the position information, the imaginary part data and the real part data of each element satisfy the following formula:

[0038] k = (Alp + Bpq) mod N;

[0039]

[0040] wherein l is the rearrangement number, A and B are preset coefficients, N is the length of the data sequence, p and q are the row number and the column number of the element in the merging matrix respectively, the real part data of the element in the pth row and the qth column of the merging matrix corresponding to the lth block in the nth calculation stage, the imaginary part data of the element in the pth row and the qth column of the merging matrix corresponding to the lth block in the nth calculation stage.

[0041] In an implementable manner, the determining module is configured to:

[0042] arranging each odd row in the merging matrix to each even row or arranging each even row in the merging matrix to each odd row to obtain a rearranged merging matrix; and determining the product of the input sequence of the target calculation stage and the rearranged merging matrix as the output sequence of the target calculation stage.

[0043] In an implementable manner, the dividing module is configured to divide the FFT calculation into a plurality of calculation stages based on the length of the data sequence and the priority of the plurality of candidate bases, and determine the base corresponding to each calculation stage, wherein the candidate base is less than or equal to one half of the calculation size of the matrix multiplication unit performing the FFT calculation, and the priority of the candidate base is proportional to the numerical size of the candidate base.

[0044] In an implementable manner, at least one target calculation stage is a calculation stage other than the first calculation stage and the last calculation stage in the plurality of calculation stages.

[0045] In a third aspect, a computing device is provided, which includes a processor and a memory; the processor is configured to execute instructions stored in the memory, so that the computing device performs the method in the first aspect.

[0046] In a fourth aspect, a computer program product including instructions is provided, when the instructions are executed by a computing device, so that the computing device performs the method in the first aspect.

[0047] In a fifth aspect, a computer-readable storage medium is provided, the computer-readable storage medium comprising computer program instructions, when the computer program instructions are executed by a computing device, the computing device performs the method according to the first aspect. BRIEF DESCRIPTION OF DRAWINGS

[0048] Figure 1 is a flowchart of implementing 18-point FFT calculation by Cooley-Tukey;

[0049] Figure 2 is a method flowchart provided by an embodiment of the application for performing FFT calculation;

[0050] Figure 3 is a butterfly network diagram for implementing 8-point FFT calculation based on frequency domain decimation and frequency domain decimation respectively in the related art;

[0051] Figure 4 is a structural schematic diagram of a computing device provided by an embodiment of the application;

[0052] Figure 5 is a method flowchart provided by an embodiment of the application for performing FFT calculation;

[0053] Figure 6 is a method flowchart provided by an embodiment of the application for performing FFT calculation;

[0054] Figure 7 is a structural schematic diagram of a device for performing FFT calculation provided by an embodiment of the application. DETAILED DESCRIPTION

[0055] In order to make the purpose, technical scheme and advantages of the present application more clear, the embodiments of the present application will be further described in detail below with reference to the drawings.

[0056] Discrete Fourier Transform (DFT) is a form of Fourier transform that presents discrete in time domain data and frequency domain data, which is used to transform discrete time domain sampling data into discrete frequency domain sampling data. In terms of data form, the input data (discrete time domain sampling data) and output data (discrete frequency domain data) of DFT are finite length complex number sequences, and the lengths of the two complex number sequences are equal.

[0057] Fast Fourier Transform (FFT): an algorithm for fast computing Discrete Fourier Transform (DFT) or its inverse transform (IDFT), which can reduce the original O(N 2The computational complexity of the calculation of the DFT of a complex sequence of length N is reduced to O(NlogN).

[0058] The Cooley-Tukey algorithm is a commonly used FFT algorithm. The algorithm is based on a divide-and-conquer strategy, which can divide the DFT of a complex sequence of length N into N1 DFTs of length N2 and complex multiplications with twiddle factors, where N=N1*N2.

[0059] Figure 1 is a flow chart for implementing 18-point FFT calculation by Cooley-Tukey, which can be called a butterfly network. As shown in Figure 1 The calculation process of the FFT calculation can be divided into multiple calculation stages. The number of calculation stages is equal to the number of bases into which the length of the data sequence for which the FFT calculation is performed is divided. The data sequence is a complex sequence. For an FFT calculation of a data sequence of length N, it can be called N-point FFT calculation. For example, for N-point FFT calculation, N can be divided into N1, N2, …, Ni (N=N1*N2*…*Ni), and the calculation process of the N-point FFT can include i calculation stages. N1, N2, …, Ni can be called a base. N1 is the base corresponding to the first calculation stage, N2 is the base corresponding to the second calculation stage, and Ni is the base corresponding to the i-th calculation stage.

[0060] In the FFT calculation, the input sequence of the first calculation stage can be obtained from the corresponding data sequence of the FFT calculation. For other calculation stages after the first calculation stage, the input sequence of each calculation stage is obtained from the output sequence of the previous calculation stage, and the length of the input sequence of each calculation stage is the same. One calculation stage can be divided into at least one section, and one section can be divided into at least one butterfly. The output sequence of the calculation stage can be obtained by performing butterfly calculation on each butterfly in the calculation stage. In one calculation stage, there are N / Ni butterflies, where N is the length of the input data of the calculation stage, and Ni is the base corresponding to the calculation stage. The butterfly calculation can be divided into a twiddle factor calculation and a DFT calculation. In one example, the twiddle factor calculation can be a complex vector multiplication calculation of the input data of the butterfly and a twiddle factor, and the DFT calculation can be a complex matrix multiplication calculation of the input data after rotation (the input data after the complex multiplication calculation of the twiddle factor) and the DFT coefficient matrix corresponding to the butterfly. The DFT coefficient matrix corresponding to the butterfly is related to the structure of the butterfly, and the DFT coefficient matrix corresponding to each butterfly in each calculation stage is the same. Alternatively, in another example, the DFT calculation can be a complex matrix multiplication calculation of the input data of the butterfly and a DFT coefficient matrix, and the twiddle factor calculation can be a complex vector multiplication calculation of the twiddle factor and the calculation result corresponding to the complex matrix multiplication calculation. The DFT coefficient matrix corresponding to the butterfly is related to the structure of the butterfly, and the DFT coefficient matrix corresponding to each butterfly in each calculation stage is the same. There can be multiple butterflies corresponding to the same twiddle factor in each calculation stage.

[0061] Each calculation stage in the FFT calculation includes a large number of twiddle factor calculations and DFT calculations. Although the twiddle factor calculation can be implemented by vector operation or matrix operation to improve the execution efficiency of the FFT calculation, the optimization effect of the execution efficiency of the FFT calculation is still not ideal.

[0062] Embodiments of the present application provide a calculation method for performing FFT. The method can determine the product of the twiddle factor and the corresponding DFT coefficient matrix in each calculation stage in the FFT calculation before performing the FFT calculation. The product can be referred to as a combined matrix in embodiments of the present application. In this way, in the process of performing the FFT calculation, only the input sequence and the corresponding combined matrix need to be multiplied in each calculation stage to obtain the output sequence of each calculation stage. In this way, the multiplication calculation of the twiddle factor in the process of performing the FFT calculation is avoided, and the execution efficiency of the FFT calculation can be improved.

[0063] Figure 2is a schematic diagram of a method for performing FFT calculation provided by an embodiment of the present application. As shown in Figure 2 The original one calculation stage can include matrix multiplication operation of the DFT matrix and the input data matrix composed of the input data of each butterfly unit in the calculation stage, and vector multiplication operation of the result corresponding to the matrix multiplication and the rotation factor of each butterfly unit. Wherein, if the rotation factors corresponding to multiple butterfly units are the same, the rotation factors corresponding to multiple butterfly units can be converted into a diagonal matrix (which can be referred to as a rotation factor matrix), and the result corresponding to the matrix multiplication is subjected to matrix operation. Then, by using the combination rate of the matrix multiplication, the calculation in the calculation stage can include matrix multiplication operation of the rotation factor matrix and the DFT matrix, and then matrix multiplication operation of the input data matrix. Since the DFT matrix and the rotation factor matrix are fixed in each calculation stage, the result of the matrix multiplication operation of the DFT matrix and the rotation factor matrix is fixed, i.e. the combination matrix corresponding to each calculation stage is fixed. Therefore, in the process of performing FFT, the calculation corresponding to each calculation stage can be performed by obtaining the combination matrix of each calculation stage, the rotation factor calculation in the calculation stage can be avoided, and thus the calculation amount corresponding to each calculation stage is reduced, and the efficiency of performing FFT calculation is improved.

[0064] In order to facilitate the understanding of the embodiments of the present application, some terms related to the embodiments of the present application are introduced as follows:

[0065] Multi-dimensional array: an array including at least two dimensions. In an example, two-dimensional data is a matrix, the number of rows in the matrix is the first dimension of the two-dimensional data, also referred to as the first level dimension, and the number of columns in the matrix is the second dimension of the two-dimensional data, also referred to as the second level dimension. Correspondingly, a three-dimensional array includes three levels of dimensions, and an n-dimensional array includes n levels of dimensions.

[0066] Frequency domain decimation and time domain decimation: two methods for implementing FFT calculation. As shown in Figure 3 Figure 3 is a butterfly network diagram for implementing 8-point FFT calculation based on frequency domain decimation and time domain decimation respectively in the related art.

[0067] Figure 4 is a structural schematic diagram of a computing device provided by an embodiment of the present application. As shown in Figure 4 ​As shown, the computing device 400 can include a bus 402, a processor 404, a memory 406, and optionally a communication interface 408. The processor 404, the memory 406, and the communication interface 408 communicate via the bus 402. The computing device 400 can be a server or a terminal device. It should be understood that the number of processors and memories in the computing device 400 is not limited. The computing device 400 can be a device running a model, which can be a terminal or a server. When the computing device 400 is a terminal, the computing device 400 includes, but is not limited to, a desktop computer, a mobile phone, a notebook computer, a tablet computer, and the like. When the computing device 400 is a server, the computing device 400 can be a single server or a server cluster composed of multiple servers, and can be a physical machine or a virtual machine, a container, and the like virtualized by a virtual technology.

[0068] The bus 402 can be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus, etc. The bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 4 Although only one line is used in the figure, it does not mean that there is only one bus or only one type of bus. The bus 402 can include a path for transmitting information between various components (e.g., the memory 406, the processor 404, the communication interface 408) of the computing device 400.

[0069] The processor 404 can include any one or more of a central processing unit (CPU), a graphics processing unit (GPU), a microprocessor (MP), or a digital signal processor (DSP), etc. The processor 404 can further include a matrix multiplication unit, which can be used to perform matrix multiplication operations involved in the FFT calculation process.

[0070] The memory 406 can include volatile memory, such as random access memory (RAM), and non-volatile memory, such as read-only memory (ROM), flash memory, a hard disk drive (HDD), or a solid-state drive (SSD). The memory 406 can store program code that, when executed by the processor 404, implements the method of performing FFT computation provided by embodiments of the present application. For example, in response to a fast Fourier transform (FFT) computation request, a data sequence to be executed for FFT computation is obtained. Based on the length of the data sequence, the FFT computation is divided into multiple computation stages. The multiple computation stages are sequentially executed, wherein, when a target computation stage is executed, a product of an input sequence of the target computation stage and a merging matrix is determined as an output sequence of the target computation stage. Based on the output sequence of the last computation stage in the multiple computation stages, a computation result of performing the FFT computation on the data sequence is determined, and the like.

[0071] The communication interface 408 uses a transceiving module such as, but not limited to, a network interface card, a transceiver, and the like to enable communication between the computing device 400 and other devices or communication networks.

[0072] Figure 5 is a flowchart of a method of performing FFT computation provided by embodiments of the present application. The method can be executed by the computing device 400 shown in FIG. 4, and further can be executed by the processor 404 in the computing device 400, as shown in FIG. 4. The method includes the following steps. Figure 4 Figure 5

[0073] In step 501, in response to a fast Fourier transform (FFT) computation request, a data sequence to be executed for FFT computation is obtained.

[0074] ​​In implementation, an application program in which FFT calculation is performed can run in the computing device, for example, the application program can be a High Performance Computing (HPC) application program, an Artificial Intelligence (AI) application program, etc. During running of the application program, when FFT calculation is needed, the application program can send an execution request of FFT to the processor. For example, the application program can be a VASP (Vienna Ab-initio Simulation Package), when wave function needs to be solved in the VASP, a wave function solving request can be sent to the processor, the wave function solving request being the execution request of FFT. The wave function is a common function in the field of quantum mechanics, and the solution of the wave function can be obtained by performing FFT calculation on input data of the wave function.

[0075] After receiving the execution request of FFT calculation, the processor can obtain a data sequence to be subjected to FFT calculation, and perform subsequent steps 502 to 505. The data sequence to be subjected to FFT calculation can be carried in the execution request of FFT calculation.

[0076] In an example, for the method of performing FFT provided in the present application, a corresponding processing program can be written as an FFT processing function and added to a mathematical library, wherein the mathematical library can be stored in a computing device in which an application program is executed, and a large number of processing functions can be included in the mathematical library, which can be used to implement various mathematical calculations involved in the application program. When FFT calculation needs to be performed in the application program, an execution request of FFT can be sent to the processor, and then the processor can call the FFT processing function to implement the following steps.

[0077] Step 502: dividing the FFT calculation into multiple calculation stages based on the length of the data sequence.

[0078] In an example, after receiving the execution request of FFT calculation, the processor can obtain the length of the input data to be subjected to FFT calculation, and divide the FFT calculation into multiple calculation stages. For example, the processor can decompose the length of the input data according to the Cooley-Tukey algorithm to obtain each calculation stage of performing FFT calculation on the input data and the base corresponding to each calculation stage. For example, when the number of data elements in the input data is 8, 8 can be decomposed into 2*2*2, and the process of performing FFT on the input data includes three calculation stages, and the base corresponding to each calculation stage is 2. For example, when the number of data elements in the input data is 27, 27 can be decomposed into 3*3*3, and the process of performing FFT on the input data includes three calculation stages, and the base corresponding to each calculation stage is 3.

[0079] Step 503, for at least one target computing stage in the plurality of computing stages, determining a combination matrix corresponding to the target computing stage based on the plurality of computing stages respectively corresponding bases and execution orders of the target computing stage in the plurality of computing stages, wherein the combination matrix is a product of a discrete Fourier transform (DFT) coefficient matrix in the target computing stage and a rotation factor.

[0080] In the FFT calculation, after the number of computing stages and the base of each computing stage are determined, the DFT sparse matrix corresponding to each computing stage and the rotation factor corresponding to the element at each position in the input sequence of each computing stage are also determined. That is, in the FFT calculation, after the number of computing stages and the base of each computing stage are determined, the combination matrix corresponding to each computing stage can also be determined.

[0081] The target computing stage refers to a computing stage in which DFT matrix calculation and rotation factor calculation are realized through the combination matrix in the FFT calculation process. The target computing stage can be any computing stage in the plurality of computing stages included in the FFT calculation, for example, can be each computing stage in the plurality of computing stages. In an example, the number of computing stages, the execution order of the computing stage in the plurality of computing stages, the base corresponding to the computing stage, and the corresponding relationship with the combination matrix can be pre-stored in the computing device. Before performing the FFT calculation, the combination matrix corresponding to the target computing stage can be determined according to the corresponding relationship.

[0082] Step 504, sequentially performing the plurality of computing stages, wherein when the target computing stage is executed, the product of the input sequence of the target computing stage and the combination matrix is determined as the output sequence of the target computing stage.

[0083] After the combination matrix corresponding to the target computing stage is determined, the plurality of computing stages in the FFT calculation can be sequentially executed. When the target computing stage is executed each time, the input sequence of the target computing stage can be converted into an input data matrix, and then the multiplication operation of the input data matrix and the combination matrix is performed through the matrix multiplication unit included in the processor.

[0084] Step 505, determining a calculation result of performing the FFT calculation on the data sequence based on the output sequence of the last computing stage in the plurality of computing stages.

[0085] After each computing stage in the FFT calculation is executed in turn, the output sequence of the last computing stage can be determined as the calculation result of performing the FFT calculation, and the result is returned to the application program requesting the FFT calculation.

[0086] In the embodiment of the present application, the matrix multiplication operation is only needed to be performed once, and the twiddle factor calculation and the DFT calculation included in the target calculation stage can be completed, so that the execution efficiency of the target calculation stage can be improved, and the efficiency of performing the FFT calculation can be improved.

[0087] The FFT calculation can be divided into calculation based on a time domain decimation manner and calculation based on a frequency domain decimation manner. The execution manner of the FFT calculation is combined to further introduce the method for performing the FFT calculation provided in the embodiment of the present application.

[0088] Scheme one: performing the FFT calculation based on the frequency domain decimation manner

[0089] Step R1: obtaining a data sequence to be calculated by the FFT.

[0090] Step R2: dividing the FFT calculation into multiple calculation stages based on the length of the data sequence.

[0091] In the implementation, the FFT calculation can be divided into multiple calculation stages in combination with the length of the data sequence and the calculation size of the matrix multiplication unit in the processor for performing the matrix multiplication operation.

[0092] In each calculation stage, the size of the combination matrix is equal to the size of the DFT coefficient matrix, and the size of the DFT coefficient matrix is related to the base corresponding to the calculation stage. For example, when the base corresponding to the calculation stage is 8, the size of the DFT coefficient matrix and the combination matrix is 8*8. In actual calculation, the real part data and the imaginary part data in the combination matrix are split into 2*2 matrices, so the size of the combination matrix in actual calculation is 16*16. That is, when the base of a calculation stage is n, the size of the combination matrix corresponding to the calculation stage in actual calculation is 2n*2n.

[0093] The calculation size of the matrix multiplication unit can be used to indicate the maximum matrix size supported by the matrix multiplication unit in performing a matrix multiplication operation once. For example, if the maximum matrix size supported by the matrix multiplication unit in performing a matrix multiplication operation once is M*M, the calculation size of the matrix multiplication unit can be M. In performing a matrix multiplication operation once, the closer the size of the matrix multiplication operation matrix to the maximum matrix size corresponding to the matrix multiplication unit, the higher the utilization rate of the matrix multiplication unit. Therefore, when determining the base corresponding to each calculation stage, the base corresponding to each calculation stage can be made as close to half of the calculation size of the matrix multiplication unit as possible, so as to improve the utilization rate of the matrix multiplication unit. For example, when the calculation size of the matrix multiplication unit is 16 and the base corresponding to the calculation stage is 8, the size of the combination matrix corresponding to the calculation stage is 16*16, and therefore, when the matrix multiplication unit performs the operation of the calculation stage, the combination matrix can fully occupy the matrix multiplication unit, so as to fully utilize the performance of the matrix multiplication unit.

[0094] In an example, a plurality of candidate bases can be set in advance, and a corresponding priority can be set for each candidate base. The plurality of candidate bases is less than or equal to half of the calculation size of the matrix multiplication unit performing the FFT calculation, and the priority of the candidate base is proportional to the numerical size of the candidate base.

[0095] When the FFT calculation is divided into a plurality of calculation stages, the FFT calculation can be divided into a plurality of calculation stages according to the plurality of candidate bases set, and the base of each calculation stage can be determined. For example, the calculation size of the matrix multiplication unit is 16, and the plurality of candidate bases can be 8, 7, 6, 5, 4, 3, and 2 respectively, and the priorities of the plurality of candidate bases decrease in turn.

[0096] Figure 6 is a method flowchart provided by an embodiment of the present application for performing data sequence. As shown in Figure 6 the method comprises:

[0097] Step R21, according to the priority of the plurality of candidate bases, setting the order list corresponding to the candidate set, n=[8, 7, 6, 5, 4, 3, 2], initializing k=0, and initializing the decomposition list of the base of each calculation stage as empty, i.e. base=[].

[0098] Step R22, dividing the length N of the data sequence performing the FFT calculation by n[k].

[0099] Step R23, determining whether N can be divided by n[k].

[0100] If it can be divided, step R24 is performed, and if it cannot be divided, step R25 is performed.

[0101] Step R24, add n[k] to the decomposition list base, update N = N / n[k], and go to perform step R22.

[0102] Step R25, determine whether n[k] is the last element in the order list n.

[0103] If not, perform step R26, and if so, perform step R27.

[0104] Step R26, let k = k + 1, and go to perform step R22.

[0105] Step R27, add N to the decomposition list base.

[0106] After the performance of step R27 is completed, the number of elements included in the decomposition list base is the number of calculation stages in the FFT calculation, and the elements included in the decomposition list base are the bases corresponding to each calculation stage in order.

[0107] In this way, by means of the method for decomposing a data sequence shown in FIG. 7, the base of each calculation stage in the FFT calculation can be made as close as possible to half of the calculation size of the matrix multiplication unit, and thus the utilization rate of the matrix multiplication unit can be improved, and the efficiency of performing the FFT calculation can be improved. Figure 6

[0108] Step R3, perform rearrangement processing on the data sequence for the FFT calculation, and determine the data sequence after the rearrangement processing as the input sequence of the first calculation stage in the FFT calculation.

[0109] In the process of implementing the FFT calculation in the conventional manner based on frequency domain extraction, the input sequence of the first calculation stage in the FFT calculation is the data sequence for performing the FFT calculation, and after the calculation of the last calculation stage is completed, rearrangement processing needs to be performed on the output sequence of the last calculation stage to obtain the result sequence of the FFT calculation. However, in the process of implementing the FFT calculation in the conventional manner based on frequency domain extraction, the elements corresponding to the same twiddle factor are not continuously arranged in the input sequence of the calculation stage, and thus in the process of loading the input sequence in the form of an input data matrix to a vector register or a matrix register, non-continuous reading of the input sequence is required.

[0110] In order to avoid the occurrence of the problem of non-continuous reading, in the embodiments of the present application, the arrangement order of the elements in the input sequence of the first calculation stage is modified relative to the process of implementing the FFT calculation in the conventional manner based on frequency domain extraction, so that the elements corresponding to the same twiddle factor of the output sequence of each calculation stage can be continuously arranged in the input sequence when serving as the input sequence of the next calculation stage.

[0111] ​The rearranging the elements in the input sequence of the first calculation stage can include: determining the data sequence as a first multi-dimensional array with dimensions in sequence corresponding to bases of the plurality of calculation stages, transposing the first multi-dimensional array to obtain a second multi-dimensional array, and the order of the dimensions corresponding to the second multi-dimensional array being opposite to the order of the dimensions corresponding to the first multi-dimensional array.

[0112] For example, in the FFT calculation, m calculation stages are included, and the bases corresponding to the m calculation stages are N1, N2, … Nm, respectively. In implementation, the data sequence of the FFT calculation can be converted into a first multi-dimensional array with dimensions in sequence corresponding to N1, N2, … Nm. Then, the first multi-dimensional array is transposed into a second multi-dimensional array with dimensions in sequence corresponding to Nm, Nm-1, … N1. The order of the elements in the second multi-dimensional array is the order of the elements in the input sequence of the first calculation stage after rearrangement. The input sequence of the first calculation stage after rearrangement is actually the input sequence of the first calculation stage in the process of implementing the FFT calculation based on the conventional time domain decimation.

[0113] Taking an 8-point FFT calculation including three calculation stages as an example, for the input sequence N = [0, 1, 2, 3, 4, 5, 6, 7] of the first calculation stage before rearrangement, the input sequence N = [0, 4, 2, 6, 1, 5, 3, 7] of the first calculation stage after rearrangement. As shown in FIG. 2, the elements corresponding to the rotation factor W2 / 8 of the second calculation stage before rearrangement are respectively located at the 4th position and the 8th position of the input sequence. The elements corresponding to the rotation factor W2 / 8 of the second calculation stage after rearrangement are respectively located at the 7th position and the 8th position of the input sequence. Figure 3

[0114] It can be seen that, in the embodiments of the present application, after the rearrangement of the input sequence of the first calculation stage, the elements corresponding to the same rotation factor in the input sequence of each calculation stage are arranged continuously. In the embodiments of the present application, the elements corresponding to the same rotation factor in the input sequence can be read as each row of the input data matrix and stored in the vector register or the matrix register, which can avoid the non-continuous reading of the input sequence, and thus the efficiency of performing the FFT calculation can be improved.

[0115] Step R4, determining a combination matrix corresponding to a target calculation stage in the plurality of calculation stages.

[0116] ​The elements in the DFT coefficient matrix in the calculation stage and the rotation factor can be calculated by a trigonometric function with a period of N, where N is the length of the data sequence for which the FFT calculation is performed. Therefore, for each element in the combination matrix, it can also be calculated by a trigonometric function with a period of N. Therefore, the application exemplarily provides a method for determining the combination matrix based on a trigonometric function with a period of N, as follows:

[0117] Step R41, determining a rearrangement number corresponding to each block included in the target calculation stage, where the rearrangement number is used to indicate the arrangement order of each block in the target calculation stage without changing the input sequence of the first calculation stage.

[0118] Since the input sequence of the first calculation stage is rearranged in the above step R2, the order of the blocks in each calculation stage is different from the order of the blocks in each calculation stage in the conventional FFT calculation. Therefore, in the embodiment of the application, the arrangement order of each block in the target calculation stage without changing the input sequence can be determined first, and then the combination matrix in the target calculation stage is determined according to the rearrangement number.

[0119] In the case where the decimation mode of the FFT calculation is frequency domain decimation, determining a rearrangement number corresponding to each block included in the target calculation stage includes: obtaining a third multi-dimensional array, the order of the dimensions of the third multi-dimensional array is opposite to the order of the dimensions of a fourth multi-dimensional array, the elements in the fourth multi-dimensional array are sequentially arranged from 0 and the length is the number of blocks included in the target calculation stage, and the dimensions of the fourth multi-dimensional array are the bases corresponding to the calculation stages after the target calculation stage in turn. The elements in the third multi-dimensional array are sequentially determined as the rearrangement numbers corresponding to each block included in the target calculation stage.

[0120] In implementation, the rearrangement number corresponding to each block included in the target calculation stage can be indicated by a third multi-dimensional array Q3. The third multi-dimensional array Q3 can be obtained by transposing a fourth multi-dimensional array Q4. In an example, the FFT calculation includes m calculation stages, the target calculation stage is the nth calculation stage, and includes r blocks. The fourth multi-dimensional array Q4 = [0, 1, 2, … r], and the corresponding dimensions are N n+1 , N n+2 , … N m in turn. Correspondingly, the third multi-dimensional array Q3 is obtained by transposing the fourth multi-dimensional array Q4, and the corresponding dimensions are N m , … N n+1 , N n+1 in turn. The value of the first element in the third multi-dimensional array Q3 is the rearrangement number corresponding to the first block in the current target calculation stage.

[0121] Step R42: Based on the rearrangement number of each block in the target calculation stage, determine the merge matrix corresponding to each block.

[0122] After determining the rearrangement number corresponding to each block, the rearrangement number of each block can be substituted into the following formula to obtain the imaginary part and real part of each element in the merge matrix.

[0123] k = (Alp + Bpq) mod N;

[0124]

[0125] Where l is the rearrangement number, N is the length of the data sequence, and p and q are the row and column numbers of the elements in the merge matrix, respectively. The real part data corresponding to the element in the p-th row and q-th column of the merge matrix corresponding to the l-th block in the nth computation stage. The imaginary part data corresponding to the element in the q-th row and p-th column of the merge matrix corresponding to the l-th block in the n-th computation stage. A and B are preset coefficients, where A is equal to the product of the bases corresponding to the computation stages before the target computation stage, and B is equal to the ratio of the data sequence length N to the base corresponding to the target computation stage.

[0126] After obtaining the real and imaginary parts of each element in the merge matrix corresponding to the target computation stage, the merge matrix can be calculated using the real and imaginary parts of each element in the target computation stage. It should be noted that the number of merge matrices in the target computation stage is the same as the number of blocks. A merge matrix can be represented by multiple butterfly units corresponding to the same twiddle factor, and the input data matrix multiplied by this merge matrix is ​​composed of the input data from these multiple butterfly units.

[0127] Step R5: Perform multiple calculation stages sequentially to obtain the FFT calculation results.

[0128] After obtaining the assemblage matrix corresponding to each block in the target computation stage, each computation stage of the FFT computation can be executed sequentially. When reaching the target computation stage, the input data of the target computation stage can be used to form an input data matrix that is multiplied by the assemblage matrix corresponding to each block. The multiplication operation between the assemblage matrix and the input data matrix is ​​then performed using matrix multiplication units, thereby realizing the computation of the target computation stage. For example, in the target computation stage, the assemblage matrix corresponding to the l-th block is... When performing calculations, this can be... The input data matrix is composed of input data of each butterfly unit in the first block, and a multiplication operation is performed to obtain the calculation result corresponding to the first block. Thus, when the target calculation stage is executed in the embodiment of the application, the multiplication operation of the combination matrix and the input data matrix can be performed to realize the calculation of the target calculation stage, thereby improving the execution efficiency of the target calculation stage and further improving the execution efficiency of the FFT calculation.

[0129] In an implementable manner, since the same rotation factor does not exist in the first calculation stage and the rotation factor of the last calculation stage is 1, the target calculation stage can be the calculation stages between the first calculation stage and the last calculation stage. The calculation of the first calculation stage and the last calculation stage can adopt a conventional calculation manner, which will not be described in detail in the application. In addition, the application also provides a method for determining the rotation factor matrix corresponding to the first calculation stage based on the trigonometric function with a period of N, and a method for the DFT system matrix in the first and last calculation stages, as follows:

[0130] For the rotation factor matrix of the first calculation stage, the rearrangement number corresponding to each block in the first calculation stage can be obtained. The rearrangement number corresponding to each block in the first calculation stage can be obtained in the manner described in the above step R41, which will not be described here. After obtaining the rearrangement number corresponding to each block in the first calculation stage, the real part data and the imaginary part data corresponding to each element in the rotation factor matrix can be determined by the following calculation formula.

[0131] k = Ij mod N;

[0132]

[0133] Wherein, I is the rearrangement number, N is the length of the data sequence, i and j are the row number and column number of the element in the rotation factor matrix R1, R1_r[i,j] is the real part data corresponding to the element in the first row and the jth column of the rotation factor matrix R1, R1_i[i,j] is the imaginary part data corresponding to the element in the first row and the jth column of the rotation factor matrix R1. i∈[0,N2N3…N m ), j∈[0,N1), N1 is the base corresponding to the first calculation stage, N2N3…N m N1N2N3…N is the product of the bases corresponding to each calculation stage after the first calculation stage.

[0134] For the DFT coefficient matrix of the first calculation stage, another i,j∈[0,N1), k = Nij / N1mod N is calculated, and the real part and the imaginary part are obtained. Where W1_r[i,j] is the real part of the element in the i-th row and j-th column of the DFT coefficient matrix W1 in the first calculation stage, and W1_i[i,j] is the imaginary part of the element in the i-th row and j-th column of the DFT coefficient matrix W1 in the first calculation stage.

[0135] For the DFT coefficient matrix of the last computation stage, let i,j∈[0,N] m ), calculate k = Nij / N m mod N, we get the real part and the imaginary part W. m _r[i,j]=C[k],W m _i[i,j]=S[k]. Where, W m _r[i,j] is the DFT coefficient matrix W of the last computation stage. m The real data corresponding to the element in the i-th row and j-th column, W m _r[i,j] is the DFT coefficient matrix W of the last computation stage. m The imaginary part of the element in the i-th row and j-th column.

[0136] Option 2: Performing FFT computation based on temporal decimation

[0137] Step S1: Obtain the data sequence to be calculated using FFT.

[0138] Step S2: Based on the length of the data sequence, the FFT calculation is divided into multiple calculation stages.

[0139] The processing of steps S1 and S2 is the same as that of steps R1 and R2 described above, and will not be repeated here.

[0140] Step S3: Determine the data sequence for FFT calculation as the input sequence for the first calculation stage in FFT calculation.

[0141] In the traditional FFT computation based on time-domain decimation, the input sequence for the first computation stage needs to be rearranged from the data sequence to be computed. The result after rearrangement is the same as the result after rearrangement in step R3. However, in the traditional time-domain decimation-based FFT computation, elements with the same twiddle factor are not consecutively arranged in the input sequence of the computation stage. Therefore, when loading the input sequence into the vector register or matrix register as an input data matrix, the input sequence needs to be read non-contiguously.

[0142] In order to avoid the non-continuous reading problem, the embodiment of the present application changes the data sequence of the FFT calculation as the input sequence of the first calculation stage, and does not rearrange the data sequence of the FFT calculation, compared with the traditional time domain extraction based method. In this way, the output sequence corresponding to each calculation stage can be continuously arranged in the input sequence of the next calculation stage when it is used as the input sequence of the next calculation stage.

[0143] Taking an 8-point FFT calculation and 8-point FFT calculation including three calculation stages as an example, the input sequence N of the first calculation stage before rearrangement is [0, 1, 2, 3, 4, 5, 6, 7], and the input sequence N of the first calculation stage after rearrangement is [0, 4, 2, 6, 1, 5, 3, 7]. As shown in FIG. 2, the elements corresponding to the rotation factor W2 / 8 of the second calculation stage before rearrangement are respectively located at the 4th position and the 8th position of the input sequence, and the elements corresponding to the rotation factor W2 / 8 of the second calculation stage after rearrangement are respectively located at the 7th position and the 8th position of the input sequence. Figure 3

[0144] It can be seen that in the embodiment of the present application, the elements corresponding to the same rotation factor are continuously arranged in the input sequence of each calculation stage after the input sequence of the first calculation stage is changed. Furthermore, in the embodiment of the present application, the elements corresponding to the same rotation factor in the input sequence can be read as each row of the input data matrix stored in the vector register or the matrix register, which can avoid the non-continuous reading of the input sequence, and further improve the efficiency of the FFT calculation.

[0145] Step S4, determining the combination matrix corresponding to the target calculation stage in the plurality of calculation stages.

[0146] The same as step R4, in scheme two, the embodiment of the present application also provides a method for determining the combination matrix based on the trigonometric function with a period of N, comprising:

[0147] Step S41, determining the rearrangement number corresponding to each block included in the target calculation stage, wherein the rearrangement number is used to indicate the arrangement order of each block in the target calculation stage without changing the input sequence of the first calculation stage.

[0148] Since the input sequence of the first calculation stage is rearranged in the above step S2, the order of the blocks in each calculation stage is different from the order of the blocks in each calculation stage in the traditional FFT calculation. Therefore, in the embodiment of the present application, the arrangement order of each block in the target calculation stage without changing the input sequence can be determined first, and then the combination matrix in the target calculation stage is determined according to the rearrangement number. ​

[0149] In the case that the decimation manner of the FFT calculation is time domain decimation, determining the rearrangement number corresponding to each block included in the target calculation stage comprises: obtaining a fifth multi-dimensional array, the order of each level dimension of the fifth multi-dimensional array being opposite to the order of each level dimension of a sixth multi-dimensional array, the elements in the sixth multi-dimensional array being sequentially arranged from 0 and the length of the sixth multi-dimensional array being the number of blocks included in the target calculation stage, the dimensions of the sixth multi-dimensional array being the bases corresponding to the calculation stages before the target calculation stage in turn. The elements in the fifth multi-dimensional array are sequentially determined as the rearrangement numbers corresponding to each block included in the target calculation stage.

[0150] In implementation, the rearrangement number corresponding to each block included in the target calculation stage can be indicated by the fifth multi-dimensional array Q5. The fifth multi-dimensional array Q5 can be obtained by transposing the sixth multi-dimensional array Q6. In an example, the FFT calculation includes m calculation stages, the target calculation stage is the nth calculation stage, and includes r blocks, then the sixth multi-dimensional array Q6 = [0, 1, 2, … r], and the corresponding dimensions of each level are N1, N2, … Nm in turn. Correspondingly, the fifth multi-dimensional array Q5 is obtained by transposing the sixth multi-dimensional array Q6, and the corresponding dimensions of each level are Nm, Nm-1, … N2, N1 in turn. Wherein, N1, N2, … Nm-1 are the bases corresponding to the first n-1 calculation stages. The elements of the fifth multi-dimensional array Q5 sequentially arranged are the rearrangement numbers corresponding to each block of the target calculation stage, for example, the value of the first element in the fifth multi-dimensional array Q5 is the rearrangement number corresponding to the first block in the current target calculation stage, and the value of the second element in the fifth multi-dimensional array Q5 is the rearrangement number corresponding to the second block in the current target calculation stage. n-1 n-1 n-1

[0151] Step S42, determining the merging matrix corresponding to each block based on the rearrangement number of each block in the target calculation stage.

[0152] The processing of step S42 is the same as the processing of step R42, which will not be described here.

[0153] Step S5, sequentially executing the plurality of calculation stages to obtain the calculation result of the FFT calculation.

[0154] After obtaining the merging matrix corresponding to each block of the target calculation stage, each calculation stage included in the FFT calculation can be sequentially executed. When the target calculation stage is executed, the input data of the target calculation stage can be respectively composed into an input data matrix for multiplication with the merging matrix corresponding to each block, and the multiplication operation of the merging matrix and the input data matrix can be implemented based on a matrix multiplication unit, so as to implement the calculation of the target calculation stage. For example, in the target calculation stage, the merging matrix corresponding to the lth block is ​​​When performing calculations, this can be... The input data matrix, composed of the input data of each butterfly unit in the l-th block, is multiplied to obtain the calculation result corresponding to the l-th block. Thus, in the target calculation stage of this embodiment, only the multiplication operation between the combination matrix and the input data matrix needs to be performed to realize the calculation of the target calculation stage, thereby improving the execution efficiency of the target calculation stage and further improving the execution efficiency of FFT calculation.

[0155] In one feasible approach, similar to Scheme 1 above, since the rotation factors in the first calculation stage are all 1, and there are no identical rotation factors in the last calculation stage, the target calculation stage can be multiple calculation stages, specifically the calculation stages between the first and last calculation stages. This application also provides a method for determining the DFT system matrix in the last calculation stage based on a trigonometric function with a period of N, as follows:

[0156] For the rotation factor matrix of the last calculation stage, the rearrangement number corresponding to each block in the last calculation stage can be obtained. The method for obtaining the rearrangement number corresponding to each block in the last calculation stage can be referred to step S41 above, and will not be repeated here. After obtaining the rearrangement number corresponding to each block in the last calculation stage, the real and imaginary data corresponding to each element in the rotation factor matrix can be determined using the following formula.

[0157] k = lj mod N;

[0158]

[0159] Where l is the rearrangement number, N is the length of the data sequence, and i and j are the rotation factor matrices R. m The row and column numbers of elements in R m _r[i,j] is the rotation factor matrix R m The real part data corresponding to the element in the i-th row and j-th column, R m _i[i,j] is the rotation factor matrix R m The element in the i-th row and j-th column corresponds to the imaginary part data. i∈[0,N1N2…N] m-1 ), j∈[0,N m ), N m Let N1, N2, ..., N be the basis corresponding to the last calculation stage. m-1 It is the product of the bases corresponding to each computational stage after the last computational stage.

[0160] For the DFT coefficient matrix of the first calculation stage and the DFT coefficient matrix of the last calculation stage, please refer to the calculation method of Scheme 1 above, which will not be repeated here.

[0161] Scheme three: another time domain extraction based way to perform FFT calculation

[0162] Step T1, obtaining a data sequence to be performed FFT calculation.

[0163] Step T2, dividing the FFT calculation into multiple calculation stages based on the length of the data sequence.

[0164] Step T3, determining the data sequence of the FFT calculation as the input sequence of the first calculation stage in the FFT calculation.

[0165] Wherein, the processing of step T1 to step T3 is the same as the processing of step R1 to step R3 described above, which will not be repeated here. The difference between scheme two and scheme three is that scheme two rearranges the output sequence of the last calculation stage in the FFT calculation to obtain the calculation result of the FFT, and scheme three rearranges the output sequence of each calculation stage after the second calculation stage to obtain the calculation result of the FFT.

[0166] Step T4, determining the combination matrix corresponding to the target calculation stage in the multiple calculation stages.

[0167] The same as step R4 and S4 described above, in scheme three, the embodiment of the application also provides a method for determining a combination matrix based on a trigonometric function with a period of N, comprising:

[0168] Step T41, determining the rearrangement number corresponding to each block included in the target calculation stage, wherein the rearrangement number is used to indicate the arrangement order of each block in the target calculation stage without changing the input sequence of the first calculation stage.

[0169] Since in scheme three, the output sequence of each calculation stage after the second calculation stage will be rearranged, the order of the blocks in each calculation stage will be different from the order of the blocks in each calculation stage in the traditional FFT calculation. Therefore, in the embodiment of the application, the arrangement order of each block in the target calculation stage without rearranging the output sequence can be determined first, and then the combination matrix in the target calculation stage is determined according to the rearrangement number. Wherein, the processing of rearranging the output sequence of each calculation stage after the second calculation stage can be referred to step T5, which will not be introduced here.

[0170] In the third scheme, the rearrangement number corresponding to each block included in the target calculation stage is determined by obtaining a first sequence matrix, the first sequence matrix being a transpose matrix of a second sequence matrix, the second sequence matrix being sequentially arranged in a row-first manner from 0, the number of columns of the second sequence matrix being equal to the base of the previous calculation stage of the target calculation stage, and the number of rows of the second sequence matrix being equal to the product of the respective bases of the calculation stages before the previous calculation stage. The elements in the first sequence matrix are sequentially determined as the rearrangement number corresponding to each block included in the target calculation stage.

[0171] In implementation, the rearrangement number corresponding to each block included in the target calculation stage can be indicated by a first sequence matrix P1. The first sequence matrix P1 can be obtained by transposing a second sequence matrix P2. In an example, m calculation stages are included in the FFT calculation, and the respective dimensions of the stages are N1, N2, …, Nm in sequence. The target calculation stage is the nth calculation stage, and includes r blocks. The elements in the second sequence matrix P2 can be arranged in a row-first manner as [0, 1, 2, …, r], the number of columns of the second sequence matrix being equal to Nn, and the number of rows being equal to N1*N2*…*Nm. m The target calculation stage is the nth calculation stage, and includes r blocks. The elements in the second sequence matrix P2 can be arranged in a row-first manner as [0, 1, 2, …, r], the number of columns of the second sequence matrix being equal to Nn, and the number of rows being equal to N1*N2*…*Nm. n-1 The target calculation stage is the nth calculation stage, and includes r blocks. The elements in the second sequence matrix P2 can be arranged in a row-first manner as [0, 1, 2, …, r], the number of columns of the second sequence matrix being equal to Nn, and the number of rows being equal to N1*N2*…*Nm. n-2 The target calculation stage is the nth calculation stage, and includes r blocks. The elements in the second sequence matrix P2 can be arranged in a row-first manner as [0, 1, 2, …, r], the number of columns of the second sequence matrix being equal to Nn, and the number of rows being equal to N1*N2*…*Nm. n-1 The target calculation stage is the nth calculation stage, and includes r blocks. The elements in the second sequence matrix P2 can be arranged in a row-first manner as [0, 1, 2, …, r], the number of columns of the second sequence matrix being equal to Nn, and the number of rows being equal to N1*N2*…*Nm. n-2 The target calculation stage is the nth calculation stage, and includes r blocks. The elements in the second sequence matrix P2 can be arranged in a row-first manner as [0, 1, 2, …, r], the number of columns of the second sequence matrix being equal to Nn, and the number of rows being equal to N1*N2*…*Nm. n-2 The target calculation stage is the nth calculation stage, and includes r blocks. The elements in the second sequence matrix P2 can be arranged in a row-first manner as [0, 1, 2, …, r], the number of columns of the second sequence matrix being equal to Nn, and the number of rows being equal to N1*N2*…*Nm. n-1 The target calculation stage is the nth calculation stage, and includes r blocks. The elements in the second sequence matrix P2 can be arranged in a row-first manner as [0, 1, 2, …, r], the number of columns of the second sequence matrix being equal to Nn, and the number of rows being equal to N1*N2*…*Nm. n-1 The target calculation stage is the nth calculation stage, and includes r blocks. The elements in the second sequence matrix P2 can be arranged in a row-first manner as [0, 1, 2, …, r], the number of columns of the second sequence matrix being equal to Nn, and the number of rows being equal to N1*N2*…*Nm. n-2 The target calculation stage is the nth calculation stage, and includes r blocks. The elements in the second sequence matrix P2 can be arranged in a row-first manner as [0, 1, 2, …, r], the number of columns of the second sequence matrix being equal to Nn, and the number of rows being equal to N1*N2*…*Nm.

[0172] In step T42, the merging matrix corresponding to each block is determined based on the rearrangement number of each block in the target calculation stage.

[0173] The processing of step T42 is the same as that of step R42, which will not be described here.

[0174] In step T5, the plurality of calculation stages are sequentially executed to obtain the calculation result of the FFT calculation.

[0175] After obtaining the combination matrix corresponding to each block of the target computing stage, each computing stage included in the FFT computation can be sequentially executed. When executing to the target computing stage, the input data of the target computing stage can be respectively grouped into input data matrices for multiplication with the combination matrix corresponding to each block, and the multiplication operation of the combination matrix and the input data matrix can be implemented based on the matrix multiplication unit, thereby implementing the computation of the target computing stage.

[0176] In the third scheme, for each computing stage after the second computing stage among the plurality of computing stages, the computing result corresponding to each computing stage can be stored according to a set storage order. The computing result corresponding to each block is a short output sequence, and the computing results corresponding to the blocks included in one computing stage can form an output sequence corresponding to the computing stage. The storage order of each computing stage after the second computing stage is introduced as follows.

[0177] For each computing stage between the second computing stage and the second-to-last computing stage: a seventh multi-dimensional array can be obtained, the order of the dimensions after the first dimension of the seventh multi-dimensional array is the same as the order of the dimensions before the last dimension of the eighth multi-dimensional array, the first dimension of the seventh multi-dimensional array is equal to the last dimension of the eighth multi-dimensional array, the elements in the eighth multi-dimensional array are sequentially arranged from 0 and have a length equal to the number of blocks included in the computing stage, and the last dimension is the base corresponding to the previous computing stage of the computing stage, and the dimensions before the last dimension are the bases corresponding to the computing stages before the previous computing stage in sequence. The seventh multi-dimensional array is determined as the storage order of each block in each computing stage.

[0178] In implementation, the storage order of each block in each computing stage can be indicated by the seventh multi-dimensional array Q7. The seventh multi-dimensional array Q7 is obtained by transposing the eighth multi-dimensional array Q8. The elements in the eighth multi-dimensional array Q8 are sequentially arranged from 0 and correspondingly have a length equal to the number of blocks included in the computing stage. For example, the computing stage is the nth computing stage in the FFT computation, and the number of blocks included is m, where the nth computing stage is between the 2nd computing stage and the 2nd-to-last computing stage. Correspondingly, the elements in the eighth multi-dimensional array Q8 can be sequentially arranged from 0 to m, and the corresponding dimensions are N n-2 , N n-3 , … N1, N n-1 , where N1, … N n-3 , N n-2 , N n-1 , and N

[0179] After the eighth multi-dimensional array Q8 is determined, the eighth multi-dimensional array Q8 can be processed by the device to obtain a seventh multi-dimensional array Q7. For example, the above eighth multi-dimensional array Q8 is transposed into the seventh multi-dimensional array Q7, and each level dimension of the seventh multi-dimensional array Q7 is N n-1 , N n-2 , …, N1 in turn. After the seventh multi-dimensional array Q7 is obtained, the storage order corresponding to the calculation result of each block in the calculation stage can be indicated according to the value of each element in the seventh multi-dimensional array Q7. For example, the elements in the seventh multi-dimensional array Q7 are 0, 3, 1, 4, 2, and 5 in turn, which can indicate that in the corresponding calculation stage, the calculation result of the first block is stored in the first position, the calculation result of the third block is arranged after the calculation result of the first block, the calculation result of the fifth block is arranged after the calculation result of the third block, the calculation result of the second block is arranged after the calculation result of the fifth block, the calculation result of the fourth block is arranged after the calculation result of the second block, and the calculation result of the sixth block is arranged after the calculation result of the fourth block.

[0180] For the second last calculation stage: the storage order of the calculation result corresponding to each block in the second last calculation stage can be the same as the storage order corresponding to the calculation stage between the above second calculation stage and the second last calculation stage. The difference is that in the second last calculation stage, the calculation result corresponding to the same block is stored with an interval of X elements, and the value of X is equal to the number of blocks included in the second last calculation stage. And in the second last calculation stage, the elements at the same position in the calculation results corresponding to the plurality of blocks are stored according to the corresponding calculation order.

[0181] For the last calculation stage: after the calculation of the last calculation stage is completed, Y elements can be read in turn, and the value of Y is equal to the product of the bases corresponding to each calculation stage before the second last calculation stage. Then the elements read each time are stored according to the storage order indicated by the third sequence matrix. The third sequence matrix is the transpose matrix of the fourth sequence matrix, the fourth sequence matrix is sequentially arranged in row-major order starting from 0, the column number of the fourth sequence matrix is equal to the base corresponding to the last calculation stage, and the row number of the fourth sequence matrix is equal to the base corresponding to the second last calculation stage.

[0182] After the calculation results of each block included in each calculation stage are stored in the above storage manner, the calculation result of the FFT calculation performed on the data sequence can be obtained. In this way, when the target calculation stage is executed in the embodiment of the present application, only the multiplication operation combined with the matrix and the input data matrix needs to be performed to realize the calculation of the target calculation stage, thereby improving the execution efficiency of the target calculation stage and further improving the execution efficiency of the FFT calculation.

[0183] In one feasible approach, similar to Scheme 2 above, since the rotation factors in the first calculation stage are all 1, and there are no identical rotation factors in the last calculation stage, the target calculation stage can be multiple calculation stages, specifically the calculation stages between the first and last calculation stages. This application also provides a method for determining the DFT system matrix in the last calculation stage based on a trigonometric function with a period of N, as follows:

[0184] For the rotation factor matrix in the last calculation stage, we can set i∈[0,N] m ),j∈[0,N1N2…N m-1 ), calculate k = ij mod N, and obtain the real and imaginary parts. Where N is the length of the data sequence, and i and j are the rotation factor matrices R. m The row and column numbers of elements in R m _r[i,j] is the rotation factor matrix R m The real part data corresponding to the element in the i-th row and j-th column, R m _i[i,j] is the rotation factor matrix R m The element in the i-th row and j-th column corresponds to the imaginary part of the data. m Let N1, N2, ..., N be the basis corresponding to the last calculation stage. m-1 This is the product of the bases corresponding to each computational stage following the last computational stage. Additionally, based on the computational method provided in this application, the rotation factor matrix R of the last computational stage is obtained. m After that, R needs to be further processed. m Perform conversion processing, including converting R... m Reshape (transform) to have dimensions N in sequence. m N m-1 N m-2 ...a multidimensional array of size N1, then swap the coordinate axes to transform the multidimensional array into one with dimensions N. m-1 N m N m-2 ...a multidimensional array of N1, and then reshape the resulting multidimensional array to have dimensions N. m-1 N m N m-2 …a two-dimensional array of N1. This two-dimensional data is the rotation factor matrix of the last calculation stage.

[0185] For the DFT coefficient matrix of the first calculation stage and the DFT coefficient matrix of the last calculation stage, please refer to the calculation method of Scheme 1 above, which will not be repeated here.

[0186] The embodiment of the present application further provides a matrix operation method, which can be applied to the matrix multiplication operation of the input data matrix and the combination matrix in the above embodiment, and the method is as follows: arranging each odd row in the combination matrix to each even row or arranging each even row in the combination matrix to each odd row to obtain a rearranged combination matrix. The product of the input sequence of a target calculation stage and the rearranged combination matrix is determined as the output sequence of the target calculation stage.

[0187] In the matrix multiplication operation process, the input data matrix is composed of real part data and imaginary part data of complex numbers arranged alternately by row. Each row and each column of the combination matrix includes real part data and imaginary part data of complex numbers, and the real part data and the imaginary part data are arranged alternately in each row and each column. In the result matrix obtained by performing the matrix multiplication operation on the input data matrix and the combination matrix, the real part data and the imaginary part data of complex numbers are also arranged alternately by row. Therefore, when reshaping the result matrix into the input sequence of the next calculation stage, each row of real part data in the result matrix needs to be read at intervals, each row of imaginary part data in the result matrix needs to be read at intervals, and then non-continuous reading is caused, and the calculation efficiency of the FFT is reduced.

[0188] The matrix operation method provided by the embodiment of the present application can arrange each odd row in the combination matrix to each even row or arrange each odd row in the combination matrix to each even row to obtain a rearranged combination matrix. In this way, in the result matrix obtained by performing the matrix multiplication operation on the rearranged combination matrix and the input data matrix, the real part data of complex numbers is arranged continuously by row, and the imaginary part data of complex numbers is arranged continuously by row. Therefore, when reshaping the result matrix into the input sequence of the next calculation stage, each row of real part data in the result matrix and each row of imaginary part data in the result matrix do not need to be read at intervals, and then non-continuous reading is avoided, and the calculation efficiency of the FFT can be improved.

[0189] Figure 7 The device for performing the FFT calculation provided by the embodiment of the present application can be the processor in the above embodiment, and the device comprises:

[0190] The acquisition module 710 is configured to acquire a data sequence to be subjected to the FFT calculation in response to an FFT calculation request, and can be specifically configured to implement the acquisition function of the step 501 and the implicit steps.

[0191] The division module 720 is configured to divide the FFT calculation into a plurality of calculation stages based on the length of the data sequence, and can be specifically configured to implement the division function of the step 502 and the implicit steps.

[0192] The determining module 730 is configured to determine, for at least one target calculation stage of the plurality of calculation stages, a merging matrix corresponding to the target calculation stage based on bases respectively corresponding to the plurality of calculation stages, and an execution sequence of the target calculation stage in the plurality of calculation stages, where the merging matrix is a product of a discrete Fourier transform (DFT) coefficient matrix in the target calculation stage and a rotation factor, and the determining module 730 can be specifically configured to implement the determination function of step 503 and the implicit steps.

[0193] The execution module 740 is configured to sequentially execute the plurality of calculation stages, where when the target calculation stage is executed, a product of an input sequence of the target calculation stage and the merging matrix is determined as an output sequence of the target calculation stage, and the execution module 740 can be specifically configured to implement the execution function of step 504 and the implicit steps.

[0194] The determining module 720 is configured to determine a calculation result of performing the FFT calculation on the data sequence based on an output sequence of a last calculation stage of the plurality of calculation stages, and the determining module 720 can be specifically configured to implement the determination function of step 505 and the implicit steps.

[0195] In an implementable manner, when the extraction manner corresponding to the FFT calculation is time domain extraction, an input sequence of a first calculation stage of the plurality of calculation stages is changed to the data sequence.

[0196] When the extraction manner corresponding to the FFT calculation is frequency domain extraction, the input sequence of the first calculation stage is changed to a sequence obtained by performing rearrangement processing on the data sequence, where the rearrangement processing refers to determining the data sequence as a first multi-dimensional array with dimensions of each level being bases corresponding to the plurality of calculation stages, performing transpose processing on the first multi-dimensional array to obtain a second multi-dimensional array, and the order of dimensions of each level corresponding to the second multi-dimensional array is opposite to the order of dimensions of each level corresponding to the first multi-dimensional array.

[0197] In an implementable manner, the determining module is configured to:

[0198] determine a rearrangement number corresponding to each block included in the target calculation stage, where the rearrangement number is used to indicate an arrangement sequence of the each block in the target calculation stage when the input sequence of the first calculation stage is not changed.

[0199] determine a merging matrix corresponding to the each block based on the rearrangement number of the each block in the target calculation stage.

[0200] In an implementable manner, when the extraction manner of the FFT calculation is frequency domain extraction, the determining module is configured to:

[0201] obtaining a third multi-dimensional array, an order of dimensions of the third multi-dimensional array being opposite to an order of dimensions of a fourth multi-dimensional array, elements in the fourth multi-dimensional array being sequentially arranged from 0 and having a length of a number of blocks included in the target calculation stage, dimensions of the fourth multi-dimensional array being corresponding bases of calculation stages in sequence after the target calculation stage;

[0202] determining elements in the third multi-dimensional array in sequence as the rearrangement numbers corresponding to each block included in the target calculation stage.

[0203] In an implementable manner, in a case where the decimation manner of the FFT calculation is time domain decimation, the determining module is configured to:

[0204] obtaining a fifth multi-dimensional array, an order of dimensions of the fifth multi-dimensional array being opposite to an order of dimensions of a sixth multi-dimensional array, elements in the sixth multi-dimensional array being sequentially arranged from 0 and having a length of a number of blocks included in the target calculation stage, dimensions of the sixth multi-dimensional array being corresponding bases of calculation stages in sequence before the target calculation stage;

[0205] determining elements in the fifth multi-dimensional array in sequence as the rearrangement numbers corresponding to each block included in the target calculation stage.

[0206] In an implementable manner, in a case where the decimation manner of the FFT calculation is time domain decimation, the determining module is configured to:

[0207] obtaining a first sequence matrix, the first sequence matrix being a transpose matrix of a second sequence matrix, the second sequence matrix being sequentially arranged from 0 in a row-first manner, a column number of the second sequence matrix being equal to a base of a previous calculation stage of the target calculation stage, and a row number of the second sequence matrix being equal to a product of bases of calculation stages before the previous calculation stage;

[0208] determining elements in the first sequence matrix in sequence as the rearrangement numbers corresponding to each block included in the target calculation stage.

[0209] In an implementable manner, the apparatus further includes a storage module configured to:

[0210] For each of the computing stages between the second computing stage and the second-to-last computing stage of the plurality of computing stages, a seventh multi-dimensional array is obtained, the seventh multi-dimensional array has the same order of dimensions after the first level of dimensions as the order of dimensions before the last level of dimensions of the eighth multi-dimensional array, the first level of dimensions of the seventh multi-dimensional array is equal to the last level of dimensions of the eighth multi-dimensional array, the elements in the eighth multi-dimensional array are sequentially arranged from 0 and have a length of the number of blocks included in the computing stage, the last level of dimensions is the corresponding base of the previous computing stage of the computing stage, and the dimensions before the last level are the corresponding bases of the computing stages before the previous computing stage in sequence;

[0211] The seventh multi-dimensional array is determined as the storage order of the blocks in the each of the computing stages;

[0212] Based on the storage order, the computing results of the blocks in the each of the computing stages are stored.

[0213] In an implementable manner, the determining module is configured to:

[0214] Based on the rearrangement number of the each block in the target computing stage and the position information of each element in the merging matrix, the imaginary part data and the real part data of each element in the merging matrix corresponding to the each block are determined, where the rearrangement number, the position information, the imaginary part data and the real part data of each element satisfy the following formula:

[0215] k = (Alp + Bpq) mod N;

[0216]

[0217] wherein, l is the rearrangement number, A and B are preset coefficients, N is the length of the data sequence, p and q are the row number and the column number of the element in the merging matrix respectively, the real part data of the element in the pth row and the qth column of the merging matrix corresponding to the lth block in the nth computing stage, the imaginary part data of the element in the pth row and the qth column of the merging matrix corresponding to the lth block in the nth computing stage.

[0218] In an implementable manner, the determining module is configured to:

[0219] The odd rows in the merging matrix are arranged to the even rows, or the even rows in the merging matrix are arranged to the odd rows, to obtain a rearranged merging matrix;

[0220] The product of the input sequence of the target computing stage and the rearranged merging matrix is determined as the output sequence of the target computing stage.

[0221] In an implementable manner, the dividing module is configured to:

[0222] divide the FFT calculation into a plurality of calculation stages based on the length of the data sequence and priorities of a plurality of candidate bases, and determine a base corresponding to each calculation stage, wherein the candidate base is less than or equal to one half of a calculation size of a matrix multiplication unit performing the FFT calculation, and the priority of the candidate base is proportional to a numerical size of the candidate base.

[0223] In an implementable manner, the at least one target calculation stage is a calculation stage other than a first calculation stage and a last calculation stage in the plurality of calculation stages.

[0224] The division of the modules in the embodiments of the present application is illustrative, and is merely a logical functional division. In actual implementation, another division manner can also be used. In addition, each functional module in each embodiment of the present application can be integrated in one processor, or can be physically separated, or two or more modules can be integrated into one module. The integrated module can be realized in the form of hardware or in the form of a software functional module. In addition, the apparatus for performing the FFT calculation and the method for performing the FFT calculation provided in the above embodiments belong to the same concept, and the specific implementation process is described in the method embodiments, which will not be repeated here.

[0225] When the integrated module is realized in the form of a software functional module and sold or used as an independent product, the integrated module can be stored in a computer readable storage medium. Based on this understanding, the technical solutions of the present application or all or part of the technical solutions that essentially contribute to the prior art can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes a plurality of instructions for causing an end device (which can be a personal computer, a mobile phone, or a network device, etc.) or a processor to execute all or part of the steps of the method according to the embodiments of the present application. The foregoing storage medium includes a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and various media that can store program codes.

[0226] The embodiments of the present application further provide a computer program product containing instructions. The computer program product can be a software or program product containing instructions, which can run on a power consumption management device or be stored in any available medium. When the computer program product runs on the power consumption management device, at least one computing device is caused to execute the method for performing the FFT calculation provided in the embodiments of the present application.

[0227] The computer readable storage medium can be any available media or data storage device that can be accessed by a computing device and includes one or more of a magnetic media, (e.g., a floppy disk, a hard disk, a magnetic tape), an optical media (e.g., a DVD), or a semiconductor media (e.g., a solid state hard drive), etc. The computer readable storage medium includes instructions for carrying out the method of performing FFT calculation provided by the embodiments of the present application.

[0228] The terms "first", "second", and the like in the present application are used to distinguish between similar or identical items or elements having substantially the same function and should be understood that there is no logical or chronological dependency between "first" and "second", nor does it limit the number and execution order. It should also be understood that although the following description uses the terms first, second, and the like to describe various elements, these elements should not be limited by the terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of various examples, a first multi-dimensional array can be referred to as a second multi-dimensional array, and similarly, a second multi-dimensional array can be referred to as a first multi-dimensional array. The first multi-dimensional array and the multi-dimensional array can both be collectively referred to as a multi-dimensional array, and in some cases, can be separate and distinct multi-dimensional arrays.

[0229] The term "at least one" in the present application means one or more, and the term "a plurality" in the present application means two or more.

[0230] The above description is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto, and any skilled person in the art can easily think of various equivalent modifications or replacements within the technical scope disclosed by the present application, and these modifications or replacements should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A method of performing an FFT computation, characterized by, The method is executed by a processor, and the method comprises: in response to a fast Fourier transform (FFT) calculation request sent by an application program, obtaining a data sequence to be subjected to FFT calculation in the application program, the application program being an artificial intelligence application or a high-performance computing application; based on the length of the data sequence, dividing the FFT calculation into a plurality of calculation stages; for a first calculation stage of the plurality of calculation stages, based on the bases respectively corresponding to the plurality of calculation stages and the execution order of the first calculation stage in the plurality of calculation stages, determining a merging matrix corresponding to the first calculation stage, wherein the merging matrix is a product of a discrete Fourier transform (DFT) coefficient matrix in the first calculation stage and a rotation factor; sequentially executing the plurality of calculation stages, wherein, when the first calculation stage is executed, a multiplication operation of an input sequence of the first calculation stage and the merging matrix is executed by a matrix multiplication unit in the processor, and a product obtained by executing the multiplication operation is determined as an output sequence of the first calculation stage, wherein, in a case where an extraction manner corresponding to the FFT calculation is time domain extraction, an input sequence of a first calculation stage of the plurality of calculation stages is changed to the data sequence; in a case where the extraction manner corresponding to the FFT calculation is frequency domain extraction, the input sequence of the first calculation stage is changed to a sequence obtained by performing rearrangement processing on the data sequence, wherein the rearrangement processing refers to determining the data sequence as a first multi-dimensional array whose dimensions at each level are the bases corresponding to the plurality of calculation stages in turn, performing transpose processing on the first multi-dimensional array to obtain a second multi-dimensional array, and the order of the dimensions at each level corresponding to the second multi-dimensional array is opposite to the order of the dimensions at each level corresponding to the first multi-dimensional array; based on an output sequence of a last calculation stage of the plurality of calculation stages, determining a calculation result of performing the FFT calculation on the data sequence.

2. The method of claim 1, wherein, The method comprises: determining a rearrangement number corresponding to each block included in the first calculation stage, wherein the rearrangement number is used to indicate an arrangement order of the each block in the first calculation stage in a case where the input sequence of the first calculation stage is not changed; based on the rearrangement number of the each block in the first calculation stage, determining a merging matrix corresponding to the each block.

3. The method of claim 2, wherein, In a case where the extraction manner of the FFT calculation is frequency domain extraction, the method comprises: obtaining a third multi-dimensional array, the order of the dimensions at each level of the third multi-dimensional array being opposite to the order of the dimensions at each level of a fourth multi-dimensional array, the elements in the fourth multi-dimensional array being sequentially arranged from 0 and having a length of the number of blocks included in the first calculation stage, and the dimensions of the fourth multi-dimensional array being the bases respectively corresponding to the calculation stages after the first calculation stage in turn; The elements in the third multi-dimensional array are sequentially determined as the rearrangement numbers corresponding to each block included in the first calculation stage.

4. The method of claim 2, wherein, In a case where the extraction manner of the FFT calculation is time domain extraction, the determination of the rearrangement numbers corresponding to each block included in the first calculation stage comprises: A fifth multi-dimensional array is obtained, the order of each level dimension of the fifth multi-dimensional array is opposite to the order of each level dimension of a sixth multi-dimensional array, the elements in the sixth multi-dimensional array are sequentially arranged from 0 and the length is the number of blocks included in the first calculation stage, and the dimensions of the sixth multi-dimensional array are the bases corresponding to the calculation stages before the first calculation stage, respectively. The elements in the fifth multi-dimensional array are sequentially determined as the rearrangement numbers corresponding to each block included in the first calculation stage.

5. The method of claim 4, wherein, In a case where the extraction manner of the FFT calculation is time domain extraction, the determination of the rearrangement numbers corresponding to each block included in the first calculation stage comprises: A first sequence matrix is obtained, the first sequence matrix is a transpose matrix of a second sequence matrix, the second sequence matrix is sequentially arranged from 0 in a row-first manner, the column number of the second sequence matrix is equal to the base of a calculation stage before the first calculation stage, and the row number of the second sequence matrix is equal to the product of the bases corresponding to the calculation stages before the calculation stage. The elements in the first sequence matrix are sequentially determined as the rearrangement numbers corresponding to each block included in the first calculation stage.

6. The method of claim 5, wherein, The method further comprises: For each calculation stage between a second calculation stage and a penultimate calculation stage in the plurality of calculation stages, a seventh multi-dimensional array is obtained, the order of each dimension after the first level dimension of the seventh multi-dimensional array is the same as the order of each dimension before the last level dimension of an eighth multi-dimensional array, the dimension of the first level of the seventh multi-dimensional array is equal to the dimension of the last level of the eighth multi-dimensional array, the elements in the eighth multi-dimensional array are sequentially arranged from 0 and the length is the number of blocks included in the calculation stage, the last level dimension is the base corresponding to a calculation stage before the calculation stage, and the dimensions before the last level are the bases corresponding to the calculation stages before the calculation stage, respectively. The seventh multi-dimensional array is determined as the storage order of each block in the calculation stage. Based on the storage order, the calculation results of each block in the calculation stage are stored.

7. The method of claim 2, wherein, The determination of the merging matrix corresponding to each block in the first calculation stage based on the rearrangement numbers of each block in the first calculation stage comprises: Based on the rearrangement numbers of each block in the first calculation stage and the position information of each element in the merging matrix, the imaginary part data and the real part data of each element in the merging matrix corresponding to each block are determined, wherein the rearrangement numbers, the position information and the imaginary part data and the real part data of each element satisfy the following formula: in, For the rearrangement number, , For preset coefficients, The length of the data sequence. , These are the row and column numbers of the elements in the merged matrix, respectively. No. In the first calculation stage The merge matrix corresponding to the nth block is the nth Line number The real data corresponding to the elements of the column. No. In the first calculation stage The merge matrix corresponding to the nth block is the nth Line number The imaginary data corresponding to the elements of the column.

8. The method according to any one of claims 1 to 7, characterized in that, The multiplication operation of the input sequence of the first calculation stage and the merging matrix performed by the matrix multiplication unit in the processor determines the product of the multiplication operation as the output sequence of the first calculation stage, comprising: arrange each odd row in the combined matrix to each even row, or arrange each even row in the combined matrix to each odd row, to obtain a rearranged combined matrix; perform multiplication operation of input sequence of the first calculation stage and the rearranged combined matrix by the matrix multiplication unit, and determine the product of the multiplication operation as output sequence of the first calculation stage.

9. The method according to any one of claims 1 to 7, characterized in that, The FFT calculation is divided into multiple calculation stages based on the length of the data sequence, including: The FFT calculation is divided into multiple calculation stages based on the length of the data sequence and the priority of multiple candidate bases, and the base corresponding to each calculation stage is determined, wherein the candidate base is less than or equal to one half of the calculation size of the matrix multiplication unit performing the FFT calculation, and the priority of the candidate base is proportional to the numerical size of the candidate base.

10. The method according to any one of claims 1 to 7, characterized in that, The first calculation stage is other than the first calculation stage and the last calculation stage in the multiple calculation stages.

11. An apparatus for performing a FFT computation, the apparatus comprising: The device is configured in a processor, and the device includes: An acquisition module is configured to, in response to a fast Fourier transform (FFT) calculation request sent by an application program, acquire a data sequence to be executed in the FFT calculation in the application program, the application program being an artificial intelligence application or a high-performance computing application; A division module is configured to divide the FFT calculation into multiple calculation stages based on the length of the data sequence. A determination module is configured to, for a first calculation stage in the multiple calculation stages, determine a combined matrix corresponding to the first calculation stage based on bases corresponding to the multiple calculation stages, and an execution order of the first calculation stage in the multiple calculation stages, wherein the combined matrix is a product of a discrete Fourier transform (DFT) coefficient matrix in the first calculation stage and a rotation factor. An execution module is configured to sequentially execute the multiple calculation stages, wherein, when the first calculation stage is executed, multiplication operation of input sequence of the first calculation stage and the combined matrix is performed by a matrix multiplication unit in the processor, and the product of the multiplication operation is determined as output sequence of the first calculation stage, wherein, when an extraction mode corresponding to the FFT calculation is time domain extraction, input sequence of a first calculation stage in the multiple calculation stages is changed to the data sequence; when the extraction mode corresponding to the FFT calculation is frequency domain extraction, input sequence of the first calculation stage is changed to a sequence after rearrangement processing of the data sequence, wherein the rearrangement processing refers to determining the data sequence as a first multi-dimensional array with dimensions of each level being the bases corresponding to the multiple calculation stages in turn, performing transpose processing on the first multi-dimensional array to obtain a second multi-dimensional array, and the order of dimensions of each level corresponding to the second multi-dimensional array is opposite to the order of dimensions of each level corresponding to the first multi-dimensional array. The determination module is configured to determine a calculation result of the FFT calculation performed on the data sequence based on output sequence of a last calculation stage in the multiple calculation stages.

12. The apparatus of claim 11, wherein, The determination module is configured to: determining a rearrangement number corresponding to each block in the first calculation stage, wherein the rearrangement number is used to indicate an arrangement order of the each block in the first calculation stage without changing an input sequence of the first calculation stage; determining a merging matrix corresponding to the each block based on the rearrangement number of the each block in the first calculation stage.

13. The apparatus of claim 12, wherein, In a case where the extraction manner of the FFT calculation is frequency domain extraction, the determining module is configured to: obtain a third multi-dimensional array, wherein an order of each level dimension of the third multi-dimensional array is opposite to an order of each level dimension of a fourth multi-dimensional array, elements in the fourth multi-dimensional array are sequentially arranged from 0 and have a length of a number of blocks included in the first calculation stage, and dimensions of the fourth multi-dimensional array are corresponding bases of calculation stages after the first calculation stage in sequence; determine elements in the third multi-dimensional array as the rearrangement number corresponding to each block included in the first calculation stage in sequence.

14. The apparatus of claim 13, wherein, In a case where the extraction manner of the FFT calculation is time domain extraction, the determining module is configured to: obtain a fifth multi-dimensional array, wherein an order of each level dimension of the fifth multi-dimensional array is opposite to an order of each level dimension of a sixth multi-dimensional array, elements in the sixth multi-dimensional array are sequentially arranged from 0 and have a length of a number of blocks included in the first calculation stage, and dimensions of the sixth multi-dimensional array are corresponding bases of calculation stages before the first calculation stage in sequence; determine elements in the fifth multi-dimensional array as the rearrangement number corresponding to each block included in the first calculation stage in sequence.

15. The apparatus of claim 12, wherein, In a case where the extraction manner of the FFT calculation is time domain extraction, the determining module is configured to: obtain a first sequence matrix, wherein the first sequence matrix is a transpose matrix of a second sequence matrix, the second sequence matrix is sequentially arranged from 0 in a row-first manner, a column number of the second sequence matrix is equal to a base of a previous calculation stage of the first calculation stage, and a row number of the second sequence matrix is equal to a product of corresponding bases of calculation stages before the previous calculation stage; determine elements in the first sequence matrix as the rearrangement number corresponding to each block included in the first calculation stage in sequence.

16. The apparatus of claim 15, wherein, The apparatus further includes a storage module configured to: for each calculation stage between a second calculation stage and a penultimate calculation stage in the plurality of calculation stages, obtain a seventh multi-dimensional array, wherein an order of each dimension after a first level dimension of the seventh multi-dimensional array is same as an order of each dimension before a last level dimension of an eighth multi-dimensional array, the first level dimension of the seventh multi-dimensional array is equal to the last level dimension of the eighth multi-dimensional array, elements in the eighth multi-dimensional array are sequentially arranged from 0 and have a length of a number of blocks included in the calculation stage, the last level dimension is a base corresponding to a previous calculation stage of the calculation stage, and the dimensions before the last level dimension are corresponding bases of each calculation stage before the previous calculation stage in sequence; determine the seventh multi-dimensional array as a storage order of each block in the each calculation stage. store the calculation result of each block in each of the calculation stages based on the storage order.

17. The apparatus of claim 12, wherein, The determination module is configured to: determine the imaginary part data and the real part data of each element in the merging matrix corresponding to each block based on the rearrangement number of each block in the first calculation stage and the position information of each element in the merging matrix, wherein the rearrangement number, the position information, and the imaginary part data and the real part data of each element satisfy the following formula: wherein, is the reordering number, , is the preset coefficient, is the length of the data sequence, , are the row number and the column number of the element in the merging matrix, respectively, the real part data corresponding to the element in the merging matrix in the first row and the first column corresponding to the element in the merging matrix of the first block in the first calculation stage, the imaginary part data corresponding to the element in the merging matrix in the first row and the first column corresponding to the element in the merging matrix of the first block in the first calculation stage.

18. The apparatus of any one of claims 11 to 17, wherein, The determination module is configured to: arrange each odd row in the merging matrix to each even row or arrange each even row in the merging matrix to each odd row to obtain a rearranged merging matrix; perform multiplication operation of the input sequence of the first calculation stage and the rearranged merging matrix by the matrix multiplication unit, and determine the product of the multiplication operation as the output sequence of the first calculation stage.

19. The apparatus of any one of claims 11 to 17, wherein, The division module is configured to: divide the FFT calculation into a plurality of calculation stages based on the length of the data sequence and the priority of a plurality of candidate bases, and determine the base corresponding to each calculation stage, wherein the candidate base is less than or equal to one half of the calculation size of the matrix multiplication unit performing the FFT calculation, and the priority of the candidate base is proportional to the numerical size of the candidate base.

20. The apparatus of any one of claims 11 to 17, wherein, The first calculation stage is other calculation stage than the first calculation stage and the last calculation stage in the plurality of calculation stages.

21. A computing device, comprising: The computing device comprises a processor and a memory; The processor is configured to execute instructions stored in the memory, so that the computing device performs the method of any one of claims 1 to 10.

22. A computer program product comprising instructions, wherein: When the instructions are executed by the computing device, the computing device performs the method of any one of claims 1 to 10.

23. A computer-readable storage medium, characterized in that, Computer program instructions are included, when the computer program instructions are executed by the computing device, the computing device performs the method of any one of claims 1 to 10.

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