Line exchange and line exchanging method

Abstract

To achieve a scalable call environment at low cost without increasing the complexity or size of a device.SOLUTION: A line exchange switches lines between a first terminal, which is an input-side terminal, and a second terminal, which is an output-side terminal. The line exchange includes: a first interface unit that is an input-side interface for connecting to the first terminal, the first interface unit packetizing voice data received from the first terminal in predetermined units and outputting the packetized packet data; a packet switch unit that routes the packet data output from the first interface unit; and a second interface unit that is an output-side interface for connecting to the second terminal, the second interface unit having a clock matching unit that writes the routed packet data to a data buffer and reads out the written packet data at a read timing indicated by a time margin value determined based on delay and / or fluctuation of the packet switch unit.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a circuit switching device and a circuit switching method. [Background technology]

[0002] Conventionally, there is known an exchange equipped with a time division switch that controls calls between terminals such as telephones by time division multiplexing. For example, Patent Document 1 describes a system including "a receiving memory and a transmitting memory into which digital voice data is sequentially written and read out in predetermined byte units, a multiplexing means for time-dividing digital voice data of a plurality of channels in the predetermined byte units, multiplexing the data according to channel numbers, and writing the data into the receiving memory, a first function block for sequentially reading the digital voice data written into the receiving memory in the predetermined byte units and linking digital voice data belonging to the same channel together to assemble a receiving voice data field of a predetermined length, and a header for adding headers to the receiving voice data field assembled by this first function block." The document describes a private branch exchange comprising: a second functional block that assembles a receiving voice packet by adding a header field; a third functional block that sequentially inputs transmitting voice packets of a plurality of channels and divides them into a header field and a transmitting voice data field; a fourth functional block that separates the digital voice data in the transmitting voice data field taken in from the third functional block into the predetermined byte units and writes them sequentially to the transmitting memory according to the channel number; and a demultiplexing means that reads out the digital voice data stored in the transmitting memory and demultiplexes it into digital voice data of a plurality of channels. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 11-215191 Summary of the Invention [Problem to be solved by the invention]

[0004] Conventional exchanges equipped with time division switches, such as those described in Patent Document 1, have limitations on adding time slots due to physical and design constraints, making it difficult to expand as the number of subscribers increases. To avoid these limitations, it is possible to consider replacing the time division switch with a packet switch. However, simply replacing the time division switch with a packet switch handles asynchronous communication in terms of clocks. Therefore, to achieve the same functionality as before the replacement, the packet switch must be equipped with the function of outputting voice data synchronized with a reference clock. However, if the packet switch is equipped with this function, the packet switch itself will become more complex and larger, resulting in a higher cost burden.

[0005] FIG. 22 is a diagram illustrating an example of an exchange equipped with a conventional time division switch. As shown in FIG. 22, in the conventional exchange 2200, an input-side interface unit 2201 receives a call signal transmitted from a calling terminal, reads the received call signal, and performs predetermined call control processing. Then, a multiplexing unit 2203 multiplexes the call signal after the call control processing in a predetermined format. The time division switch 2203 then time-divides the multiplexed call signal in units of a predetermined number of bytes. A demultiplexing unit 2204 demultiplexes the multiplexed and time-divided call signal into the original call signals, which are then output to an output-side interface unit 2205. The interface unit 2205 transmits the demultiplexed call signals to a receiving terminal. The processing and signals performed by these units are synchronized by a reference clock (e.g., 8 kHz) output by a clock unit 2206, and a call between designated terminals (e.g., a call 2207 between a terminal connected to interface unit 1 and a terminal connected to interface unit N) is realized.

[0006] Fig. 23 is a diagram for explaining the operating principle of the conventional time division switch shown in Fig. 22. As shown in Fig. 23, the time division switch 2203 has a data memory 2301, a control memory 2302, and a counter circuit 2303, and operates on a reference clock output from a clock unit 2206, similar to other units such as the interface units 2201 and 2205. A call signal is sequentially written into the data memory 2301 via the multiplexing unit 2202 in the order of an INF number for identifying the interface unit 2201 on the input side and a Ch number for identifying the channel (W data, W address). An INF number for identifying the interface unit 2205 on the output side and a Ch number for identifying the channel are written into an address of the control memory 2302 (W data). The W data is set by the control unit of the interface unit based on information from a central processing unit such as a CPU, and is updated at the timing of call origination, call reception, disconnection, etc. Then, using the reference clock counted by counter circuit 2303, the call signal of the INF number and Ch number of output-side interface unit 2205 written in control memory 2302 is read out (R data, R address), passed through demultiplexer 2204, and output to output-side interface unit 2205. In this example, the INF number "INF-2" and Ch number "Ch7" of input-side interface unit 2201 to be output as data are written in data memory 2201, and the INF number "INF-1" and Ch number "Ch3" of output-side interface unit 2205 are written in control memory 2302, so that a call between these channels is realized.

[0007] As such, due to the limitations of conventional exchanges, even when an increase in the number of new call signals handled is expected as the number of subscribers increases, it is not always possible to create a call environment that matches the increase.In addition, the technology for controlling call signals using time division multiplexing has been around for many years, and there is a need for technology that can create a scalable call environment that matches the increasing number of lines that has accompanied the recent spread of remote work, at low cost, without increasing the complexity or size of the equipment.

[0008] An object of the present invention is to provide a circuit switching device and a circuit switching method that can realize a scalable communication environment at low cost without increasing the complexity or size of the device. [Means for solving the problem]

[0009] The circuit switch according to the present invention is a circuit switch that switches lines between a first terminal that is an input terminal and a second terminal that is an output terminal, and is configured as a circuit switch comprising: a first interface unit that is an input interface for connecting to the first terminal, the first interface unit packetizing voice data received from the first terminal in predetermined units and outputting the packetized packet data; a packet switch unit that routes the packet data output from the first interface unit; and a second interface unit that is an output interface for connecting to the second terminal, the second interface unit having a clock alignment unit that writes the routed packet data to a data buffer and reads the written packet data at a read timing indicated by a time margin value determined based on delay and / or fluctuation of the packet switch unit. [Effects of the Invention]

[0010] According to the present invention, a scalable communication environment can be realized at low cost without increasing the complexity or size of the device. [Brief explanation of the drawings]

[0011] [Figure 1] FIG. 2 is a diagram illustrating an example of the configuration of a circuit switch according to the first embodiment. [Figure 2] FIG. 2 is a diagram illustrating a more specific configuration of the circuit switch illustrated in FIG. [Figure 3] 2 is a diagram showing an example of line connection information for voice data processed by the circuit switch shown in FIG. 1. FIG. [Figure 4]FIG. 2 is a diagram illustrating an example of packet data generated by an interface unit. [Figure 5] FIG. 10 is a sequence diagram illustrating an example of the operation of the circuit switch according to the first embodiment (individual transfer of voice data). [Figure 6] 10A and 10B are diagrams for explaining an example of specific processing performed in a clock matching unit; [Figure 7] FIG. 10 is a diagram illustrating an example of the configuration of a circuit switch according to a second embodiment. [Figure 8] FIG. 1 is a diagram illustrating an example of the configuration of a conventional circuit switching device. [Figure 9] 8 is a diagram for explaining an example of specific processing performed in a clock matching unit of the circuit switch shown in FIG. 7.

[0023] FIG. [Figure 10] FIG. 1 is a diagram for explaining a method for adding a circuit switch. [Figure 11] FIG. 1 is a diagram for explaining a conventional method for adding a circuit exchange having a time division switch. [Figure 12] FIG. 10 is a diagram illustrating an example of the configuration of a circuit switch according to a fourth embodiment. [Figure 13] FIG. 13 is a diagram illustrating a more specific configuration of the circuit switch illustrated in FIG. [Figure 14] FIG. 11 is a sequence diagram illustrating an example of the operation of the circuit switch according to the fourth embodiment (voice data integrated transfer). [Figure 15] FIG. 10 is a diagram for explaining an example of specific processing performed in a clock matching unit in the fourth embodiment. [Figure 16] FIG. 13 is a diagram for explaining an example of specific processing performed by a clock matching unit in the fifth embodiment. [Figure 17] FIG. 13 is a diagram illustrating an example of the configuration of a circuit switch according to a sixth embodiment. [Figure 18] FIG. 20 is a diagram illustrating the relationship between line connection information and packet configuration in the seventh embodiment. [Figure 19] FIG. 20 is a diagram for explaining the relationship between line connection information and packet configuration in the eighth embodiment. [Figure 20] FIG. 13 is a diagram illustrating an example of the configuration of a circuit switch according to an eighth embodiment. [Figure 21] FIG. 21 is a diagram for explaining an example of specific processing performed by the circuit switch shown in FIG. 20. [Figure 22] FIG. 1 is a diagram illustrating an example of a conventional exchange equipped with a time division switch. [Figure 23] 23 is a diagram for explaining the operating principle of the conventional time division switch shown in FIG. 22. FIG. DETAILED DESCRIPTION OF THE INVENTION

[0012] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. The following description and drawings are examples for explaining the present invention, and some omissions and simplifications have been made as appropriate for clarity of explanation. The present invention can be implemented in various other forms. Unless otherwise specified, each component may be singular or plural.

[0013] In order to facilitate understanding of the invention, the position, size, shape, range, etc. of each component shown in the drawings may not represent the actual position, size, shape, range, etc. Therefore, the present invention is not necessarily limited to the position, size, shape, range, etc. disclosed in the drawings.

[0014] In the following explanation, various types of information may be described using expressions such as "database," "table," and "list," but the various types of information may also be expressed in data structures other than these. To indicate that the information is not dependent on the data structure, "XX table," "XX list," etc. may be referred to as "XX information." When describing identification information, expressions such as "identification information," "identifier," "name," "ID," and "number" are used, and these are interchangeable.

[0015] When there are multiple components with the same or similar functions, they may be described using the same reference numeral with different subscripts. However, when there is no need to distinguish between these multiple components, the subscripts may be omitted.

[0016] Furthermore, in the following description, processing may be described as being performed by a circuit, but the processing is executed by a processor (e.g., a CPU (Central Processing Unit), a GPU (Graphics Processing Unit)), and the specified processing is performed using storage resources (e.g., memory) and / or interface devices (e.g., communication ports) as appropriate, so the subject of the processing may be the processor. Similarly, the subject of the processing performed by the circuit may be a controller, device, system, computer, or node having a processor. The subject of the processing performed by the circuit may be any arithmetic unit, and may include a dedicated circuit (e.g., an FPGA (Field-Programmable Gate Array) or an ASIC (Application Specific Integrated Circuit)) that performs specific processing.

[0017] Example 1 FIG. 1 is a diagram illustrating a configuration example of a circuit switch according to a first embodiment. As illustrated in FIG. 1, the circuit switch 100 includes an input-side interface unit 101 that receives a call signal from a terminal (not shown) at which a user makes a call and packetizes the received call signal; a packet switch unit 102 that routes the call signal packetized by the interface unit 101; an output-side interface unit 103 that outputs a call signal to a terminal (not shown) at which a user receives a call; a clock unit 104 that outputs a reference clock (e.g., 8 kHz) to these interface units; and a central processing unit 105 that includes a processing device such as a CPU and controls the entire circuit switch 100. The output-side interface unit 103 further includes a clock adjustment unit 1031 that adjusts and absorbs delays and fluctuations in asynchronous packets output from the packet switch unit 102. The following description will be given on the assumption that the input-side interface unit 101 and the output-side interface unit 103 are physically provided on different interface cards, but they may also be physically provided on a single interface card.

[0018] FIG. 2 is a diagram showing a more specific configuration of the circuit switch 100 shown in FIG. 1. As shown in FIG. 2, an input-side interface unit 101 packets voice data contained in a call signal from a terminal at which a user speaks, in predetermined units. The packetized packet data is assigned, as header information, an INF number and a channel number of the output destination interface unit 103. The interface unit 101 outputs the above-mentioned packet data to a packet switch unit 102. The packet switch unit 102 operates asynchronously without using a reference clock. The packet switch unit 102 may be any of various conventionally known packet switches.

[0019] The packet switch unit 102 routes the packet data based on the INF number of the interface unit 103 to which the packet data is to be output, which is added to the header information of the packet data.

[0020] The output-side interface unit 103 reads the channel number included in the header information of packet data asynchronously routed from the packet switch unit 102, and outputs the voice data included in the packet data to the clock alignment unit 1031. The clock alignment unit 1031 adjusts the output timing of the asynchronously received voice data based on the clock received from the clock unit 104. The clock alignment unit 1031 outputs the adjusted voice data to the channel with the specified channel number. In FIG. 2, the input-side interface unit 101 (INF-2) reads predetermined line connection information (described later) set in advance by the central processing unit 105, compares the header information of the packet data with the line connection information, and outputs the packet data to the slot with INF number "1" and channel number "3." At this time, the clock alignment unit 1031 adjusts the timing of the output. The specific operation of the clock alignment unit 1031 will be described later.

[0021] Fig. 3 is a diagram showing an example of line connection information for voice data processed by the circuit switch 100 shown in Fig. 1. The line connection information is information that defines the Ch numbers that are the connection destinations of the interface units, i.e., the input-side interface unit 101 and the output-side interface unit 103. By reading the line connection information, the lines between the terminals making a call are connected. The line connection information is set by the central processing unit 105 for each of the input-side interface unit 101 and the output-side interface unit 103.

[0022] As shown in Fig. 3, line connection information 301 associates input source information, which is the terminal on the calling side, with output destination information, which is the terminal on the receiving side. Fig. 3 illustrates an example of line connection information 301 set in input-side interface unit 101 (INF number "3"). In this example, the input INF number "3" and the Ch number (e.g., "1") of the own device, which are identification information of the own device, are associated with the output INF number (e.g., "1"), which is identification information of output-side interface unit 103 to which the own device is connected, and the Ch number (e.g., "2") to which the output-side interface unit 103 identified by the output INF number is connected.

[0023] Each of the input-side interface units 101 references such line connection information 301 and outputs packet data, which is obtained by packetizing the voice data in a predetermined unit (for example, 8 bits), to the packet switch unit 102 .

[0024] Fig. 4 is a diagram showing an example of packet data generated by interface unit 101. Packet data is data in which voice data included in a call signal from a terminal at which a user speaks is packetized in the above-mentioned predetermined unit. As shown in Fig. 4, packet data 401 is configured as data in which the above-mentioned output destination INF number and output destination Ch number are assigned to voice data, which is main information.

[0025] Fig. 5 is a sequence diagram for explaining an example of the operation of the circuit switch 100 in the first embodiment (individual voice data transfer). Although Fig. 5 illustrates an example of one channel number, the same process is performed for all channel numbers (for example, channel numbers "1" to "8") that each interface unit has.

[0026] 5, input-side interface unit 101 adds header information, packets the audio data at an 8 kHz reference clock period, and sequentially outputs the packetized packet data (e.g., 8-bit packet data) to packet switch unit 102. Packet switch unit 102 routes the packet data by referring to the header information included in the packet data received from interface unit 101, and outputs the packet data to output-side interface unit 103, which is the destination of the connection. At this time, packet switch unit 102 operates asynchronously, so delays and fluctuations 501 occur.

[0027] Therefore, the output-side interface unit 103 stores 502 the packet data received asynchronously from the packet switch unit 102 in a ring-type data buffer that can hold, for example, eight packets of packet data. The interface unit 103 reads 503 the stored packet data at an 8 kHz reference clock cycle with a certain time margin that is sufficient to absorb delays and fluctuations in the packet switch unit 102. In this example, the interface unit 103 reads 503 the data so as to allow an average delay 504 of four packets of data.

[0028] Fig. 6 is a diagram for explaining an example of specific processing performed in the clock alignment unit. Fig. 6 illustrates an example for one Ch number, but similar to Fig. 5, the same processing is performed for all Ch numbers possessed by each interface unit.

[0029] As shown in Fig. 6, in the input-side interface unit 101, a subscriber circuit (SLIC) 601 writes 6021 the voice data contained in the call signal to a data register (e.g., an 8-bit register) 602 using a reference clock (e.g., 8 kHz). At the timing when the voice data is buffered 6022 in the data register, a CPU 603 reads 6031 the written voice data. At this time, the CPU 603 reads line connection information 604, generates packet data by adding the above-mentioned header information to the voice data, and outputs the generated packet data to the packet switch unit 102. The packet switch unit 102 refers to the header information and asynchronously routes the packet data. The line connection information 604 is the same information as that shown in Fig. 3.

[0030] The CPU 605 of the output-side interface unit 103 writes packet data received asynchronously from the packet switch unit 102 to the data register 606 of the clock alignment unit 1031. The CPU 605 outputs a write request (REQ) to the buffer write circuit 607 to write the packet data written to the data register 606 to the data buffer 608. In accordance with the write request, the buffer write circuit 607 reads the packet data written to the data register 606 and writes it to the data buffer 608. When the writing is complete, the buffer write circuit 607 returns a response (CMP) to that effect to the CPU 605 and counts up the buffer number counter 609, which counts the number of packet data written to the data buffer 608. When the CPU 605 receives the response, it outputs a write request for the next packet data. The processing up to this point is the write-side processing of the clock alignment unit 1031.

[0031] Then, the SLIC transmission circuit 611, which outputs packet data to the transmitting subscriber circuit 612, reads the packet data written to the data buffer 608 at a reference clock (e.g., 8 kHz). At this time, the SLIC transmission circuit 611 manages the number of untransmitted buffers for the packet data (e.g., 8 packet data) written to the data buffer 608 by counting down the value counted by the buffer number counter 609 by the number of packet data read. The buffer operation monitoring circuit 610 monitors the value of the buffer number counter 609 after counting up and down.

[0032] The SLIC transmitter circuit 611 reads packet data written to the data buffer 608 so that the value always satisfies a margin value that takes into account fluctuations in delay and jitter. For example, if the predetermined time margin value, determined taking into account fluctuations in delay and jitter, is "4" packets of data, the SLIC transmitter circuit 611 repeatedly reads and counts down packet data so that the value of the buffer number counter 609 monitored by the buffer operation monitor circuit 610 is equal to or less than "4." If the value of the buffer number counter 609 exceeds the margin value, the buffer operation monitor circuit 610 resets the buffer number counter 609 and resets the data buffer 608 to a value greater than the margin value (e.g., "5"). This resetting may be performed if the value of the buffer number counter 609 is counted a predetermined number of times consecutively to the margin value. In this case, exceeding the margin value can be prevented, enabling more stable and continuous reading. By resetting in this manner, even if the number of packet data processed by the packet switch unit 102 changes over time or if there is a high possibility that this will happen, the above-mentioned margin value can be determined according to the change or the degree of the possibility. As a result, even if the number of unsent packets increases, the delay and fluctuation that accompanies this increase can be absorbed simply by setting the value without changing the circuit configuration.

[0033] The first embodiment has been described above. According to this embodiment, in a circuit switch 100 that switches a line between a first terminal (a terminal from which a user speaks) that is an input side terminal and a second terminal (a terminal at which a user receives a call) that is an output side terminal, a first interface unit (input side interface unit 101) that is an input side interface for connecting to the first terminal, the first interface unit packetizes voice data received from the first terminal in predetermined units (for example, 8-bit units) and outputs the packetized packet data, and the packet data output from the first interface unit is and a second interface unit (output interface unit 103) which is an output interface for connecting to the second terminal, the second interface unit having a clock alignment unit (clock alignment unit 1031) which writes the routed packet data to a data buffer (data buffer 608) and reads the written packet data at a read timing indicated by a time margin value (for example, a predetermined margin value "4") determined based on the delay and / or fluctuation of the packet switch unit.With this configuration, even when line connection is performed by a packet switch instead of a time division switch, a scalable communication environment can be realized at low cost without increasing the complexity or size of the device.

[0034] Example 2 In the first embodiment, a case has been described in which asynchronous packet data with delays and fluctuations output from the packet switch unit 102 is synchronized and output by the output-side interface unit 103. Normally, when a call is made between terminals, supervisory control information for controlling the call, such as line connection information (switch control), call instructions, incoming call notification, and dial information, is transmitted and received. Therefore, in the second embodiment, a case in which such supervisory control information is also communicated asynchronously via the packet switch unit 102 will be described.

[0035] Fig. 7 is a diagram showing an example of the configuration of a circuit switch according to the second embodiment. As shown in Fig. 7, a circuit switch 700 has an input interface unit 101, a packet switch unit 102, an output interface unit 103, and a clock unit 104 similar to those in the first embodiment, and also has a central processing unit 701 different from those in the first embodiment. In the following, the same components as those in the first embodiment are denoted by the same reference numerals, and their description will be omitted.

[0036] As shown below, the central processing unit 701 transfers the voice data and the supervisory control information via the same common packet switch unit 102. As explained in the first embodiment, a call is made by exchanging voice data between the input interface unit 101 and the output interface unit 103 via the packet switch unit 102. In the second embodiment, by connecting the central processing unit 701 and the packet switch unit 102, it becomes possible to transfer the supervisory control information using the same switch as that used to transfer the voice data.

[0037] Conventionally, as shown in Fig. 8, a supervisory control information transfer unit 802, which is a circuit for transferring supervisory control information, was provided in addition to a central processing unit 801 that transfers time-shared voice data via a time division switch, which resulted in a complicated and large-sized internal configuration of the circuit switching equipment. According to the configuration of this embodiment, the internal configuration of the circuit switching equipment can be simplified, and a compact circuit switching equipment can be realized.

[0038] Fig. 9 is a diagram for explaining an example of specific processing performed in the clock matching unit of the circuit switch shown in Fig. 7. In Fig. 9, in addition to the same processing as in the first embodiment, the CPU 603 of the input-side interface unit 101 further performs 901 reception of supervisory control information (e.g., line connection information) 604 from the central processing unit 801, packetizes the received supervisory control information 604 together with the audio data to which the above-mentioned header information has been added at a reference clock (e.g., 8 kHz), and outputs the packetized packet data to the packet switch unit 102.

[0039] The CPU 605 of the interface unit 103 on the output side writes the packet data, which is received asynchronously from the packet switch unit 102 and includes the audio data and the supervisory control information, into the data register 606 of the clock matching unit 1031. Thereafter, the same processing as in the first embodiment is performed.

[0040] As described above, the second embodiment has been described. According to this embodiment, the first interface unit packetizes the supervisory control information for controlling the call together with the voice data, and the clock matching unit of the second interface unit writes the packetized supervisory control information and voice data to the data buffer and reads them out at the read timing. With this configuration, even when line connection is made by a packet switch instead of a time division switch, the supervisory control information can be transferred together with the voice data.

[0041] Example 3 In the first and second embodiments, the control when a call is made via the packet switch unit 102 has been described. The configurations described in these embodiments have made it possible to provide a circuit switch that does not become complicated or large in size. In this embodiment, a configuration when combining the circuit switchers described in each embodiment will be described.

[0042] Fig. 10 is a diagram for explaining a method for adding a circuit switch. As shown in Fig. 10, in a packet switch-based circuit switch, one unit is configured as a basic unit 1001, and one or more circuit switches corresponding to the number of lines that exceeds the number of lines handled by the basic unit are configured as extension units 1002, and both are physically and electrically connected to form a single system.

[0043] The basic unit 1001 is equipped with the central processing unit 105, central processing unit 801, and clock unit 104 described in each embodiment, and the remaining slots are equipped with the input-side interface unit 101, packet switch unit 102, and output-side interface unit 103 (for example, five units). On the other hand, the extension unit 1002 is equipped with the input-side interface unit 101, packet switch unit 102, and output-side interface unit 103 (for example, ten units), as well as a connection interface with the basic unit 1001. As in each embodiment, each interface unit is equipped with channels identified by multiple Ch numbers (for example, eight channels). With this configuration, a call can be established (1003) between a terminal at the other end of the call and the call originating from a terminal (not shown) in a closed environment inside a circuit switch that receives a call signal from the terminal where the user made a call. The number of extension units 1002 may be determined according to the number of call terminals to be accommodated. For example, if one basic unit 1001 and ten extension units 1002 are installed, 840 channels of call terminals can be accommodated.

[0044] FIG. 11 is a diagram illustrating a method for expanding a circuit switch having a conventional time division switch. As shown in FIG. 10, in a conventional time division switch-based circuit switch, even when an expansion unit 1102 is added to a base unit 1101, voice data transfer 1103 is always required between the expansion unit 1102 and the base unit 1101 in order to perform time division control, such as allocating time slots to the expansion unit. Therefore, the base unit 1101 and the expansion unit 1102 had to be designed based on a configuration that assumed the maximum number of call terminals expected to be accommodated. In other words, a conventional circuit switch having a time division switch could not adopt a distributed configuration such as that shown in FIG. 10. Ideally, the cost of a circuit switch should be proportional to the number of call terminals accommodated. To achieve this, it is desirable for the switch section to be distributed to each unit.

[0045] As explained in this embodiment, the switch unit is a packet switch, and the circuit switch can be configured as a system connecting multiple circuit switches according to the number of the first terminal and the second terminal (by connecting the expansion unit 1002 to the base unit 1101). This allows for processing to connect the line only in one expansion unit when the line from the terminal where the user made a call to the terminal at the other end of the call is closed within one expansion unit. As a result, unlike conventional circuit switches using time-division switches, there is no need to design the base unit assuming the maximum number of call terminals. This significantly reduces costs compared to that case, and improves the economy and expandability of the distributed switch configuration. This can be considered similarly not only when increasing the number of call terminals, but also when decreasing the number of call terminals, in that an appropriate call environment can be created according to the reduced number of call terminals simply by removing the expansion unit.

[0046] In conventional circuit switching systems, the constraints imposed by the time-sharing control described above make it difficult to flexibly change the configuration in response to an increase or decrease in the number of call terminals. The configuration of this embodiment makes it possible to quickly create an appropriate call environment in response to an increase or decrease in the number of call terminals without incurring costs, and in the current environment where remote work is becoming more prevalent, it becomes possible to flexibly respond to such an increase or decrease in the number of call terminals.

[0047] Example 4 In the first embodiment, packet data packetized by the input interface unit 101 is sequentially output to the packet switch unit 102, and is read out by the output interface unit 103 while taking delays and fluctuations into consideration. In this embodiment, instead of sequentially outputting packet data by the input interface unit 101, the packet data is buffered on the interface unit 101 side to integrate the packet data, and then the integrated packet data is output to the packet switch unit 102. In other words, adjusting the transmission timing of the packet data before outputting it to the packet switch unit 102 improves the transfer efficiency of the packet data. Integrating packet data can also be said to be re-packetizing the packet data. Instead of the re-packetizing, the buffered voice data may be packetized in units of buffering, and output as integrated packet data.

[0048] FIG. 12 is a diagram illustrating a configuration example of a circuit switch according to the fourth embodiment. As illustrated in FIG. 12, the circuit switch 1200 differs from the circuit switch 100 according to the first embodiment in that, in addition to the circuit switch 100 according to the first embodiment, the input-side interface unit 101 includes a transmission timing adjustment unit 1201, and the output-side interface unit 103 includes a clock alignment unit 1202 different from that of the first embodiment. In the following, the same components as those of the first embodiment are denoted by the same reference numerals, and their description will be omitted. The transmission timing adjustment unit 1201 is a processing unit that adjusts the output timing of packet data packetized by the interface unit 101. The clock alignment unit 1202 is a processing unit that reads out the integrated packet data, the transmission timing of which has been adjusted, at a predetermined cycle and outputs it to the subscriber circuit. Specific operations of these units will be described later.

[0049] Fig. 13 is a diagram showing a more specific configuration of the circuit switch 1200 shown in Fig. 12. As shown in Fig. 13, the input-side interface unit 101, as in the first embodiment, packetizes voice data included in a call signal from a terminal at which a user speaks in a predetermined unit, and assigns the INF number and Ch number of the output-destination interface unit 103 to header information of the packet data. Furthermore, in the fourth embodiment, the transmission timing adjustment unit 1201 of the interface unit 101 buffers the packet data in a predetermined unit, and then integrates the buffered packet data into one packet data, and outputs the integrated packet data to the input-side interface unit 101 and the packet switch unit 102 at a predetermined timing determined for each of the input-side interface unit 101 and its channel.

[0050] As in the first embodiment, the packet switch unit 102 operates asynchronously without using a reference clock, and routes packet data based on the INF number of the output interface unit 103 that is assigned to the header information of the packet data that constitutes the integrated packet data.

[0051] The output interface unit 103 writes each piece of packet data that makes up the integrated packet data asynchronously routed from the packet switch unit 102 into a buffer memory configured with multiple addresses. The packet data written to each address is then read out at a predetermined interval (for example, 8 bits at a time at 8 kHz), thereby absorbing delays and fluctuations in the packet switch unit 102.

[0052] Fig. 14 is a sequence diagram for explaining an example of the operation of the circuit switch 1200 in the fourth embodiment (voice data integrated transfer). In Fig. 14, as in the first embodiment, one Ch number is illustrated as an example, but the same process is performed for all Ch numbers that each interface unit has.

[0053] 14, the input-side interface unit 101 packetizes audio data at an 8 kHz frequency, which is a reference clock, buffers the packetized packet data (e.g., 8 bits), and integrates 1401 the buffered packet data. In this example, to improve transfer efficiency by integrating packet data, 1 msec (e.g., 8 frames) is buffered as one group in a predetermined buffer memory or the like to form integrated packet data. In this way, the input-side interface unit 101 integrates the packet data buffered in predetermined units, thereby reducing the total number of packet data handled by the packet switch unit 102.

[0054] 14, as an example, 80 bytes including header information are buffered, and the buffered packet data is output as integrated packet data to the packet switch unit 102. The transmission timing adjustment unit 1201 of the interface unit 101 adjusts the transmission timing of the buffered integrated packet data so that it is distributed among the interface units 101 and their channels, and outputs the adjusted timing, thereby preventing packet congestion that may occur in the packet switch unit 102. The adjustment of the transmission timing will be described later.

[0055] The packet switch unit 102 refers to the header information of the packet data constituting the integrated packet data received from the interface unit 101, routes the integrated packet data, and outputs it to the destination interface unit 103 on the output side. At this time, since the packet switch unit 102 operates asynchronously, delays and fluctuations occur, as in the first embodiment.

[0056] Therefore, in this embodiment, the output-side interface unit 103 is configured with a buffer memory with multiple addresses (four buffer memory surfaces in this example) to absorb delays and fluctuations in the integrated packet data received asynchronously from the packet switch unit 102, and writes 1403 integrated packet data with different transmission timings 1402 into each buffer memory surface. Thereafter, the interface unit 103 reads 1404 the written integrated packet data at an 8 kHz reference clock period with a certain time margin (the same predetermined margin value as in the first embodiment) that is sufficient to absorb delays and fluctuations in the packet switch unit 102. By reading in this manner, the packet data constituting the integrated packet data output at different transmission timings is read in each channel with the delays and fluctuations in the packet data absorbed while preventing packet congestion.

[0057] Various parameters such as the buffering unit of the input-side interface unit 101, the transmission timing of the transmission timing adjustment unit 1201, the number of buffer memories with multiple addresses, and the read timing of the output-side interface unit 103 are determined by the scale of the system handled by the circuit switching equipment and the performance of the packet switch. The larger these parameters are compared to the threshold value for satisfying the required requirements, the more time leeway there is and the more secure it is, but since they affect the circuit scale and data delay time of each interface unit, it is desirable to set them to appropriate values.

[0058] Fig. 15 is a diagram for explaining an example of specific processing performed in the clock alignment unit in Example 4. Fig. 15 illustrates one Ch number as in Fig. 14, but similar processing is performed for all Ch numbers possessed by each interface unit.

[0059] As shown in FIG. 15, in the input-side interface unit 101, a subscriber circuit (SLIC) 1501 writes a speech signal to a data register (e.g., an 8-bit register) 1502 at a reference clock (e.g., 8 kHz). A CPU 1503 performs data integration processing 1505, which aggregates the voice data contained in the speech signal written to the data register 1502 at a 1 kHz cycle and aggregates the 8N bits accumulated at an 8 kHz cycle into aggregated packet data. The CPU 1503 then adjusts the transmission timing of the aggregated packet data that has undergone the data integration processing. The transmission timing adjustment means, for example, that each channel transmits packets at its assigned timing among eight data transmission timings, the number of which corresponds to the number of channel numbers. For example, the CPU 1503 performs processing such as modulo-8 INF number (assigning the remainders 0 to 7 when divided by 8 to timings 1 to 8). The CPU 1503 reads line connection information 1504, which is the same as line connection information 604, and the various parameters received from the central processing unit 1506, and after adjusting the transmission timing, packetizes the integrated packet data at a reference clock (e.g., 8 kHz), and outputs the packet to the packet switch unit 102. The packet switch unit 102 asynchronously routes the integrated packet data with reference to the line connection information 1504.

[0060] The CPU 1507 of the output interface unit 103 writes the integrated packet data received asynchronously from the packet switch unit 102 to the data register 1508 of the clock alignment unit 1202. At this time, the CPU 1507 writes the integrated packet data for each channel number. In this example, the integrated packet data (e.g., 80 bytes including a header) for each of channels "1" to "8" is written to an address in the data register 1508 corresponding to each channel. Furthermore, the clock alignment unit 1202 writes the integrated packet data for each channel with different transmission timings written to the data register 1508 to each of the multiple-address buffer memories 1510 (a four-sided buffer memory in this example). Although a four-sided buffer memory is shown as an example in this example, an eight-sided buffer memory may also be used if the internal structure allows.

[0061] Furthermore, the buffer memory read circuit 1511 reads out the packet data that make up the written integrated packet data at a reference clock period of 8 kHz with a certain time margin that is sufficient to absorb delays and fluctuations in the packet switch unit 102, and the SLIC transmission circuit 1512 outputs the read integrated packet data to the subscriber circuit 1513. In this example, 8N-bit integrated packet data is read out at a period of 1 kHz, and then read out 8 bits at a time at 8 kHz and output to the subscriber circuit.

[0062] The unit (N) for buffering the integrated packet data into one group and the number of buffer memory surfaces (M) are set 1514 by the central processing unit as packet integration parameters 1509. As with the various parameters mentioned above, these values ​​are determined by the scale of the system handled by the circuit switch and the performance of the packet switch.

[0063] The fourth embodiment has been described above. According to this embodiment, the first interface buffers the packet data in predetermined units (one group of 1 msec (e.g., 8 frames)), and outputs the integrated packet data obtained by integrating the buffered packet data to the packet switch unit at predetermined transmission timings (the assigned timings 1 to 8) determined according to the channel. The packet switch unit routes the integrated packet data output from the first interface. The clock alignment unit (clock alignment unit 1202) of the second interface writes the integrated packet data written in a data register (data register 1508) for each channel to a buffer memory (buffer memory 1510) having multiple addresses, and reads out the integrated packet data of the channel written to each of the multiple addresses at the readout timings. This configuration can prevent packet congestion and improve packet data transfer efficiency.

[0064] Example 5 In the first embodiment, the explanation is given on the assumption that all of the voice data included in the call signal input to the input interface unit 101 contains voice (not silence). However, if the line input to the channel is not set up, packet data or integrated packet data is not generated, and this packet data does not arrive at the output interface unit 103. As a result, the call terminal connected to the output interface unit 103 does not output any signal, and it is not possible to determine whether or not a call with the other party is possible. Below, a description is given of processing when there is a channel for which a line is not set up.

[0065] Fig. 16 is a diagram for explaining an example of specific processing performed in the clock alignment unit in the fifth embodiment. Fig. 16 illustrates one Ch number, but similar processing is performed for all Ch numbers of each interface unit, as in the other embodiments. Furthermore, since the input-side interface unit 101 performs the same processing as in the previous embodiments, the following will explain the output-side interface unit 103, and the same components as in the first embodiment will be assigned the same reference numerals and their explanations will be omitted.

[0066] 16, the line unassigned monitoring circuit 1601 of the output-side interface unit 103 monitors the value of the buffer number counter 609, similar to the buffer operation monitoring circuit 610. For example, the line unassigned monitoring circuit 1601 monitors whether or not it has detected that the value of the buffer number counter 609 is "0" (that is, it has detected that there is no data to be read, and the value of the buffer number counter 609 is zero without counting up or down for a certain period of time). If it detects that the value of the buffer number counter 609 is "0", the silence pattern inserter 1602 determines that there is no packet data in the data buffer 608 and that there is silence, and outputs a value indicating that the channel is silent (for example, all bits are "1") to the subscriber circuit 612 as silence packet data.

[0067] As described above, the fifth embodiment has been described. According to this embodiment, the second interface unit has a silence pattern inserting unit (silence pattern inserting unit 1602) that outputs a value indicating silence as silence packet data (for example, all bits are "1") when the packet data does not exist in the data buffer. With this configuration, it is possible to determine whether a call terminal connected to a channel for which a line is not set can communicate with the other party.

[0068] Example 6 In the above embodiments, the case where voice data included in a call signal is processed has been described, but there are also cases where a circuit switch needs to exchange various data other than voice data. Therefore, a case where the circuit switch is equipped with an interface unit conforming to the Ethernet standard will be described. In the following, the same reference numerals as in the first embodiment are used and their description will be omitted.

[0069] Fig. 17 is a diagram showing an example of the configuration of a circuit switch according to the sixth embodiment. As shown in Fig. 17, the circuit switch 1700 has, as each interface unit, an input-side interface unit 101 and an output-side interface unit 103 similar to those in the first embodiment, as well as an input-side Ethernet interface unit 1701 and an output-side Ethernet interface unit 1702 for performing data communication. These Ethernet interfaces may use various conventionally known Ethernet-compatible interface cards. The Ethernet interfaces 1701 and 1702 do not use a reference clock, and therefore, like the packet switch unit 102, are not connected to the clock unit 104.

[0070] As described above, the sixth embodiment has been described. According to this embodiment, the circuit switch is provided with a plurality of the first interface units and the second interface units, and some of the first interface units and the second interface units are configured as interface units conforming to the Ethernet standard. With this configuration, in addition to the voice interface, an Ethernet interface can be compatible mounted in the slots of each interface unit, thereby enabling mixed accommodation of voice and data while keeping the packet switch unit common.

[0071] Example 7 In the above embodiments, the voice data included in the call signal input to the input interface unit is output from a different output interface unit, but there are cases where the voice data is output to the same interface unit among the output interface units. Below, a case where the voice data input from the input interface unit is output to the same output interface unit will be described.

[0072] Fig. 18 is a diagram for explaining the relationship between line connection information and packet configuration in the seventh embodiment. Fig. 18 illustrates an example of line connection information 301 set in one input interface unit 101 (INF number "3"), but the same can be applied to other interface units.

[0073] 18, in the line connection information of the input-side interface unit 101 with INF number "3," as in the first embodiment, the input INF number "3" as identification information of the own device and the channel number (e.g., "1") of the own device are associated with the output INF number (e.g., "1") as identification information of the output-side interface unit 103 to which the own device is connected, and the channel number (e.g., "2") to which the output-side interface unit 103 identified by the output INF number is connected. In the output-side interface unit 103, the interface unit 103 with INF number "5" occupies three lines, and the interface unit 103 with INF number "7" occupies two lines, among the settings of the output-side interface unit 103. Therefore, the input-side interface unit 101 combines packet data to be transmitted to these two output-side interface units 103 into one packet data and outputs the combined packet data to the packet switch unit 102.

[0074] 18, for example, the input interface unit 101 with INF number "3" generates channel integrated packet data 1801 by integrating packet data to be transmitted to each channel of the output interface unit 103 with INF number "5." The integration method can be realized by the method described in the fourth embodiment, but the differences will be described below.

[0075] In channel-integrated packet data 1801, in addition to the configuration of embodiment 1 (FIG. 4, items of audio data, output destination INF number, and output destination Ch number), a "number of transmission Ch" item, which is the number of channels of output side interface unit 103, is added to the packet configuration. For example, in packet data 1803 output to INF number "1" of output side interface unit 103, a "number of transmission Ch" item 1811 (in this case, Ch number "1") is added to the audio data in addition to the output destination INF number and output destination Ch number.

[0076] On the other hand, in packet data 1801 output to INF number "3" of output-side interface unit 103, in addition to the output destination INF number and output destination Ch number, a "number of transmission Ch" item 1811 (in this case, the number of Ch "3") is added for the audio data. This is because the packet data output from the channels identified by Ch numbers "3," "4," and "5" of input-side interface unit 101 with INF number "3" are all set as INF number "5" of output-side interface unit 103. In packet data 1802 output to INF number "7" of output-side interface unit 103, in addition to the output destination INF number and output destination Ch number, a "number of transmission Ch" item 1811 (in this case, the number of Ch "2") is added for the audio data.

[0077] In this way, when multiple identical INF numbers are set as output destinations, the input-side interface unit 101 in this embodiment generates channel-aggregated packet data that aggregates them into a single packet. The "number of transmission channels" included in the channel-aggregated packet data indicates how many channels are aggregated. That is, if no channels are aggregated, the "number of transmission channels" is set to "1," and if N channels are aggregated, the "number of transmission channels" is set to "N." The channel-aggregated packet data is configured in such a way that N pairs of "output destination channel number + audio data" are lined up following the "number of transmission channels" item.

[0078] As described above, the seventh embodiment has been described. According to this embodiment, when the first interface unit includes the same interface unit as the interface unit to which the line to be switched is connected, the first interface unit generates channel-aggregated packet data that aggregates the packet data to be output to the same interface unit. This configuration can further reduce the number of packet data items processed by the packet switch unit 102. In the example of FIG. 18, if channel-aggregated packet data is not generated, the number of packet data items output to the output interface unit 103 is "8." However, if channel-aggregated packet data is generated as in this embodiment, this number is reduced to "5." This reduces the number of packets processed by the packet switch unit 102, thereby avoiding packet congestion and preventing a decrease in communication speed, poor connection, packet loss, etc.

[0079] Example 8 In the embodiments described so far, it has been assumed that packet data output from the input interface unit 101 is transmitted to the output interface unit 103, but there are also cases where packet data is output to a channel of the same input interface unit 101. Below, a case where a line is connected between different channels of the same interface unit will be described.

[0080] Fig. 19 is a diagram for explaining the relationship between line connection information and packet configuration in Example 8. As shown in Fig. 19, in the line connection information of the input-side interface unit 101 with INF number "3," as in Example 1, the input INF number "3" and the Ch number (for example, "1") of the own device, which are identification information of the own device, the output INF number (for example, "1"), which is identification information of the output-side interface unit 103 to which the own device is connected, and the Ch number (for example, "2") to which the output-side interface unit 103 identified by the output INF number are connected are associated.

[0081] In the setting of the output-side interface unit 103, an INF number "3," i.e., channels with Ch numbers "3" and "4" of the input-side interface unit 101, are set. In this example, the voice data included in the speech signal input to Ch numbers "3" and "4" of the input-side interface unit 101 is output, i.e., transferred, to Ch numbers "4" and "3" of the input-side interface unit 101, respectively. For example, as described in FIG. 6, the input-side interface unit 101 writes 6021 the voice data included in the speech signal to a data register (e.g., an 8-bit register) 602. Thereafter, at the timing when the voice data is buffered 6022 in the data register, the CPU 603 reads 6031 the written voice data and transfers it to the same input-side interface unit 101 without packetizing it, with reference to the line connection information shown in FIG. 19.

[0082] In this way, when the line connection information in a certain input interface unit 101 (for example, INF number "3") results in a connection between different channels within the input interface unit 101 with the same INF number, the interface unit 101 enables the connection within the input interface unit without generating packet data. This makes it possible to reduce the number of packets input to the packet switch unit 102 and the amount of data communicated between the input interface unit and the packet switch unit, thereby avoiding packet congestion and preventing a decrease in communication speed, connection failures, packet loss, etc.

[0083] 20 is a diagram illustrating an example of the configuration of a circuit switch according to an eighth embodiment. As illustrated in FIG. 1, the circuit switch 100 includes an input-side interface unit 101 that receives a call signal from a terminal at which a user (not shown) speaks and packetizes the received call signal, a packet switch unit 102 that routes the call signal packetized by the interface unit 101, an output-side interface unit 103 that outputs the call signal to a terminal at which a user (not shown) speaks, a clock unit 104 that outputs a reference clock (e.g., 8 kHz) to the interfaces 101 and 103, and a central processing unit 105 that includes a processing device such as a CPU and controls the entire circuit switch 100. The interface unit 103 further includes a clock adjustment unit 1031 that adjusts and absorbs delays and fluctuations in asynchronous packets output from the packet switch unit 102.

[0084] In Figure 20, it can be seen that the voice data contained in the call signal input to a channel of INF2 of the input side interface unit 101 of the circuit switch 2000 is output 2001 to a channel of the output side interface unit 103 (i.e., the input side interface unit 101) of the circuit switch 2000 itself, without going through the packet switch unit 102.

[0085] Fig. 21 is a diagram for explaining an example of specific processing performed in the circuit switch shown in Fig. 20. In Fig. 20, as in the first embodiment, in the input-side interface unit 101, a subscriber circuit (SLIC) 601 writes 6021 voice data included in a call signal to a data register (e.g., an 8-bit register) 602 at a reference clock (e.g., 8 kHz), and a CPU 603 reads 6031 the written voice data at the timing when the voice data is buffered 6022 in the data register. Then, the CPU 603 reads line connection information 604 and determines whether the INF number of the input-side interface unit and the INF number of the output-side interface unit are the same. If the CPU 603 determines that the INF numbers are the same, the CPU 603 outputs 2101 the voice data read 6031 to the CPU 605 for the interface unit with the INF number without performing the packetization described above.

[0086] The CPU 605 of the output-side interface unit 103 writes the audio data received from the input-side interface unit 101 into the data register 606 of the clock matching unit 1031. Thereafter, the CPU 605 outputs the audio data written into the data register 606 directly to the subscriber circuit 612.

[0087] As described above, the eighth embodiment has been described. According to this embodiment, when the interface unit to which the line to be exchanged is connected is the first interface unit, the first interface unit transfers the voice data to the first interface unit without packetizing the data. With this configuration, lines can be connected between different channels of the same interface unit, and as in the seventh embodiment, the number of packets processed by the packet switch unit 102 can be reduced to avoid packet congestion, thereby preventing a decrease in communication speed, connection failures, packet loss, etc.

[0088] Each embodiment has been described above. The packet switch unit of the circuit switch in each embodiment can be, for example, an L2 switch or a PCI Express switch. By applying the packet switch unit in each embodiment to these switches, a scalable call environment can be realized at low cost in switches of various specifications without increasing the complexity or size of the equipment. The present invention is not limited to the various examples described above, and various modifications are possible by combining part or all of the configurations in each embodiment without departing from the spirit of the present invention. [Explanation of symbols]

[0089] 100, 700, 800, 1200, 2000 circuit switching machines 101 Input side interface section 102 Packet switch section 103 Output interface section 104 Clock section 105, 701, 801 Central Processing Unit 802 Supervisory Control Information Transfer Unit 1031 Clock matching unit 301, 604, 1504 line connection information 401 Packet Data 1001 Basic Unit 1002 Expansion Unit 1201 Transmission timing adjustment unit 1509 Packet Integration Parameters 1701, 1702 Ethernet interface section

Claims

1. A circuit exchange that exchanges a line between a first terminal that is an input terminal and a second terminal that is an output terminal, a first interface unit that is an input interface for connecting to the first terminal, the first interface unit packetizing voice data received from the first terminal in predetermined units and outputting the packetized packet data; a packet switch unit that routes the packet data output from the first interface unit; a second interface unit that is an output side interface for connecting to the second terminal, the second interface unit having a clock alignment unit that writes the routed packet data into a data buffer and reads the written packet data at a read timing indicated by a time margin value determined based on delay and / or fluctuation of the packet switch unit; A circuit switching system comprising:

2. the first interface unit packetizes supervisory control information for controlling the call together with the voice data; the clock alignment unit of the second interface unit writes the packetized supervisory control information and the audio data to the data buffer and reads them out at the read timing; 2. The circuit switching system according to claim 1.

3. the circuit exchange can be configured as a system in which a plurality of the circuit exchanges are connected in accordance with the number of the first terminals and the second terminals; 2. The circuit switching system according to claim 1.

4. the first interface unit buffers the packet data in a predetermined unit, and outputs integrated packet data obtained by integrating the buffered packet data to the packet switch unit at a predetermined transmission timing determined according to a channel; the packet switch unit routes the integrated packet data output from the first interface unit, the clock alignment unit of the second interface unit writes the integrated packet data written in the data register for each channel to a buffer memory having a plurality of addresses, and reads out the integrated packet data of the channel written in each of the plurality of addresses at the read timing; 2. The circuit switching system according to claim 1.

5. The packet switch unit is configured by an L2 switch.

2. The circuit switching system according to claim 1.

6. The packet switch unit is configured by a PCI Express switch.

2. The circuit switching system according to claim 1.

7. the second interface unit has a silence pattern inserter that outputs a value indicating silence as silence packet data when the packet data does not exist in the data buffer.

2. The circuit switching system according to claim 1.

8. a plurality of the first interface units and a plurality of the second interface units are provided in the circuit switch; a part of the first interface unit and the second interface unit is configured as an interface unit conforming to the Ethernet standard; 2. The circuit switching system according to claim 1.

9. When the first interface unit includes the same interface unit as the interface unit to which the line to be exchanged is connected, the first interface unit generates channel-aggregated packet data by aggregating the packet data to be output to the same interface unit.

2. The circuit switching system according to claim 1.

10. the first interface unit transfers the voice data to the first interface unit without packetizing the voice data when the first interface unit is the interface unit to which the line to be exchanged is connected; 2. The circuit switching system according to claim 1.

11. A circuit switching method performed in a circuit switch that switches a line between a first terminal that is an input terminal and a second terminal that is an output terminal, comprising: a first interface unit serving as an input interface for connecting to the first terminal, packetizing the voice data received from the first terminal in predetermined units; The first interface unit outputs the packetized packet data; a packet switch unit that routes the packet data output from the first interface unit; writing the routed packet data into a data buffer in a second interface unit that is an output interface for connecting to the second terminal; a clock matching unit of the second interface unit reading out the written packet data at a read timing indicated by a time margin value determined based on the delay and / or fluctuation of the packet switch unit; A circuit switching method comprising:

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