Image sensor and operation method for the same

Abstract

To provide an image sensor that minimizes the delay of a clock supply by reducing the electric power, and an operation method for the same.SOLUTION: An image sensor includes a plurality of clock consumers (CCs), a plurality of block clock management units (BCMUs), and a top clock management unit (TCMU). Each BCMU transmits a second clock demand signal to TCMU in response to a first clock demand signal received from at least one CC among the CCs. TCMU transmits each clock response signal in accordance with each second clock demand signal. TCMU transmits a second clock signal to each BCMU through a channel formed in transmission and reception of the second clock demand signal and the clock response signal. While the second clock signal is transmitted through the channel, each BCMU transmits the first clock signal corresponding to the first clock demand signal to the CC to which the first clock demand signal has been transmitted among the CCs, on the basis of the second clock signal.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to image processing, and more particularly to an image sensor that provides the clocks required for image processing via a clock management unit, and a method of operating the same. [Background technology]

[0002] In recent years, as the performance of image sensors has improved, image sensors are widely used in a variety of home appliances in addition to portable devices such as smartphones and digital cameras. In the field of mobile devices, where power consumption must be reduced as much as possible, active research is being conducted into reducing the power consumption of image sensors.

[0003] The image data provided from the image sensor is organized in units of frames, and there is a signal indicating the start of a frame. It can also be ensured that no image data is input during the period from when the last image data of the current frame is processed until when the first image data of the next frame is processed.

[0004] Taking advantage of the characteristics of such image sensors, it is necessary to control the clock in a manner suitable for the image sensor while reducing power consumption, which is a challenge. Summary of the Invention [Problem to be solved by the invention]

[0005] The present invention has been made in consideration of the above-mentioned problems with conventional image sensors, and an object of the present invention is to provide an image sensor and an operating method thereof that reduce power consumption and minimize delay in clock supply when supplying a clock to the image sensor. [Means for solving the problem]

[0006] In order to achieve the above object, an image sensor according to the present invention includes a pixel array including a plurality of sensing pixels, a readout circuit that converts an electrical signal received from the pixel array into image data, and an image signal processor that processes the image data output from the readout circuit, wherein the image signal processor includes: a clock consumer that generates a first clock request signal and receives a first clock signal corresponding to the first clock request signal; a block clock management unit that receives the first clock request signal from the clock consumer, generates a second clock request signal corresponding to the first clock request signal, and receives a clock response signal and a second clock signal corresponding to the second clock request signal; and a top clock management unit that receives the second clock request signal from the block clock management unit, generates the clock response signal and the second clock signal corresponding to the second clock request signal, and transmits the clock response signal and the second clock signal to the block clock management unit, wherein the block clock management unit generates the first clock signal corresponding to the first clock request signal based on the second clock signal, and transmits the first clock signal to the clock consumer.

[0007] An image sensor according to an embodiment of the present invention includes a plurality of clock consumers, each of which generates a first clock request signal and receives a first clock signal corresponding to the first clock request signal; a block clock management unit that receives the first clock request signal from each of the plurality of clock consumers, generates a second clock request signal corresponding to the first clock request signal, and receives a clock response signal and a second clock signal corresponding to the second clock request signal; and a block clock management unit that receives the second clock request signal from the block clock management unit, generates the clock response signal and the second clock signal corresponding to the second clock request signal, and receives the clock response signal and a previous clock signal. and a top clock management unit that transmits the second clock signal to the block clock management units, wherein the block clock management units generate the first clock signal corresponding to the first clock request signal based on the second clock signal and transmit the first clock signal to each of the plurality of clock consumers, and the block clock management units can generate the second clock request signal when they receive the first clock request signal from one of the plurality of clock consumers, and can stop generating the second clock request signal when all of the plurality of clock consumers stop transmitting the first clock request signal.

[0008] In order to achieve the above object, an operating method of an image sensor according to the present invention is a method for operating an image sensor including a clock consumer, a block clock management unit, and a top clock management unit, the method comprising: generating a first clock request signal by the clock consumer; transmitting the first clock request signal to the block clock management unit by the clock consumer; generating a second clock request signal corresponding to the first clock request signal by the block clock management unit and transmitting the second clock request signal to the top clock management unit; generating a clock response signal and a second clock signal corresponding to the second clock request signal by the top clock management unit and transmitting the clock response signal and the second clock signal to the block clock management unit; transmitting a first clock signal corresponding to the first clock request signal to the clock consumer based on the second clock signal by the block clock management unit; and, if transmission of the first clock request signal by the clock consumer is interrupted, interrupting transmission of the first clock signal to the clock consumer by the block clock management unit. [Effects of the Invention]

[0009] According to the image sensor and the operating method thereof of the present invention, a clock can be supplied to each of a plurality of clock consumers included in the image sensor only during a period when image processing is required, thereby reducing power consumption due to unnecessary clock supply. Furthermore, since the delay in clock supply can be minimized for a plurality of clock consumers included in the image sensor, clock control suitable for the image sensor can be performed. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a block diagram showing a schematic configuration of an image sensor according to an embodiment of the present invention. [Figure 2] 1 is a block diagram showing a schematic configuration of an image signal processor according to an embodiment of the present invention; [Figure 3] 1 is a block diagram showing a schematic configuration of an image signal processor according to an embodiment of the present invention; [Figure 4] 2 is a block diagram illustrating the operation of a block of an image signal processor according to an embodiment of the present invention; [Figure 5A] 3 is a timing diagram of transmitted and received signals in the operation of a block of an image signal processor according to an embodiment of the present invention. [Figure 5B] 3 is a timing diagram of transmitted and received signals in the operation of a block of an image signal processor according to an embodiment of the present invention. [Figure 6] 2 is a block diagram illustrating the operation of a block of an image signal processor according to an embodiment of the present invention; [Figure 7A] 3 is a timing diagram of signals in the operation of a block of an image signal processor according to an embodiment of the present invention; [Figure 7B] 3 is a timing diagram of signals in the operation of a block of an image signal processor according to an embodiment of the present invention; [Figure 8] 2 is a block diagram illustrating the operation of a block of an image signal processor according to an embodiment of the present invention; [Figure 9] 3 is a timing diagram of signals in the operation of a block of an image signal processor according to an embodiment of the present invention; [Figure 10] 3 is a timing diagram of signals in the operation of a block of an image signal processor according to an embodiment of the present invention; [Figure 11] 2 is a block diagram illustrating the operation of a block of an image signal processor according to an embodiment of the present invention; [Figure 12] 3 is a timing diagram of signals in the operation of a block of an image signal processor according to an embodiment of the present invention; [Figure 13] 1 is a flowchart illustrating an operation method of an image sensor according to an embodiment of the present invention. [Figure 14] 1 is a block diagram showing a schematic configuration of an image processing device according to an embodiment of the present invention; DETAILED DESCRIPTION OF THE INVENTION

[0011] Next, specific examples of embodiments for carrying out an image sensor and an operating method thereof according to the present invention will be described with reference to the drawings.

[0012] FIG. 1 is a block diagram showing a schematic configuration of an image sensor according to an embodiment of the present invention. The image sensor 100 converts an optical signal of an object incident through an optical lens LS into image data. The image sensor 100 can be installed in electronic devices that have image or light sensing capabilities.

[0013] For example, the image sensor 100 can be installed in electronic devices such as digital still cameras, digital video cameras, smartphones, wearable devices, Internet of Things (IoT), tablet PCs (Personal Computers), PDAs (Personal Digital Assistants), PMPs (Portable Multimedia Players), and navigation devices. The image sensor 100 can also be mounted on electronic devices that are provided as components in vehicles, furniture, manufacturing equipment, doors, various measuring instruments, and the like.

[0014] Referring to FIG. 1, an image sensor 100 includes a pixel array 1100, a readout circuit 1200, a control logic circuit 1300, an image signal processor 1400, and an output circuit 1500. The pixel array 1100 may be implemented as a photoelectric conversion element such as a charge coupled device (CCD) or a complementary metal oxide semiconductor (CMOS), or may be implemented as various other types of photoelectric conversion elements. The pixel array 1100 includes a plurality of sensing pixels PX that convert received optical signals (light) into electrical signals, and the plurality of sensing pixels PX are arranged in a matrix. Each of the plurality of sensing pixels PX includes a light-sensing element. For example, the light-sensing element may include a photodiode, an organic photodiode, a phototransistor, a photogate, or a pinned photodiode.

[0015] Readout circuitry 1200 receives electrical signals from pixel array 1100 and converts the received electrical signals into image data. The readout circuit 1200 amplifies the electrical signal and performs analog-to-digital conversion of the amplified electrical signal. The image data generated by the readout circuit 1200 includes a plurality of pixels corresponding to the plurality of sensing pixels PX of the pixel array 1100 . Here, the sensing pixels PX of the pixel array 1100 are also physical structures that generate signals according to received light, and the pixels included in the image data represent data corresponding to the sensing pixels PX. The readout circuit 1200 together with the pixel array 1100 form the sensing core.

[0016] The control logic circuit 1300 controls the overall operation of the image sensor 100 . In the exemplary embodiment, the control logic circuit 1300 controls the readout circuit 1200, the image signal processor 1400, and the output circuit 1500 to generate the image data IDT. The image signal processor 1400 may perform image processing on the image data output from the readout circuit 1200. For example, the image signal processor 1400 may perform image processing such as bad pixel correction, remosaic, and noise removal on the image data.

[0017] The output circuit 1500 communicates with an external processor based on one of a variety of high-speed interface schemes. For example, the output circuit 1500 communicates with an external processor based on the MIPI (Mobile Industry Processor Interface) standard. The output circuit 1500 converts the image data output from the image signal processor 1400 into image data IDT having a data format according to a set interface method, and transmits the image data IDT to an external processor. The external processor may include a main processor, an application processor, a graphics processor, or the like of the electronic device in which the image sensor 100 is installed.

[0018] The control logic circuit 1300, the image signal processor 1400, and the output circuit 1500 are implemented as digital circuits, and a clock signal is provided to each of the digital circuits. When each digital circuit transmits a clock request signal to the clock management unit, the clock management unit provides each digital circuit with a clock signal corresponding to the clock request signal. This allows the digital circuits to be independently provided with clock signals only when necessary for operation, thereby reducing unnecessary power consumption.

[0019] FIG. 2 is a block diagram showing a schematic configuration of an image signal processor according to an embodiment of the present invention. Referring to FIG. 2, the image signal processor 1400 includes a number of intellectual property (IP) blocks 1410 . In FIG. 2, the multiple IP blocks 1410 are shown as including first to third IP blocks (1411, 1412, 1413), but are not limited to this, and the multiple IP blocks 1410 may include two or more IP blocks.

[0020] Each of the multiple IP blocks 1410, that is, the first to third IP blocks (1411, 1412, 1413), executes image processing set as a functional block for image processing, and the first to third IP blocks (1411, 1412, 1413) execute different image processing from each other. In the exemplary embodiment, the first IP block (12-1) corrects bad pixels in the image data, the second IP block (12-2) performs remosaic, and the third IP block (12-3) removes noise. The first to third IP blocks (1411, 1412, 1413) perform image processing on the image frames sequentially, but are not limited to this. The IP blocks 1410 require a clock signal to perform image processing. Each of the multiple IP blocks 1410 is also referred to as a clock consumer. Although the above description has been given using the multiple IP blocks 1410 included in the image signal processor 1400 as an example, multiple IP blocks included in digital circuits such as the control logic circuit 1300 and the output circuit 1500 can also be clock consumers.

[0021] FIG. 3 is a block diagram showing a schematic configuration of an image signal processor according to an embodiment of the present invention. FIG. 3 shows the clock architecture of the image signal processor 1400. Referring to FIG. 3, the image signal processor 1400 includes a Top clock management unit (TopCMU) 110, a plurality of blocks 120, and analog control logic 140.

[0022] The clock consumers included in each of the multiple blocks 120 in FIG. 3 correspond to the multiple IP blocks 1410 in FIG. 2, and the clock signal management below corresponds to the clock signal management provided to the multiple IP blocks 1410 in FIG. 2. One top clock management unit 110 provides n clock signals (CLK1 to CLKn) to n blocks (BLK1 to BLKn) via n channels (CH1 to CHn), where n is 1 or greater. The n channels (CH1 to CHn) are formed through transmission and reception of n clock request signals (REQ1 to REQn) and n clock response signals (ACK1 to ACKn) corresponding to each other. N clock request signals (REQ1 to REQn) are transmitted from n blocks (BLK1 to BLKn) to the top clock management unit 110, and n clock response signals (ACK1 to ACKn) are transmitted from the top clock management unit 110 to the n blocks (BLK1 to BLKn). The top clock management unit 110 simultaneously provides n clock response signals (ACK1 to ACKn) and n clock signals (CLK1 to CLKn) to n blocks (BLK1 to BLKn).

[0023] The time when the top clock management unit 110 starts or stops providing n clock signals (CLK1 to CLKn) to n blocks (BLK1 to BLKn) is the time when it starts or stops receiving n clock request signals (REQ1 to REQn) from the n blocks (BLK1 to BLKn). Each of the n blocks (BLK1 to BLKn) independently starts or stops transmitting n clock request signals (REQ1 to REQn) and starts or stops receiving n clock response signals (ACK1 to ACKn) and n clock signals (CLK1 to CLKn). The n blocks (BLK1 to BLKn) start transmitting the n clock request signals (REQ1 to REQn) to the top clock management unit 110 at the same time. As a result, the top clock management unit 110 starts providing n clock response signals (ACK1 to ACKn) and n clock signals (CLK1 to CLKn) for n blocks (BLK1 to BLKn) at the same time.

[0024] The n blocks (BLK1 to BLKn) start transmitting the n clock request signals (REQ1 to REQn) to the top clock management unit 110 at different times. As a result, the top clock management unit 110 starts providing n clock response signals (ACK1 to ACKn) and n clock signals (CLK1 to CLKn) for the n blocks (BLK1 to BLKn) at different times. The n blocks (BLK1 to BLKn) stop transmitting the n clock request signals (REQ1 to REQn) to the top clock management unit 110 at the same time. As a result, the time when the top clock management unit 110 stops providing the n clock response signals (ACK1 to ACKn) and the n clock signals (CLK1 to CLKn) to the n blocks (BLK1 to BLKn) is the same. The n blocks (BLK1 to BLKn) stop transmitting the n clock request signals (REQ1 to REQn) to the top clock management unit 110 at different times. As a result, the time points at which the top clock management unit 110 stops providing the n clock response signals (ACK1 to ACKn) and the n clock signals (CLK1 to CLKn) for the n blocks (BLK1 to BLKn) are different from each other.

[0025] Each of the n blocks (BLK1 to BLKn) includes a block clock management unit and a plurality of clock consumers. The number of clock consumers included in the n blocks (BLK1 to BLKn) may be the same or different. For example, the first block BLK1 includes a first block clock management unit (130-1) and m clock consumers (1201-1 to 1201-m). Hereinafter, for n blocks (BLK1 to BLKn), the description of the same configurations and operations as the first block BLK1 will be omitted or simplified, and the other configurations and operations will be described in more detail.

[0026] One first block clock management unit (130-1) provides m clock signals (CLK1-1 to CLK1-m) to M clock consumers (1201-1 to 1201-m). m is 1 or greater. The first block clock management unit (130-1) receives m clock request signals (REQ1-1 to REQ1-m) from M clock consumers (1201-1 to 1201-m) and transmits m clock signals (CLK1-1 to CLK1-m) corresponding to the m clock request signals (REQ1-1 to REQ1-m) to the m clock consumers (1201-1 to 1201-m). The first block clock management unit 130-1 responds to M clock request signals REQ1-1 to REQ1-m and provides m clock signals CLK1-1 to CLK1-m without m clock response signals, i.e., without channels. That is, the first block clock management unit 130-1 provides m clock signals CLK1-1 to CLK1-m using a method other than the handshake method.

[0027] The time when the m clock consumers (1201-1 to 1201-m) start or stop providing the m clock signals (CLK1-1 to CLK1-m) from the first block clock management unit (130-1) is the time when the m clock consumers (1201-1 to 1201-m) start or stop transmitting the m clock request signals (REQ1-1 to REQ1-m) to the first block clock management unit (130-1). The m clock consumers 1201-1 to 1201-m start transmitting the m clock request signals REQ1-1 to REQ1-m to the first block clock management unit 130-1 at the same time. As a result, the first block clock management unit (130-1) starts providing the m clock signals (CLK1-1 to CLK1-m) to the m clock consumers (1201-1 to 1201-m) at the same time. The m clock consumers 1201-1 to 1201-m start transmitting the m clock request signals REQ1-1 to REQ1-m to the first block clock management unit 130-1 at different times. As a result, the first block clock management unit (130-1) starts providing the m clock signals (CLK1-1 to CLK1-m) to the m clock consumers (1201-1 to 1201-m) at different times.

[0028] The m clock consumers 1201-1 to 1201-m stop transmitting the m clock request signals REQ1-1 to REQ1-m to the first block clock management unit 130-1 at the same time. As a result, the first block clock management unit 130-1 stops providing the m clock signals CLK1-1 to CLK1-m to the m clock consumers 1201-1 to 1201-m at the same time. The m clock consumers 1201-1 to 1201-m stop transmitting the m clock request signals REQ1-1 to REQ1-m to the first block clock management unit 130-1 at different times. As a result, the first block clock management unit 130-1 stops providing the m clock signals CLK1-1 to CLK1-m to the m clock consumers 1201-1 to 1201-m at different times.

[0029] The image sensor (100 in FIG. 1) has the characteristics that image data is processed on a frame-by-frame basis, transmitted in only one direction, and the function to stop processing is applied only to a limited extent, so it is necessary to prevent the loss of image data due to this. According to an embodiment of the present invention, the top clock management unit 110 stably supplies a clock signal to the block clock management unit through a channel formed by a handshake method, and the block clock management unit immediately supplies a clock signal to the clock consumer in response to a clock request signal from the clock consumer, thereby minimizing the latency of clock supply to the clock consumer and reducing data loss. The analog control logic 140 transmits a start signal to each of the multiple clock consumers. The start signal indicates the end point of a vertical blank section of an image frame. That is, the start signal indicates the start time of an active section of an image frame. The vertical blanking interval refers to the interval from the time when all the clock consumers finish operating in the current image frame to the time when the start signal is generated in the next image frame. The plurality of clock consumers each generate a clock request signal in response to a start signal received from the analog control logic 140, but this is not limiting.

[0030] Hereinafter, the operation of the image signal processor blocks according to the embodiment of the present invention will be described in detail with reference to FIGS. FIG. 4 is a block diagram illustrating the operation of the blocks of an image signal processor according to an embodiment of the present invention. 5A and 5B are timing diagrams illustrating transmit and receive signals in operation of blocks of an image signal processor according to an embodiment of the present invention.

[0031] Referring to Figures 4 and 5A, the (1-1)th clock consumer 1201-1 generates a (1-1)th clock request signal REQ1-1, transmits it to the first block clock management unit 130-1, and receives a (1-1)th clock signal CLK1-1 corresponding to the (1-1)th clock request signal REQ1-1 from the first block clock management unit 130-1. The (1-1)th clock consumer 1201-1 generates a (1-1)th clock request signal REQ1-1 in response to the start signal received from the analog control logic 140. That is, the (1-1)th clock consumer 1201-1 generates the (1-1)th clock request signal REQ1-1 at the end of the vertical blank section Vblank of the image frame. For example, the (1-1)th clock consumer 1201-1 generates the (1-1)th clock request signal REQ1-1 at the first time point t1 when it receives the start signal.

[0032] The first block clock management unit (130-1) generates a second clock request signal REQ1 corresponding to the (1-1)th clock request signal REQ(1-1) and transmits it to the top clock management unit 110, and receives a clock response signal ACK1 and a second clock signal CLK1 corresponding to the second clock request signal REQ1 from the top clock management unit 110. The first block clock management unit 130-1 generates a second clock request signal REQ1 when it receives any one of the M clock request signals REQ1-1 to REQ1-m. For example, the first block clock management unit 130-1 generates a second clock request signal REQ1 at the first time point t1 when it receives the (1-1)th clock request signal REQ1-1.

[0033] The top clock management unit 110 generates a clock response signal ACK1 and a second clock signal CLK1 corresponding to the second clock request signal REQ1 received from the first block clock management unit 130-1 and transmits them to the first block clock management unit 130-1. For example, the top clock management unit 110 generates a clock response signal ACK1 and a second clock signal CLK1 at a first time t1 when it receives a second clock request signal REQ1, and the clock response signal ACK1 maintains a high level from the first time t1 to the second time t2 when the second clock request signal REQ1 maintains a high level, and the second clock signal CLK1 toggles from the first time t1 to the second time t2 when the second clock request signal REQ1 maintains a high level.

[0034] The first block clock management unit 130-1 transmits the (1-1)th clock signal CLK1-1 corresponding to the (1-1)th clock request signal REQ1-1 based on the second clock signal CLK1 received from the top clock management unit 110. The first block clock management unit (130-1) includes a plurality of adapters (1301-1 to 1301-m) and a plurality of clock gate units (1302-1 to 1302-m). The (1-1)th adapter (1301-1) controls the (1-1)th clock gate unit (1302-1). The (1-1)th clock gate unit (1302-1) transmits the (1-1)th clock signal (CLK1-1).

[0035] The (1-1)th clock gate unit (1302-1) is a unit that performs clock gating and is provided in the first block clock management unit (130-1). The (1-1)th clock gate unit 1302-1 may be implemented in various ways, and may include logic elements such as flip-flops and AND gates. The (1-1)th clock gate unit (1302-1) transmits the (1-1)th clock signal (CLK1-1) or blocks transmission of the (1-1)th clock signal (CLK1-1) under the control of the (1-1)th adapter (1301-1). When the (1-1)th clock request signal (REQ1-1) is transmitted from the (1-1)th clock consumer (1201-1), the (1-1)th adapter (1301-1) controls the (1-1)th clock gate unit (1302-1) to transmit the (1-1)th clock signal (CLK1-1), and when the transmission of the (1-1)th clock request signal (REQ1-1) from the (1-1)th clock consumer (1201-1) is interrupted, the (1-1)th clock gate unit (1302-1) controls the (1-1)th clock gate unit (1302-1) to interrupt the transmission of the (1-1)th clock signal (CLK1-1).

[0036] For example, when the (1-1)th adapter 1301-1 receives the (1-1)th clock request signal REQ1-1, it generates a second clock request signal REQ1 corresponding to the (1-1)th clock request signal REQ1-1 and transmits it to the top clock management unit 110, and controls the (1-1)th clock gate unit 1302-1 to transmit the second clock signal CLK1 to the (1-1)th clock consumer 1201-1 as the (1-1)th clock signal CLK1-1. If the reception of the (1-1)th clock request signal (REQ1-1) is interrupted, the (1-1)th adapter (1301-1) controls the (1-1)th clock gate unit (1302-1) to cut off the transmission of the (1-1)th clock signal (CLK1-1) to the (1-1)th clock consumer (1201-1). That is, the first block clock management unit 130-1 transmits the (1-1)th clock signal CLK1-1 corresponding to the (1-1)th clock request signal REQ1-1 to the (1-1)th clock consumer 1201-1 from the first time t1 when reception of the (1-1)th clock request signal REQ1-1 begins to the (1-1)th time t1-1 when reception of the (1-1)th clock request signal REQ1-1 is interrupted.

[0037] Meanwhile, the first block clock management unit 130-1 transmits the (1-2) clock signal CLK1-2 corresponding to the (1-2) clock request signal REQ1-2 to the (1-2) clock consumer 1201-2 from the first time t1 when reception of the (1-2) clock request signal REQ1-2 begins to the second time t2 when reception of the (1-2) clock request signal REQ1-2 is interrupted. The first block clock management unit 130-1 stops generating the second clock request signal REQ1 when the reception of all M clock request signals REQ1-1 to REQ1-m is stopped. For example, if the (1-1)th time (t1-1) at which the (1-1)th clock consumer (1201-1) stops generating the (1-1)th clock request signal (REQ1-1) is different from the second time t2 at which the (1-2)th clock consumer (1201-2) stops generating the (1-2)th clock request signal (REQ1-2), the first block clock management unit (130-1) stops generating the second clock request signal REQ1 at the later second time t2, and the top clock management unit 110 stops transmitting the clock response signal ACK1 and the second clock signal CLK1 at the second time t2. According to an embodiment of the present invention, a clock can be supplied to each of the IP blocks included in the image sensor 1000 only for the period required for each of the IP blocks to execute image processing, thereby reducing power consumption due to unnecessary clock supply.

[0038] 4 and 5B, for example, when the (1-1)th clock consumer 1201-1 and the (1-2)th clock consumer 1201-2 generate the (1-1)th clock request signal REQ1-1 and the (1-2)th clock request signal REQ1-2 at the first time point t1 and transmit them to the first block clock management unit 130-1, the first block clock management unit 130-1 generates a second clock request signal REQ1 at the first time point t1 when it receives either the (1-1)th clock request signal REQ1-1 or the (1-2)th clock request signal REQ1-2 and transmits it to the top clock management unit 110. The first block clock management unit 130-1 generates and transmits a second clock request signal REQ1, for example, between the first time point t1 and the second time point t2, while receiving either the (1-1)th clock request signal REQ1-1 or the (1-2)th clock request signal REQ1-2.

[0039] The top clock management unit 110 generates a clock response signal ACK1 between the first time point t1 and the second time point t2 and transmits it to the first block clock management unit (130-1), and a first channel CH1 is formed between the first time point t1 and the second time point t2. During the period from the first time point t1 to the second time point t2 when the first channel CH1 is formed, the top clock management unit 110 generates and transmits the second clock signal CLK1 to the first block clock management unit 130-1.

[0040] The (1-1)th clock consumer 1201-1 generates a (1-1)th clock request signal (REQ1-1) and transmits it to the first block clock management unit 130-1 between the first time point t1 and the (1-1)th time point (t1-1), suspends the generation of the (1-1)th clock request signal (REQ1-1) between the (1-1)th time point (t1-1) and the (1-2)th time point (t1-2), generates a (1-1)th clock request signal (REQ1-1) and transmits it to the first block clock management unit 130-1 between the (1-2)th time point (t1-2) and the (1-3)th time point (t1-3), and suspends the generation of the (1-1)th clock request signal (REQ1-1) at the second time point t2. Correspondingly, the (1-1)th clock consumer (1201-1) receives the (1-1)th clock signal (CLK1-1) from the first time point t1 to the (1-1)th time point (t1-1), suspends reception of the (1-1)th clock signal (CLK1-1) from the (1-1)th time point (t1-1) to the (1-2)th time point (t1-2), receives the (1-1)th clock signal (CLK1-1) from the (1-2)th time point (t1-2) to the (1-3)th time point (t1-3), and suspends reception of the (1-1)th clock signal (CLK1-1) at the second time point t2.

[0041] In this case, since the first block clock management unit 130-1 receives the second clock signal CLK1 from the top clock management unit 110 via the first channel CH1 between the first time point t1 and the second time point t2, after the time point (1-1) (t1-1) when the reception of the (1-1) clock request signal (REQ1-1) is interrupted, the first block clock management unit 130-1 immediately receives the (1-1) clock signal (CLK1-1) corresponding to the (1-1) clock request signal (REQ1-1) based on the second clock signal CLK1 at the time point (1-2) (t1-2) when the reception of the (1-1) clock request signal (REQ1-1) starts again, thereby minimizing the delay in clock supply to the (1-1) clock consumer 1201-1. According to the embodiment of the present invention, a clock can be supplied to clock consumers included in the image sensor 100 with a minimum delay, so that clock control suitable for the image sensor 1000 can be performed.

[0042] FIG. 6 is a block diagram illustrating the operation of a block of an image signal processor according to an embodiment of the present invention, and FIGS. 7A and 7B are timing diagrams of signals in the operation of a block of an image signal processor according to an embodiment of the present invention. Referring to FIG. 6, the (1-3)th clock consumer (1201-3) generates the (1-3)th clock request signal (REQ1-3) based on the start signal transmitted from the analog control logic 140 and the enable signal generated by the 1-3 enable register 150-3.

[0043] The analog control logic 140 may transmit a start signal to multiple clock consumers. For example, the analog control logic 140 transmits a start signal to the (1-1)th clock consumer (1201-1), the (1-2)th clock consumer (1201-2), and the (1-3)th clock consumer (1201-3). The (1-1)th clock consumer (1201-1), the (1-2)th clock consumer (1201-2), and the (1-3)th clock consumer (1201-3) include the (1-1)th enable register (150-1), the (1-2)th enable register (150-2), and the (1-3)th enable register (150-3). The (1-1)th enable register (150-1), the (1-2)th enable register (150-2), and the (1-3)th enable register (150-3) each receive an enable control signal from an external device such as the CPU 200. The enable control signal is a signal that changes the enable signal of the enable register to an activation signal or a deactivation signal.

[0044] Referring to Figures 7A and 7B, the (1-3)th clock consumer (1201-3) generates the (1-1)th clock request signal (REQ1-1) in response to the start signal if the enable signal is an activation signal, and does not respond to the start signal if the enable signal is a deactivation signal. For example, as shown in FIG. 7A, when the (1-3) enable register 150-3 generates a high level activation signal in response to the enable control signal received from the CPU 200, the (1-3) clock consumer 1201-3 generates a (1-3) clock request signal REQ1-3 at the first time t1 when the start signal is changed to a high level, transmits the generated signal to the first block clock management unit 130-1, and provides a (1-3) clock signal CLK1-3 corresponding to the (1-3) clock request signal REQ1-3 at the first time t1.

[0045] For example, as shown in FIG. 7B, when the (1-3) enable register 150-3 generates a low level deactivation signal in response to the enable control signal received from the CPU 200, the (1-3) clock consumer 1201-3 does not generate the (1-3) clock request signal REQ1-3 at the first time t1 when the start signal is changed to a high level, and the (1-3) clock signal CLK1-3 is not provided. At this time, the (1-3)th clock consumer (1201-3) executes a bypass operation to output the input image data as is without image processing. The bypass operation is performed without a clock. According to an embodiment of the present invention, it is possible to control the clock supply to at least one IP block that needs to perform image processing only for a specified image frame or for a specified period among multiple IP blocks included in an image sensor, thereby reducing power consumption due to unnecessary clock supply.

[0046] FIG. 8 is a block diagram illustrating the operation of a block of an image signal processor according to an embodiment of the present invention, and FIG. 9 is a timing diagram of signals in the operation of a block of an image signal processor according to an embodiment of the present invention. Referring to FIGS. 8 and 9, the analog control logic 140 transmits a start signal to the (1-1)th clock consumer 1201-1 and the (1-2)th clock consumer 1201-2.

[0047] Meanwhile, the register 160 generates the (1-3)th clock request signal (REQ1-3), and the (1-3)th clock consumer (1201-3) receives the (1-3)th clock signal (CLK1-3) corresponding to the (1-3)th clock request signal (REQ1-3) generated by the register 160. The (1-3)th clock consumer (1201-3) does not receive a start signal from the analog control logic 140. Therefore, the (1-3)th clock consumer (1201-3) receives the (1-3)th clock signal (CLK1-3) regardless of the start signal. When the (1-3)th adapter (1301-3) receives the (1-3)th clock request signal (REQ1-3) from the register 160, it controls the (1-3)th clock gate unit (1302-3) to transmit the second clock signal CLK1 to the (1-3)th clock consumer (1201-3). For example, the register 160 generates the (1-3)th clock request signal (REQ1-3) at the second time t2, which is not the first time t1 at which the start signal is provided, and transmits it to the (1-3)th adapter (1301-3), and the (1-3)th adapter (1301-3) controls the (1-3)th clock gate unit (1302-3) to transmit the (1-3)th clock signal (CLK1-3) to the (1-3)th clock consumer (1201-3) at the second time t2.

[0048] That is, the (1-1)th clock consumer 1201-1 and the (1-2)th clock consumer 1201-2 generate the (1-1)th clock signal CLK1-1 and the (1-2)th clock signal CLK1-2 at the first time t1 when they receive the start signal and transmit them to the first block clock management unit 130-1, and the register 160 generates the (1-3)th clock request signal REQ1-3 at the second time t2, which is different from the first time t1, and transmits them to the first block clock management unit 130-1. If the transmission of the (1-3) clock request signal (REQ1-3) from the register 160 is interrupted at the third time point t3, the (1-3) adapter (1301-3) controls the (1-3) clock gate unit (1302-3) to interrupt the transmission of the (1-3) clock signal (CLK1-3) to the (1-3) clock consumer (1201-3) at the third time point t3. According to an embodiment of the present invention, it is possible to control the clock supply to at least one IP block that needs to perform image processing independently of the start signal among multiple IP blocks included in the image sensor 1000, thereby reducing power consumption due to unnecessary clock supply.

[0049] FIG. 10 is a timing diagram of signals in the operation of a block of an image signal processor according to an embodiment of the present invention. Referring to FIG. 10, the first block clock management unit 130-1 transmits the (1-1) clock signal (CLK1-1) corresponding to the (1-1) clock request signal (REQ1-1) to the (1-1) clock consumer 1201-1 from the first time point t1 when reception of the (1-1) clock request signal (REQ1-1) begins to the fourth time point t4 when reception of the (1-1) clock request signal (REQ1-1) is interrupted, until the (4-1) time point t4-1 when the first margin value (Margin Value 1) has elapsed. The margin value is predetermined and can be changed via the controller (11 in FIG. 2).

[0050] The first block clock management unit 130-1 transmits the (1-2) clock signal (CLK1-2) corresponding to the (1-2) clock request signal (REQ1-2) to the (1-2) clock consumer 1201-2 from the second time point t2 when reception of the (1-2) clock request signal (REQ1-2) begins to the fifth time point t5 when reception of the (1-2) clock request signal (REQ1-2) is interrupted, to the (5-1) time point t5-1 when the second margin value (Margin Value 1) has elapsed. The first block clock management unit 130-1 transmits the (1-3) clock signal (CLK1-3) corresponding to the (1-3) clock request signal (REQ1-3) to the (1-3) clock consumer 1201-3 during the period from the third time point t3 when reception of the (1-3) clock request signal (REQ1-3) begins to the sixth time point t6 when reception of the (1-3) clock request signal (REQ1-3) is interrupted, to the (6-1) time point t6-1 when the third margin value (Margin Value 1) has elapsed.

[0051] The first margin value (Margin Value 1) is 3 cycles, the second margin value (Margin Value 2) is 4 cycles, and the third margin value (Margin Value 3) is 2 cycles. That is, the margin values ​​of the (1-1)th clock consumer (1201-1), the (1-2)th clock consumer (1201-2), and the (1-3)th clock consumer (1201-3) are different from one another, but are not limited to this. According to an embodiment of the present invention, if a clock consumer retransmits a clock request signal within a margin value after the clock consumer's clock request signal transmission is interrupted, the delay in clock supply to the clock consumer is minimized, thereby enhancing the stability of the image processing operation of the image sensor 1000.

[0052] FIG. 11 is a block diagram illustrating the operation of a block of an image signal processor according to an embodiment of the present invention, and FIG. 12 is a timing diagram of signals in the operation of a block of an image signal processor according to an embodiment of the present invention. 11 and 12, the first block BLK1 includes a first block clock management unit 130-1 and clock consumers (1-1) to (1-5) 1201-5.

[0053] The first block clock management unit (130-1) includes a (1-2)th adapter (1301-2), a (1-4)th adapter (1301-4), and a (1-5)th adapter (1301-5), a (1-2)th clock gate unit (1302-2), a (1-4)th clock gate unit (1302-4), a (1-5)th clock gate unit (1302-5), and an OR gate unit 170. The (1-1)th clock consumer (1201-1) is a case where no start signal is provided from the analog control logic 140 and no corresponding clock gate unit or adapter exists. The (1-2)th clock consumer (1201-2) and the (1-3)th clock consumer (1201-3) receive the (1-2)th clock signal (CLK1-2) corresponding to the (1-2)th clock request signal (REQ1-2) generated by the (1-2)th clock consumer (1201-2) and transmitted to the first block clock management unit (130-1).

[0054] The (1-3)th clock consumer (1201-3) is a case where no start signal is provided from the analog control logic 140 and no corresponding clock gate unit or adapter exists. The (1-3)th clock consumer (1201-3) shares the (1-2)th adapter (1301-2) and the (1-2)th clock gate unit (1302-2) with the (1-2)th clock consumer (1201-2). For example, when the (1-2) clock request signal (REQ1-2) is transmitted from the (1-2) clock consumer (1201-2), the (1-2) adapter (1301-2) controls the (1-2) clock gate unit (1302-2) to transmit the second clock signal CLK1 to the (1-2) clock consumer (1201-2) and the (1-3) clock consumer (1201-3) as the (1-2) clock signal (CLK1-2) and the (1-3) clock signal (CLK1-3). That is, the (1-2)th clock signal (CLK1-2) and the (1-3)th clock signal (CLK1-3) are the same clock signal.

[0055] If the transmission of the (1-2) clock request signal (REQ1-2) from the (1-2) clock consumer (1201-2) is interrupted, the (1-2) adapter (1301-2) controls the (1-2) clock gate unit (1302-2) to interrupt the transmission of the (1-2) clock signal (CLK1-2) and the (1-3) clock signal (CLK1-3) to the (1-2) clock consumer (1201-2) and the (1-3) clock consumer (1201-3). As a result, the (1-2) clock consumer (1201-2) and the (1-3) clock consumer (1201-3) receive the (1-2) clock signal (CLK1-2) corresponding to the (1-2) clock request signal (REQ1-2) from the first time point t1 when the transmission of the (1-2) clock request signal (REQ1-2) begins to the fifth time point t5 when the transmission of the (1-2) clock request signal (REQ1-2) is interrupted. That is, the (1-3)th clock consumer (1201-3) operates during the same period as the (1-2)th clock consumer (1201-2). According to an embodiment of the present invention, the number of adapters and clock gate units included in the image sensor 1000 is minimized, thereby reducing the power consumption of the image sensor 1000.

[0056] The (1-4)th clock consumer (1201-4) receives the (1-4)th clock signal (CLK1-4) corresponding to the (1-4)th clock request signal (REQ1-4) generated by the (1-4)th clock consumer (1201-4) and transmitted to the first block clock management unit (130-1), and the (1-5)th clock consumer (1201-5) receives the (1-5)th clock signal (CLK1-5) corresponding to at least one of the (1-4)th clock request signal (REQ1-4) and the (1-5)th clock request signal (REQ1-5) generated by the (1-5)th clock consumer (1201-5) and transmitted to the first block clock management unit (130-1). The OR gate unit 170 receives at least one of the (1-4)th clock request signal (REQ1-4) and the (1-5)th clock request signal (REQ1-5) from the (1-4)th clock consumer 1201-4 and the (1-5)th clock consumer 1201-5, and transmits at least one of the (1-4)th clock request signal (REQ1-4) and the (1-5)th clock request signal (REQ1-5) to the (1-5)th adapter 1301-5.

[0057] Thus, when the (1-5) adapter 1301-5 receives at least one of the (1-4) clock request signal (REQ1-4) and the (1-5) clock request signal (REQ1-5), the (1-5) clock gate unit 1302-5 generates the (1-5) clock signal (C) corresponding to at least one of the (1-4) clock request signal (REQ1-4) and the (1-5) clock request signal (REQ1-5). If the (1-4) clock request signal (REQ1-4) and the (1-5) clock request signal (REQ1-5) are both interrupted, the (1-5) clock gate unit 1302-5 controls to interrupt the transmission of the (1-5) clock signal (CLK1-5) to the (1-5) clock consumer 1201-5.

[0058] The (1-5)th clock consumer (1201-5) receives the (1-5)th clock signal (CLK1-5) corresponding to at least one of the (1-4)th clock request signal (REQ1-4) and the (1-5)th clock request signal (REQ1-5). As a result, the (1-5)th clock consumer (1201-5) receives the (1-5)th clock signal (CLK1-5) in response to the transmission of the (1-4)th clock request signal (REQ1-4) even from the second time point t2 to the second time point t3 when the transmission of the (1-5)th clock request signal (REQ1-5) is interrupted. That is, the (1-5)th clock consumer (1201-5) operates for the same period as the (1-4)th clock consumer (1201-4). On the other hand, the (1-5)th clock consumer (1201-5) can operate as needed even during a period unrelated to the operation of the (1-4)th clock consumer (1201-4).

[0059] The (1-1)th clock consumer (1201-1) is a case where no start signal is provided from the analog control logic 140 and no corresponding clock gate unit or adapter exists. The (1-1)th clock consumer (1201-1) receives the second clock signal CLK1 as the (1-1)th clock signal (CLK1-1). For example, the first block clock management unit 130-1 generates and transmits a second clock request signal REQ1 to the top clock management unit 110 and receives a second clock signal CLK1 corresponding to the second clock request signal REQ1 from the first time point t1, when the first block clock management unit 130-1 receives at least one of the (1-2) clock request signal REQ1-2, the (1-4) clock request signal REQ1-4, and the (1-5) clock request signal REQ1-5, to the sixth time point t6, when the first block clock management unit 130-1 stops receiving all of the (1-2) clock request signal REQ1-2, the (1-4) clock request signal REQ1-4, and the (1-5) clock request signal REQ1-5. As a result, the (1-1)th clock consumer (1201-1) receives the second clock signal CLK1 as the (1-1)th clock signal (CLK1-1) from the first time point t1 to the sixth time point t6 at which the second clock signal CLK1 is received. According to the embodiment of the present invention, clock control suitable for the image sensor 1000 is performed based on the association between clock consumers.

[0060] FIG. 13 is a flowchart illustrating a method of operating an image sensor according to an embodiment of the present invention. Hereinafter, n means the number of blocks, and m means the number of clock consumers, where n and m are each 1 or greater. That is, one top clock management unit manages n blocks, and one block clock management unit manages m clock consumers. The number of clock consumers managed by each block clock management unit may be the same or different.

[0061] Referring to FIG. 13, the nm-th clock consumer 120n-m generates a first clock request signal (step S110) and transmits the first clock request signal to the nm-th block clock management unit 130n-m (step S120). The clock consumer or register (160 in FIG. 8) determines when to generate the clock request signal. For example, the clock consumer generates a clock request signal upon receiving a start signal from the analog control logic (140 in FIG. 3).

[0062] The start signal is a signal transmitted simultaneously to a plurality of clock consumers, and the clock request signal generated by the register (160 in FIG. 8) is a signal generated only for a specific clock consumer. The start signal is held for multiple cycles, and the time at which the start signal changes from low to high, the number of cycles the start signal is held, the time at which the start signal changes from high to low, etc. are predetermined and can be changed via the controller (11 in Figure 2).

[0063] The nm-th block clock management unit 130n-m generates a second clock request signal corresponding to the first clock request signal (step S130) and transmits the second clock request signal to the top clock management unit 110 (step S140). The (nm)-th block clock management unit (130n-m) generates a second clock request signal when it receives a first clock request signal from one of the M clock consumers, and stops generating the second clock request signal when it stops receiving the first clock request signal from all m clock consumers. Steps S110 to S140 may also be performed without a clock.

[0064] The top clock management unit 110 generates a clock response signal and a second clock signal in response to the second clock request signal (step S150), and transmits the clock response signal and the second clock signal to the nm-th block clock management unit (130n-m) (step S160). Steps S140 and S150 show that a handshake method is applied to the communication between the top clock management unit 110 and the nm-th block clock management units 130n-m.

[0065] The (nm)-th block clock management unit (130n-m) generates a first clock signal corresponding to the first clock request signal based on the second clock signal (step S170), and transmits the first clock signal to the (nm)-th clock consumer (120n-m) (step S180). In step S170, the (nm) block clock management unit (130n-m) may transmit the first clock signal to the (nm) clock consumer (120n-m) without generating a clock response signal corresponding to the first clock signal and transmitting it to the (nm) clock consumer (120n-m), which indicates that the communication method between the (nm) block clock management unit (130n-m) and the (nm) clock consumer (120n-m) is independent of the handshake method.

[0066] The transmission of the first clock signal from the (nm) block clock management unit (130n-m) to the (nm) clock consumer (120n-m) is maintained until the time when the transmission of the first clock request signal from the (nm) clock consumer (120n-m) is interrupted, but is not limited to this. The transmission of the first clock signal from the (nm) block clock management unit 130n-m to the (nm) clock consumer 120n-m can be maintained until a margin value has elapsed after the point in time when the transmission of the first clock request signal from the (nm) clock consumer 120n-m is interrupted. That is, according to an embodiment of the present invention, the top clock management unit and the block clock management unit only provide clock signals based on the clock request signals of the clock consumers, and cannot provide clock signals regardless of the clock request signals of the clock consumers.

[0067] FIG. 14 is a block diagram showing a schematic configuration of an image processing apparatus according to an embodiment of the present invention. The image processing device 2000 in FIG. 14 is also a portable terminal. Referring to FIG. 14, an image processing device 2000 according to an embodiment of the present invention includes an application processor 2100, an image sensor 2200, a display device 2400, a working memory 2500, a storage 2600, a user interface 2700, and a wireless handset 2800.

[0068] The application processor 2100 is provided as a system-on-chip (SoC) that controls the overall operation of the image processing device 2000 and runs application programs, an operating system, and the like. The application processor 2100 provides the image data received from the image sensor 2200 to the display device 2400 or stores it in the storage 2600 . In an embodiment, the application processor 2100 may further include an image signal processor that performs image processing on the image data received from the image sensor 2200 . The image signal processor included in the application processor 2100 can perform various image processing operations on image data, such as noise reduction, demosaic, sharpening, and HDR (High Dynamic Range) processing. The image sensor 2200 generates image data, eg, far-eye image data, based on the received optical signals and provides the image data to an image signal processor 2300 .

[0069] The image sensor 2200 described with reference to Figures 1 to 12 includes a plurality of clock consumers, a plurality of block clock management units, and a top clock management unit, and each block clock management unit transmits a second clock request signal to the top clock management unit in response to a first clock request signal received from at least one clock consumer among the plurality of clock consumers, the top clock management unit transmits clock response signals corresponding to each second clock request signal, and the top clock management unit transmits the second clock signal to each block clock management unit via a channel formed for transmitting and receiving the second clock request signal and the clock response signal. While the second clock signal is transmitted through the channel, each block clock management unit transmits a first clock signal corresponding to the first clock request signal to a clock consumer that transmitted the first clock request signal among the plurality of clock consumers, based on the second clock signal. This allows the image sensor 2200 to supply clocks only when necessary for each of the multiple clock consumers to execute image processing, thereby reducing power consumption due to unnecessary clock supply.

[0070] The working memory 2500 may be implemented as a volatile memory such as DRAM, SRRAM, or a non-volatile resistive memory such as FeRAM, RRAM, or PRAM. The working memory 2500 stores programs and / or data that are processed or executed by the application processor 2100. The storage 2600 may be implemented as a non-volatile memory device such as a DDR flash memory or a resistive memory, and for example, the storage 2600 may be provided as a memory card (MMC, eMMC, SD, microSD), etc. The storage 2600 stores data and / or programs for executing algorithms that control the image processing operations of the image signal processor 2300, and the data and / or programs are loaded into the working memory 2500 when the image processing operations are performed. In an embodiment, storage 2600 stores image data generated by image signal processor 2300, for example, transformed image data or post-processed image data.

[0071] The user interface 2700 may be implemented as a variety of devices for receiving user input, such as a keyboard, a curtain key panel, a touch panel, a fingerprint sensor, or a microphone. The user interface 2700 receives user input and provides signals corresponding to the received user input to the application processor 2100 . The wireless handset 2800 may include a transceiver 2810 , a modem 2820 , and an antenna 2830 .

[0072] The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the technical scope of the present invention. [Explanation of symbols]

[0073] 100 image sensors 110 Top Clock Management Unit 1201-1 to 1201-m (1st to mth) clock consumers 120n-1 to 120n-m (n-1th to nmth) clock consumers 130-1 1st Block Clock Management Unit 1301-1~1301-m (1-1~1-m) adapter 1302-1~1302-m (1-1~1-m) Clock Gate Unit 140 Analog Control Logic 1100 pixel array 1200 Readout Circuit 1300 Control Logic Circuit 1400 Image Signal Processor 1410 IP Block 1411, 1412, 1413 (1st to 3rd) IP blocks 1500 output circuit BLK(1~n) (1st to nth) block LS Optical Lens PX Sensing Pixel IDT Image Data

Claims

1. a pixel array including a plurality of sensing pixels; a readout circuit for converting electrical signals received from the pixel array into image data; an image signal processor for image processing the image data output from the readout circuit, The image signal processor a clock consumer that generates a first clock request signal and receives a first clock signal corresponding to the first clock request signal; a block clock management unit that receives the first clock request signal from the clock consumer, generates a second clock request signal corresponding to the first clock request signal, and receives a clock response signal corresponding to the second clock request signal and the second clock signal; a top clock management unit that receives the second clock request signal from the block clock management unit, generates the clock response signal and the second clock signal corresponding to the second clock request signal, and transmits the clock response signal and the second clock signal to the block clock management unit, The block clock management unit generates the first clock signal corresponding to the first clock request signal based on the second clock signal, and transmits the first clock signal to the clock consumer.

2. further comprising analog control logic for transmitting a start signal indicating an end point of a vertical blanking interval of an image frame to the clock consumer; 2. The image sensor of claim 1, wherein the clock consumer generates the first clock request signal in response to the start signal.

3. analog control logic for transmitting a start signal to the clock consumer indicating an end point of a vertical blanking interval of an image frame; an enable register that generates an enable signal for controlling activation of the clock consumer; The clock consumer If the enable signal is an activation signal, generating the first clock request signal in response to the start signal; 2. The image sensor according to claim 1, wherein the enable signal is a deactivation signal and does not correspond to the start signal.

4. 2. The image sensor of claim 1, wherein the block clock management unit transmits the first clock signal corresponding to the first clock request signal from a time when reception of the first clock request signal starts until a time when a margin value has elapsed after a time when reception of the first clock request signal is interrupted.

5. a plurality of clock consumers, each of which generates a first clock request signal and receives a first clock signal corresponding to the first clock request signal; a block clock management unit that receives the first clock request signal from each of the plurality of clock consumers, generates a second clock request signal corresponding to the first clock request signal, and receives a clock response signal corresponding to the second clock request signal and the second clock signal; a top clock management unit that receives the second clock request signal from the block clock management unit, generates the clock response signal and the second clock signal corresponding to the second clock request signal, and transmits the clock response signal and the second clock signal to the block clock management unit; the block clock management unit generates the first clock signal corresponding to the first clock request signal based on the second clock signal, and transmits the first clock signal to each of the plurality of clock consumers; The block clock management unit generating the second clock request signal when receiving the first clock request signal from one of the plurality of clock consumers; The image sensor is characterized in that, when all of the plurality of clock consumers stop transmitting the first clock request signal, the image sensor stops generating the second clock request signal.

6. the plurality of clock consumers include a first clock consumer and a second clock consumer; 6. The image sensor of claim 5, wherein the time when the first clock consumer stops generating the first clock request signal is different from the time when the second clock consumer stops generating the first clock request signal.

7. the plurality of clock consumers include a first clock consumer and a second clock consumer; analog control logic for transmitting a start signal indicating an end point of a vertical blanking interval of an image frame to the first clock consumer; a register for controlling activation of the second clock consumer; the first clock consumer generates the first clock request signal in response to the start signal; 6. The image sensor of claim 5, wherein the first clock request signal of the second clock consumer is generated by the register.

8. 8. The image sensor of claim 7, wherein the time when the first clock consumer generates the first clock request signal is different from the time when the register generates the first clock request signal.

9. the block clock management unit transmits the first clock signal corresponding to the first clock request signal from a time when reception of the first clock request signal starts until a time when a margin value has elapsed after a time when reception of the first clock request signal is interrupted, the plurality of clock consumers include a first clock consumer and a second clock consumer; 6. The image sensor of claim 5, wherein the first margin value of the first clock consumer and the second margin value of the second clock consumer are different from each other.

10. 1. A method of operating an image sensor including a clock consumer, a block clock management unit, and a top clock management unit, comprising: generating a first clock request signal by the clock consumer; transmitting the first clock request signal to the block clock management unit by the clock consumer; generating a second clock request signal corresponding to the first clock request signal by the block clock management unit and transmitting the second clock request signal to the top clock management unit; generating a clock response signal and a second clock signal corresponding to the second clock request signal by the top clock management unit, and transmitting the clock response signal and the second clock signal to the block clock management unit; transmitting, by the block clock management unit, a first clock signal corresponding to the first clock request signal based on the second clock signal to the clock consumer; and if the transmission of the first clock request signal by the clock consumer is interrupted, interrupting the transmission of the first clock signal to the clock consumer by the block clock management unit.

Images