Inductance Detection for a Power Converter

Abstract

In one example, circuit (100) includes an emulate current generator (114) configured to provide an emulate current signal in response to a charge current and a discharge current. The emulate current signal may represent an emulate current (EI) through an output inductor. A comparator (116) is configured to provide a comparator signal in response to the emulate current signal and a sense current signal representing a measured value of a current (EI) through the output inductor. An inductor code counter (134) is configured to adjust an inductor code count value in response to the comparator signal. In response to the inductor code count value, a slope of the emulate current signal can be adjusted.

Description

Technical Field

[0001] This description relates to inductance detection for a power converter.

Background Art

[0002] Power converter circuits such as switched-mode power supplies can use external inductors having a wide range of inductances. For some power converters, prior knowledge of the output inductance is used to configure the power converter to operate. However, in some situations, such prior knowledge is not readily available.

Summary of the Invention

[0003] In the example described, the circuit includes an emulated current generator having a current output. A current sensor has a sensor output. A comparator has a first comparator input, a second comparator input, and a comparator output. The first comparator input is coupled to the current output, and the second comparator input is coupled to the sensor output. An inductor code counter has a counter input and a counter output, and the counter input is coupled to the comparator output. A charging circuit has an input coupled to the comparator output, the charging circuit includes a variable slope resistor, and the variable slope resistor has a trim input coupled to the counter output. A discharging circuit has an input coupled to the comparator output, the discharging circuit includes a variable valley resistor, and the variable valley resistor has a trim input coupled to the counter output.

[0004] In another example to be described, the circuit includes an emulate current generator configured to provide an emulate current signal in response to a charging current and a discharging current that respectively charge or discharge timing capacitors. The emulate current signal may represent an emulate current through an output inductor. A comparator is configured to provide a comparator signal in response to the emulate current signal and a sense current signal, and the comparator signal represents a measured value of the current through the output inductor. An inductor code counter is configured to adjust an inductor code count value in response to the comparator signal. In response to the inductor code count value, the slope of the emulate current signal can be adjusted.

[0005] In a further example to be described, the system includes an inductor and a power stage, and the power stage includes a high-side switch and a low-side switch. The high-side switch is coupled between a voltage supply terminal and a switching output terminal. The low-side switch is coupled between the switching output terminal and a ground terminal, and the inductor is coupled to the switching output terminal. A driver is configured to control the high-side switch and the low-side switch in response to a pulse-width modulation control signal. The power stage also includes an inductance detection circuit element including an emulate current generator having a current output. A comparator has a first comparator input, a second comparator input, and a comparator output. The first comparator input is coupled to the current output, and the second comparator input is configured to receive a measured value of the current through the inductor. An inductor code counter has a counter input and a counter output, and the counter input is coupled to the comparator output. A charging circuit has an input coupled to the comparator output, the charging circuit includes a variable slope resistor having a trim input coupled to the counter output. A discharging circuit has an input coupled to the comparator output, the discharging circuit includes a variable valley resistor having a trim input coupled to the counter output.

Brief Description of the Drawings

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Figure 1

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DETAILED DESCRIPTION OF THE INVENTION

[0015] An example relates to a system and method for detecting an output inductance for a power converter. For example, an inductance detection circuit element includes a counter configured to provide an inductor code that is adjusted (e.g., incremented or decremented) in response to a comparison of an emulate current and a sensed inductor current. The emulate current can be generated to simulate the inductor current in response to a charge current and a discharge current. The circuit element is configured to provide the charge current and the discharge current in response to the inductor code, and thus, the charge current and the discharge current provide a measured value of the output inductance. Therefore, by changing the inductor code in response to a comparison over a plurality of cycles, the inductor code can converge to a value representing an estimated value of the output inductance, and the resulting inductor code value can be stored (e.g., in a memory).

[0016] In one example, the inductance detection circuit element can include an additional detection circuit element that uses the stored inductor code value. Such an additional detection circuit element is configured to fine-tune the charge current and the discharge current in response to a comparison of an emulate inductor current and a sensed inductor current over another set of cycles. The inductance detection circuit element can be implemented to perform self-regulating (e.g., adaptive) output inductance detection in addition to, or as part of, the power stage circuit element. Therefore, the techniques described herein provide a practical manufacturing solution that enables detecting the output inductance without requiring the power stage circuit element to add dedicated pins to an integrated circuit die including each power stage.

[0017] FIG. 1 shows a block diagram of a power converter circuit 100 configured to provide a regulated output voltage at output 102. For example, the power converter circuit 100 can be implemented as a buck regulator, a boost regulator, a buck-boost regulator, or other regulator depending on the requirements of the application. The power converter circuit 100 also includes an output stage 104 having an output 106 (e.g., a switching output terminal). For example, the output stage 104 is configured to supply a switching voltage VSW at output 106 in response to a drive signal provided by a driver circuit element 108. A control circuit 110 can be configured to implement one or more control loops for generating a control signal (e.g., a pulse width modulation signal) that commands an increase or decrease in the output power (e.g., voltage and / or current) at output 102. The power converter circuit 100 also includes an inductance detection circuit element 112 configured to detect the inductance of an output inductor L1 coupled between output 102 and output 106. For example, the inductor L1 is external to an integrated circuit (IC) including the power converter circuit 100. An output capacitor COUT can also be coupled between output 102 and a ground terminal.

[0018] As used herein, the term "circuit" can include a collection of active and / or passive elements that implement circuit functions, such as an analog circuit or a control circuit. Further or alternatively, for example, the term "circuit" can include an IC in which all and / or some of the circuit elements are fabricated on a common substrate (e.g., a semiconductor substrate such as a die or chip). Therefore, an IC can be provided by implementing the power converter circuit 100 or its components on a semiconductor substrate. In one example, a power stage circuit including the output stage 104, the driver 108, the control circuit 110, and the inductance detection circuit element 112 is implemented in a discrete IC, and the inductor L1 is coupled to the output 106 of the IC. In another example, the control circuit 110 is implemented as a separate IC from the IC implementing the power stage circuit.

[0019] The inductance detection circuit element 112 includes an emulate current generator 114. The emulate current generator 114 has a current input 117 and a current input 118, and a current output 120. The current output 120 is coupled to an input of a comparator 116. The current input 117 is coupled to a charge current generator circuit (also referred to as a charge circuit) 122, and the current input 118 is coupled to a discharge current generator circuit (also referred to as a discharge circuit) 124. The emulate current generator 114 is configured to provide an emulate current signal I_EM at the current output 120 in response to a charge current I_CHARGE and a discharge current I_DISCHARGE generated by the respective charge circuit 122 and discharge circuit 124. The emulate current signal I_EM represents a simulate current through an output inductor. As described herein, the inductance detection circuit element 112 is configured to implement a self-regulating closed-loop control to adjust the slope of the emulate current I_EM to approximate or match the actual current through the inductor L1.

[0020] For example, a current sensor 126 has a sensor input 128 and a sensor output 130. The sensor input 128 is coupled to the output stage 104, and the sensor output is coupled to another input of the comparator 116. The current sensor 126 is configured to provide a sensed current signal I_SNS representing a measured value of the current through the inductor L1 at the sensor output 130. In an example where the output stage includes a high-side switch and a low-side switch, the current sensor 126 can be coupled across the low-side output switch and configured to provide the signal I_SNS as a measured value of the inductor current when the low-side switch is turned on and the high-side switch is turned off.

[0021] Comparator 116 has a comparator output 132 and is configured to provide a comparator output signal in response to an emulate current signal I_EM and a sense current signal I_SNS. In one example, the comparator is implemented as a mutual conductance amplifier configured to generate a current error signal at 132 in response to the emulate current signal I_EM and the sense current signal I_SNS (e.g., in this case, I_EM and I_SNS are currents). In another example, such as when I_EM and I_SNS are provided as voltage signals, comparator 116 can be implemented as a voltage comparator.

[0022] The inductance detection circuit element 112 also includes an inductor code counter 134 having a counter input 136 and a counter output 138. The counter input 136 is coupled to the comparator output 132, and the counter output 138 is coupled to respective inputs of the charge circuit 122 and the discharge circuit 124. The inductor code counter 134 is configured to adjust a count value representing an inductor code in response to the comparator signal received at 136 and provide the count value at the counter output 138. Therefore, counter 134 can increment or decrement the count value each cycle depending on the relative value of I_EM and I_SNS. For example, if I_EM > I_SNS, counter 134 can increment (e.g., count up) the count value, and if I_EM < I_SNS, the counter can decrement (e.g., count down) the count value.

[0023] As described herein, the charging circuit 122 and the discharging circuit 124 are configured to adjust the slopes of their respective charging current I_CHARGE and discharging current I_DISCHARGE in response to the count value at 138 (e.g., the inductor code count value). For example, the charging current generator circuit 122 includes a variable resistor 140, and the variable resistor 140 is shown as a slope resistor RSLP coupled to the path of the generated charging current I_CHARGE. The discharging current generator circuit 124 also includes a variable resistor 142, and the variable resistor 142 is shown as a valley resistor RVAL coupled to the path of the generated discharging current I_DISCHARGE. The variable resistor 140 and the variable resistor 142 each have an input coupled to the counter output 138, receive the inductor code count value, and trim their respective resistances accordingly. In one example, each of the variable resistor 140 and the variable resistor 142 is trimmed to the same resistance in response to the inductor code count value at 138. In another example, the variable resistor 140 and the variable resistor 142 are trimmed to different resistances in response to the inductor code count value at 138. Therefore, the charging circuit 122 and the discharging circuit 124 are configured to adjust their respective charging current I_CHARGE and discharging current I_DISCHARGE over a plurality of clock cycles (e.g., PWM cycles) in response to the inductor code count value at 138 that sets the resistances of the variable resistor 140 and the variable resistor 142. As a result of adjusting the respective charging and discharging currents, the slope of the emulate current I_EM (e.g., the rise slope and fall slope of I_EM) is adjusted to converge and match the slope of the sensed inductor current I_SNS.

[0024] In some examples, the controller 144 is configured to control the inductance detection circuit element 112 over multiple cycles during the power-on phase of the power converter 100. For example, the controller 144 has a power input 146 and a control output 148. The power input 146 is coupled to a power supply terminal, such as to receive a supply voltage indicated as VDD. The control output 148 can be coupled to the enable input of the inductor code counter 134. For example, in response to power-on, the voltage VDD is supplied at 146, and the controller 144 is configured to provide an enable signal at 148 to enable (e.g., activate) the inductor code counter 134. The controller 144 can be configured to enable the inductor code counter 134 over multiple cycles of a PWM signal or a clock signal. Alternatively, the controller 144 can be configured to enable the inductor code counter 134 over a plurality (e.g., variable number) of cycles in response to detecting dithering between the I_EM signal and the I_SNS signal. For example, the controller 144 can detect dithering in response to the difference between I_EM and I_SNS remaining below a dither threshold. Other techniques can be used to detect sufficient convergence between the I_EM signal and the I_SNS signal. The controller 144 can also be configured to store (e.g., latch) the inductor code count value provided by the inductor code counter 134 in a memory (e.g., a register). As a result, in response to the stored inductor code count value, the values of the variable resistor 140 and the variable resistor 142 can be fixed.

[0025] As described herein, in response to the controller 144 detecting the convergence of the I_EM signal and the I_SNS signal, the controller 144 can be configured to disable the inductor code counter 134 and enable the charge counter 150 of the charging circuit 122 and the discharge counter 152 of the discharging circuit 124. For example, the controller 144 also has a control output 153, and the control output 153 is coupled to the enable inputs of the respective charge counter 150 and discharge counter 152. The charge counter 150 has an input 154 coupled to the comparator output 132. The discharge counter 152 also has an input 156 coupled to the comparator output 132. The charge counter 150 and the discharge counter 152 are configured to adjust their respective count values in response to the comparator output at 132 when activated in response to the enable signal provided at 153 by the controller 144. For example, the charging circuit 122 includes a trim circuit, and the trim circuit is configured to set respective offset voltages for adjusting the charging current I_CHARGE in response to the charge counter output. The discharging circuit 124 may also include a trim circuit, and the trim circuit is configured to set respective offset voltages for adjusting the discharging current I_DISCHARGE in response to the discharge counter output. The variable resistor 140 and the variable resistor 142 are fixed in response to the stored inductor code values, but the controller 144 is configured to perform fine adjustments of the charging current and the discharging current over a plurality of cycles that can be a fixed number or a variable number of cycles. As a result of such fine adjustments, the inductance detection circuit element 112 can be operated to provide an emulate current I_EM that matches the actual inductor current I_SNS with a desired accuracy.

[0026] FIG. 2 illustrates another example of a power converter 200 implementing an inductance detection circuit. The inductance detection circuit 200 can be used to implement the inductance detection circuit 112 of FIG. 1. Therefore, the description of FIG. 2 also refers to FIG. 1. For example, the circuit 200 includes an output stage 104, and the output stage 104 has a switching output (e.g., a switching node or a switching terminal) 106 capable of coupling an inductor L1. In the example of FIG. 2, the output stage 104 includes field effect transistors (FETs) Q1 and Q2 coupled in series between a supply voltage VIN and ground, where Q1 is a high-side FET and Q2 is a low-side FET in this case. The source of Q1 is coupled to the drain of Q2, and they are also coupled to the switching output 106. A driver circuit (not shown in FIG. 2, refer to driver 108 in FIG. 1) is configured to supply gate drive signals to control Q1 and Q2 and provide a switching voltage VSW at 106.

[0027] The current sensor 126 has an input coupled across Q2 and is configured to provide a sensor current signal representative of a measured value of the current through the inductor L1 at 130. For example, the current sensor 126 is configured to measure a low-side output waveform of the low-side FET Q2, such as the voltage across the low-side FET (e.g., drain-source voltage) when Q2 is turned on. The current sensor 126 can be configured to provide a sensor signal I_SNS as a current signal proportional to the inductor output current through L1. Alternatively, the sensor signal I_SNS can also be a voltage representing the inductor output current.

[0028] Also, as described with respect to FIG. 1, circuit 200 also includes an inductor code counter 134 having a counter input 136 and a counter output 138. The counter input 136 is coupled to the comparator output 132, and the counter output 138 is coupled to the inputs of the charge circuit 122 and the discharge circuit 124. The inductor code counter 134 is configured to adjust a count value representing the inductor code in response to the comparator signal at 136 and provide the count value at the counter output 138.

[0029] FIG. 2 also shows a controller 144 having a control output 148 coupled to the enable input of the inductor code counter 134. The controller 144 is configured to provide a control signal at 148 for enabling / disabling the inductor code counter 134 and another control signal at 153 for enabling / disabling the charge counter 150 and the discharge counter 152 during the inductance detection phase of the circuit 200. For example, the controller 144 is configured to enable the inductor code counter over a first plurality of cycles of the inductance detection phase to perform a coarse inductance detection while disabling the charge counter 150 and the discharge counter 152. The controller is also configured to enable the charge counter 150 and the discharge counter 152 over a subsequent second plurality of cycles in the inductance detection phase to perform a more refined inductance detection while disabling the inductor code counter 134.

[0030] In the example of FIG. 2, the emulated current generator 114 includes a charging current source 204 and a discharging current source 206. The charging current source 204 is coupled between a voltage supply terminal shown to provide a voltage VDD and a switch shown as FET Q3. The charging current source 204 is configured to provide a charging current I_CHARGE (or a current proportional to I_CHARGE) in response to a current generated by the charging current generator circuit 122. The discharging current source 206 is coupled between Q3 and the ground terminal. The discharging current source 206 is configured to provide a discharging current I_DISCHARGE (or a current proportional to I_DISCHARGE) in response to a current generated by the discharging current generator circuit 124.

[0031] A switching voltage (VSW) detector 208 has an output coupled to the control input (e.g., gate) of Q3. In one example, the VSW detector 208 has an input coupled to the switching output 106 and is configured to control Q3 in response to the switching voltage VSW at 106. The VSW detector can be implemented as a driver circuit configured to supply a drive signal to turn Q3 on and conduct when the switching voltage VSW is greater than a threshold voltage and turn Q3 off when VSW is less than the threshold voltage. A timing capacitor C1 is coupled in parallel with the discharging current source 206 between the source of Q3 and ground. Therefore, the emulated current generator 114 is configured to provide an emulated current I_EM in response to the charging current I_CHARGE and the discharging current I_DISCHARGE and based on the operation of Q3 (responsive to VSW). For example, I_CHARGE and I_DISCHARGE are configured to charge and discharge the timing capacitor C1, respectively, to generate the emulated current I_EM.

[0032] FIG. 2 also shows an exemplary charge current generator circuit 122 and a discharge current generator circuit 124. For example, the charge current generator circuit 122 includes a resistor divider circuit of resistor R1 and resistor R2 coupled between an input voltage (VIN) terminal and ground. The output of the divider (e.g., the node between R1 and R2) is coupled to the non-inverting input 210 of amplifier 212. The divider circuit can be configured to provide a divided portion of VIN to the amplifier input 210 according to the ratio of resistor R1 to resistor R2. The amplifier 212 has an output coupled to the gate of a transistor shown as FET Q4. A compensation capacitor C2 is coupled between the amplifier output and ground.

[0033] A charge current source 214 is coupled between a voltage supply terminal VDD and Q4. A variable resistor 140 having a resistance shown as RSLP is coupled between the source of Q4 and ground. As described herein, the resistor 140 has a trim input coupled to the output 138 of the inductor code counter 134. A variable input offset voltage source 216 is coupled between the source of Q4 and the inverting input 218 of amplifier 212. As shown in FIG. 2, the offset voltage source 216 has an input coupled to the output 219 of the charge counter 150 and is configured to provide an input offset voltage VIO1 to the input 218 in response to the charge count value at 219.

[0034] In one example, amplifier 212 is implemented as a transconductance amplifier configured to provide an output current in response to the difference between the voltage at input 210 and the voltage at input 218. Thus, amplifier 212 can provide an output current as a linear function of the differential input voltage at 210 and 218. Charge current source 214 is configured to provide a current I_CHARGE, the value of I_CHARGE varying in response to the resistance RSLP of variable resistor 140. Thus, charge current I_CHARGE varies in accordance with adjusting the resistance RSLP of variable resistor 140 over a plurality of cycles. Charge current generator circuit 122 can be configured to provide charge current I_CHARGE to emulate current generator 114 via one or more current mirrors (not shown). In another example, charge current generator circuit 122 can be used to implement charge current source 204 within emulate current generator 114.

[0035] Discharge current generator circuit 124 can be configured to generate a discharge current I_DISCHARGE in a manner similar to charge current generator circuit 122. Discharge circuit 124 includes a resistor divider circuit of resistor R3 and resistor R4 coupled between an output (VOUT) terminal and ground. The output of the divider (e.g., the node between R3 and R4) is coupled to the non-inverting input 220 of amplifier 222. The divider circuit can be configured to provide a divided portion of output voltage VOUT to amplifier input 220 in accordance with the ratio of resistors R3 and R4. Amplifier 222 has an output coupled to the gate of a transistor shown as FET Q5. Compensation capacitor C3 is coupled between the amplifier output and ground.

[0036] The discharge current source 224 is coupled between the voltage supply terminal VDD and Q5. A variable resistor 142 having a resistor shown as RVAL is coupled between the source of Q5 and ground. As described herein, the resistor 142 has a trim input coupled to the output 138 of the inductor code counter 134, such that RVAL varies in response to the count value at 138. A variable input offset voltage source 226 is coupled between the source of Q5 and the inverting input 228 of the amplifier 222. The offset voltage source 226 has an input coupled to the output 230 of the discharge counter 152. The offset voltage source 226 is configured to provide an input offset voltage VIO2 to the input 228 in response to the discharge count value at 230. The amplifier 222 can be implemented as a transconductance amplifier configured to provide an output current in response to the difference between the voltage at the input 220 and the voltage at the input 228. The discharge current source 224 can be configured to provide a current I_DISCHARGE that varies in response to the resistor RVAL. Therefore, the value of the discharge current I_DISCHARGE changes accordingly by adjusting the resistor RVAL of the variable resistor 140 (142?) over a plurality of cycles.

[0037] As described herein, during a first plurality of cycles when powered on, the inductor code counter 134 is configured to adjust a count value (e.g., representing an inductor code) from an initial value in response to a comparator output signal at 138. The initial value can be set to an initial value such as an intermediate count value or a value near the middle between a minimum count value and a maximum count value. The count value at 138 is used to set the resistance RSLP of resistor 140 and the resistance RVAL of resistor 142 (e.g., by pin strapping). The resistance values of RSLP and RVAL can be set to the same resistance or different resistances in response to the count value at 138. As described herein, the values of the charging current I_CHARGE and the discharging current I_DISCHARGE change in response to respective changes in RSLP and RVAL. The inductor code counter 134 is enabled during the first plurality of cycles (e.g., by a controller), while the charge counter 150 and the discharge counter 152 can be disabled, so that VIO1 and VIO2 remain constant during this phase. Therefore, the inductance detection circuit element 112 can implement a coarse adjustment of the charging current I_CHARGE and the discharging current I_DISCHARGE, and the emulate current I_EM signal becomes sloped over the first phase of the inductance detection process. The first inductance detection phase can be set to a plurality of programmable cycles (e.g., a plurality of PWM cycles, or a period). Alternatively, or as an alternative, the controller 144 can implement the first inductance detection phase until it detects the convergence of I_EM and I_SNS as described herein. The count value at 138 at the end of the first inductance detection phase can be stored in memory, and the controller can disable the inductor code counter 134.

[0038] After the first phase of the inductance detection process is completed, the inductance detection circuit element 112 can implement the second phase of the inductance detection process. For example, the inductance detection circuit element 112 can perform a more refined adjustment of the charging current I_CHARGE and the discharging current I_DISCHARGE over a second plurality of cycles that define the second inductance detection phase. For example, the controller can provide a control signal at 153 to enable the charge counter 150 and the discharge counter 152, while the inductor code counter remains disabled. The charge counter 150 is configured to trim the offset voltage source 216 and adjust VIO1 in response to the comparator output at 138 and the slope clock signal (SLP_CLK). For example, the slope clock signal controls the sampling of I_EM and I_SNS. The discharge counter 152 can also be configured to trim the offset voltage source 226 and adjust VIO2 in response to the comparator output at 138 and the valley clock signal (VAL_CLK). For example, the valley clock signal VAL_CLK controls the sampling of I_EM and I_SNS at a time different from the time used by the charge counter 150.

[0039] Figure 3 shows another example of an inductance detection circuit 300. The inductance detection circuit 300 can be used to implement the inductance detection circuit 112 of FIG. 1 or FIG. 2. Therefore, the description of FIG. 3 also refers to FIGS. 1 and 2. For example, the circuit 300 includes an emulate current generator circuit 114, a charge current generator circuit 122, and a discharge current generator circuit 124.

[0040] In the example of FIG. 3, the charge current generator circuit 122 includes an amplifier 212, and the amplifier 212 has a non-inverting input 210 configured to receive an input voltage VIN (or a voltage derived from VIN). The amplifier 212 has an output coupled to the gate of transistor Q4. A diode-connected transistor Q6 is coupled between the voltage supply terminal VDD and the drain of Q4. A variable resistor 140 is coupled between the source of Q4 and ground. As described herein, the resistor 140 has a trim input configured to receive an inductor code value from the inductor code counter 134. A variable offset voltage source 216 is coupled between the source of Q4 and the inverting input 218 of the amplifier 212. The output of the charge counter 150 is coupled to the variable offset voltage source 216 and is configured to set the voltage VIO1.

[0041] The charge current generator circuit 122 is configured to generate a charge current through Q4 and the resistor 140 in response to the amplifier output signal. A current mirror 302 including Q6 and another FET Q7 is configured to mirror the generated charge current I_CHARGE from the charge current generator circuit 122 to the emulate current generator 114. For example, the output of the current mirror 302 (e.g., the drain of Q7) is coupled to a first terminal of a switch 304 (e.g., shown as FET Q3 in FIG. 2). The switch 304 has a control input configured to receive a switching voltage signal VSW (e.g., at the switching output 106). A timing capacitor C1 is coupled between a second terminal of the switch 304 and ground. The second terminal of the switch 304 is coupled to another current mirror 306, and the other current mirror 306 is configured to mirror the discharge current generated by the discharge current generator circuit 124 to another leg of the emulate current generator 114.

[0042] The discharge current generator circuit 124 includes an amplifier 222, which has a non-inverting input 220 configured to receive an output voltage VOUT, or a voltage derived from VOUT. The amplifier 222 has an output coupled to the gate of Q5. A diode-connected transistor Q8 is coupled between the voltage supply terminal VDD and the drain of Q5. A variable resistor 142 is coupled between the source of Q5 and ground. The resistor 142 has a trim input configured to receive an inductor code value. A variable offset voltage source 226 is coupled between the source of Q5 and the inverting input 228 of the amplifier 222. The output of the discharge counter 152 is coupled to the variable offset voltage source 226 and is configured to set the voltage VIO2. The discharge current generator circuit 124 is configured to generate a discharge current through Q5 and the resistor 142 in response to an output signal at the output of the amplifier 222. A current mirror 308 including Q8 and another FET Q9 is configured to mirror the generated discharge current I_DISCHARGE to the current mirror 306 and ultimately to the emulate current generator 114.

[0043] In the example of FIG. 3, the inductor code counter 134 has a multi-bit output 312 coupled to respective multi-bit inputs of the register 314. The inductor code value can be shifted (e.g., latched) from the counter 134 to the register 314 during a first inductance detection phase. The output 316 of the register 314 (e.g., representing output 138) provides a multi-bit code for setting the resistance of respective variable resistor 140 and variable resistor 142. As described herein, when the first inductance detection phase is complete, the controller 144 can disable the inductor code counter 134 and leave the last final inductor code stored in the register 314. As a result, the resistance value RSLP and the resistance value RVAL remain constant during further operations including a second phase of the inductance detection process. In some examples, the second inductance detection phase is omitted.

[0044] To provide higher accuracy, circuit 300 can implement more refined adjustments for I_CHARGE and I_DISCHARGE. In the example of FIG. 3, circuit 300 includes a charge-side sample and hold (S / H) circuit 320 and circuit 322. Sample and hold circuit 320 has a sample input coupled to current sensor output 130 and a clock input configured to receive a slope sample clock signal (SLPS_CLK). A clock circuit (not shown) can be configured to provide SLPS_CLK to control the sampling of I_SNS and I_EM, such as during a charging cycle. Sample and hold circuit 322 has a sample input coupled to the output 120 of emulate current generator circuit 114 and a clock input configured to receive SLPS_CLK. Circuits 320 and 322 have respective outputs coupled to the non-inverting input and the inverting input of comparator 324 (e.g., an error amplifier). The output of comparator 324 is coupled to the input of charge counter 150 and the input (e.g., input 136) of inductor code counter 134. Counter 134 and counter 150 can each have respective clock inputs configured to receive an update clock signal (UP_CLK) that can be generated once per PWM cycle by an update clock circuit, for example. However, as described herein, during the second inductance detection phase, charge counter 150 can be enabled while inductor code counter 134 is disabled.

[0045] Circuit 300 also includes a discharge - side sample - hold (S / H) circuit 330 and circuit 332. The sample - hold circuit 330 has a sample input coupled to the current sensor output 130 and a clock input configured to receive a valley sample clock signal (VALS_CLK). The sample - hold circuit 332 has a sample input coupled to the output 120 of the emulate current generator circuit 114 and a clock input configured to receive VALS_CLK such that a clock signal CLK1 for sampling the current signals I_SNS and I_EM can be derived therefrom. Circuits 330 and 332 have respective outputs coupled to the non - inverting input and the inverting input of a comparator 334 (e.g., another error amplifier). The output of the comparator 334 is coupled to the input of the discharge counter 152.

[0046] Circuit 300 also includes a DC reset circuit element 340. The DC reset circuit element 340 has one input coupled to the output 120 of the emulate current generator 114 and another input coupled to the current sensor output 130. As an example, the DC reset circuit element 340 includes a switch 342 (e.g., FET) coupled in series with respective buffers 344 and 346 between the output 120 and the output 130. The switch 342 has a control input configured to receive a clock signal (CLK2). The switch 342 is configured to close (e.g., turn on) in response to CLK2 to couple (e.g., short - circuit) the output 130 and the output 120 together. The short - circuit through the switch 342 forces the signal I_SNS and the signal I_EM to be equal, thereby resetting (e.g., making zero) the cumulative AC error in the signal I_SNS and the signal I_EM. The cycle - by - cycle reset by activating the switch 342 in each cycle also helps to track the DC value in the inductor current. In one example, the clock signal CLK2 is asserted to close the switch in each cycle with a certain delay after the low - side switch Q4 (see FIG. 2) is turned on.

[0047] As a further example, FIG. 4 shows a timing diagram 400 regarding signals used to control the inductance detection circuit 300 of FIG. 3. The timing diagram shows a PWM signal 402 as supplied by the control circuit 110. FIG. 4 also shows a low-side on signal 404, a clock signal CLK1, and a clock signal CLK2. The low-side on signal 404 represents the activation of the low-side FET Q2 in the output stage of the power stage. CLK1 includes a slope sampling clock signal SLPS_CLK 406, a valley sampling clock signal VALS_CLK 408, and an update clock signal UP_CLK 410. As described with respect to FIG. 3, SLPS_CLK 406 is used to control the sampling of I_SNS and I_EM by the sample-and-hold circuits 320 and 322 of the charge generator circuit 122. VALS_CLK is used to control the sampling of I_SNS and I_EM by the sample-and-hold circuits 330 and 332 of the discharge generator circuit 124. The update clock signal UP_CLK is used to control when the counter adjustment is made in response to the outputs of the respective comparators 324 and 334. The second clock signal CLK2 is generated to control the reset circuit 340 in each cycle during the inductance detection process, as described herein.

[0048] FIG. 5 shows an exemplary power converter system 500 configured to provide a regulated output voltage VOUT at output 102. System 500 can implement an inductance detector circuit element 112 as described herein with respect to FIGS. 1 - 3. Thus, the description of FIG. 5 also refers to FIGS. 1 - 3. The system includes one or more instances of a power stage 502 having respective switching outputs 106. An inductor L1 is coupled between the switching output 106 and the output 102. The power stage 502 includes an output stage 104 having a high - side switch and a low - side switch coupled between a supply voltage terminal VIN and ground. In the example of FIG. 5, a driver 508 (e.g., a gate driver if switches 504 and 506 are implemented as FETs) has outputs coupled to the control inputs of respective switches 504 and 506. The driver is configured to supply drive signals to turn switches 504 and 506 on and off in response to a PWM signal provided by a control circuit 110. For example, the control circuit 110 is configured to implement one or more control loops for regulating the output voltage VOUT to a reference voltage. The power stage 502 is configured to control the output stage 104 in response to drive signals to provide the output voltage VOUT.

[0049] The power stage 502 can be configured to implement a type of power converter topology (e.g., buck, boost, buck-boost, etc.) according to the requirements of the application example. In some examples, the power converter system 500 includes a plurality of power stages 502 configured as a multi-phase power system, and in a multi-phase power system, each power stage has an inductor coupled to its switching output and the output 102. In a multi-phase power system, each power stage 502 can be configured to implement an inductance detection circuit element 112. In one example, the control circuit 110 can be implemented as an IC chip, and each power stage 502 can be implemented as a respective IC chip having a switching output terminal (e.g., a pin), and an output inductor is coupled to the switching output terminal. In another example, the control circuit 110 and the power stage can be implemented on a single IC chip.

[0050] Figure 6 is a flowchart showing an exemplary method 600 for detecting inductance. This method can be implemented by the inductance detection circuit element 112 shown in FIGS. 1-3 and FIG. 5. Therefore, the description of FIG. 6 also refers to FIGS. 1-3 and FIG. 5. The method 600 begins at 602 when the power converter circuits 100, 200, 300, 500 are powered on in response to, for example, power being supplied from a battery, an inverter, or another power source. At power-on, the counters 134, 150, and 152 can be initialized to respective starting values, such as a maximum count value, or a count value between a maximum count value and a minimum count value.

[0051] At 604, it is determined whether the emulated inductor current I_EM is greater than the sensed inductor current I_SNS. For example, comparators 116, 324, 334 are configured to provide a comparator output signal based on the difference between the emulated inductor current I_EM and the sensed inductor current I_SNS. At 604, if I_EM is greater than I_SNS, the method proceeds to 606 and decreases the slope of the emulated current I_EM. For example, the inductor code counter 134 decrements its count value, whereby the charge current generator circuit 122 and the discharge current generator circuit 124 decrease the slopes of their respective charge current I_CHARGE and discharge current I_DISCHARGE, and thus, the emulated current generator 114 decreases the slope of I_EM accordingly.

[0052] In 604, in response to detecting that I_EM is smaller than I_SNS, the method proceeds to 608 and increases the slope of the emulated current I_EM. For example, in 608, the inductor code counter 134 increments its count value, and as a result, the charge current generator circuit 122 and the discharge current generator circuit 124 increase the slopes of their respective charge current I_CHARGE and discharge current I_DISCHARGE. The emulated current generator 114 increases the slope of I_EM accordingly. The method 600 proceeds from 606 or 608 to 610 to determine whether the inductance detection process is complete. For example, the determination in 610 can be based on a plurality of cycles (e.g., PWM cycles), a fixed period, or detection of convergence (e.g., dithering) between I_EM and I_SNS. If the process is not complete, the method returns to 604 for the next cycle. If it is determined that the process is complete, the method proceeds from 610 to 612. In 612, the inductor code can be set. For example, the last inductor code value from the inductor counter 134 can be stored in memory (e.g., register 314) to fix the slope of the emulated inductor current I_EM. The method can end from 612, or in some examples, the method 600 can further include the next phase of finely tuning the emulated inductor current I_EM, such as by adjusting an adjustable offset in response to I_EM and I_SNS, as described herein.

[0053] FIG. 7 is a graph 700 of current over time showing how the emulate current I_EM and I_SNS change over time (e.g., cycle by cycle) during inductance detection. In the example of FIG. 7, samples of I_EM and samples of I_SNS are shown as dots 702 and dots 704, respectively, for each cycle. The samples of I_EM and the samples of I_SNS can be compared for each cycle. For example, the emulate current 702 starts with a gentle slope in response to, for example, initializing the inductor code counter to its maximum count value. The slope of the emulate current signal I_EM can be increased (indicated by the upward arrow 706) or decreased (indicated by the downward arrow 708) until two samples match (e.g., converge to the same value). The sampled value 702 and the value 704 converge over time, and after several cycles, as shown at 710, the slope of the emulate signal I_EM dithers near the optimal slope. After N cycles in which dithering occurs, the inductor code can be stored in memory (where N is a positive integer).

[0054] FIG. 8 is a graph 800 of simulation results of signals implemented by the inductance detection circuit 112. The graph 800 shows a low-side on signal 802 such as is applied to the gate of Q2, or the control input of switch 506. The graph 800 also shows an emulate current signal 804 and a sense current signal 806 in the exemplary power stage 502 during inductance detection.

[0055] Figure 9 is another graph 900 of simulation results showing the signal implemented by the inductance detection circuit 112. In the example of Figure 9, an enable signal 902 can be provided by the controller 144 to enable the inductor code counter 134. A count signal 904 can be provided by the comparator 134 to command the inductor code counter 134 to count up or count down to provide a multi-bit count value indicated by 906. For example, graph 900 also shows a sensed current signal 910 and an emulated current signal 912 over a plurality of cycles during inductance detection. As shown in the graph, the counter signal 906 can be adjusted at each cycle in response to the comparison of the emulated current 912 and the sensed current 910.

[0056] In this description, the term "coupled" means either an indirect connection or a direct connection. Therefore, when a first device is coupled to a second device, the connection can be by a direct connection or by an indirect connection through other devices and connections. For example, if device A generates a signal to control device B to perform a certain action, (a) in a first example, device A is coupled to device B, or (b) in a second example, if an intervening component C does not change the functional relationship between device A and device B, device A is coupled to device B through the intervening component C, and therefore, device B is controlled by device A through the control signal generated by device A.

[0057] The description "based on" means "at least partially based on". Therefore, when X is based on Y, X can be a function of Y and any number of other factors.

[0058] Within the scope of the claims, modifications to the described embodiments are possible, and other embodiments are also possible.

Claims

1. It is a circuit, An emulated current generator having an output, A current sensor having an output, A comparator having a first input coupled to the output of the emulated current generator, a second input coupled to the output of the current sensor, and an output, A counter having an input and an output coupled to the output of the comparator, A charging circuit having an input coupled to the output of the comparator, the charging circuit including a first variable resistor having a trim input coupled to the output of the counter, A discharge circuit having an input coupled to the output of the comparator, the discharge circuit including a second variable resistor having a trim input coupled to the output of the comparator, A circuit that includes this.

2. The circuit according to claim 1, The emulated current generator is configured to provide an emulated current signal representing the emulated current through the inductor to the output of the emulated current generator, The current sensor is configured to provide a sensed current signal representing a measured value of the current through the inductor to the output of the current sensor. The comparator is configured to provide a comparator signal to the output of the comparator in response to the emulated current signal and the sensed current signal. The counter is configured to adjust the inductor code value at the output of the counter in response to the comparator signal. A circuit in which the resistance of the first variable resistor and the resistance of the second variable resistor are set in response to the inductor code value.

3. The circuit according to claim 2, A circuit further comprising a controller having an input and a first output coupled to the enable input of the counter, the controller being configured to provide a control signal to the first output to enable the counter in response to a voltage in the input.

4. The circuit according to claim 3, The controller is further configured to activate the counter for a duration in response to (1) multiple cycles of a pulse-width modulated signal, or (2) the difference between the emulated current signal and the sensed current signal is less than a threshold.

5. The circuit according to claim 3, The aforementioned charging circuit A charge counter having an input and an output coupled to the output of the comparator, A first offset voltage source having a trim input coupled to the output of the charge counter and an output coupled to the first variable resistor, It further includes, The discharge circuit, A discharge counter having an input coupled to the output of the comparator and an output, A second offset voltage source having a trim input coupled to the output of the discharge counter and an output coupled to the second variable resistor, A circuit that further includes the following.

6. The circuit according to claim 5, The charging counter is configured to set a first variable offset voltage for the charging circuit in response to a signal at the output of the charging counter. A circuit in which the discharge counter is configured to set a second variable offset voltage for the discharge circuit in response to a signal at the output of the discharge counter.

7. The circuit according to claim 5, A circuit wherein the controller further has a second output that is coupled to the inputs of the charge counter and the discharge counter, respectively.

8. The circuit according to claim 7, The aforementioned controller During the first part of the inductance detection phase, the counter is enabled, and the charge counter and the discharge counter are disabled. During the second portion of the inductance detection phase, the counter is disabled and the charge counter and the discharge counter are enabled. A circuit further configured in this way.

9. The circuit according to claim 1, The aforementioned output stage, The output stage further includes a high-side switch coupled between a voltage supply terminal and a switching output terminal and a low-side switch coupled between the switching output terminal and a ground terminal, A circuit in which the current sensor is coupled to the low-side switch and is configured to provide a sensed current signal representing the current through an inductor coupled to the switching output terminal when the low-side switch is turned on.

10. The circuit according to claim 9, The emulated current generator, The first current source and A third switch having a control input, which is coupled in series with the first current source between the first voltage terminal and the output of the emulated current generator, A second current source coupled between the output of the emulated current generator and the ground terminal, A capacitor is coupled between the output of the emulated current generator and the ground terminal, A detector having an input coupled to the switching output terminal and an output coupled to the control input of the third switch, wherein the detector is configured to activate the third switch in response to a voltage at the switching output terminal, A circuit that includes this.

11. The circuit according to claim 9, An inductor coupled to the switching output terminal, A gate driver having a pulse width modulation (PWM) input and driver outputs coupled to the control inputs of the low-side and high-side switches, A power control circuit having a PWM output coupled to the PWM input, wherein the power control circuit is configured to provide a PWM control signal to the gate driver in order to provide a regulated voltage to VOUT, A circuit that further includes the following.

12. The circuit according to claim 11, A circuit further comprising a reset circuit coupled between the output of the emulated current generator and the output of the current sensor, the reset circuit being configured to connect the output of the emulated current generator and the output of the current sensor in response to a clock signal.

13. The circuit according to claim 1, A circuit in which the emulated current generator, the current sensor, the comparator, the counter, the charging circuit, and the discharging circuit are mounted on a semiconductor substrate of an integrated circuit.

14. It is a circuit, An emulated current generator including a switching voltage detector, configured to provide an emulated current signal representing an emulated current via an output inductor in response to a charging current and a discharging current that charge or discharge a capacitor, respectively, A comparator configured to provide a comparator signal in response to the emulated current signal and a sensed current signal representing a measured value of the current through the output inductor, A counter configured to adjust the inductor code count value in response to the comparator signal, Includes, A circuit in which the slope of the emulated current signal is adjusted in response to the inductor code count value.

15. The circuit according to claim 14, A charging current generator including a first variable resistor having a resistance set in response to the inductor code count value, the charging current generator being configured to provide the charging current having a value in response to the resistance of the first variable resistor, A discharge current generator including a second variable resistor having a resistance set in response to the inductor code count value, configured to provide the discharge current having a value in response to the resistance of the second variable resistor, A circuit that further includes the following.

16. The circuit according to claim 15, The circuit further includes a controller configured to provide a control signal for enabling the counter in response to a voltage at a power terminal.

17. The circuit according to claim 16, The controller is further configured to activate the counter during an inductance detection phase having at least one of the following: (1) a duration corresponding to a plurality of cycles of a pulse-width modulated signal, or (2) a duration corresponding to a duration corresponding to the difference between the emulated current signal and the sensed current signal being less than a threshold.

18. The circuit according to claim 16, The charging current generator further includes a first variable offset voltage source and a charging counter, wherein the charging counter is configured to set the voltage of the first variable offset voltage source in response to a first sample of the emulated current and the sensed current. The discharge current generator circuit further includes a second variable offset voltage source and a discharge counter, wherein the discharge counter is configured to set the voltage of the second variable offset voltage source in response to a second sample of the emulated current and the sensed current.

19. The circuit according to claim 18, The aforementioned controller During the first part of the inductance detection phase, the counter is enabled, and the charge counter and the discharge counter are disabled. During the second portion of the inductance detection phase, the counter is disabled and the charge counter and the discharge counter are enabled. A circuit further configured in this way.

20. The circuit according to claim 19, The circuit further includes a reset circuit configured to short-circuit the emulated current signal and the sensed current signal together for a portion of the time of each cycle of the inductance detection phase.

21. The circuit according to claim 14, An output stage including a high-side switch coupled between a switching output terminal connected to the output inductor and a voltage supply terminal, and a low-side switch coupled between the switching output terminal and a ground terminal, A driver configured to control the high-side switch and the low-side switch in response to a pulse width modulation control signal, A current sensor coupled to the low-side switch, configured to provide a sensing current signal representing a measured value of the current through the output inductor when the low-side switch is turned on, A circuit that further includes the following.

22. The circuit according to claim 21, The emulated current generator, A first current source configured to provide the aforementioned charging current, A second current source coupled to the output of the emulated current generator, configured to provide the discharge current, A switch coupled between the first current source and the second current source, configured to connect the first current source to the output of the emulated current generator, A capacitor is coupled between the output of the emulated current generator and the ground terminal, A detector configured to activate the switch such that the emulated current is provided in response to the switching voltage at the switching output terminal, A circuit that includes this.

23. It is a system, Inductor and Power stage, A first switch coupled to the inductor, A second switch coupled to the first switch and the inductor, A driver configured to control the first and second switches in response to a pulse width modulation control signal, An inductance detection circuit, An emulated current generator having an output, A comparator having a first input coupled to the output of the emulated current generator, a second input configured to receive a measurement of the current through the inductor, and an output, A counter having an input and an output coupled to the output of the comparator, A charging circuit having an input coupled to the output of the comparator, the charging circuit including a first variable resistor having a trim input coupled to the output of the counter, A discharge circuit having an input coupled to the output of the comparator, comprising a second variable resistor having a trim input coupled to the output of the comparator, The inductance detection circuit includes, The power stage includes, A system that includes this.

24. The system according to claim 23, The present invention further includes a current sensor configured to provide a sensed current signal representing a measured value of the current through the inductor, The emulated current generator is configured to provide an emulated current signal representing the emulated current through the inductor to the output. The comparator is configured to provide a comparator signal to the output in response to the emulated current signal and the sensed current signal. The counter is configured to adjust the inductor code value at the output in response to the comparator signal. A system in which the resistance of the first variable resistor and the resistance of the second variable resistor are set in response to the inductor code value.

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