Imaging apparatus

Abstract

To provide a semiconductor device capable of performing authentication in a short time.SOLUTION: A semiconductor device comprising: a light-emitting device; and an imaging device. The imaging device includes a row driver circuit, and the row driver circuit includes first to m-th latch circuits (m is an integer of 2 or more) and first to m-th register circuits. A first start pulse signal is input to the first latch circuit, and a second start pulse signal is input to the first to m-th latch circuits. Scan signals output from the first to m-1-th register circuits are input to the second to m-th latch circuits, respectively. The first latch circuit has a function of outputting one of a first start pulse signal and a second start pulse signal to the first register circuit in accordance with the retained data. The second to m-th latch circuits have a function of outputting one of a scan signal and a second start pulse signal to the second to m-th register circuits in accordance with the retained data.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] 1. Field of the Invention

[0003] One embodiment of the present invention relates to a semiconductor device and a driving method thereof. One embodiment of the present invention relates to a semiconductor device including a light-emitting device and an imaging device and a driving method thereof. One embodiment of the present invention relates to an imaging device and a driving method thereof. One embodiment of the present invention relates to an electronic device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. Examples of the technical field of one embodiment of the present invention disclosed in this specification and the like include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, electronic devices, lighting devices, input devices (e.g., touch sensors), input / output devices (e.g., touch panels), and operation methods thereof or manufacturing methods thereof. A semiconductor device refers to any device that can function by utilizing semiconductor characteristics. [Background technology]

[0003] While imaging devices have traditionally been installed in devices such as digital cameras, the widespread use of mobile information terminals such as smartphones and tablet devices has led to a demand for improved performance, smaller size, and lower cost. Furthermore, imaging devices are now used for a variety of purposes, including not only taking photographs or videos but also biometric authentication such as face authentication, fingerprint authentication, and vein authentication, or as input devices such as touch sensors and motion sensors. Patent Document 1 discloses an electronic device such as a smartphone that is capable of fingerprint authentication. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 2019-79415 Summary of the Invention [Problem to be solved by the invention]

[0005] One method of fingerprint authentication, which is one form of authentication, is to irradiate light onto a finger from a light-emitting element and detect the light reflected by the finger with a light-receiving element. In this case, fingerprint authentication can be performed with high accuracy by taking time to perform fingerprint authentication. However, if authentication such as fingerprint authentication takes a long time, it can be stressful for the person being authenticated.

[0006] An object of one embodiment of the present invention is to provide a semiconductor device that can perform authentication in a short time and a driving method thereof.An object of one embodiment of the present invention is to provide a semiconductor device that can perform authentication with high accuracy and a driving method thereof.An object of one embodiment of the present invention is to provide a highly reliable semiconductor device and a driving method thereof.An object of one embodiment of the present invention is to provide a novel semiconductor device and a driving method thereof.

[0007] Another object of the present invention is to provide an imaging device that can perform authentication in a short time and a driving method thereof.Another object of the present invention is to provide an imaging device that can perform authentication with high accuracy and a driving method thereof.Another object of the present invention is to provide a highly reliable imaging device and a driving method thereof.Another object of the present invention is to provide a novel imaging device and a driving method thereof.

[0008] Note that the description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of these problems. Note that problems other than these can be extracted from the description in the specification, drawings, claims, etc. [Means for solving the problem]

[0009] One embodiment of the present invention is a semiconductor device including a light-emitting device and an imaging device. The imaging device includes a first register circuit, a second register circuit, and a latch circuit. The first register circuit has a function of outputting a scan signal. The scan signal and a start pulse signal are input to the latch circuit. The latch circuit has a function of outputting one of the scan signal and the start pulse signal to the second register circuit based on data held in the latch circuit.

[0010] Alternatively, in the above embodiment, the first register circuit, the second register circuit, and the latch circuit may each include a transistor, and the transistor may include a metal oxide in a channel formation region.

[0011] Alternatively, one embodiment of the present invention is a semiconductor device including a light-emitting device and an imaging device. The imaging device includes first to m-th latch circuits (m is an integer greater than or equal to 2) and first to m-th register circuits. A first start pulse signal is input to the first latch circuit, a second start pulse signal is input to the first to m-th latch circuits, and scanning signals output from the first to m-1-th register circuits are input to the second to m-th latch circuits, respectively. The first latch circuit has a function of outputting one of the first start pulse signal or the second start pulse signal to the first register circuit based on data held in the first latch circuit. The second to m-th latch circuits have a function of outputting one of the scanning signal or the second start pulse signal to the second to m-th register circuits based on data held in the second to m-th latch circuits, respectively.

[0012] Alternatively, in the above aspect, the imaging device may have a function of operating in a first mode in which a first latch circuit outputs a first start pulse signal and the second to mth latch circuits output scanning signals, and the imaging device may have a function of operating in a second mode in which any of the first to mth latch circuits outputs a second start pulse signal, and the transmission speed of the scanning signal in the first mode may be faster than the transmission speed of the scanning signal in the second mode.

[0013] Alternatively, in the above aspect, in the second mode, the first latch circuit may not output the first start pulse signal.

[0014] Alternatively, in the above aspect, in the second mode, when the pth latch circuit (p is an integer between 2 and m) outputs the second start pulse signal, the first latch circuit may not output either the first start pulse signal or the second start pulse signal, and the second to p-1th latch circuits may not output either the scanning signal or the second start pulse signal.

[0015] Alternatively, in the above aspect, the imaging device may have a pixel section in which pixels are arranged in a matrix of m rows and n columns (n ​​is an integer greater than or equal to 1), a detection circuit, and a control circuit, wherein the detection circuit has a function of detecting an object contacting the pixel section, and the control circuit has a function of generating data to be written to the first to mth latch circuits based on the detection result.

[0016] Alternatively, in the above aspect, the first to m-th latch circuits and the first to m-th register circuits may each include a transistor, and the transistor may include a metal oxide in a channel formation region.

[0017] An electronic device including a semiconductor device according to one embodiment of the present invention and an operation button is also one embodiment of the present invention.

[0018] Another embodiment of the present invention is a method for driving a semiconductor device including a light-emitting device and an imaging device, the imaging device including a shift register circuit in which first to m-th latch circuits (m is an integer of 2 or more) and first to m-th register circuits are alternately connected in series, the method including: inputting a first start pulse signal to the first register circuit via the first latch circuit in a first period; outputting a first scan signal from the first register circuit in a second period; and sequentially transmitting the first scan signal to the second to m-th register circuits via the second to m-th latch circuits; In a third period, a first start pulse signal is input to a first latch circuit, and then data is written to a pth latch circuit (p is any integer between 1 and m inclusive); in a fourth period, a second start pulse signal is input to a pth register circuit via the pth latch circuit; in a fifth period, the pth register circuit outputs a second scanning signal, and the second scanning signal is transmitted to the p+1th register circuit via the p+1th latch circuit, and the transmission speed of the first scanning signal is faster than the transmission speed of the second scanning signal.

[0019] Alternatively, in the above aspect, the imaging device may have a pixel portion in which pixels are arranged in a matrix of m rows and n columns (n ​​is an integer greater than or equal to 1), and before the start of a first period, the pixels acquire imaging data, and during a second period, the shift register circuit sequentially supplies a selection signal for selecting a pixel from which imaging data is to be read to the pixels in the first to mth rows in correspondence with a first scanning signal, and after the end of the second period, the semiconductor device detects the position of an object contacting the pixel portion based on the imaging data, and during a third period, the latch circuit to which data is to be written may be determined based on the position of the object.

[0020] Alternatively, in the above aspect, the semiconductor device may perform authentication after the fifth period ends.

[0021] Alternatively, in the above aspect, the first to m-th latch circuits and the first to m-th register circuits may each include a transistor, and the transistor may include a metal oxide in a channel formation region.

[0022] Another embodiment of the present invention is an imaging device including a first register circuit, a second register circuit, and a latch circuit. The first register circuit has a function of outputting a scan signal. The scan signal and a start pulse signal are input to the latch circuit. The latch circuit has a function of outputting one of the scan signal and the start pulse signal to the second register circuit based on data held in the latch circuit.

[0023] Alternatively, in the above embodiment, the first register circuit, the second register circuit, and the latch circuit may each include a transistor, and the transistor may include a metal oxide in a channel formation region.

[0024] Alternatively, one embodiment of the present invention is an imaging device including first to m-th latch circuits (m is an integer of 2 or more) and first to m-th register circuits, in which a first start pulse signal is input to the first latch circuit, a second start pulse signal is input to the first to m-th latch circuits, scanning signals output from the first to m-1-th register circuits are input to the second to m-th latch circuits, respectively, and the first latch circuit has a function of outputting one of the first start pulse signal or the second start pulse signal to the first register circuit based on data held in the first latch circuit, and the second to m-th latch circuits have a function of outputting one of the scanning signal or the second start pulse signal to the second to m-th register circuits based on data held in the second to m-th latch circuits, respectively.

[0025] Alternatively, in the above aspect, the imaging device may have a function of operating in a first mode in which a first latch circuit outputs a first start pulse signal and the second to mth latch circuits output scanning signals, and the imaging device may have a function of operating in a second mode in which any of the first to mth latch circuits outputs a second start pulse signal, and the transmission speed of the scanning signal in the first mode may be faster than the transmission speed of the scanning signal in the second mode.

[0026] Alternatively, in the above aspect, in the second mode, the first latch circuit may not output the first start pulse signal.

[0027] Alternatively, in the above aspect, in the second mode, when the pth latch circuit (p is an integer between 2 and m) outputs the second start pulse signal, the first latch circuit may not output either the first start pulse signal or the second start pulse signal, and the second to p-1th latch circuits may not output either the scanning signal or the second start pulse signal.

[0028] Alternatively, in the above aspect, the imaging device may have a pixel section in which pixels are arranged in a matrix of m rows and n columns (n ​​is an integer greater than or equal to 1), a detection circuit, and a control circuit, wherein the detection circuit has a function of detecting an object contacting the pixel section, and the control circuit has a function of generating data to be written to the first to mth latch circuits based on the detection result.

[0029] Alternatively, in the above aspect, the first to m-th latch circuits and the first to m-th register circuits may each include a transistor, and the transistor may include a metal oxide in a channel formation region.

[0030] An electronic device including the imaging device of one embodiment of the present invention and an operation button is also one embodiment of the present invention.

[0031] Another embodiment of the present invention is a method for driving an imaging device including a shift register circuit in which first to m-th latch circuits (m is an integer greater than or equal to 2) and first to m-th register circuits are alternately connected in series, the method including: inputting a first start pulse signal to the first register circuit through the first latch circuit in a first period; outputting a first scanning signal from the first register circuit in a second period; and sequentially transmitting the first scanning signal to the second to m-th register circuits through the second to m-th latch circuits in a third period. a first start pulse signal is input to the pth latch circuit, and then data is written to the pth latch circuit (p is any integer between 1 and m inclusive); in a fourth period, a second start pulse signal is input to the pth register circuit via the pth latch circuit; in a fifth period, the pth register circuit outputs a second scanning signal, and the second scanning signal is transmitted to the p+1th register circuit via the p+1th latch circuit, and the transmission speed of the first scanning signal is faster than the transmission speed of the second scanning signal.

[0032] Alternatively, in the above aspect, the imaging device may have a pixel section in which pixels are arranged in a matrix of m rows and n columns (n ​​is an integer greater than or equal to 1), and before the start of a first period, the pixels acquire imaging data, and during a second period, the shift register circuit sequentially supplies a selection signal for selecting a pixel from which imaging data is to be read to the pixels in the first to mth rows in correspondence with a first scanning signal, and after the end of the second period, the imaging device detects the position of an object contacting the pixel section based on the imaging data, and during a third period, the latch circuit to which data is to be written may be determined based on the position of the object.

[0033] Alternatively, in the above aspect, the imaging device may perform authentication after the fifth period ends.

[0034] Alternatively, in the above aspect, the first to m-th latch circuits and the first to m-th register circuits may each include a transistor, and the transistor may include a metal oxide in a channel formation region. [Effects of the Invention]

[0035] According to one embodiment of the present invention, a semiconductor device capable of performing authentication in a short time and a driving method thereof can be provided. Alternatively, a semiconductor device capable of performing authentication with high accuracy and a driving method thereof can be provided. Alternatively, a highly reliable semiconductor device and a driving method thereof can be provided. Alternatively, a novel semiconductor device and a driving method thereof can be provided.

[0036] Alternatively, it is possible to provide an imaging device that can perform authentication in a short time and a driving method thereof. Alternatively, it is possible to provide an imaging device that can perform authentication with high accuracy and a driving method thereof. Alternatively, it is possible to provide an imaging device that is highly reliable and a driving method thereof. Alternatively, it is possible to provide a novel imaging device and a driving method thereof.

[0037] Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of these effects. Note that effects other than these can be extracted from the description in the specification, drawings, claims, etc. [Brief explanation of the drawings]

[0038] [Figure 1] 1A and 1B are schematic diagrams showing configuration examples of a semiconductor device. [Figure 2] Fig. 2A is a block diagram showing an example of the configuration of an imaging device, Fig. 2B1 is a circuit diagram showing an example of the configuration of an imaging device, and Fig. 2B2 is a timing chart showing an example of a method of driving the imaging device. [Figure 3] FIG. 3 is a block diagram showing an example of the configuration of a row driver circuit. [Figure 4] 4A and 4B are circuit diagrams showing configuration examples of register circuits. [Figure 5] 5A1, 5A2, 5B1, and 5B2 are circuit diagrams showing examples of the configuration of a latch circuit. [Figure 6] 6A and 6B are schematic diagrams showing an example of a method for driving a row driver circuit. [Figure 7] FIG. 7 is a timing chart showing an example of a method for driving the row driver circuit. [Figure 8] FIG. 8 is a timing chart showing an example of a method for driving the row driver circuit. [Figure 9] FIG. 9 is a timing chart showing an example of a method for driving the row driver circuit. [Figure 10] FIG. 10 is a block diagram showing an example of the configuration of a row driver circuit. [Figure 11] 11A and 11B are circuit diagrams showing configuration examples of register circuits. [Figure 12] FIG. 12 is a timing chart showing an example of a method for driving the row driver circuit. [Figure 13] FIG. 13 is a timing chart showing an example of a method for driving the row driver circuit. [Figure 14] FIG. 14 is a timing chart showing an example of a method for driving the row driver circuit. [Figure 15] FIG. 15 is a block diagram showing an example of the configuration of a row driver circuit. [Figure 16] 16A and 16B are circuit diagrams showing configuration examples of multiplexer circuits. [Figure 17] FIG. 17A and FIGS. 17B1 to 17B3 are circuit diagrams showing configuration examples of demultiplexer circuits. [Figure 18] FIG. 18 is a timing chart showing an example of a method for driving the row driver circuit. [Figure 19] FIG. 19 is a timing chart showing an example of a method for driving a row driver circuit. [Figure 20] FIG. 20 is a block diagram showing an example of the configuration of a row driver circuit. [Figure 21] FIG. 21 is a timing chart showing an example of a method for driving a row driver circuit. [Figure 22] FIG. 22 is a timing chart showing an example of a method for driving the row driver circuit. [Figure 23] FIG. 23 is a block diagram showing an example of the configuration of a row driver circuit. [Figure 24] FIG. 24 is a timing chart showing an example of a method for driving the row driver circuit. [Figure 25] FIG. 25 is a timing chart showing an example of a method for driving a row driver circuit. [Figure 26] FIG. 26 is a block diagram showing an example of the configuration of a row driver circuit. [Figure 27] FIG. 27 is a block diagram showing an example of the configuration of a row driver circuit. [Figure 28] Fig. 28A is a block diagram showing an example of terminals electrically connected to a register circuit and a signal supply circuit, and Fig. 28B is a diagram showing the connection relationship of the register circuit. [Figure 29] 29A and 29B are circuit diagrams showing configuration examples of register circuits. [Figure 30] FIG. 30 is a timing chart showing an example of a method for driving a row driver circuit. [Figure 31] FIG. 31 is a timing chart showing an example of a method for driving a row driver circuit. [Figure 32] FIG. 32 is a block diagram showing a configuration example of a semiconductor device. [Figure 33] FIG. 33 is a block diagram showing a configuration example of a semiconductor device. [Figure 34] 34A to 34C are circuit diagrams showing examples of pixel configurations. [Figure 35] FIG. 35 is a cross-sectional view showing a configuration example of a semiconductor device. [Figure 36] 36A to 36C are cross-sectional views showing configuration examples of a semiconductor device. [Figure 37] 37A and 37B are cross-sectional views showing configuration examples of a semiconductor device. [Figure 38] FIG. 38 is a perspective view showing a configuration example of a semiconductor device. [Figure 39] FIG. 39 is a cross-sectional view showing a configuration example of a semiconductor device. [Figure 40] Fig. 40A is a diagram explaining the classification of IGZO crystal structures. Fig. 40B is a diagram explaining the XRD spectrum of a quartz glass substrate. Fig. 40C is a diagram explaining the XRD spectrum of a crystalline IGZO film. Fig. 40D is a diagram explaining the electron microbeam diffraction pattern of a quartz glass substrate. Fig. 40E is a diagram explaining the electron microbeam diffraction pattern of a crystalline IGZO film. [Figure 41] 41A to 41D are diagrams showing an example of an electronic device. [Figure 42] 42A and 42B are graphs showing the change in potential over time. [Figure 43] 43A and 43B are graphs showing the change in potential over time. [Figure 44] 44A and 44B are graphs showing the change in potential over time. [Figure 45] FIG. 45 is a block diagram illustrating a configuration of an imaging device according to an embodiment. [Figure 46] 46A to 46C are graphs showing the change in potential over time. [Figure 47] 47A to 47D are graphs showing the change in potential over time. DETAILED DESCRIPTION OF THE INVENTION

[0039] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be readily understood by those skilled in the art that various changes can be made in form and detail without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments shown below. In the configuration of the invention described below, the same parts or parts having similar functions will be denoted by the same reference numerals in different drawings, and repeated descriptions thereof will be omitted.

[0040] Furthermore, the position, size, range, etc. of each component shown in the drawings, etc. may not represent the actual position, size, range, etc. in order to facilitate understanding of the invention. Therefore, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings, etc. For example, in an actual manufacturing process, a resist mask, etc. may be unintentionally eroded by a process such as etching, but this may not be reflected in the drawings in order to facilitate understanding.

[0041] Furthermore, the terms "electrode" and "wiring" used in this specification and the like do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wiring," and vice versa. Furthermore, the terms "electrode" and "wiring" also include cases where, for example, multiple "electrodes" or "wirings" are integrally formed.

[0042] In this specification and the like, the resistance value of a "resistor" may be determined by the length of the wiring, or by connecting a conductive layer having a different resistivity from the conductive layer used in the wiring, or by doping an impurity into a semiconductor layer.

[0043] In this specification, a "terminal" in an electric circuit refers to a portion where a current is input or output, a voltage is input or output, or a signal is received or transmitted. Therefore, a part of a wiring or an electrode may function as a terminal.

[0044] In this specification, the terms "above," "upper," "lower," or "below" do not limit the positional relationship of components to being directly above or below and in direct contact with each other. For example, the expression "electrode B on insulating layer A" does not require that electrode B be formed in direct contact with insulating layer A, and does not exclude cases where other components are included between insulating layer A and electrode B. Furthermore, the expression "conductive layer D above conductive layer C" does not require that conductive layer D be formed in direct contact with conductive layer C, and does not exclude cases where other components are included between conductive layer C and conductive layer D. Furthermore, "above" or "lower" does not exclude cases where components are arranged in an oblique direction.

[0045] In addition, the functions of the source and drain are interchangeable depending on operating conditions, such as when transistors of different polarities are used or when the direction of current changes during circuit operation, making it difficult to define which is the source and which is the drain. For this reason, the terms source and drain can be used interchangeably in this specification.

[0046] Furthermore, in this specification, "electrically connected" includes both direct connection and connection via "something that has some kind of electrical action." Here, "something that has some kind of electrical action" is not particularly limited as long as it allows for the exchange of electrical signals between the connected objects. Therefore, even when the expression "electrically connected" is used, in an actual circuit, there may be no physical connection and only an extending wiring. Furthermore, even when the expression "directly connected" is used, it includes cases where wiring is formed on different conductive layers via contacts. Therefore, in wiring, there may be cases where different conductive layers contain one or more of the same elements or different elements.

[0047] In this specification, when referring to counting values ​​and measurement values, terms such as "same," "equal," "uniform," etc. are used, they are considered to include an error of plus or minus 20% unless otherwise specified.

[0048] Furthermore, voltage often refers to the potential difference between a certain potential and a reference potential (for example, ground potential or source potential). Therefore, voltage and potential can often be interchanged. In this specification and the like, unless otherwise specified, voltage and potential can be interchanged.

[0049] It should be noted that even when written as a "semiconductor," if the conductivity is sufficiently low, it will have the properties of an "insulator." Therefore, it is also possible to use "semiconductor" instead of "insulator." In this case, the boundary between "semiconductor" and "insulator" is vague, and it is difficult to strictly distinguish between the two. Therefore, "semiconductor" and "insulator" described in this specification may be read interchangeably.

[0050] Furthermore, even when written as "semiconductor," if the conductivity is sufficiently high, it will have the properties of a "conductor." Therefore, it is also possible to use "semiconductor" instead of "conductor." In this case, the boundary between "semiconductor" and "conductor" is vague, and it is difficult to strictly distinguish between the two. Therefore, "semiconductor" and "conductor" described in this specification may be read interchangeably.

[0051] Note that ordinal numbers such as "first" and "second" used in this specification are used to avoid confusion between components and do not indicate any order or ranking, such as the order of processes or stacking. Furthermore, even if a term does not have an ordinal number in this specification, an ordinal number may be added in the claims to avoid confusion between components. Furthermore, even if a term has an ordinal number in this specification, a different ordinal number may be added in the claims. Furthermore, even if a term has an ordinal number in this specification, the ordinal number may be omitted, for example, in the claims.

[0052] In this specification and the like, the "on state" of a transistor refers to a state in which the source and drain of the transistor are considered to be electrically short-circuited (also referred to as a "conducting state"). The "off state" of a transistor refers to a state in which the source and drain of the transistor are considered to be electrically disconnected (also referred to as a "non-conducting state"). For example, a transistor in an on state can operate in a linear region.

[0053] In this specification, the term "on-state current" may refer to a current that flows between the source and drain of a transistor when the transistor is on, and the term "off-state current" may refer to a current that flows between the source and drain of a transistor when the transistor is off.

[0054] In this specification and the like, a gate refers to a gate electrode and a part or the whole of a gate wiring. A gate wiring refers to a wiring for electrically connecting the gate electrode of at least one transistor to another electrode or another wiring.

[0055] In this specification, the term "source" refers to a source region, a source electrode, and part or all of a source wiring. The term "source region" refers to a region of a semiconductor layer having a resistivity equal to or lower than a certain value. The term "source electrode" refers to a conductive layer connected to a source region. The term "source wiring" refers to wiring for electrically connecting the source electrode of at least one transistor to another electrode or another wiring.

[0056] In this specification, the term "drain" refers to a drain region, a drain electrode, and part or all of a drain wiring. The term "drain region" refers to a region of a semiconductor layer whose resistivity is equal to or less than a certain value. The term "drain electrode" refers to a conductive layer connected to the drain region. The term "drain wiring" refers to wiring for electrically connecting the drain electrode of at least one transistor to another electrode or another wiring.

[0057] (Embodiment 1) In this embodiment, a semiconductor device according to one embodiment of the present invention will be described.

[0058] A semiconductor device according to one embodiment of the present invention includes a light-emitting device and an imaging device. The light-emitting device has a function of emitting, for example, infrared light or visible light. The imaging device has a function of detecting light. For example, a detection target can be irradiated with light emitted from the light-emitting device, and the imaging device can detect light reflected by the detection target. If the detection target is, for example, a finger of a user of the semiconductor device according to one embodiment of the present invention, the semiconductor device according to one embodiment of the present invention can perform fingerprint authentication or the like.

[0059] An imaging device included in a semiconductor device according to one embodiment of the present invention includes a pixel portion in which pixels are arranged in a matrix and a row driver circuit having a function of selecting, for each row, pixels from which image data is to be read.

[0060] For example, when fingerprint authentication is performed using the semiconductor device of one embodiment of the present invention, a row driver circuit first selects pixels in all rows and reads out first image data. This allows, for example, the position of a finger in contact with a pixel portion to be detected. Next, the row driver circuit selects only pixels in the row in contact with the finger and in rows surrounding the selected row and reads out second image data. In this way, the semiconductor device of one embodiment of the present invention performs fingerprint authentication.

[0061] Here, when reading out the first imaging data, it is only necessary to detect the position of a finger, and fingerprint authentication is not required. Therefore, the readout period per pixel row can be shorter than when fingerprint authentication is performed. On the other hand, when reading out the second imaging data, fingerprint authentication is required, so the readout period per pixel row is longer than when reading out the first imaging data. In the semiconductor device of one embodiment of the present invention, the pixels from which the second imaging data is read out for fingerprint authentication can be only a portion of the pixels provided in the pixel portion. Therefore, fingerprint authentication can be performed in a shorter time than when the second imaging data is read out from all the pixels. Furthermore, even if it takes a long time to read out the second imaging data, the time required for fingerprint authentication, for example, the total time required to read out the first imaging data and the second imaging data, can be prevented from being significantly longer. Therefore, the semiconductor device of one embodiment of the present invention can perform fingerprint authentication in a short time with high accuracy.

[0062] <Configuration example of semiconductor device_1> 1A is a diagram showing an example of the configuration of a semiconductor device 10. The semiconductor device 10 has a substrate 11 and a substrate 12, and a light emitting device 13 and an imaging device 15 are provided between the substrates 11 and 12.

[0063] The light emitting device 13 has a function of emitting light 23. The light 23 can be infrared light or visible light.

[0064] The imaging device 15 has a function of detecting the irradiated light 25. Specifically, the imaging device 15 is provided with a light receiving element, and has a function of detecting the light 25 irradiated to the light receiving element.

[0065] In this specification, the term "element" can be appropriately replaced with "device." For example, a light-receiving element can be called a light-receiving device.

[0066] The light receiving element can be a photoelectric conversion element that detects incident light and generates an electric charge. The amount of electric charge generated by the light receiving element is determined based on the amount of incident light. For example, a pn-type or pin-type photodiode can be used as the light receiving element.

[0067] As the light receiving element, it is preferable to use an organic photodiode having an organic compound in a photoelectric conversion layer. Organic photodiodes can be easily made thin, lightweight, and large in area. In addition, they have a high degree of freedom in shape and design, so they can be applied to various imaging devices. Alternatively, photodiodes using amorphous silicon, crystalline silicon (single crystal silicon, polycrystalline silicon, microcrystalline silicon, etc.), metal oxides, etc. can also be used as the light receiving element.

[0068] When an organic compound is used in the photoelectric conversion layer of a photodiode, sensitivity from ultraviolet light to infrared light can be achieved by appropriately selecting the material. When amorphous silicon is used in the photoelectric conversion layer, sensitivity is mainly to visible light, and when crystalline silicon is used, sensitivity is mainly to visible light to infrared light. Because metal oxides have a large band gap, when a metal oxide is used in the photoelectric conversion layer, high sensitivity is mainly to light with higher energy than visible light. Note that, for example, In-M-Zn oxide can be used as the metal oxide.

[0069] The semiconductor device 10 can irradiate, for example, light 23 onto the detection object, and the imaging device 15 can detect the light reflected by the detection object as light 25.

[0070] 1B is a diagram showing an example of the function of the semiconductor device 10. In Fig. 1B, the object to be detected is a finger 27. The finger 27 may be, for example, the finger of the user of the semiconductor device 10.

[0071] 1B, light 23 is irradiated onto finger 27, and image capture device 15 detects light reflected by finger 27 as light 25, thereby detecting fingerprint 29 on finger 27. This allows for authentication such as fingerprint authentication.

[0072] <Configuration example of imaging device_1> FIG. 2A is a block diagram showing an example configuration of an imaging device 15. The imaging device 15 includes a pixel section 30 in which m rows and n columns of pixels 31 (m and n are integers equal to or greater than 1) are arranged in a matrix, a control circuit 32, a row driver circuit 33, a CDS circuit 34, a readout circuit 36, and a detection circuit 37. Although not shown in FIG. 2A, the row driver circuit 33 includes a shift register circuit. A specific configuration example of the shift register circuit will be described later. A CDS circuit 34 can be provided for each column of pixels 31. FIG. 2A shows an example in which n CDS circuits 34 are provided for each column.

[0073] In this specification and the like, when the same reference numeral is used for multiple elements, particularly when it is necessary to distinguish between them, the reference numeral may be accompanied by an identifying symbol such as "[ ]", "< >", "( )", or "_". For example, the pixel 31 in the first row and first column will be referred to as pixel 31[1,1], and the pixel 31 in the mth row and nth column will be referred to as pixel 31[m,n]. Furthermore, the CDS circuit 34 in the first column will be referred to as CDS circuit 34[1], and the CDS circuit 34 in the nth column will be referred to as CDS circuit 34[n].

[0074] The row driver circuit 33 is electrically connected to the pixels 31 via wiring 43. The row driver circuit 33 is also electrically connected to the pixels 31 via wiring 44. Here, the wiring 43 is electrically connected to the terminal SL, and the wiring 44 is electrically connected to the terminal RS.

[0075] The CDS circuit is electrically connected to the pixel 31 via a wiring 45. The CDS circuit is also electrically connected to a readout circuit .

[0076] 2A illustrates a configuration in which pixels 31 in the same row are electrically connected to the same wiring 43 (terminal SL) and the same wiring 44 (terminal RS), and pixels 31 in the same column are electrically connected to the same wiring 45. In this specification, for example, the wiring 43 (terminal SL) electrically connected to the pixels 31 in the first row is referred to as wiring 43[1] (terminal SL[1]), and the wiring 43 (terminal SL) electrically connected to the pixels 31 in the mth row is referred to as wiring 43[m] (terminal SL[m]). Furthermore, for example, the wiring 44 (terminal RS) electrically connected to the pixels 31 in the first row is referred to as wiring 44[1] (terminal RS[1]), and the wiring 44 (terminal RS) electrically connected to the pixels 31 in the mth row is referred to as wiring 44[m] (terminal RS[m]). Furthermore, for example, the wiring 45 electrically connected to the pixels 31 in the first column is referred to as wiring 45[1], and the wiring 45 electrically connected to the pixels 31 in the nth column is referred to as wiring 45[n].

[0077] The control circuit 32 has a function of generating signals for controlling the driving of the row driver circuit 33. The control circuit 32 has a function of generating, for example, a start pulse signal, a clock signal, etc., and supplying them to the row driver circuit 33. Details of the signals that the control circuit 32 can generate will be described later.

[0078] The row driver circuit 33 has a function of selecting the pixel 31 from which imaging data is to be read. Specifically, by supplying a signal to a wiring 43 (terminal SL), the pixel 31 from which acquired imaging data is to be read can be selected. The row driver circuit 33 also has a function of selecting the pixel 31 from which imaging data is to be reset. Specifically, by supplying a signal to a wiring 44 (terminal RS), the pixel 31 from which acquired imaging data is to be reset can be selected. The row driver circuit is also called a gate driver circuit or a scan driver circuit.

[0079] In this specification and the like, for example, a high-potential signal may be simply referred to as a “signal.” For example, supplying a high-potential signal may be simply referred to as “supplying a signal,” and supplying a low-potential signal may be simply referred to as “stopping the supply of a signal.”

[0080] The CDS circuit 34 has a function of performing correlated double sampling (CDS) on the imaging data read out from the pixels 31. Correlated double sampling refers to taking the difference between the potential output from the pixels 31 when the imaging data is read out and the potential output from the pixels 31 when the imaging data is reset. By performing correlated double sampling, it is possible to reduce noise contained in the read imaging data.

[0081] The readout circuit 36 ​​has a function of sequentially outputting the imaging data output from the CDS circuits 34[1] to 34[n] to a detection circuit 37, for example.

[0082] The detection circuit 37 has a function of, for example, detecting an object based on the data output from the readout circuit 36. For example, when the semiconductor device 10 is driven as shown in FIG. 1B, the detection circuit 37 has a function of detecting a finger 27. The detection circuit 37 also has a function of detecting a fingerprint 29 on the finger 27 and performing authentication.

[0083] The detection result by the detection circuit 37 is supplied to the control circuit 32. This allows the row driver circuit 33 to perform driving in accordance with the detection result by the detection circuit 37.

[0084] 2A do not all need to be provided in the imaging device 15. For example, the control circuit 32 and the detection circuit 37 may be provided outside the imaging device 15.

[0085] <Pixel configuration example 1> 2B1 is a circuit diagram showing a configuration example of a pixel 31. The pixel 31 having the configuration shown in FIG. 2B1 includes a light-receiving element 50, a transistor 51, a transistor 52, a transistor 53, a transistor 54, a capacitor 56, and a capacitor 57. Note that the capacitor 56 and / or the capacitor 57 are not necessarily provided. Note that although the following description assumes that the transistors 51 to 54 are n-channel transistors, the following description can be referred to even when p-channel transistors are included by, for example, appropriately reversing the magnitude relationship of potentials.

[0086] One electrode of the light-receiving element 50 is electrically connected to one electrode of a capacitor 57. One electrode of the capacitor 57 is electrically connected to one of the source and drain of a transistor 51. The other of the source and drain of the transistor 51 is electrically connected to the gate of a transistor 52. One of the source and drain of the transistor 52 is electrically connected to one of the source and drain of a transistor 53. The gate of the transistor 52 is electrically connected to one of the source and drain of a transistor 54. One of the source and drain of the transistor 54 is electrically connected to one electrode of a capacitor 56. Note that a node to which the other of the source and drain of the transistor 51, the gate of the transistor 52, the one of the source and drain of the transistor 54, and one electrode of the capacitor 56 are electrically connected is referred to as a node FD.

[0087] The gate of the transistor 51 is electrically connected to the wiring 41. The gate of the transistor 53 is electrically connected to the wiring 43 (terminal SL). The gate of the transistor 54 is electrically connected to the wiring 44 (terminal RS). The other of the source and the drain of the transistor 53 is electrically connected to the wiring 45. The other electrode of the light-receiving element 50 and the other electrode of the capacitor 57 are electrically connected to the wiring 46. The other of the source and the drain of the transistor 52 is electrically connected to the wiring 47. The other of the source and the drain of the transistor 54 is electrically connected to the wiring 48. The other electrode of the capacitor 56 is electrically connected to the wiring 49.

[0088] A power supply potential can be supplied to the wirings 46 to 49. Therefore, the wirings 46 to 49 can be said to function as power supply lines. For example, a high potential can be supplied to the wiring 47, and a low potential can be supplied to the wiring 49. Furthermore, as shown in FIG. 2B1, when the cathode of the light-receiving element 50 is electrically connected to the wiring 46, the wiring 46 can be at a high potential, and the wiring 48 can be at a low potential. On the other hand, when the anode of the light-receiving element 50 is electrically connected to the wiring 46, the wiring 46 can be at a low potential, and the wiring 48 can be at a high potential.

[0089] 2B2 is a timing chart illustrating an example of a method for driving the pixel 31 having the configuration shown in FIG. 2B1. Here, the potential of the wiring 46 is high, and the potential of the wiring 48 is low. Note that in FIG. 2B2, "H" indicates high potential, and "L" indicates low potential. The same notation is used in other timing charts. In FIG. 2B2, periods T1 to T5 are shown as periods during which the pixel 31 is driven.

[0090] In the period T1, the potentials of the wiring 41 and the wiring 44 (terminal RS) are set to high potential, and the potential of the wiring 43 (terminal SL) is set to low potential. As a result, the transistors 51 and 54 are turned on, and the transistor 53 is turned off. When the transistor 54 is turned on, the potential of the node FD becomes low, which is the potential of the wiring 48. Furthermore, when the transistor 51 and the transistor 54 are turned on, the potential of one electrode of the light-receiving element 50 also becomes low, which is the potential of the wiring 48, although not shown in FIG. 2B2. As a result, the charges accumulated in the capacitors 56 and 57, etc. are reset. Therefore, the period T1 can be considered a reset period, and the operation performed in the period T1 can be considered a reset operation.

[0091] In the period T2, the potentials of the wiring 41 and the wiring 44 (terminal RS) are set to low. As a result, the transistors 51 and 54 are turned off. When the light-receiving element 50 is irradiated with light in this state, charge corresponding to the energy of the light incident on the light-receiving element 50 is accumulated in the capacitor 57. Therefore, the period T2 can be considered an exposure period, and the operation performed in the period T2 can be considered an exposure operation.

[0092] In the period T3, the potential of the wiring 41 is set to a high potential. This turns on the transistor 51, and the charge accumulated in the capacitor 57 is transferred to the node FD. This causes the potential of the node FD to rise. Therefore, the period T3 is a transfer period, and the operation performed in the period T3 can be considered a transfer operation.

[0093] In the period T4, the potential of the wiring 41 is set to low, which turns off the transistor 51 and stops the transfer of charge from the capacitor 57 to the node FD.

[0094] In this way, the imaging data is acquired by the pixel 31. Specifically, the potential of the node FD becomes a potential corresponding to the imaging data. Therefore, it can be said that the periods T1 to T4 are acquisition periods, and the operations performed during the periods T1 to T4 are acquisition operations.

[0095] Next, an example of a driving method in the period T5 will be described. During the period T5, the potential of the wiring 43 (terminal SL) is set to high. This turns on the transistor 53, and a signal representing imaging data acquired by the pixel 31 is output to the wiring 45. Specifically, the potential of the wiring 45 becomes a potential corresponding to the potential of the node FD. This allows the imaging data acquired by the pixel 31 to be read.

[0096] As described above, by supplying a high-potential signal to the wiring 43 (terminal SL), the imaging data acquired by the pixel 31 is read out. That is, the pixel 31 from which imaging data is to be read can be selected by the signal supplied to the wiring 43 (terminal SL). Therefore, the signal supplied to the wiring 43 (terminal SL) can be said to be a selection signal.

[0097] After the image data is read, the potential of the wiring 44 (terminal RS) is set to high. This turns on the transistor 54, and the image data acquired by the pixel 31 is reset. Specifically, the potential of the node FD becomes low, which is the potential of the wiring 48. Here, because the transistor 53 is on, the potential of the wiring 45 also changes in response to the change in the potential of the node FD. As a result, correlated double sampling can be performed by the CDS circuit 34 electrically connected to the wiring 45.

[0098] As described above, supplying a high-potential signal to the wiring 44 (terminal RS) resets the imaging data acquired by the pixel 31. Therefore, the signal supplied to the wiring 44 (terminal RS) can be said to be a reset signal.

[0099] After the correlated double sampling, the potential of the wiring 44 (terminal RS) is set to low to turn off the transistor 54, and the potential of the wiring 43 (terminal SL) is set to low to turn off the transistor 53.

[0100] The above is an example of a driving method for the period T5. During the period T5, imaging data acquired by the pixels 31 is read out. Therefore, the period T5 is a readout period, and the operation performed during the period T5 can be said to be a readout operation.

[0101] It is preferable that the acquisition of imaging data by pixels 31[1,1] to 31[m,n] be performed using a global shutter system. Here, the global shutter system refers to a system in which imaging data is acquired simultaneously by all pixels. By acquiring imaging data using the global shutter system, it is possible to ensure the simultaneity of imaging, and therefore it is possible to easily obtain an image with little distortion even when the subject is moving at high speed.

[0102] On the other hand, the reading of imaging data from pixels 31[1,1] to 31[m,n] is performed, for example, row by row. Therefore, when imaging data is acquired using the global shutter method, there are pixels 31 for which the period from acquisition to reading of imaging data is long. Therefore, when imaging data is acquired using the global shutter method, it is preferable to be able to hold the charge transferred from capacitor 57 to node FD for a long period of time.

[0103] To hold charge in the node FD for a long period of time, a transistor electrically connected to the node FD may have a low off-state current. An example of a transistor with a low off-state current is a transistor having a metal oxide in a channel formation region (hereinafter referred to as an OS transistor). Therefore, the transistor 51 and the transistor 54 are preferably OS transistors.

[0104] The OS transistor preferably has a metal oxide in a channel formation region. The metal oxide preferably contains at least indium or zinc. In particular, it preferably contains indium and zinc. Furthermore, it preferably contains aluminum, gallium, yttrium, tin, or the like in addition to the above. Furthermore, the metal oxide may contain one or more elements selected from the group consisting of boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and cobalt.

[0105] The OS transistor has an off-state current of 1 yA / μm per 1 μm of channel width (y: yocto, 10-24 ) or more than 1zA / μm (z: Zepto, 10 -21 ) or less.

[0106] It is preferable to apply a cloud-aligned composite (CAC)-OS to the OS transistor, which will be described in detail in a later embodiment.

[0107] As long as the off-state current is low, OS transistors may not be used as the transistors 51 and 54. For example, transistors including a semiconductor with a wide band gap may be used. A wide band gap semiconductor may refer to a semiconductor with a band gap of 2.2 eV or more. Examples of such semiconductors include silicon carbide, gallium nitride, and diamond.

[0108] Note that the transistors 51 and 54 may be, for example, transistors having silicon in their channel formation regions (hereinafter referred to as Si transistors). Si transistors have a higher off-state current than OS transistors. However, even if the on-state currents of the transistors 51 and 54 are high, by increasing the capacitance of the capacitor 56, for example, image data from the pixels 31[1,1] to 31[m,n] can be acquired by the global shutter method. Note that the image data from the pixels 31[1,1] to 31[m,n] may be acquired by the rolling shutter method. In this case, even if the transistors 51 and 54 are transistors with a high off-state current, the capacitance of the capacitor 56 does not need to be increased.

[0109] The transistors 52 and 53 may be Si transistors or OS transistors. For example, when transistors including crystalline silicon (typically, low-temperature polysilicon, single-crystal silicon, or the like) are used as the transistors 52 and 53, the on-state current of the transistors 52 and 53 can be increased. Therefore, image data can be read at high speed. On the other hand, when the transistors 51 to 54 are all OS transistors, all the transistors included in the pixel 31 can be formed in the same layer. Furthermore, when all the transistors included in the semiconductor device 10, including the transistors 51 to 54, are OS transistors, all the transistors included in the semiconductor device 10 can be formed in the same layer. As described above, the manufacturing process of the semiconductor device 10 can be simplified. Note that the transistors 51 to 54 may be transistors including amorphous silicon in their channel formation regions.

[0110] <Shift register circuit configuration example 1> 3 is a diagram showing an example of the configuration of the row driver circuit 33. Specifically, it is a diagram showing an example of the configuration of a shift register circuit included in the row driver circuit 33. The shift register circuit includes a latch circuit LAT, a register circuit R, a register circuit RD, and a signal supply circuit SS. Here, the shift register circuit may be provided with, for example, m latch circuits LAT, m register circuits R, and m signal supply circuits SS, and one register circuit RD. In other words, the latch circuit LAT, the register circuit R, and the signal supply circuit SS may be provided for each row of pixels 31.

[0111] The latch circuit LAT, the register circuit R, the register circuit RD, and the signal supply circuit SS are electrically connected to input terminals for inputting signals and output terminals for outputting signals, respectively.

[0112] In this specification, an input terminal electrically connected to the latch circuit LAT may be referred to as an input terminal of the latch circuit LAT or an input terminal of the latch circuit LAT. Also, an output terminal electrically connected to the latch circuit LAT may be referred to as an output terminal of the latch circuit LAT or an output terminal of the latch circuit LAT. The same applies to other circuits.

[0113] The input terminal of the latch circuit LAT[1] is electrically connected to the terminal SP1. The output terminal of the latch circuit LAT[1] is electrically connected to the terminal LIN[1], and the terminal LIN[1] is electrically connected to the input terminal of the register circuit R[1]. In other words, the signal output by the latch circuit LAT[1] is input to the register circuit R[1] via the terminal LIN[1]. Note that the terminal SP1 may also be referred to as the terminal ROUT[0].

[0114] The output terminal of the register circuit R[1] is electrically connected to the terminal ROUT[1], and the terminal ROUT[1] is electrically connected to the input terminal of the latch circuit LAT[2]. In other words, the signal output by the register circuit R[1] is input to the latch circuit LAT[2] via the terminal ROUT[1].

[0115] Similarly, the output terminals of the latch circuits LAT[2] to LAT[m] are electrically connected to the terminals LIN[2] to LIN[m], respectively, and the terminals LIN[2] to LIN[m] are electrically connected to the input terminals of the register circuits R[2] to R[m], respectively. In addition, the output terminals of the register circuits R[2] to R[m-1] are electrically connected to the terminals ROUT[2] to ROUT[m-1], respectively, and the terminals ROUT[2] to ROUT[m-1] are electrically connected to the input terminals of the latch circuits LAT[3] to LAT[m], respectively.

[0116] That is, the register circuits R[1] to R[m] are connected in series with the latch circuits LAT[2] to LAT[m] sandwiched between them. In other words, the latch circuits LAT[1] to LAT[m] and the register circuits R[1] to R[m] are alternately connected in series.

[0117] The output terminal of the register circuit R[m] is electrically connected to the terminal ROUT[m]. The terminal ROUT[m] is electrically connected to the terminal LIN_D, which is electrically connected to the input terminal of the register circuit RD.

[0118] Here, the terminals ROUT[2] to ROUT[m] are electrically connected to the terminals RIN[1] to RIN[m-1], respectively, and the terminals RIN[1] to RIN[m-1] are electrically connected to the input terminals of the register circuits R[1] to R[m-1], respectively. This allows the signal output by the register circuit R to the terminal ROUT to be supplied to the register circuit R in the preceding stage. In addition, the output terminal of the register circuit RD is electrically connected to the terminal ROUT_D, and the terminal ROUT_D is electrically connected to the terminal RIN[m]. The terminal RIN[m] is then electrically connected to the input terminal of the register circuit R[m]. Therefore, the signal output by the register circuit RD to the terminal ROUT_D is supplied to the register circuit R[m].

[0119] The input terminals of the latch circuits LAT[1] to LAT[m] are electrically connected to terminals SMP and SP2, respectively. The input terminals of the register circuits R[1] to R[m] and the register circuit RD are electrically connected to, for example, two terminals CLK among the terminals CLK(1) to CLK(4). For example, as shown in FIG. 3, the register circuit R[1] is electrically connected to terminals CLK(1) and CLK(2), the register circuit R[2] is electrically connected to terminals CLK(2) and CLK(3), the register circuit R[3] is electrically connected to terminals CLK(3) and CLK(4), the register circuit R[m] is electrically connected to terminals CLK(4) and CLK(1), and the register circuit RD is electrically connected to terminals CLK(1) and CLK(2). The number of terminals CLK in the row driver circuit 33 is not limited to four, and the number of terminals CLK electrically connected to one register circuit R is not limited to two.

[0120] The terminal OFFS is electrically connected to the input terminals of the register circuits R[1] to R[m] and the input terminal of the register circuit RD. The terminals OSS[1] to OSS[m] are electrically connected to the output terminals of the register circuits R[1] to R[m], respectively.

[0121] The terminals OSS[1] to OSS[m] are electrically connected to the input terminals of the signal supply circuits SS[1] to SS[m], respectively. Therefore, the signal output from the register circuit R to the terminal OSS is input to the signal supply circuit SS.

[0122] Terminals SL[1] to SL[m] and terminals RS[1] to RS[m] are electrically connected to the output terminals of the signal supply circuits SS[1] to SS[m], respectively. As described above, the signal output to the terminal SL is a selection signal, and the signal output to the terminal RS is a reset signal. Therefore, the terminal SL is a selection signal output terminal, and the terminal RS is a reset signal output terminal.

[0123] A start pulse signal is input to terminals SP1 and SP2. Therefore, terminals SP1 and SP2 are start pulse signal input terminals. By inputting a start pulse signal to terminal SP1 or terminal SP2, the shift register circuit shown in FIG. 3 can start operating.

[0124] A clock signal is input to the terminal CLK. Therefore, the terminal CLK is a clock signal input terminal. For example, the clock signals input to the terminals CLK(1) to CLK(4) can be signals with different phases, and the register circuit R and the register circuit RD can be driven in response to the clock signals.

[0125] Specifically, by inputting a start pulse signal to terminal SP1 or terminal SP2, any one of register circuits R[1] to R[m] outputs a signal to terminal ROUT and terminal OSS in response to the clock signal. The signal output to terminal ROUT can be input to the register circuit R in the next stage via latch circuit LAT and terminal LIN, allowing the register circuit R in the next stage to output a signal. Therefore, the signal output by register circuit R to terminal ROUT and the signal input to register circuit R via terminal LIN can be called a scanning signal.

[0126] As described above, the signal output from the register circuit R to the terminal OSS is input to the signal supply circuit SS. In response to this, the signal supply circuit SS outputs a selection signal from the terminal SL to the pixel 31, and outputs a reset signal from the terminal RS to the pixel 31.

[0127] Here, by inputting a signal to the terminal OFFS, the register circuits R[1] to R[m] can stop outputting signals to the terminals ROUT[1] to ROUT[m] and to the terminals OSS[1] to OSS[m]. Also, the register circuit RD can stop outputting signals to the terminal ROUT_D. In other words, by inputting a signal to the terminal OFFS, scanning by the shift register circuit can be stopped. Therefore, the signal input to the terminal OFFS can be called a scanning stop signal.

[0128] Furthermore, by inputting a signal to the register circuit R via the terminal RIN, the register circuit R can stop outputting a signal to the terminal ROUT and to the terminal OSS. As described above, the signal output to the terminal ROUT by the register circuit R in the next stage is input to the terminal RIN. Therefore, for example, after the register circuit R outputs a signal to the terminal ROUT and the terminal OSS, it is possible to prevent the same register circuit R from outputting a signal again. Therefore, it is possible to prevent malfunction of the imaging device 15.

[0129] By inputting a signal to the terminal SMP, data corresponding to the potential of the terminal SP1 is written to the latch circuit LAT[1], and data corresponding to the potentials of the terminals ROUT[1] to ROUT[m-1] are written to the latch circuits LAT[2] to LAT[m], respectively. Therefore, the signal input to the terminal SMP can be called a sampling signal. The data held in the latch circuit LAT can be 1-bit digital data.

[0130] The latch circuit LAT[1] has a function of outputting to the terminal LIN[1] either a signal input from the terminal SP1 or a signal input from the terminal SP2, depending on the data held in the latch circuit LAT[1]. For example, when the latch circuit LAT[1] holds data with a value of "0", it can output a signal input from the terminal SP1, and when the latch circuit LAT[1] holds data with a value of "1", it can output a signal input from the terminal SP2.

[0131] The row driver circuit 33 does not necessarily have to include the latch circuit LAT[1]. In this case, the terminal LIN[1] can be used as the terminal SP1.

[0132] The latch circuits LAT[2] to LAT[m] have a function of outputting to the terminals LIN[2] to LIN[m] either a signal input from the terminal ROUT[1] to the terminal ROUT[m-1] or a signal input from the terminal SP2, depending on the data held in the latch circuits LAT[2] to LAT[m], respectively. For example, when data with a value of "0" is held in the latch circuit LAT[2], the signal input from the terminal ROUT[1] can be output, and when data with a value of "1" is held in the latch circuit LAT[2], the signal input from the terminal SP2 can be output.

[0133] The signals input to the terminals shown in FIG. 3 can be generated by, for example, the control circuit 32 shown in FIG. 2A.

[0134] 4A is a circuit diagram showing an example configuration of a register circuit R. The register circuit R includes transistors Tr11, Tr13, Tr15, Tr17, Tr19, Tr20, Tr21, Tr23, and Tr25, as well as capacitors C11 and C21. In FIG. 4A, for example, a circuit 60 is configured by transistors Tr19, Tr20, and capacitor C11.

[0135] In this specification, the potential VDD indicates a high potential, and the potential VSS indicates a low potential.

[0136] 4A can be any of the multiple terminals CLK described above. For example, the shift register circuit included in the row driver circuit 33 has terminals CLK(1) to CLK(4). In this case, the terminal CLK(k1) can be any one of the terminals CLK(1) to CLK(4), and the terminal CLK(k2) can be any one of the terminals CLK(1) to CLK(4) except for the terminal CLK that is the same as the terminal CLK(k1).

[0137] Specifically, for example, in the register circuit R[1], the terminal CLK(k1) can be the terminal CLK(1), and the terminal CLK(k2) can be the terminal CLK(2). In addition, in the register circuit R[2], the terminal CLK(k1) can be the terminal CLK(2), and the terminal CLK(k2) can be the terminal CLK(3). Furthermore, in the register circuit R[3], the terminal CLK(k1) can be the terminal CLK(3), and the terminal CLK(k2) can be the terminal CLK(4).

[0138] In the register circuit R having the configuration shown in FIG. 4A, the terminal CLK(k1) is electrically connected to one of the source or drain of the transistor Tr20. The terminal CLK(k2) is electrically connected to the gate of the transistor Tr13. The terminal LIN is electrically connected to the gate of the transistor Tr11 and the gate of the transistor Tr23. The terminal RIN is electrically connected to the gate of the transistor Tr15. The terminal OFFS is electrically connected to the gate of the transistor Tr17. The terminal ROUT is electrically connected to the other of the source or drain of the transistor Tr20, one of the source or drain of the transistor Tr25, and one electrode of the capacitor C11. The terminal OSS is electrically connected to one of the source or drain of the transistor Tr11, one of the source or drain of the transistor Tr19, and one of the source or drain of the transistor Tr21.

[0139] The source or drain of transistor Tr13, the source or drain of transistor Tr15, the source or drain of transistor Tr17, the gate of transistor Tr21, the source or drain of transistor Tr23, the gate of transistor Tr25, and one electrode of capacitor C21 are electrically connected to one another. Note that if the gate capacitances of transistors Tr21 and Tr25 are sufficiently large, the register circuit R does not need to have capacitor C21.

[0140] The other of the source and drain of transistor Tr19, the gate of transistor Tr20, and the other electrode of capacitor C11 are electrically connected to one another. By providing transistor Tr19 in register circuit R, circuit 60 can be configured as a bootstrap circuit. Note that register circuit R does not necessarily have to include transistor Tr19. In this case, the capacitor C11 can also be omitted.

[0141] In the following explanation, transistors Tr11, Tr13, Tr15, Tr17, Tr19, Tr20, Tr21, Tr23, and Tr25 are assumed to be n-channel transistors. However, the following explanation can be referred to even if p-channel transistors are included, for example, by appropriately reversing the magnitude relationship of the potentials.

[0142] A high potential can be supplied to the other electrode of the source or drain of transistor Tr11, the other electrode of the source or drain of transistor Tr13, the other electrode of the source or drain of transistor Tr15, the other electrode of the source or drain of transistor Tr17, and the gate of transistor Tr19. A low potential can be supplied to the other electrode of the source or drain of transistor Tr21, the other electrode of the source or drain of transistor Tr23, the other electrode of the source or drain of transistor Tr25, and the other electrode of capacitor C21.

[0143] When a high-potential signal is input to the terminal LIN, the transistors Tr11 and Tr23 are turned on. If the transistor Tr11 is turned on and the transistor Tr21 is turned off, a high-potential signal is output from the terminal OSS, and the potential of the gate of the transistor Tr20 becomes high. The high potential of the gate of the transistor Tr20 turns the transistor Tr20 on. Therefore, the signal input to the terminal CLK(k1) can be output to the terminal ROUT.

[0144] On the other hand, when a high-potential signal is input to the terminal CLK(k2), the transistor Tr13 is turned on. As a result, the potentials of the gates of the transistors Tr21 and Tr25 become high. When the potential of the gate of the transistor Tr21 becomes high, the transistor Tr21 is turned on. Therefore, if the transistor Tr11 is turned off, the potential of the terminal OSS becomes low. Furthermore, when the potential of the gate of the transistor Tr25 becomes high, the transistor Tr25 is turned on. When the transistors Tr21 and Tr25 are turned on, the potential of the terminal ROUT becomes low. Similarly, when a high-potential signal is input to the terminal RIN or the terminal OFFS, the potentials of the terminals OSS and ROUT become low.

[0145] Here, the transistor Tr19 is preferably a transistor with a low off-state current, such as an OS transistor. This allows the gate potential of the transistor Tr20 to be maintained for a long period of time even after the potential of the terminal LIN becomes low and the transistor Tr11 is turned off. Therefore, the signal input to the terminal CLK(k1) can be continuously output to the terminal ROUT until the potential of the terminal CLK(k2), the terminal RIN, or the terminal OFFS becomes high.

[0146] In addition, the transistors Tr11, Tr13, Tr15, Tr17, Tr20, Tr21, Tr23, and Tr25 may also be OS transistors. By using OS transistors as all the transistors included in the register circuit R, all the transistors included in the register circuit R can be manufactured in the same process.

[0147] Furthermore, Si transistors can be used for transistors Tr11, Tr13, Tr15, Tr17, Tr19, Tr20, Tr21, Tr23, and Tr25. In particular, using transistors having crystalline silicon in their channel formation regions as these transistors can increase the on-state current. This allows the register circuit R to operate at high speed. Furthermore, transistors having amorphous silicon in their channel formation regions can be used for transistors Tr11, Tr13, Tr15, Tr17, Tr19, Tr20, Tr21, Tr23, and Tr25.

[0148] 4B is a circuit diagram showing a configuration example of a register circuit RD. The register circuit RD differs from the register circuit R in that it does not have a transistor Tr15. The register circuit RD also differs from the register circuit R in that the gates of the transistors Tr11 and Tr23 are electrically connected to the terminal LIN_D. The register circuit RD also differs from the register circuit R in that the other of the source or drain of the transistor Tr20, one of the source or drain of the transistor Tr25, and one electrode of the capacitor C11 are electrically connected to the terminal ROUT_D. The register circuit RD also differs from the register circuit R in that one of the source or drain of the transistor Tr11, one of the source or drain of the transistor Tr19, and one of the source or drain of the transistor Tr21 are not electrically connected to the terminal OSS.

[0149] 5A1 is a circuit diagram showing an example of the configuration of a latch circuit LAT. The latch circuit LAT shown in FIG. 5A1 includes transistors Tr31, Tr33, Tr35, Tr36, a capacitor C31, and an inverter circuit INV1. In FIG. 5A1, a node N is defined as a node electrically connecting one of the source and drain of transistor Tr33, the gate of transistor Tr35, and one electrode of capacitor C31.

[0150] In the latch circuit LAT shown in FIG. 5A1, when a high-potential signal is input to the terminal SMP, the transistor Tr33 is turned on. As a result, the potential of the node N becomes a potential corresponding to the potential of the terminal ROUT, and data corresponding to the signal input from the terminal ROUT to the latch circuit LAT is written to the latch circuit LAT. After the data is written to the latch circuit LAT, if the potential of the terminal SMP is set to a low potential, the transistor Tr33 is turned off. As a result, the potential of the node N is maintained, and the data written to the latch circuit LAT is maintained. Specifically, for example, when the potential of the node N is low, it can be assumed that data with a value of "0" is held in the latch circuit LAT, and when the potential of the node N is high, it can be assumed that data with a value of "1" is held in the latch circuit LAT.

[0151] The transistor Tr33 is preferably a transistor with a low off-state current, such as an OS transistor. This allows the latch circuit LAT to retain data for a long period of time, thereby reducing the frequency of rewriting data to the latch circuit LAT.

[0152] Fig. 5A2 is a circuit diagram showing a configuration example of the inverter circuit INV1 shown in Fig. 5A1. The inverter circuit INV1 includes a transistor Tr41, a transistor Tr43, a transistor Tr45, a transistor Tr47, and a capacitor C41.

[0153] By configuring the latch circuit LAT as shown in Figure 5A1 and the inverter circuit INV1 as shown in Figure 5A2, all of the transistors in the latch circuit LAT can be transistors of the same polarity, for example, n-channel transistors. As a result, for example, transistor Tr33, as well as transistors Tr31, Tr35, Tr36, Tr41, Tr43, Tr45, and Tr47, can be OS transistors. Therefore, all of the transistors in the latch circuit LAT can be manufactured using the same process.

[0154] Fig. 5B1 is a circuit diagram showing an example of the configuration of the latch circuit LAT, which is different from that of Fig. 5A1. The latch circuit LAT shown in Fig. 5B1 includes transistors Tr51, Tr52, Tr53, Tr54, Tr55, Tr56, Tr57, Tr58, Tr59, Tr60, Tr61, Tr62, and inverter circuits INV2_1, INV2_2, and INV2_3.

[0155] 5B2 is a circuit diagram showing an example configuration of the inverter circuit INV2. The inverter circuit INV2 includes a transistor Tr71 and a transistor Tr72. The gates of the transistors Tr71 and Tr72 can serve as input terminals of the inverter circuit INV2. One of the source or drain of the transistor Tr71 and one of the source or drain of the transistor Tr72 can serve as output terminals of the inverter circuit INV2.

[0156] The transistors Tr53, Tr54, Tr57, Tr58, Tr59, Tr61, and Tr72 may be n-channel transistors, and the transistors Tr51, Tr52, Tr55, Tr56, Tr60, Tr62, and Tr71 may be p-channel transistors.

[0157] The transistors Tr53, Tr54, Tr57, Tr58, Tr59, Tr61, and Tr72 may be, for example, OS transistors or Si transistors. The transistors Tr51, Tr52, Tr55, Tr56, Tr60, Tr62, and Tr71 may be, for example, Si transistors.

[0158] As described above, by inputting a high-potential signal to the terminal SMP, data corresponding to the signal input from the terminal ROUT to the latch circuit LAT is written to the latch circuit LAT. For example, when the potential of the terminal ROUT is low, data with a value of "0" can be written to the latch circuit LAT, and when the potential of the terminal ROUT is high, data with a value of "1" can be written to the latch circuit LAT. After writing data to the latch circuit LAT, if the potential of the terminal SMP is set to low, the data written to the latch circuit LAT is held.

[0159] When the potential of the terminal SP2 is low, the latch circuit LAT can output the signal input from the terminal ROUT to the terminal LIN. Furthermore, when the potential of the terminal SP2 is high and data with a value of "0" is held in the latch circuit LAT, the latch circuit LAT does not output a signal from the terminal LIN, or can set the potential of the terminal LIN to a low potential. Furthermore, when the potential of the terminal SP2 is high and data with a value of "1" is held in the latch circuit LAT, the latch circuit LAT can output the signal input from the terminal SP2 to the terminal LIN.

[0160] In this specification and the like, writing data into the latch circuit LAT such that a signal input from the terminal SP2 is output to the terminal LIN may be simply referred to as "writing data into the latch circuit LAT." In other words, writing data with a value of "1" into the latch circuit LAT may be simply referred to as "writing data into the latch circuit LAT."

[0161] An example of a method for driving the row driver circuit 33 will be described below. Specifically, an example of a method for driving the shift register circuit included in the row driver circuit 33 during the period T5, which is the readout period, shown in FIG. 2B2 will be described. By using the driving method described below, the semiconductor device of one embodiment of the present invention can perform authentication such as fingerprint authentication, for example.

[0162] 6A and 6B are schematic diagrams illustrating an example of a method for driving the row driver circuit 33 during a readout period. In Fig. 6A and Fig. 6B, the area of ​​the pixel section 30 that includes the pixels 31 from which imaging data is read out is indicated by hatching. Similar notations may be used in other figures.

[0163] In this specification, the driving method shown in Fig. 6A may be referred to as a first mode or a first driving mode, and the driving method shown in Fig. 6B may be referred to as a second mode or a second driving mode.

[0164] For example, when fingerprint authentication is performed, first, as shown in FIG. 6A, the row driver circuit 33 scans the entire pixel unit 30. As a result, for example, image data is read from all the pixels 31. The read image data is supplied to, for example, the detection circuit 37 shown in FIG. 2A. The detection circuit 37 detects the position in the pixel unit 30 of the finger 70 that is in contact with the pixel unit 30 based on the image data. When the operation shown in FIG. 6A is performed, for example, the latch circuits LAT[1] to LAT[m] shown in FIG. 3 can hold data with a value of "0."

[0165] Next, based on the detected position of the finger 70, the control circuit 32 shown in FIG. 2A, for example, determines the row of the pixels 31 from which image data is to be read for fingerprint detection. After the determination, the control circuit 32, for example, generates data indicating the row from which the row driver circuit 33 starts scanning when reading image data for fingerprint detection. This data is written to the latch circuit LAT shown in FIG. 3, for example. Specifically, data with a value of "1" is written to the latch circuit LAT corresponding to the row from which the row driver circuit 33 starts scanning.

[0166] Thereafter, as shown in Fig. 6B, the row driver circuit 33 scans a portion of the pixel unit 30 based on the above determination result. This makes it possible to read out imaging data only from the pixels 31 in the row in contact with the finger 70, for example. Alternatively, it is possible to read out imaging data only from the pixels 31 in the row in contact with the finger 70 and the surrounding rows. In Fig. 6B, the region of the pixel unit 30 that includes the pixels 31 from which imaging data is to be read out is designated as pixel unit 30R.

[0167] 6B is supplied to, for example, the detection circuit 37 shown in FIG. 2A. The detection circuit 37 detects a fingerprint 71 of the finger 70 based on the image data. In this way, the semiconductor device of one embodiment of the present invention can perform fingerprint authentication.

[0168] Here, during the period shown in FIG. 6A , it is sufficient to detect the position of the finger 70, and fingerprint authentication is not required. Therefore, the readout period per row of the pixels 31 can be shorter than that in the case of performing fingerprint authentication. On the other hand, during the period shown in FIG. 6B , fingerprint authentication is required, and therefore the readout period per row of the pixels 31 is longer than that in the case of performing fingerprint authentication. In the semiconductor device of one embodiment of the present invention, as shown in FIG. 6B , the pixels 31 from which image data for fingerprint authentication is read can be only a portion of the pixels 31 provided in the pixel portion 30. Therefore, fingerprint authentication can be performed in a shorter time than when image data for fingerprint authentication is read from all the pixels 31. Furthermore, even if it takes a long time to read image data for fingerprint authentication, a significant increase in the overall readout period can be prevented. Therefore, the semiconductor device of one embodiment of the present invention can perform fingerprint authentication in a short time with high accuracy.

[0169] In this specification and the like, the imaging data read out by the method shown in Fig. 6A may be referred to as the first imaging data, and the imaging data read out by the method shown in Fig. 6B may be referred to as the second imaging data. However, the imaging device 15 can acquire imaging data by the method shown in periods T1 to T4 in Fig. 2B2, for example, read the imaging data as the first imaging data by the method shown in Fig. 6A, and then read the second imaging data by the method shown in Fig. 6B without acquiring imaging data again. Therefore, the first imaging data and the second imaging data can be imaging data acquired during the same period.

[0170] A detailed example of the driving method shown in Figures 6A and 6B will be described with reference to Figures 7 to 9. Figure 7 is a timing chart showing a detailed example of the driving method shown in Figure 6A, and shows an example of the driving method of the row driver circuit 33 divided into periods T501 to T508.

[0171] Before the period T501, the potential of the terminal SMP and the potential of the terminal OFFS are low, and the latch circuits LAT[1] to LAT[m] hold data with a value of "0." For example, FIG. 7 shows data held in the latch circuit LAT[p] (p is an integer between 4 and m-2) as an example.

[0172] In period T501, a high-potential signal is input to terminal SP1 as a start pulse signal. Since the data value held in latch circuit LAT[1] is "0," the signal input to terminal SP1 is output to terminal LIN[1]. Therefore, the potential of terminal LIN[1] becomes high. As the potential of terminal LIN[1] becomes high, a high-potential signal is output from terminal OSS[1]. Note that in period T501, the potentials of terminals CLK(1) to CLK(4) are all low.

[0173] In period T502, the potential of terminal CLK(1) becomes high. Note that the potentials of terminals CLK(2) to CLK(4) remain low as in period T501. In period T501, the potential of terminal LIN[1] becomes high, and in period T502, the potential of terminal CLK(1) becomes high. As a result, although not shown in FIG. 7, the potential of terminal ROUT[1] becomes high. Because the data value held in the latch circuit LAT[2] is "0," the signal input to terminal ROUT[1] is output to terminal LIN[2]. Therefore, the potential of terminal LIN[2] becomes high. As the potential of terminal LIN[2] becomes high, a high-potential signal is output from terminal OSS[2].

[0174] Furthermore, the potential of the terminal OSS[1] is high during the period T502, which causes a selection signal to be output to the terminal SL[1] and a reset signal to be output to the terminal RS[1].

[0175] During period T503, the potential of terminal CLK(1) becomes low, and the potential of terminal CLK(2) becomes high. Note that the potentials of terminals CLK(3) and CLK(4) remain low as they were during period T502. During period T502, the potential of terminal LIN[2] becomes high, and during period T503, the potential of terminal CLK(2) becomes high, causing the potential of terminal ROUT[2] to become high. Because the data value held in latch circuit LAT[3] is "0," the signal input to terminal ROUT[2] is output to terminal LIN[3]. Therefore, the potential of terminal LIN[3] becomes high. Because the potential of terminal LIN[3] becomes high, a high-potential signal is output from terminal OSS[3]. Note that the potentials of terminals ROUT[2], LIN[3], and OSS[3] are not shown in FIG. 7.

[0176] Also, the potential of the terminal OSS[2] during the period T503 is high. As a result, a selection signal is output from the terminal SL[2] and a reset signal is output from the terminal RS[2]. Furthermore, as the potential of the terminal CLK(2) becomes high, the potential of the terminal OSS[1] becomes low.

[0177] In the period T504, the potential of the terminal LIN[p] is set to a high potential. As an example, the potential of the terminal CLK(1) is set to a high potential, and the potentials of the terminals CLK(2) to CLK(4) are set to a low potential. The potentials of the terminals CLK(1) to CLK(4) can be determined according to the value of p.

[0178] When the potential of the terminal LIN[p] becomes high, a high-potential signal is output from the terminal OSS[p]. Although not shown in FIG. 7, during the period T504, a selection signal is output from the terminal SL[p-1] and a reset signal is output from the terminal RS[p-1].

[0179] During period T505, the potential of terminal CLK(1) becomes low, and the potential of terminal CLK(2) becomes high. Note that the potentials of terminals CLK(3) and CLK(4) remain low as they were during period T504. During period T504, the potential of terminal LIN[p] becomes high, and during period T505, the potential of terminal CLK(2) becomes high. As a result, although not shown in FIG. 7, the potential of terminal ROUT[p] becomes high. Because the data value held in latch circuit LAT[p+1] is "0," the signal input to terminal ROUT[p] is output to terminal LIN[p+1]. Therefore, the potential of terminal LIN[p+1] becomes high. As the potential of terminal LIN[p+1] becomes high, a high-potential signal is output from terminal OSS[p+1].

[0180] Furthermore, the potential of the terminal OSS[p] is high during the period T505, which causes a selection signal to be output to the terminal SL[p] and a reset signal to be output to the terminal RS[p].

[0181] During period T506, the potential of terminal CLK(2) becomes low, and the potential of terminal CLK(3) becomes high. Note that the potentials of terminals CLK(1) and CLK(4) remain low as they were during period T505. During period T505, the potential of terminal LIN[p+1] becomes high, and during period T506, the potential of terminal CLK(3) becomes high, causing the potential of terminal ROUT[p+1] to become high. Because the data value held in latch circuit LAT[p+2] is "0," the signal input to terminal ROUT[p+1] is output to terminal LIN[p+2]. Therefore, the potential of terminal LIN[p+2] becomes high. Because the potential of terminal LIN[p+2] becomes high, a high-potential signal is output from terminal OSS[p+2]. Note that the potentials of terminals ROUT[p+1], LIN[p+2], and OSS[p+2] are not shown in FIG. 7.

[0182] Also, the potential of the terminal OSS[p+1] during the period T506 is high. As a result, a selection signal is output from the terminal SL[p+1], and a reset signal is output from the terminal RS[p+1]. Furthermore, as the potential of the terminal CLK(3) becomes high, the potential of the terminal OSS[p] becomes low.

[0183] During period T507, the potential of terminal LIN[m] becomes high. Also, the potential of terminal CLK(3) becomes high, and the potentials of terminals CLK(1), CLK(2), and CLK(4) become low. As a result of the potential of terminal LIN[m] becoming high, a high-potential signal is output from terminal OSS[m]. Although not shown in FIG. 7, during period T507, a selection signal is output from terminal SL[m-1], and a reset signal is output from terminal RS[m-1].

[0184] In period T508, the potential of terminal CLK(3) becomes low and the potential of terminal CLK(4) becomes high, and the potentials of terminals CLK(1) and CLK(2) remain low as in period T507. Since the potential of terminal LIN[m] becomes high in period T507 and the potential of terminal CLK(4) becomes high in period T508, the potential of terminal ROUT[m] becomes high, although not shown in FIG.

[0185] Furthermore, the potential of the terminal OSS[m] is high during the period T508, which causes a selection signal to be output to the terminal SL[m] and a reset signal to be output to the terminal RS[m].

[0186] As described above, in the driving method shown in FIG. 7, a start pulse signal is input to terminal SP1 in period T501, and the start pulse signal is supplied to register circuit R[1] via latch circuit LAT[1]. After that, scanning signals are sequentially supplied to register circuits R[2] to R[m] and register circuit RD. In response to the scanning signals, selection signals are sequentially output to terminals SL[1] to SL[m], and reset signals are sequentially output to terminals RS[1] to RS[m]. This allows image data to be sequentially read from the pixels 31 in the first to mth rows. Here, in the driving method shown in FIG. 7, a start pulse signal is not input to terminal SP2.

[0187] FIG. 8 is a timing chart showing an example of a method for writing data with a value of "1" to the latch circuit LAT[p], and shows an example of a method for driving the row driver circuit 33, divided into periods T511 to T516.

[0188] It is preferable that no signals be output from the terminals SL and RS during the periods T511 to T516. For example, in FIG. 8, no high-potential signals are output from the terminals SL and RS during the periods T511 to T516.

[0189] The operations in the periods T511 to T513 can be similar to those in the periods T501 to T503 shown in FIG. 7 except for the potentials of the terminals SL and RS.

[0190] At the start of period T514, the latch circuit LAT[p] holds data with a value of 0. Also, during period T514, a high-potential signal is input to terminal ROUT[p-1], causing the latch circuit LAT[p] to output a high-potential signal from terminal LIN[p].

[0191] In period T514, a high-potential signal is input to terminal SMP. Because a high-potential signal is input to terminal ROUT[p-1], data with a value of "1" is written to latch circuit LAT[p]. Note that because the potentials of terminal SP1, terminals ROUT[1] to ROUT[p-2], and terminals ROUT[p] to ROUT[m-1] are low, data with a value of "0" is written to latch circuits LAT[1] to LAT[p-1], and latch circuits LAT[p+1] to LAT[m].

[0192] After the value is written to the latch circuit LAT, the potential of the terminal SMP is set to low, thereby holding the data written to the latch circuit LAT.

[0193] The operation in the period T515 can be similar to the operation in the period T505 shown in FIG. 7 except for the potentials of the terminals SL and RS.

[0194] During a period T516, a high-potential signal is input to the terminal OFFS as a scanning stop signal. This stops the register circuit R from outputting signals to the terminals ROUT and OSS. This stops scanning by the shift register circuit included in the row driver circuit 33.

[0195] It is not necessary to input a scan stop signal to the terminal OFFS. In this case, the scan signal is supplied to the register circuit R[m] and the register circuit RD.

[0196] As a result of the above, data with a value of "1" is written to the latch circuit LAT[p].

[0197] 9 is a timing chart showing a detailed example of the driving method shown in FIG. 6B, and shows an example of the driving method of the row driver circuit 33 divided into periods T521 to T526. In the driving method shown in FIG. 9, pixels 31 in the pth row to pixels 31 in the qth row (q is an integer greater than or equal to p+1 and less than or equal to m) are sequentially scanned to read out imaging data from pixels 31 in the pth to qth rows.

[0198] Before the period T521, the potential of the terminal SMP and the potential of the terminal OFFS are assumed to be low. Also, it is assumed that the latch circuit LAT[p] holds data with a value of “1”, and the latch circuits LAT[1] to LAT[p−1] and the latch circuits LAT[p+1] to LAT[m] hold data with a value of “0”.

[0199] During the period T521, a high-potential signal is input to the terminal SP2 as a start pulse signal. As described above, the data value held in the latch circuit LAT[p] is "1," and the data values ​​held in the other latch circuits LAT are "0." Therefore, the signal input to the terminal SP2 is output to the terminal LIN[p] via the latch circuit LAT[p]. As a result, the potential of the terminal LIN[p] becomes high. As the potential of the terminal LIN[p] becomes high, a high-potential signal is output from the terminal OSS[p]. Note that during the period T521, the potential of the terminal CLK(1) among the terminals CLK becomes high, and the potentials of the terminals CLK(2) to CLK(4) become low. However, as described above, the potentials of the terminals CLK(1) to CLK(4) can be determined according to the value of p.

[0200] During period T522, for example, the potential of terminal CLK(1) becomes low, and the potential of terminal CLK(2) becomes high. Note that the potentials of terminals CLK(3) and CLK(4) remain low as they were during period T521. During period T521, the potential of terminal LIN[p] becomes high, and during period T522, the potential of terminal CLK(2) becomes high. As a result, although not shown in FIG. 9, the potential of terminal ROUT[p] becomes high. Because the data value held in latch circuit LAT[p+1] is "0," the signal input to terminal ROUT[p] is output to terminal LIN[p+1]. Therefore, the potential of terminal LIN[p+1] becomes high. As the potential of terminal LIN[p+1] becomes high, a high-potential signal is output from terminal OSS[p+1].

[0201] Furthermore, the potential of the terminal OSS[p] is high during the period T522, which causes a selection signal to be output to the terminal SL[p] and a reset signal to be output to the terminal RS[p].

[0202] During period T523, the potential of terminal CLK(2) becomes low, and the potential of terminal CLK(3) becomes high. Note that the potentials of terminals CLK(1) and CLK(4) remain low as they were during period T522. During period T522, the potential of terminal LIN[p+1] becomes high, and during period T523, the potential of terminal CLK(3) becomes high, causing the potential of terminal ROUT[p+1] to become high. Because the data value held in latch circuit LAT[p+2] is "0," the signal input to terminal ROUT[p+1] is output to terminal LIN[p+2]. Therefore, the potential of terminal LIN[p+2] becomes high. Because the potential of terminal LIN[p+2] becomes high, a high-potential signal is output from terminal OSS[p+2]. Note that the potentials of terminals ROUT[p+1], LIN[p+2], and OSS[p+2] are not shown in FIG. 9.

[0203] Also, the potential of the terminal OSS[p+1] during the period T523 is high. As a result, a selection signal is output from the terminal SL[p+1], and a reset signal is output from the terminal RS[p+1]. Furthermore, as the potential of the terminal CLK(3) becomes high, the potential of the terminal OSS[p] becomes low.

[0204] In the period T524, the potential of the terminal LIN[q] is set to a high potential. As an example, the potential of the terminal CLK(3) is set to a high potential, and the potentials of the terminals CLK(1), CLK(2), and CLK(4) are set to a low potential. The potentials of the terminals CLK(1) to CLK(4) can be determined according to the value of q.

[0205] When the potential of the terminal LIN[q] becomes high, a high-potential signal is output from the terminal OSS[q]. Although not shown in Figure 9, during period T524, a selection signal is output from the terminal SL[q-1] and a reset signal is output from the terminal RS[q-1].

[0206] During the period T525, the potential of the terminal OSS[q] is high, so that a selection signal is output to the terminal SL[q] and a reset signal is output to the terminal RS[q].

[0207] During a period T526, a high-potential signal is input to the terminal OFFS as a scanning stop signal. This stops the register circuit R from outputting signals to the terminals ROUT and OSS. This stops scanning by the shift register circuit included in the row driver circuit 33.

[0208] After that, a high-potential signal is input to the terminal SMP. Because a high-potential signal is input to the terminal OFFS, the potentials of the terminals ROUT[1] to ROUT[m] are low. Therefore, data with a value of "0" is written to the latch circuits LAT[1] to LAT[m].

[0209] After writing the value to the latch circuit LAT, the potential of the terminal SMP is set to low. This causes the data written to the latch circuit LAT to be held. As described above, the operation shown in period T526 allows the data held in the latch circuit LAT to be reset.

[0210] As described above, in the driving method shown in FIG. 9, a start pulse signal is input to terminal SP2 in period T521, and the start pulse signal is supplied to register circuit R[p] via latch circuit LAT[p]. After that, scan signals are sequentially supplied to register circuits R[p+1] to R[q]. In response to the scan signals, selection signals are sequentially output to terminals SL[p] to SL[q], and reset signals are sequentially output to terminals RS[p] to RS[q]. This allows image data to be sequentially read from pixels 31 in rows p to q. Here, in the driving method shown in FIG. 9, a start pulse signal is not input to terminal SP1. Furthermore, latch circuits LAT[1] to LAT[p-1] do not output signals to terminals LIN[1] to LIN[p-1].

[0211] As described above, the semiconductor device of one embodiment of the present invention can perform authentication such as fingerprint authentication by the row driver circuit 33 performing the operations shown in FIGS. 7 to 9 during the read period. Note that in this specification and the like, the driving method shown in FIG. 7 may be referred to as a first mode or a first driving mode. The driving method shown in FIG. 9 may be referred to as a second mode or a second driving mode. Furthermore, the driving method shown in FIG. 8 may be referred to as a second mode or a second driving mode, and the driving method shown in FIG. 9 may be referred to as a third mode or a third driving mode.

[0212] As described above, the readout period per row of the pixels 31 can be made shorter in the period shown in Fig. 6A than in the period shown in Fig. 6B. Therefore, for example, the period T505 shown in Fig. 7 can be made shorter than the period T522 shown in Fig. 9. Therefore, the transmission speed of the scanning signal when the row driver circuit 33 is driven by the method shown in Fig. 7 can be made faster than the transmission speed of the scanning signal when the row driver circuit 33 is driven by the method shown in Fig. 9. Here, the transmission speed of the scanning signal can be represented, for example, by the number of register circuits R to which the scanning signal is transmitted per unit time.

[0213] 9, any one of the register circuits R[2] to R[m] can be driven even if a scanning signal is not input from the previous register circuit R. Therefore, any one of the register circuits R[2] to R[m] can be operated independently of the operation of the previous register circuit R.

[0214] FIG. 10 is a diagram showing a configuration example of a row driver circuit 33, which is a modification of the row driver circuit 33 shown in FIG. 3. The row driver circuit 33 shown in FIG. 10 differs from the row driver circuit 33 shown in FIG. 3 in that three terminals CLK are electrically connected to one register circuit R. The row driver circuit 33 shown in FIG. 10 also differs from the row driver circuit 33 shown in FIG. 3 in that a signal output to a terminal ROUT by a register circuit R two stages downstream is input to a terminal RIN. The row driver circuit 33 shown in FIG. 10 also differs from the row driver circuit 33 shown in FIG. 3 in that it has two register circuits RD. The row driver circuit 33 shown in FIG. 10 also differs from the row driver circuit 33 shown in FIG. 3 in that it does not have a latch circuit LAT[1]. In the row driver circuit 33 shown in FIG. 10, the terminal LIN[1] can be the terminal SP1. Note that a signal output to a terminal ROUT by a register circuit R three or more stages downstream may be input to the terminal RIN. The same applies to row driver circuits 33 with other configurations. The row driver circuit 33 shown in Fig. 10 may also include a latch circuit LAT[1].

[0215] Fig. 11A is a diagram showing an example of the configuration of the register circuit R included in the row driver circuit 33 shown in Fig. 10, which is a modified example of the register circuit R shown in Fig. 4A. The register circuit R shown in Fig. 11A differs from the register circuit R shown in Fig. 4A in that it includes a transistor Tr14.

[0216] 11A, one of the source or drain of transistor Tr13 is electrically connected to one of the source or drain of transistor Tr14. The other of the source or drain of transistor Tr14 is electrically connected to one of the source or drain of transistor Tr15, one of the source or drain of transistor Tr17, the gate of transistor Tr21, one of the source or drain of transistor Tr23, the gate of transistor Tr25, and one electrode of capacitor C21. The gate of transistor Tr14 is electrically connected to terminal CLK(k3).

[0217] The terminal CLK(k3) can be, for example, any one of the terminals CLK(1) to CLK(4) excluding the terminal CLK that is the same as the terminal CLK(k1) and the terminal CLK that is the same as the terminal CLK(k2).

[0218] Specifically, for example, in the register circuit R[1], the terminal CLK(k3) can be the terminal CLK(3). Also, in the register circuit R[2], the terminal CLK(k3) can be the terminal CLK(4). Furthermore, in the register circuit R[3], the terminal CLK(k3) can be the terminal CLK(1).

[0219] 11B is a circuit diagram showing a configuration example of a register circuit RD included in the row driver circuit 33 shown in FIG. 10. The register circuit RD differs from the register circuit R shown in FIG. 11A in that it does not include a transistor Tr15. It also differs from the register circuit R shown in FIG. 11A in that the gates of the transistors Tr11 and Tr23 are electrically connected to the terminal LIN_D. It also differs from the register circuit R shown in FIG. 11A in that the other of the source or drain of the transistor Tr20, one of the source or drain of the transistor Tr25, and one electrode of the capacitor C11 are electrically connected to the terminal ROUT_D. It also differs from the register circuit R shown in FIG. 11A in that one of the source or drain of the transistor Tr11, one of the source or drain of the transistor Tr19, and one of the source or drain of the transistor Tr21 are not electrically connected to the terminal OSS.

[0220] Figures 12 to 14 are timing charts showing an example of a driving method for the row driver circuit 33 shown in Figure 10, which is a modified example of the driving method shown in Figures 7 to 9. Below, the driving method shown in Figures 12 to 14 will be described, mainly focusing on the differences from Figures 7 to 9.

[0221] 12 will be described. The potential of the terminal SP1 (terminal LIN[1]) is high in the periods T501 and T502 and low in the periods T503 to T508. The potential of the terminal LIN[2] is high in the periods T502 and T503 and low in the periods T501 and T504 to T508. The potential of the terminal LIN[p] is high in the periods T504 and T505 and low in the periods T501 to T503 and T506 to T508. The potential of the terminal LIN[p+1] is high in the periods T505 and T506 and low in the periods T501 to T504 and T507 to T508. The potential of the terminal LIN[m] is high in the periods T507 and T508, and is low in the periods T501 to T506.

[0222] The potential of the terminal CLK(1) is high in the periods T502, T503, T504, and T505, and low in the periods T501, T506, T507, and T508. The potential of the terminal CLK(2) is high in the periods T503, T505, T506, and T507, and low in the periods T501, T502, T504, and T508. The potential of the terminal CLK(3) is high in the periods T506, T507, and T508, and low in the periods T501 to T503, T504, and T505. The potential of the terminal CLK(4) is high in the periods T504 and T508, and is low in the periods T501 to T503, T505, T506, and T507.

[0223] Furthermore, the potential of the terminal OSS[1] is high during the periods T501 to T503 and low during the periods T504 to T508. The potential of the terminal OSS[2] is high during the periods T502 and T503 and low during the periods T501 and T504 to T508. The potential of the terminal OSS[p] is high during the periods T504 to T506 and low during the periods T501 to T503, T507, and T508. The potential of the terminal OSS[p+1] is high during the periods T505 and T506 and low during the periods T501 to T504, T507, and T508. The potential of the terminal OSS[m] is high in the periods T507 and T508, and is low in the periods T501 to T506.

[0224] 13 will be described. The potential of the terminal SP1 (terminal LIN[1]) is high in the periods T511 and T512 and low in the periods T513 to T516. The potential of the terminal LIN[2] is high in the periods T512 and T513 and low in the periods T511 and T514 to T516. The potential of the terminal LIN[p] is high in the periods T514 and T515 and low in the periods T511 to T513 and T516. The potential of the terminal LIN[p+1] is high in the periods T515 and T516 and low in the periods T511 to T514.

[0225] The potential of the terminal CLK(1) is high in the periods T512, T513, T514, and T515, and low in the periods T511 and T516. The potential of the terminal CLK(2) is high in the periods T513, T515, and T516, and low in the periods T511, T512, and T514. The potential of the terminal CLK(3) is high in the period T516 and low in the periods T511 to T513, T514, and T515. The potential of the terminal CLK(4) is high in the period T514 and low in the periods T511 to T513, T515, and T516.

[0226] Furthermore, the potential of the terminal OSS[1] is high in the periods T511 to T513 and low in the periods T514 to T516. The potential of the terminal OSS[2] is high in the periods T512 and T513 and low in the periods T511 and T514 to T516.

[0227] 14 will be described. The potential of the terminal SP2 is high in the periods T521 and T522 and low in the periods T523 to T526. The potential of the terminal LIN[p] is high in the periods T521 and T522 and low in the periods T523 to T526. The potential of the terminal LIN[p+1] is high in the periods T522 and T523 and low in the periods T521 and T524 to T526. The potential of the terminal LIN[q] is high in the periods T524 and T525 and low in the periods T521 to T523 and T526.

[0228] The potential of the terminal CLK(1) is high in the periods T521, T522, and T526, and low in the periods T523, T524, and T525. The potential of the terminal CLK(2) is high in the periods T522, T523, and T524, and low in the periods T521, T525, and T526. The potential of the terminal CLK(3) is high in the periods T523, T524, and T525, and low in the periods T521, T522, and T526. The potential of the terminal CLK(4) is high in the periods T525 and T526, and low in the periods T521 to T523 and T524.

[0229] Furthermore, the potential of the terminal OSS[p] is high in the periods T521 to T523 and low in the periods T524 to T526. The potential of the terminal OSS[p+1] is high in the periods T522 and T523 and low in the periods T521 and T524 to T526.

[0230] 12 to 14, the potentials of two terminals LIN can be set to high potentials in the same period. For example, in the example shown in Fig. 12, the potentials of the terminals LIN[1] and LIN[2] can be set to high potentials in the period T502, and the potentials of the terminals LIN[p] and LIN[p+1] can be set to high potentials in the period T505.

[0231] <Shift register circuit configuration example 2> 15 is a diagram showing a configuration example of the row driver circuit 33. Specifically, it is a diagram showing a configuration example of a shift register circuit included in the row driver circuit 33. The shift register circuit includes a demultiplexer circuit DeMUX, a register circuit R, a register circuit RD, a multiplexer circuit MUX, and a signal supply circuit SS. Here, the shift register circuit configured as shown in FIG. 15 may include, for example, m register circuits R and m signal supply circuits SS, one register circuit RD, and m-1 multiplexer circuits MUX.

[0232] The input terminal of the demultiplexer circuit DeMUX is electrically connected to the terminal SPI. The output terminal of the demultiplexer circuit DeMUX is electrically connected to the terminals SP[1] to SP[m]. The selection signal input terminal of the demultiplexer circuit DeMUX is electrically connected to the terminals DSL(1) to DSL(log2(m)). Note that the terminal SP[1] can be the terminal LIN[1].

[0233] Here, the selection signal input terminal of the demultiplexer circuit DeMUX can be electrically connected to more than log2(m) terminals DSL. For example, the selection signal input terminal of the demultiplexer circuit DeMUX can be electrically connected to the smallest integer greater than or equal to log2(m), that is, the number of terminals DSL represented by the ceiling function of log2(m). For example, when m is 10, four terminals DSL can be electrically connected to the selection signal input terminal of the demultiplexer circuit DeMUX. As described above, when the selection signal input terminal of the demultiplexer circuit DeMUX is electrically connected to more than log2(m) terminals DSL, the value of m is not limited to a power of 2.

[0234] In the following description, it is assumed that m is a power of two.

[0235] The terminal SP[1] is electrically connected to the input terminal of the register circuit R[1]. The terminals SP[2] to SP[m] are electrically connected to the input terminals of the multiplexer circuits MUX[1] to MUX[m-1], respectively. That is, the output terminal of the demultiplexer circuit DeMUX is electrically connected to the input terminal of the register circuit R via the terminal SP[1], and is electrically connected to the input terminals of the multiplexer circuits MUX[1] to MUX[m-1], respectively, via the terminals SP[2] to SP[m].

[0236] The output terminal of the register circuit R[1] is electrically connected to the terminal ROUT[1], and the terminal ROUT[1] is electrically connected to the input terminal of the multiplexer circuit MUX[1]. In other words, the signal output by the register circuit R[1] is input to the multiplexer circuit MUX[1] via the terminal ROUT[1].

[0237] The output terminals of the multiplexer circuits MUX[1] to MUX[m-1] are electrically connected to the terminals LIN[2] to LIN[m], respectively, and the terminals LIN[2] to LIN[m] are electrically connected to the input terminals of the register circuits R[2] to R[m], respectively. The output terminals of the register circuits R[2] to R[m-1] are electrically connected to the terminals ROUT[2] to ROUT[m-1], respectively, and the terminals ROUT[2] to ROUT[m-1] are electrically connected to the input terminals of the multiplexer circuits MUX[2] to MUX[m-1], respectively.

[0238] That is, the register circuits R[1] to R[m] are connected in series with the multiplexer circuits MUX[1] to MUX[m-1] in between. In other words, the register circuits R[1] to R[m] and the multiplexer circuits MUX[1] to MUX[m-1] are alternately connected in series.

[0239] 3, the output terminal of the register circuit R[m] is electrically connected to the terminal ROUT[m]. The terminal ROUT[m] is electrically connected to the terminal LIN_D, and the terminal LIN_D is electrically connected to the input terminal of the register circuit RD.

[0240] The terminals ROUT[2] to ROUT[m] are electrically connected to the terminals RIN[1] to RIN[m-1], respectively, and the terminals RIN[1] to RIN[m-1] are electrically connected to the input terminals of the register circuits R[1] to R[m-1], respectively. The output terminal of the register circuit RD is electrically connected to the terminal ROUT_D, and the terminal ROUT_D is electrically connected to the terminal RIN[m]. The terminal RIN[m] is electrically connected to the input terminal of the register circuit R[m].

[0241] Also, similar to the row driver circuit 33 shown in Figure 3, two terminals CLK out of terminals CLK(1) to CLK(4) are electrically connected to the input terminals of register circuits R[1] to R[m] and register circuit RD.

[0242] A terminal OFFS is electrically connected to the input terminals of the register circuits R[1] to R[m] and the input terminal of the register circuit RD. Terminals OSS[1] to OSS[m] are electrically connected to the output terminals of the register circuits R[1] to R[m], respectively. The terminals OSS[1] to OSS[m] are electrically connected to the input terminals of the signal supply circuits SS[1] to SS[m], respectively. Terminals SL[1] to SL[m] and terminals RS[1] to RS[m] are electrically connected to the output terminals of the signal supply circuits SS[1] to SS[m], respectively.

[0243] The demultiplexer circuit DeMUX has a function of outputting a signal input to the terminal SPI to one of the terminals SP[1] to SP[m] based on the signals input to the terminals DSL(1) to DSL(log2(m)). Here, since a start pulse signal is input to the terminal SPI, the terminal SPI and the terminals SP[1] to SP[m] are start pulse signal input terminals.

[0244] A log2(m)-bit digital signal can be input to the terminal DSL. Therefore, the value of the digital signal input to the terminal DSL can be "0" to "m-1". The demultiplexer circuit DeMUX can output the start pulse signal input to the terminal SPI to the terminal SP corresponding to the value represented by the digital signal among the terminals SP[1] to SP[m]. For example, if the value of the digital signal input to the terminal DSL is "0", the demultiplexer circuit DeMUX can output the start pulse signal from the terminal SP[1]. Also, if the value of the digital signal input to the terminal DSL is "m-1", the demultiplexer circuit DeMUX can output the start pulse signal from the terminal SP[m].

[0245] In this specification, when a digital signal is input to terminal DSL, for example, the signal input to terminal DSL(1) represents the least significant bit, and the signal input to terminal DSL(log2(m)) represents the most significant bit.

[0246] The multiplexer circuit MUX has a function of outputting either a start pulse signal input from the terminal SP or a scan signal input from the terminal ROUT to the terminal LIN, thereby allowing either the start pulse signal or the scan signal to be input to the register circuits R[2] to R[m].

[0247] 15, among the register circuits R[1] to R[m], the register circuit R to which the start pulse signal is input outputs a scanning signal. The scanning signal is sequentially transmitted to the register circuit RD via the terminals ROUT, LIN, and LIN_D. In other words, scanning can be started from the register circuit R to which the start pulse signal is input.

[0248] 16A and 16B are circuit diagrams showing an example configuration of a multiplexer circuit MUX. The multiplexer circuit MUX shown in FIG. 16A includes transistors Tr101, Tr103, and Tr105, and an inverter circuit INV3. The transistors Tr101, Tr103, and Tr105 may be, for example, n-channel transistors. The inverter circuit INV3 may have the configuration shown in FIG. 5A2, for example.

[0249] In the multiplexer circuit MUX configured as shown in FIG. 16A, when the potential of the terminal SP is low, the transistor Tr101 is turned on and the transistor Tr105 is turned off. Therefore, the signal input to the terminal ROUT is output to the terminal LIN. On the other hand, when the potential of the terminal SP is high, the transistor Tr101 is turned off and the transistor Tr105 is turned on. Therefore, the signal input from the terminal SP is output to the terminal LIN.

[0250] The multiplexer circuit MUX shown in FIG. 16B includes transistors Tr111, Tr112, Tr113, and Tr114, and an inverter circuit INV4. The transistors Tr111 and Tr113 may be p-channel transistors, and the transistors Tr112 and Tr114 may be n-channel transistors. The inverter circuit INV4 may have the configuration shown in FIG. 5B2, for example.

[0251] In the multiplexer circuit MUX having the configuration shown in FIG. 16B, when the potential of the terminal SP is low, the transistors Tr111 and Tr112 are turned on, and the transistors Tr113 and Tr114 are turned off. Therefore, the signal input to the terminal ROUT is output to the terminal LIN. On the other hand, when the potential of the terminal SP is high, the transistors Tr111 and Tr112 are turned off, and the transistors Tr113 and Tr114 are turned on. Therefore, the signal input from the terminal SP is output to the terminal LIN.

[0252] 16A or 16B can output a start pulse signal to the terminal LIN during a period when a high-potential signal is input as a start pulse signal to the terminal SP. On the other hand, during a period when no start pulse signal is input to the terminal SP, the multiplexer circuit MUX can output a signal input from the terminal ROUT to the terminal LIN.

[0253] 17A is a circuit diagram showing an example of the configuration of the demultiplexer circuit DeMUX. The demultiplexer circuit DeMUX has a demultiplexer circuit D.

[0254] The demultiplexer circuit DeMUX is configured to branch into two systems per stage, with a total of m paths. In other words, the demultiplexer circuits D are connected in a tournament format. The input terminal of the first-stage demultiplexer circuit D is electrically connected to the terminal SPI. The output terminal of the final-stage, log2(m)-stage demultiplexer circuit D is electrically connected to each of the two terminals SP.

[0255] The selection signal input terminal of the demultiplexer circuit D is electrically connected to the terminal DSL and the terminal DSLB. Here, a complementary signal of the signal input to the terminal DSL is input to the terminal DSLB. For example, when a 1-bit digital signal with a value of "0" is input to the terminal DSL(1), a 1-bit digital signal with a value of "1" is input to the terminal DSLB(1). On the other hand, when a 1-bit digital signal with a value of "1" is input to the terminal DSL(1), a 1-bit digital signal with a value of "0" is input to the terminal DSLB(1). The same is true for the terminals DSLB(2) to DSLB(log2(m)).

[0256] By configuring the demultiplexer circuit DeMUX as shown in Figure 17A, the demultiplexer circuit DeMUX can output the signal input to the terminal SPI to the terminal SP corresponding to the value represented by the signal input to the terminals DSL(1) to DSL(log2(m)).

[0257] 17B1, 17B2, and 17B3 are circuit diagrams showing configuration examples of a demultiplexer circuit D. The demultiplexer circuit D having the configuration shown in Fig. 17B1 includes transistors Tr121, Tr122, Tr123, and Tr124. The transistors Tr121 to Tr124 can be, for example, n-channel transistors.

[0258] In the demultiplexer circuit D having the configuration shown in FIG. 17B1, the terminal DSL is electrically connected to one of the source or drain of the transistor Tr121. The other of the source or drain of the transistor Tr121 is electrically connected to the gate of the transistor Tr123. The terminal DSLB is electrically connected to one of the source or drain of the transistor Tr122. The other of the source or drain of the transistor Tr122 is electrically connected to the gate of the transistor Tr124. One of the source or drain of the transistor Tr123 and one of the source or drain of the transistor Tr124 are electrically connected to input terminals of the demultiplexer circuit D. The other of the source or drain of the transistor Tr123 is electrically connected to a first output terminal of the demultiplexer circuit D. The other of the source or drain of the transistor Tr124 is electrically connected to a second output terminal of the demultiplexer circuit D. In addition, a high potential can be supplied to the gates of the transistors Tr121 and Tr122.

[0259] In the demultiplexer circuit D having the configuration shown in FIG. 17B1, when the potential of the terminal DSL is high and the potential of the terminal DSLB is low, the transistor Tr123 is turned on and the transistor Tr124 is turned off. As a result, a signal input from the input terminal of the demultiplexer circuit D is output from the first output terminal of the demultiplexer circuit D. On the other hand, when the potential of the terminal DSL is low and the potential of the terminal DSLB is high, the transistor Tr123 is turned off and the transistor Tr124 is turned on. As a result, a signal input from the input terminal of the demultiplexer circuit D is output from the second output terminal of the demultiplexer circuit D.

[0260] Fig. 17B2 is a modified example of the demultiplexer circuit D shown in Fig. 17B1. The demultiplexer circuit D shown in Fig. 17B2 differs from the demultiplexer circuit D shown in Fig. 17B1 in that it includes a transistor Tr125 and a transistor Tr126.

[0261] 17B2, one of the source or drain of transistor Tr125 is electrically connected to the second output terminal of the demultiplexer circuit D, and the gate of transistor Tr125 is electrically connected to the gate of transistor Tr123. One of the source or drain of transistor Tr126 is electrically connected to the first output terminal of the demultiplexer circuit D, and the gate of transistor Tr126 is electrically connected to the gate of transistor Tr124. A low potential can be supplied to the other of the source or drain of transistor Tr125 and the other of the source or drain of transistor Tr126.

[0262] In the demultiplexer circuit D having the configuration shown in FIG. 17B2, when the potential of the terminal DSL is high and the potential of the terminal DSLB is low, the transistors Tr123 and Tr125 are turned on, and the transistors Tr124 and Tr126 are turned off. As a result, a signal input from the input terminal of the demultiplexer circuit D is output from the first output terminal of the demultiplexer circuit D, and the potential of the second output terminal of the demultiplexer circuit D is low. On the other hand, when the potential of the terminal DSL is low and the potential of the terminal DSLB is high, the transistors Tr123 and Tr125 are turned off, and the transistors Tr124 and Tr126 are turned on. As a result, a signal input from the input terminal of the demultiplexer circuit D is output from the second output terminal of the demultiplexer circuit D, and the potential of the first output terminal of the demultiplexer circuit D is low.

[0263] 17B3 includes a transistor Tr131, a transistor Tr132, a transistor Tr133, and a transistor Tr134. The transistors Tr131 and Tr133 may be n-channel transistors, and the transistors Tr132 and Tr134 may be p-channel transistors.

[0264] In the demultiplexer circuit D having the configuration shown in FIG. 17B3, the terminal DSL is electrically connected to the gate of the transistor Tr131 and the gate of the transistor Tr134. The terminal DSLB is electrically connected to the gate of the transistor Tr132 and the gate of the transistor Tr133. The input terminal of the demultiplexer circuit D is electrically connected to one of the source or drain of the transistor Tr131, one of the source or drain of the transistor Tr132, one of the source or drain of the transistor Tr133, and one of the source or drain of the transistor Tr134. The other of the source or drain of the transistor Tr131 and the other of the source or drain of the transistor Tr132 are electrically connected to a first output terminal of the demultiplexer circuit D. The other of the source or drain of the transistor Tr133 and the other of the source or drain of the transistor Tr134 are electrically connected to a second output terminal of the demultiplexer circuit D.

[0265] In the demultiplexer circuit D having the configuration shown in FIG. 17B3, when the potential of the terminal DSL is high and the potential of the terminal DSLB is low, the transistors Tr131 and Tr132 are turned on, and the transistors Tr133 and Tr134 are turned off. As a result, a signal input from the input terminal of the demultiplexer circuit D is output from the first output terminal of the demultiplexer circuit D. On the other hand, when the potential of the terminal DSL is low and the potential of the terminal DSLB is high, the transistors Tr131 and Tr132 are turned off, and the transistors Tr133 and Tr134 are turned on. As a result, a signal input from the input terminal of the demultiplexer circuit D is output from the second output terminal of the demultiplexer circuit D.

[0266] The row driver circuit 33 shown in Fig. 15 can be driven by the method shown in Fig. 6A and Fig. 6B. Fig. 18 is a timing chart showing a detailed example of a driving method when the row driver circuit 33 shown in Fig. 15 is driven in the mode shown in Fig. 6A. In Fig. 18, an example of the driving method of the row driver circuit 33 is shown divided into periods T601 to T608.

[0267] During period T601, a high-potential signal is input as a start pulse signal to terminal SPI. Also, a digital signal with a value of "0" is input to terminal DSL. As a result, a start pulse signal is input to terminal SP[1].

[0268] The potentials of terminals LIN[1] to LIN[m], terminals CLK(1) to CLK(4), terminal OFFS, terminals OSS[1] to OSS[m], terminals SL[1] to SL[m], and terminals RS[1] to RS[m] in periods T601 to T608 can be the same as the potentials in periods T501 to T508 shown in Figure 7.

[0269] By driving the row driver circuit 33 in the method shown in FIG. 18, it is possible to read out imaging data sequentially from the pixels 31 in the first to m-th rows.

[0270] Fig. 19 is a timing chart showing a detailed example of a driving method when the row driver circuit 33 shown in Fig. 15 is driven in the mode shown in Fig. 6B. In Fig. 19, the example of the driving method of the row driver circuit 33 is shown divided into periods T611 to T616.

[0271] During period T611, a high-potential signal is input to terminal SPI as a start pulse signal. Also, a digital signal with a value of "p-1" is input to terminal DSL. As a result, a start pulse signal is input to terminal SP[p], and the potential of terminal LIN[p] becomes high.

[0272] The potentials of terminals LIN[1] to LIN[m], terminals CLK(1) to CLK(4), terminal OFFS, terminals OSS[1] to OSS[m], terminals SL[1] to SL[m], and terminals RS[1] to RS[m] in periods T611 to T616 can be the same as the potentials in periods T521 to T526 shown in Figure 9.

[0273] By driving the row driver circuit 33 in the method shown in FIG. 19, it is possible to sequentially read out imaging data from the pixels 31 in the pth to qth rows.

[0274] 18 and 19 during the readout period, the semiconductor device of one embodiment of the present invention can perform authentication such as fingerprint authentication. As described above, the readout period per row of the pixel 31 can be shorter in the period shown in FIG. 6A than in the period shown in FIG. 6B. Therefore, for example, the period T605 shown in FIG. 18 can be shorter than the period T612 shown in FIG. 19. Therefore, the transmission speed of the scan signal when the row driver circuit 33 is driven by the method shown in FIG. 18 can be faster than the transmission speed of the scan signal when the row driver circuit 33 is driven by the method shown in FIG. 19.

[0275] 19, any one of the register circuits R[2] to R[m] can be driven even if a scanning signal is not input from the previous-stage register circuit R. Therefore, any one of the register circuits R[2] to R[m] can be operated independently of the operation of the previous-stage register circuit R.

[0276] 20 is a diagram illustrating a configuration example of a row driver circuit 33, which is a modification of the row driver circuit 33 shown in FIG. 15. The row driver circuit 33 shown in FIG. 20 differs from the row driver circuit 33 shown in FIG. 15 in that three terminals CLK are electrically connected to one register circuit R. The row driver circuit 33 shown in FIG. 20 also differs from the row driver circuit 33 shown in FIG. 15 in that the signal output to the terminal ROUT by the register circuit R two stages later is input to the terminal RIN. The row driver circuit 33 shown in FIG. 20 also differs from the row driver circuit 33 shown in FIG. 15 in that it has two register circuits RD.

[0277] The register circuit R included in the row driver circuit 33 shown in FIG. 20 can have the configuration shown in FIG. 11A, and the register circuit RD can have the configuration shown in FIG. 11B.

[0278] Figures 21 and 22 are timing charts showing an example of a driving method for the row driver circuit 33 shown in Figure 20, which is a modified example of the driving method shown in Figures 18 and 19. Below, the driving methods shown in Figures 21 and 22 will be described, mainly in terms of the differences from Figures 18 and 19.

[0279] 21, the potentials of the terminal SPI and the terminal SP[1] (LIN[1]) are high in the periods T601 and T602, and low in the periods T603 to T608. In addition, a digital signal with a value of "0" is input to the terminal DSL in the periods T601 and T602.

[0280] 22, the potential of the terminal SPI and the potential of the terminal SP[p] are high in the periods T611 and T612, and are low in the periods T613 to T616. In addition, a digital signal having a value of “p−1” is input to the terminal DSL in the periods T611 and T612.

[0281] 21 and 22, the potentials of the two terminals LIN can be set to a high potential during the same period, similar to the driving methods shown in Fig. 12 to 14. As a result, as described above, the signal supply circuit SS electrically connected to the register circuit R can output signals to the terminals SL and RS while the transistor Tr11 included in the register circuit R remains on.

[0282] <Shift register circuit configuration example 3> 23 is a diagram showing a configuration example of the row driver circuit 33. Specifically, it is a diagram showing a configuration example of a shift register circuit included in the row driver circuit 33. The shift register circuit includes a counter circuit CNT, a demultiplexer circuit DeMUX, and a signal supply circuit SS. Here, the shift register circuit having the configuration shown in FIG. 23 can be provided with, for example, m signal supply circuits SS.

[0283] The input terminals of the counter circuit CNT are electrically connected to the terminal CCLK, the terminal CRS, and the terminals INI(1) to INI(log2(m)). The output terminals of the counter circuit CNT are electrically connected to the terminals DSL(1) to DSL(log2(m)). Here, a clock signal can be input to the terminal CCLK. Therefore, the terminal CCLK is a clock signal input terminal.

[0284] The terminals DSL(1) to DSL(log2(m)) are electrically connected to the selection signal input terminals of the demultiplexer circuit DeMUX. That is, the output terminals of the counter circuit CNT are electrically connected to the demultiplexer circuit DeMUX via the terminals DSL.

[0285] The output terminals of the demultiplexer circuit DeMUX are electrically connected to the terminals OSS[1] to OSS[m]. Similarly to the row driver circuit 33 shown in FIG. 3, the terminals OSS[1] to OSS[m] are electrically connected to the input terminals of the signal supply circuits SS[1] to SS[m], respectively. That is, the output terminals of the demultiplexer circuit DeMUX are electrically connected to the input terminals of the signal supply circuits SS[1] to SS[m], respectively, via the terminals OSS[1] to OSS[m]. The output terminals of the signal supply circuits SS[1] to SS[m] are electrically connected to the terminals SL[1] to SL[m] and the terminals RS[1] to RS[m], respectively.

[0286] The counter circuit CNT has a function of performing counting based on the clock signal input to the terminal CCLK, using the value represented by the signal input to the terminal INI as the initial value. For example, it has a function of counting the number of times the clock signal input to the terminal CCLK rises. The counter circuit CNT may also have a function of counting the number of times the clock signal input to the terminal CCLK falls, or a function of counting the total number of times the clock signal input to the terminal CCLK rises and falls. Here, inputting a signal to the terminal CRS can reset the result of the counting by the counter circuit CNT. Therefore, the signal input to the terminal CRS is a count reset signal.

[0287] The demultiplexer circuit DeMUX has a function of outputting a signal input to the terminal DIN to one of the terminals OSS[1] to OSS[m] based on signals input from the terminals DSL(1) to DSL(log2(m)). As described above, the signal input to the terminal DSL can be a log2(m)-bit digital signal.

[0288] 23, the demultiplexer circuit DeMUX first outputs a signal input to the terminal DIN to the terminal OSS corresponding to the value represented by the digital signal input to the terminal INI. The counter circuit CNT performs counting, and the value of the digital signal input to the terminal DSL changes. In response to this, the terminal OSS, from which the demultiplexer circuit DeMUX outputs a signal, also changes.

[0289] The row driver circuit 33 shown in Fig. 23 can be driven by the method shown in Fig. 6A and Fig. 6B. In the following, an example of a method for driving the row driver circuit 33 shown in Fig. 23 will be described, assuming that the counter circuit CNT counts the number of rising edges of the clock signal input to the terminal CCLK.

[0290] Fig. 24 is a timing chart showing a detailed example of a driving method when the row driver circuit 33 shown in Fig. 23 is driven in the mode shown in Fig. 6A. In Fig. 24, an example of a driving method of the row driver circuit 33 is shown, divided into periods T701 to T705. Here, during periods T701 to T705, the clock signal input to the terminal CCLK rises and falls once each.

[0291] Before the period T701, the potential of the terminal CRS is high, and the potential of the terminal DIN is low.

[0292] In period T701, the potential of terminal CRS is set to low. In this state, when a digital signal with a value of "0" is input to terminal INI, a digital signal with a value of "0" is input to terminal DSL. Also, a high-potential signal is input to terminal DIN. As a result, the potential of terminal OSS[1] becomes high. As a result, a selection signal is output from terminal SL[1] and a reset signal is output from terminal RS[1].

[0293] During period T702, the counter circuit CNT performs counting, and the value of the digital signal input to the terminal DSL becomes "1." Also, the potential of the terminal DIN is high. As a result, the potential of the terminal OSS[2] becomes high. As a result, a selection signal is output from the terminal SL[2], and a reset signal is output from the terminal RS[2].

[0294] During period T703, the value of the digital signal input to terminal DSL is assumed to be "p-1." Also, the potential of terminal DIN is high. As a result, the potential of terminal OSS[p] becomes high. As a result, a selection signal is output from terminal SL[p], and a reset signal is output from terminal RS[p].

[0295] During period T704, the counter circuit CNT performs counting, and the value of the digital signal input to the terminal DSL becomes "p." Also, the potential of the terminal DIN is high. As a result, the potential of the terminal OSS[p+1] becomes high. As a result, a selection signal is output from the terminal SL[p+1], and a reset signal is output from the terminal RS[p+1].

[0296] During period T705, the value of the digital signal input to terminal DSL becomes "m-1." Also, the potential of terminal DIN is high. As a result, the potential of terminal OSS[m] becomes high. As a result, a selection signal is output from terminal SL[m], and a reset signal is output from terminal RS[m].

[0297] 24, the demultiplexer circuit DeMUX sequentially outputs signals to terminals OSS[1] through OSS[m] based on the clock signal input to terminal CCLK. Corresponding to these signals, selection signals are sequentially output to terminals SL[1] through SL[m], and reset signals are sequentially output to terminals RS[1] through RS[m]. This allows imaging data to be sequentially read from the pixels 31 in the first through m-th rows.

[0298] 25 is a timing chart showing a detailed example of the driving method shown in FIG. 6B, and shows an example of the driving method of the row driver circuit 33 divided into periods T711 to T714. In the driving method shown in FIG. 25, the pixels 31 in the pth row to the qth row are sequentially scanned to read imaging data from the pixels 31 in the pth to qth rows. Here, during periods T711 to T714, the clock signal input to the terminal CCLK rises and falls once each.

[0299] Before the period T711, the potential of the terminal CRS is high, and the potential of the terminal DIN is low.

[0300] In period T711, the potential of terminal CRS is set to low. In this state, when a digital signal with a value of "p-1" is input to terminal INI, a digital signal with a value of "p-1" is input to terminal DSL. Also, a high-potential signal is input to terminal DIN. As a result, the potential of terminal OSS[p] becomes high. As a result, a selection signal is output from terminal SL[p], and a reset signal is output from terminal RS[p].

[0301] During period T712, the counter circuit CNT performs counting, and the value of the digital signal input to the terminal DSL becomes "p." Also, the potential of the terminal DIN is high. As a result, the potential of the terminal OSS[p+1] becomes high. As a result, a selection signal is output from the terminal SL[p+1], and a reset signal is output from the terminal RS[p+1].

[0302] During period T713, the value of the digital signal input to terminal DSL is assumed to be "q-1." Also, the potential of terminal DIN is high. As a result, the potential of terminal OSS[q] becomes high. As a result, a selection signal is output from terminal SL[q], and a reset signal is output from terminal RS[q].

[0303] During period T714, the potential of the terminal CRS is set to high. This resets the counting result of the counter circuit CNT, and the demultiplexer circuit DeMUX stops outputting a high-potential signal to the terminal OSS. Furthermore, during and after period T714, the potential of the terminal DIN is set to low.

[0304] 25, the demultiplexer circuit DeMUX sequentially outputs signals to terminals OSS[p] through OSS[q] based on the clock signal input to terminal CCLK. Corresponding to these signals, selection signals are sequentially output to terminals SL[p] through SL[q], and reset signals are sequentially output to terminals RS[p] through RS[q]. This allows imaging data to be sequentially read from the pixels 31 in the pth through qth rows.

[0305] 24 and 25 during the readout period, the semiconductor device of one embodiment of the present invention can perform authentication such as fingerprint authentication. As described above, the readout period per row of the pixel 31 can be shorter in the period shown in FIG. 6A than in the period shown in FIG. 6B. Therefore, for example, the period T703 shown in FIG. 24 can be shorter than the period T711 shown in FIG. 25. Therefore, the transmission speed of the scan signal when the row driver circuit 33 is driven by the method shown in FIG. 24 can be faster than the transmission speed of the scan signal when the row driver circuit 33 is driven by the method shown in FIG. 25.

[0306] <Shift register circuit configuration example 4> 26 is a diagram showing a configuration example of the row driver circuit 33. Specifically, it is a diagram showing a configuration example of a shift register circuit included in the row driver circuit 33. The shift register circuit includes a register circuit R, switches SW1a and SW1b, and a signal supply circuit SS. Here, the switches SW1a and SW1b may be transistors, for example. Alternatively, the switches SW1a and SW1b may each be configured using a plurality of transistors.

[0307] Here, the number of register circuits R provided in the row driver circuit 33 shown in FIG. 26 can be less than m. For example, it can be m / 2. The following description will be given assuming that the row driver circuit 33 is provided with m / 2 register circuits R. Note that the number of register circuits R provided in the row driver circuit 33 may be, for example, m / 3, m / 4, or even less. Even in this case, the following description can be referred to by, for example, substituting the numbers as necessary. Furthermore, the row driver circuit 33 may be provided with, for example, the same number of signal supply circuits SS as the number of register circuits R.

[0308] In this specification, for example, m / 2 register circuits R are referred to as register circuits R <1> to register circuit R <m 2>and the m / 2 signal supply circuits SS are represented as signal supply circuits SS <1> ~Signal supply circuit SS <m 2>In FIG. 26, the register circuit R <1> , register circuit R <2> , register circuit R <r>, register circuit R<r+1> , register circuit R<r+2> , register circuit <2r>, signal supply circuit SS <1> , signal supply circuit SS <2> , signal supply circuit SS <r>, signal supply circuit SS<r+1> , signal supply circuit SS<r+2> , and a signal supply circuit SS<2r> (r is an integer between 2 and m / 2).

[0309] Resistor circuit R <1> The terminal SP is electrically connected to the input terminal of the register circuit R. <1> The output terminal of the switch SW1a is electrically connected to one terminal of the switch SW1a, and the other terminal of the switch SW1a is electrically connected to the resistor circuit R <2> The input terminal is electrically connected to the

[0310] Resistor circuit R <2> to register circuit R<r+1> are connected in series with each other. Specifically, for example, the register circuit R <2> The output terminal of the register circuit R <3> The resistor circuit R <3> The output terminal of the register circuit R <4> The resistor circuit R <r>The output terminal of the register circuit R<r+1> The input terminal is electrically connected to the

[0311] Resistor circuit R<r+1> The output terminal of the switch SW1a is electrically connected to one terminal of the switch SW1a, and the other terminal of the switch SW1a is electrically connected to the resistor circuit R<r+2> The resistor circuit R<r+2> to register circuits R<2r+1> are connected in series with each other.

[0312] As described above, for example, the register circuit R <1> to register circuit R <m 2>can be connected in series with each other with a switch SW1a sandwiched between every r register circuits R.

[0313] Also, the register circuit R <1> The output terminal to which one terminal of the switch SW1a is electrically connected is also electrically connected to one terminal of the switch SW1b. The other terminal of the switch SW1b is electrically connected to one terminal of the register circuit R<r+1> Among the input terminals of the register circuit R <r>Similarly, the resistor circuit R<r+1> The output terminal electrically connected to one terminal of the switch SW1a among the output terminals of the register circuit R<2r+1> is also electrically connected to one terminal of the switch SW1b. The other terminal of the switch SW1b is electrically connected to the input terminal electrically connected to the output terminal of the register circuit R<2r> among the input terminals of the register circuit R<2r+1>.

[0314] As described above, for example, the register circuit R <1> , register circuit R<r+1> , and the register circuit R<2r+1> are connected in series with each other via the switch SW1b. <1> to register circuit R<m / 2-r+1> can be connected in series to every r register circuits R via the switch SW1b.

[0315] The output terminal of the register circuit R is electrically connected to the input terminal of the signal supply circuit SS. Furthermore, two terminals SL_PWC out of the terminals SL_PWC(1) to SL_PWC(4) are electrically connected to the input terminal of the signal supply circuit SS. Furthermore, two terminals RS_PWC out of the terminals RS_PWC(1) to RS_PWC(4) are electrically connected to the input terminal of the signal supply circuit SS. In the example shown in FIG. 26, the signal supply circuit SS <1> , signal supply circuit SS <r>, and the signal supply circuit SS<r+2> The terminals SL_PWC(1), SL_PWC(2), RS_PWC(1), and RS_PWC(2) are electrically connected to the signal supply circuit SS <2> , signal supply circuit SS<r+1> , and the signal supply circuit SS<2r> are electrically connected to terminals SL_PWC(3), terminal SL_PWC(4), terminal RS_PWC(3), and terminal RS_PWC(4). Note that the number of terminals SL_PWC and the number of terminals RS_PWC that the row driver circuit 33 has are not limited to four, and the number of terminals SL_PWC and the number of terminals RS_PWC that are electrically connected to one signal supply circuit SS are not limited to two.

[0316] The terminals SL_PWC and RS_PWC can also be electrically connected to the input terminals of the signal supply circuits SS shown in FIGS.

[0317] The following description will be given assuming that r is an odd number, but the following description can also be referred to when r is an even number by appropriately varying the number of terminals SL_PWC and the number of terminals RS_PWC electrically connected to the signal supply circuit SS. Note that, for example, if m / 3 register circuits R and signal supply circuits SS are provided in the shift register circuit of the row driver circuit 33, three terminals SL_PWC and three terminals RS_PWC can be electrically connected to the input terminal of one signal supply circuit SS.

[0318] The output terminal of the signal supply circuit SS is electrically connected to a terminal SL and a terminal RS. Here, the same number of terminals SL as the number of terminals SL_PWC electrically connected to the input terminal of the signal supply circuit SS can be electrically connected to the output terminal of the signal supply circuit SS. Also, the same number of terminals RS as the number of terminals RS_PWC electrically connected to the input terminal of the signal supply circuit SS can be electrically connected to the output terminal of the signal supply circuit SS. FIG. 26 shows a configuration in which the output terminal of one signal supply circuit SS is electrically connected to two terminals SL and two terminals RS. Specifically, for example, when the signal supply circuit SS <1> The output terminals of the signal supply circuit SS can be electrically connected to the terminals SL[1], SL[2], RS[1], and RS[2]. <2> The output terminals of the signal supply circuit SS can be electrically connected to the terminals SL[3], SL[4], RS[3], and RS[4]. <r>The terminals SL[2r-1], SL[2r], RS[2r-1], and RS[2r] can be electrically connected to the output terminals of the resistor circuit R<r+1> The output terminals can be electrically connected to the terminals SL[2r+1], SL[2r+2], RS[2r+1], and RS[2r+2].

[0319] By electrically connecting a plurality of terminals SL and a plurality of terminals RS to one signal supply circuit SS, it is possible to reduce the number of register circuits R provided in the row driver circuit 33. This reduces the area occupied by the row driver circuit 33, thereby enabling the miniaturization of, for example, the semiconductor device 10.

[0320] As will be described in more detail below, the signal supply circuit SS can output a signal corresponding to a signal input to terminal SL_PWC from terminal SL, and can output a signal corresponding to a signal input to terminal RS_PWC from terminal RS.

[0321] A start pulse signal is input to the terminal SP. Therefore, the terminal SP is a start pulse signal input terminal. When the start pulse signal is input to the terminal SP, and the switch SW1a is in an on state and the switch SW1b is in an off state, the register circuit R <1> to register circuit R <m 2>In other words, all the register circuits R can output signals. Therefore, when the switch SW1a is in the on state and the switch SW1b is in the off state, for example, the register circuit R <2> is the resistor circuit R <1> It can be said that the register circuit R is the next stage after the register circuit R.

[0322] When a start pulse signal is input to the terminal SP, and the switch SW1a is in the OFF state and the switch SW1b is in the ON state, the register circuit R <1> After the signal is output, the register circuit R<r+1> In other words, the register circuit R <2> to register circuit R <r>The register circuit R can be configured not to output a signal.<r+1> After the register circuit R<2r+1> outputs a signal, the register circuit R<2r+1> outputs a signal.<m / 2-r+1> In other words, one register circuit R out of r register circuits R can output a signal. Therefore, when the switch SW1a is in the OFF state and the switch SW1b is in the ON state, for example, the register circuit R<r+1> is the resistor circuit R <1> It can be said that the register circuit R is the next stage after the register circuit R.

[0323] The row driver circuit 33 configured as shown in Fig. 26 can be driven in a first mode and a second mode. Specifically, in the first mode, the switch SW1a is turned on and the switch SW1b is turned off. This allows signals to be output from, for example, all of the terminals SL[1] to SL[m] and all of the terminals RS[1] to RS[m]. In addition, in the second mode, the switch SW1a is turned off and the switch SW1b is turned on. This allows signals to be output from some of the terminals SL and terminals RS, specifically m / r terminals SL and m / r terminals RS.

[0324] 2A and 2B1, the terminals SL and RS are electrically connected to the pixels 31. Therefore, for example, in the first mode in which signals are output from all the terminals SL and all the terminals RS, imaging data can be read out from all the pixels 31. This allows the imaging data read out from the pixels 31 to be highly accurate.

[0325] The semiconductor device 10 having the row driver circuit 33 configured as shown in Fig. 26 can perform authentication such as fingerprint authentication as shown in Fig. 1B. When performing authentication, it is preferable to drive the row driver circuit 33 configured as shown in Fig. 26 in the first mode in order to improve the accuracy of authentication.

[0326] Furthermore, the semiconductor device 10 having the row driver circuit 33 configured as shown in FIG. 26 can detect the position of a detection object, such as a finger, in contact with or in proximity to the pixel unit 30 shown in FIG. 2A. That is, the semiconductor device 10 having the row driver circuit 33 configured as shown in FIG. 26 functions as a touch sensor or near-touch sensor. Here, in the second mode in which signals are output from some of the terminals SL and RS, the number of register circuits R to be driven can be reduced compared to the first mode. This allows the row driver circuit 33 to be driven at high speed, and the imaging device 15 to capture images at a high frame frequency. Therefore, when the semiconductor device 10 having the row driver circuit 33 configured as shown in FIG. 26 is to function as a touch sensor or near-touch sensor, it is preferable to drive the semiconductor device 10 in the second mode to accurately detect the movement of the detection object.

[0327] As described above, the semiconductor device 10 having the row driver circuit 33 configured as shown in FIG. 26 can accurately detect the movement of a detection target such as a finger while improving the accuracy of authentication, for example.

[0328] As described above, it is preferable that the signal output from the register circuit R and supplied to the register circuit R in the next stage be also supplied to the register circuit R in the previous stage. This makes it possible to prevent the register circuit R in the previous stage from malfunctioning. For example, when the switch SW1a is in the on state and the switch SW1b is in the off state, <2> After signals are output from the terminals SL[3], SL[4], RS[3], and RS[4], which are electrically connected to the register circuit R <1> In addition, when the switch SW1a is in the OFF state and the switch SW1b is in the ON state, the register circuit R<r+1> After signals are output from the terminals SL[2r+1], SL[2r+2], RS[2r+1], and RS[2r+2], which are electrically connected to the register circuit R <1> It is possible to prevent signals from being output from the terminals SL[1], SL[2], RS[1], and RS[2] that are electrically connected to the terminals SL[1], SL[2].

[0329] Which register circuit R can be the preceding register circuit R depends on the driving mode of the semiconductor device 10. For example,<r+1> When the semiconductor device 10 is driven in the first mode, the register circuit R <r>When the semiconductor device 10 is driven in the second mode, the register circuit R <1> Therefore, a switch SW2a and a switch SW2b are provided in the shift register circuit of the row driver circuit 33. The switches SW2a and SW2b may be, for example, transistors. Furthermore, the switches SW2a and SW2b may each be configured with a plurality of transistors.

[0330] For example, the register circuit R<r+1> The output terminal and register circuit R <r>The input terminal of the register circuit R is electrically connected to the input terminal of the register circuit R via the switch SW2a.<r+1> The output terminal and register circuit R <1> and the input terminal of the register circuit R are electrically connected via the switch SW2b. When the semiconductor device 10 is driven in the first mode, the switch SW2a is turned on and the switch SW2b is turned off. On the other hand, when the semiconductor device 10 is driven in the second mode, the switch SW2a is turned off and the switch SW2b is turned on. As a result, when the semiconductor device 10 is driven in the first mode, for example, the register circuit R<r+1> is output, and the register circuit R<r+2> The signal supplied to the register circuit R <r>When the semiconductor device 10 is driven in the second mode, for example, the resistor circuit R<r+1> The signal output by the register circuit R<2r+1> is <1> can also be supplied.

[0331] Although not shown in FIG. 26, for example, the output terminal of the register circuit R<2r+1> and the input terminal of the register circuit R<2r> can be electrically connected via a switch SW2a.<r+1> The input terminal of the resistor circuit R can be electrically connected to the input terminal of the resistor circuit R via the switch SW2b.<m / 2-r+1> The output terminal and register circuit R <m 2-r>and the input terminal of the resistor circuit R<m / 2-r+1> The output terminal and register circuit R<m / 2-2r+1> can be electrically connected to the input terminal via switch SW2b.

[0332] 26 shows a configuration in which a signal output from a register circuit R and supplied to a register circuit R in the next stage back is also supplied to a register circuit R in the previous stage, but this is not a limitation of one aspect of the present invention. For example, a signal output from a register circuit R and supplied to a register circuit R in the next stage back may be supplied to a register circuit R in the stage two stages back, instead of the register circuit R in the stage one stage back. FIG. 27 is a diagram showing a configuration example of a row driver circuit 33 in which a signal output from a register circuit R and supplied to a register circuit R in the next stage back is supplied to a register circuit R in the stage two stages back. Note that terminals SL_PWC, RS_PWC, terminal SL, and terminal RS are not shown in FIG.

[0333] In the row driver circuit 33 having the configuration shown in FIG. 27, when the semiconductor device 10 is driven in the first mode, the register circuit R <1> , the resistor circuit R <3> When the semiconductor device 10 is driven in the second mode, the signal output from the register circuit R <1> The signal output from the register circuit R<2r+1> can be supplied to the register circuit R in the next stage. Note that the signal output from the register circuit R and supplied to the register circuit R in the next stage may be supplied to the register circuit R in the three or more stages preceding it. The same applies to row driver circuits 33 with other configurations.

[0334] FIG. 28A is a diagram showing an example of terminals electrically connected to the register circuit R and terminals electrically connected to the signal supply circuit SS. Terminals CLK(k1), CLK(k2), LIN, OFFS, and RIN are electrically connected to the input terminals of the register circuit R. Terminals ROUT, OSS, and FN are electrically connected to the output terminals of the register circuit R. Terminals OSS, FN, SL_PWC(h1), SL_PWC(h2), RS_PWC(h1), RS_PWC(h2), and RS_ALL are electrically connected to the input terminals of the signal supply circuit SS. Terminals SL[j], SL[j+1], RS[j], and RS[j+1] (j is an integer between 1 and m-1) are electrically connected to the output terminals of the signal supply circuit SS. The register circuit R and the signal supply circuit SS are electrically connected via terminal OSS and also via terminal FN.

[0335] The terminals SL_PWC(h1) and SL_PWC(h2) shown in FIG. 28A can be, for example, any of the terminals SL_PWC(1) to SL_PWC(4), and the terminals RS_PWC(h1) and RS_PWC(h2) can be, for example, any of the terminals RS_PWC(1) to RS_PWC(4). For example, the register circuit R <1> In this case, the terminal SL_PWC(h1) can be the terminal SL_PWC(1), the terminal SL_PWC(h2) can be the terminal SL_PWC(2), the terminal RS_PWC(h1) can be the terminal RS_PWC(1), and the terminal RS_PWC(h2) can be the terminal RS_PWC(2). <2> In this case, terminal SL_PWC(h1) can be terminal SL_PWC(3), terminal SL_PWC(h2) can be terminal SL_PWC(4), terminal RS_PWC(h1) can be terminal RS_PWC(3), and terminal RS_PWC(h2) can be terminal RS_PWC(4).

[0336] As described above, a clock signal can be input to the terminal CLK(k1) and the terminal CLK(k2). Furthermore, by inputting a signal to the terminal RS_ALL, a reset signal can be output from all the terminals RS, for example. This allows the charges accumulated in the capacitors 56 and 57 of the pixel 31 shown in FIG. 2B1 to be reset. Therefore, for example, by inputting a signal to the terminal RS_ALL during the period T1 shown in FIG. 2B2, a reset operation can be performed.

[0337] FIG. 28B shows a register circuit R <1> , register circuit R <2> , register circuit <r>, and a register circuit R<r+1> 28B is a diagram showing terminals LIN and RIN electrically connected to the input terminal and terminal ROUT electrically connected to the output terminal, among terminals electrically connected to the register circuit R <1> The terminals LIN, RIN, and ROUT electrically connected to the terminals LIN, RIN, and ROUT are respectively <1> , terminal RIN <1> , and terminal ROUT <1> It states:

[0338] Terminal LIN <1> A start pulse signal is input to the terminal LIN. <1> is the terminal SP.

[0339] Terminal ROUT <1> is connected to the LIN terminal via the switch SW1a. <2> and is electrically connected to the terminal LIN via switch SW1b.<r+1> Electrically connected to terminal ROUT <2> is the LIN terminal <3> (not shown), and terminal RIN <1> Electrically connected to terminal ROUT <r>is the LIN terminal<r+1> Electrically connected to terminal ROUT<r+1> Although not shown, the terminal LIN<r+2> and is electrically connected to the terminal LIN<2r+1> via the switch SW1b.<r+1> is connected to the terminal RIN via the switch SW2a. <r>and is electrically connected to the terminal RIN <1> and electrically connected to each other.

[0340] 29A is a circuit diagram showing a configuration example of a register circuit R. In the register circuit R shown in Fig. 29A, one of the source or drain of a transistor Tr13, one of the source or drain of a transistor Tr15, one of the source or drain of a transistor Tr17, the gate of a transistor Tr21, one of the source or drain of a transistor Tr23, the gate of a transistor Tr25, and one electrode of a capacitor C21 are electrically connected to a terminal FN.

[0341] 29B is a circuit diagram showing an example configuration of the signal supply circuit SS. The signal supply circuit SS includes transistors Tr81, Tr82, Tr83, Tr84, Tr85, Tr86, Tr87, Tr91, Tr92, Tr93, Tr94, Tr95, Tr96, and Tr97, as well as capacitors C81, C83, C85, C91, C93, and C95.

[0342] 29B, the terminal OSS is electrically connected to one of the source or drain of the transistor Tr81, one of the source or drain of the transistor Tr85, one of the source or drain of the transistor Tr91, and one of the source or drain of the transistor Tr95. The terminal FN is electrically connected to one of the source or drain of the transistor Tr83, the gate of the transistor Tr87, one of the source or drain of the transistor Tr93, and the gate of the transistor Tr97.

[0343] The terminal SL_PWC(h1) is electrically connected to either the source or the drain of the transistor Tr86. The terminal SL_PWC(h2) is electrically connected to either the source or the drain of the transistor Tr96. The terminal RS_PWC(h1) is electrically connected to either the source or the drain of the transistor Tr82. The terminal RS_PWC(h2) is electrically connected to either the source or the drain of the transistor Tr92.

[0344] Terminal SL[j] is electrically connected to the other of the source or drain of transistor Tr86, one of the source or drain of transistor Tr87, and one electrode of capacitor C85. Terminal SL[j+1] is electrically connected to the other of the source or drain of transistor Tr96, one of the source or drain of transistor Tr97, and one electrode of capacitor C95. Terminal RS[j] is electrically connected to the other of the source or drain of transistor Tr82, the other of the source or drain of transistor Tr84, and one electrode of capacitor C81. Terminal RS[j+1] is electrically connected to the other of the source or drain of transistor Tr92, the other of the source or drain of transistor Tr94, and one electrode of capacitor C91.

[0345] The other of the source or drain of transistor Tr81, the gate of transistor Tr82, and the other electrode of capacitor C81 are electrically connected to each other. The other of the source or drain of transistor Tr83, the gate of transistor Tr84, and the other electrode of capacitor C83 are electrically connected to each other. The other of the source or drain of transistor Tr85, the gate of transistor Tr86, and the other electrode of capacitor C85 are electrically connected to each other. The other of the source or drain of transistor Tr91, the gate of transistor Tr92, and the other electrode of capacitor C91 are electrically connected to each other. The other of the source or drain of transistor Tr93, the gate of transistor Tr94, and the other electrode of capacitor C93 are electrically connected to each other. The other of the source or drain of transistor Tr95, the gate of transistor Tr96, and the other electrode of capacitor C95 are electrically connected to each other. By providing the signal supply circuit SS with transistor Tr81, transistor Tr83, transistor Tr85, transistor Tr91, transistor Tr93, or transistor Tr95, the circuit provided in the signal supply circuit SS can be configured as a bootstrap circuit. Note that the signal supply circuit SS does not necessarily have to include transistor Tr81, transistor Tr83, transistor Tr85, transistor Tr91, transistor Tr93, or transistor Tr95. In this case, the signal supply circuit SS may also be configured without capacitor C81, capacitor C83, capacitor C85, capacitor C91, capacitor C93, or capacitor C95.

[0346] In the following description, transistors Tr81 to Tr87 and transistors Tr91 to Tr97 are assumed to be n-channel transistors. However, the following description can be referred to even if p-channel transistors are included, for example, by appropriately reversing the magnitude relationship of the potentials.

[0347] A high potential can be supplied to the gates of transistors Tr81, Tr83, Tr85, Tr91, Tr93, and Tr95. A low potential can be supplied to the other of the source or drain of transistor Tr87 and the other of the source or drain of transistor Tr97.

[0348] When a high-potential signal is input to the terminal OSS, the transistors Tr82, Tr86, Tr92, and Tr96 are turned on. As a result, if the potential of the terminal FN is low, the potential of the terminal RS[j] can be made equal to the potential of the terminal RS_PWC(h1), the potential of the terminal SL[j] can be made equal to the potential of the terminal SL_PWC(h1), the potential of the terminal RS[j+1] can be made equal to the potential of the terminal RS_PWC(h2), and the potential of the terminal SL[j+1] can be made equal to the potential of the terminal SL_PWC(h2). In other words, the signal supply circuit SS can output a signal input to terminal RS_PWC(h1) to terminal RS[j], output a signal input to terminal SL_PWC(h1) to terminal SL[j], output a signal input to terminal RS_PWC(h2) to terminal RS[j+1], and output a signal input to terminal SL_PWC(h2) to terminal SL[j+1].

[0349] When a high-potential signal is input to the terminal FN, the transistors Tr84, Tr87, Tr94, and Tr97 are turned on. As a result, if the potential of the terminal OSS is low, the potential of the terminal RS can be made equal to the potential of the terminal RS_ALL. In other words, the signal supply circuit SS can output the signal input to the terminal RS_ALL to the terminal RS.

[0350] The configuration shown in FIG. 29B can also be applied to the input terminals of the signal supply circuits SS shown in FIGS.

[0351] 30 and 31 are timing charts showing an example of a method for driving the row driver circuit 33 configured as shown in FIG. 26. Specifically, they show an example of a method for driving the shift register circuit of the row driver circuit 33 during period T5, which is the readout period shown in FIG. 2B2. FIG. 30 shows an example of a driving method in the first mode, divided into periods T801 to T805, and shows an example of a method for driving the row driver circuit 33. FIG. 31 shows an example of a driving method in the second mode, divided into periods T811 to T815, and shows an example of a method for driving the row driver circuit 33.

[0352] First, an example of a method for driving the row driver circuit 33 in the first mode will be described. As shown in Fig. 30, in periods T801 to T805, the switches SW1a and SW2a are turned on, and the switches SW1b and SW2b are turned off. As a result, the semiconductor device 10 having the row driver circuit 33 configured as shown in Fig. 26 is driven in the first mode.

[0353] Also, during the period T801, the terminal LIN <1> A high potential signal is input as a start pulse signal to the terminal SL_PWC(1). As a result, in the next period, period T802, the signal input to the terminal SL_PWC(1) can be output from the terminal SL[1], the signal input to the terminal SL_PWC(2) can be output from the terminal SL[2], the signal input to the terminal RS_PWC(1) can be output from the terminal RS[1], and the signal input to the terminal RS_PWC(2) can be output from the terminal RS[2].

[0354] In period T802, a selection signal is input to terminal SL_PWC(1), a reset signal is input to terminal RS_PWC(1), then a selection signal is input to terminal SL_PWC(2), and a reset signal is input to terminal RS_PWC(2). As a result, a selection signal is output from terminal SL[1], a reset signal is output from terminal RS[1], then a selection signal is output from terminal SL[2], and a reset signal is output from terminal RS[2].

[0355] Also, during the period T802, the terminal ROUT <1> As mentioned above, the switch SW1a is in the ON state and the switch SW1b is in the OFF state, so the terminal ROUT <1> The high potential signal output from the terminal LIN <2> A high-potential signal is input to the terminal LIN <2> By inputting the signals to terminal SL_PWC(3), in the next period, period T803, the signal input to terminal SL_PWC(3) can be output from terminal SL[3], the signal input to terminal SL_PWC(4) can be output from terminal SL[4], the signal input to terminal RS_PWC(3) can be output from terminal RS[3], and the signal input to terminal RS_PWC(4) can be output from terminal RS[4].

[0356] During period T803, a selection signal is input to terminal SL_PWC(3), a reset signal is input to terminal RS_PWC(3), then a selection signal is input to terminal SL_PWC(4), and a reset signal is input to terminal RS_PWC(4). As a result, a selection signal is output from terminal SL[3], a reset signal is output from terminal RS[3], then a selection signal is output from terminal SL[4], and a reset signal is output from terminal RS[4].

[0357] Also, during the period T803, the terminal ROUT <2> A high-potential signal is output from the terminal LIN. <3> and terminal RIN <1> are supplied to.

[0358] During period T804, terminal LIN <m 2>30, a high-potential signal is input to terminal SL_PWC(3). As a result, in the next period, period T805, the signal input to terminal SL_PWC(3) is output from terminal SL[m-1], the signal input to terminal SL_PWC(4) is output from terminal SL[m], the signal input to terminal RS_PWC(3) is output from terminal RS[m-1], and the signal input to terminal RS_PWC(4) is output from terminal RS[m]. Note that in period T804, a selection signal is input to terminal SL_PWC(1) and a reset signal is input to terminal RS_PWC(1), and then a selection signal is input to terminal SL_PWC(2) and a reset signal is input to terminal RS_PWC(2). As a result, although not shown in FIG. 30, a selection signal is output from terminal SL[m-3] and a reset signal is output from terminal RS[m-3], and then a selection signal is output from terminal SL[m-2] and a reset signal is output from terminal RS[m-2].

[0359] In period T805, a selection signal is input to terminal SL_PWC(3), a reset signal is input to terminal RS_PWC(3), then a selection signal is input to terminal SL_PWC(4), and a reset signal is input to terminal RS_PWC(4). As a result, a selection signal is output from terminal SL[m-1], a reset signal is output from terminal RS[m-1], then a selection signal is output from terminal SL[m], and a reset signal is output from terminal RS[m].

[0360] Also, during the period T805, the terminal ROUT <m 2>A high potential signal is output from the terminal RIN <m 2-1>are supplied to.

[0361] As described above, in the driving method shown in FIG. 30, the terminal LIN <1> The start pulse signal input to the register circuit R <1> From the register circuit R <m 2>In response to this, selection signals are sequentially output from terminals SL[1] to SL[m], and reset signals are sequentially output from terminals RS[1] to RS[m]. This allows imaging data to be sequentially read from the pixels 31 in the first to mth rows.

[0362] Next, an example of a method for driving the row driver circuit 33 in the second mode will be described. As shown in Fig. 31, in periods T811 to T815, the switches SW1a and SW2a are turned off, and the switches SW1b and SW2b are turned on. As a result, the semiconductor device 10 having the row driver circuit 33 configured as shown in Fig. 26 is driven in the second mode.

[0363] Also, during the period T811, the terminal LIN <1> A high potential signal is input as a start pulse signal to the terminal SL_PWC(1). As a result, in the next period, period T812, the signal input to the terminal SL_PWC(1) can be output from the terminal SL[1], the signal input to the terminal SL_PWC(2) can be output from the terminal SL[2], the signal input to the terminal RS_PWC(1) can be output from the terminal RS[1], and the signal input to the terminal RS_PWC(2) can be output from the terminal RS[2].

[0364] In period T812, a selection signal is input to terminals SL_PWC(1) and SL_PWC(2), and a reset signal is input to terminals RS_PWC(1) and RS_PWC(2). As a result, a selection signal is output from terminals SL[1] and SL[2], and a reset signal is output from terminals RS[1] and RS[2].

[0365] Also, during the period T812, the terminal ROUT <1> As mentioned above, the switch SW1a is in the OFF state and the switch SW1b is in the ON state, so the terminal ROUT <1> The high potential signal output from the terminal LIN<r+1> A high-potential signal is input to the terminal LIN<r+1> By inputting the signals to terminal SL_PWC(3), in the next period, period T813, the signal input to terminal SL_PWC(3) can be output from terminal SL[2r+1], the signal input to terminal SL_PWC(4) can be output from terminal SL[2r+2], the signal input to terminal RS_PWC(3) can be output from terminal RS[2r+1], and the signal input to terminal RS_PWC(4) can be output from terminal RS[2r+2].

[0366] In period T813, a selection signal is input to terminals SL_PWC(3) and SL_PWC(4), and a reset signal is input to terminals RS_PWC(3) and RS_PWC(4). As a result, a selection signal is output from terminals SL[2r+1] and SL[2r+2], and a reset signal is output from terminals RS[2r+1] and RS[2r+2].

[0367] Also, during the period T813, the terminal ROUT<r+1> As described above, the switches SW1a and SW2a are in the OFF state, and the switches SW1b and SW2b are in the ON state.<r+1> The signal output from terminal LIN<2r+1> and terminal RIN <1> are supplied to.

[0368] During period T814, terminal LIN<m / 2-r+1> A high-potential signal is input to terminal SL_PWC(1) and terminal SL_PWC(2). As a result, in the next period, period T815, the signal input to terminal SL_PWC(3) is output from terminal SL[m-2r+1], the signal input to terminal SL_PWC(4) is output from terminal SL[m-2r+2], the signal input to terminal RS_PWC(3) is output from terminal RS[m-2r+1], and the signal input to terminal RS_PWC(4) is output from terminal RS[m-2r+2]. Note that in period T814, a selection signal is input to terminals SL_PWC(1) and SL_PWC(2), and a reset signal is input to terminals RS_PWC(1) and RS_PWC(2). As a result, although not shown in Figure 31, a selection signal is output from terminal SL[m-4r+1] and terminal SL[m-4r+2], and a reset signal is output from terminal RS[m-4r+1] and terminal RS[m-4r+2].

[0369] In period T815, a selection signal is input to terminals SL_PWC(3) and SL_PWC(4), and a reset signal is input to terminals RS_PWC(3) and RS_PWC(4). As a result, a selection signal is output from terminals SL[m-2r+1] and SL[m-2r+2], and a reset signal is output from terminals RS[m-2r+1] and RS[m-2r+2].

[0370] Also, during the period T815, the terminal ROUT<m / 2-r+1> A high potential signal is output from the terminal RIN<m / 2-2r+1> are supplied to.

[0371] As described above, in the driving method shown in FIG. 31, the terminal LIN <1> During the period T812 to the period T815, the start pulse signal input to the register circuit R <1> From the register circuit R<m / 2-r+1> The image data is sequentially transmitted through one of the r register circuits R up to the pixel 31. In response to this, a selection signal is sequentially output from the terminal SL, and a reset signal is sequentially output from the terminal RS, thereby allowing the image data to be read out from the pixel 31.

[0372] 31, multiple terminals SL output selection signals in parallel, and multiple terminals RS output reset signals in parallel. For example, during period T812, terminals SL[1] and SL[2] output selection signals in parallel, and terminals RS[1] and RS[2] output reset signals in parallel. This increases the strength of the signal representing the imaging data output from the pixel 31 when the imaging data is read out. Therefore, for example, detection using the read imaging data can be performed with high accuracy. For example, the position of a detection object, such as a finger, in contact with or close to the pixel unit 30 can be detected with high accuracy.

[0373] <Configuration example of semiconductor device_2> Fig. 32 is a block diagram showing a configuration example of semiconductor device 10. As shown in Fig. 1A, semiconductor device 10 has light emitting device 13 and imaging device 15. Note that although Fig. 32 does not show the boundary between light emitting device 13 and imaging device 15, semiconductor device 10 shown in Fig. 32 has imaging device 15 shown in Fig. 2A. Therefore, the description of the configuration described in Fig. 2A will be omitted as appropriate.

[0374] The semiconductor device 10 has a pixel section 84 in which pixels 80 are arranged in a matrix. The semiconductor device 10 also has a control circuit 32, a row driver circuit 33, a CDS circuit 34, a readout circuit 36, a detection circuit 37, a gate driver circuit 83, and a data driver circuit 86.

[0375] The pixel 80 can be configured to include pixel 81 and pixel 82 in addition to pixel 31. For example, pixel 81 has a function of emitting light for displaying an image in a pixel section 84. Furthermore, pixel 82 has a function of emitting light for irradiating an object to be detected. In other words, pixel 82 has a function of emitting light 23 shown in FIGS. 1A and 1B, etc. Here, pixel 81, pixel 82, and pixel 31 can be referred to as sub-pixels.

[0376] The pixel 31 has a light-emitting element (also called a light-emitting device) that emits, for example, visible light, and the pixel 82 has a light-emitting element that emits infrared light.

[0377] As the light-emitting element, it is preferable to use an EL element such as an OLED (organic light-emitting diode) or a QLED (quantum-dot light-emitting diode). Examples of the light-emitting substance contained in the EL element include a fluorescent material, a phosphorescent material, a thermally activated delayed fluorescence (TADF) material, or an inorganic compound (e.g., a quantum dot material). Alternatively, an LED such as a micro LED (light-emitting diode) can be used as the light-emitting element.

[0378] The gate driver circuit 83 is electrically connected to the pixels 81 and 82 via gate lines. The data driver circuit 86 is electrically connected to the pixels 81 and 82 via data lines.

[0379] The gate driver circuit 83 has a function of selecting the pixel 81 and the pixel 82 to which data representing the light emission intensity of the light-emitting element is written. The data driver circuit 86 has a function of generating data representing the light emission intensity of the light-emitting element of the pixel 81 and data representing the light emission intensity of the light-emitting element of the pixel 82. The gate driver circuit 83 and the data driver circuit 86 are drive circuits for driving the pixel 81 and the pixel 82.

[0380] The drive circuit for driving pixel 81 and the drive circuit for driving pixel 82 may be separate. The main function of pixel 82 is to emit light to irradiate the detection target. Therefore, for example, all pixels 82 may emit light of the same brightness. In this case, the drive circuit for driving pixel 82 may have a simplified configuration that does not include, for example, a high-performance sequential circuit.

[0381] Fig. 33 is a block diagram showing a configuration example of the semiconductor device 10, which is a modified example of the semiconductor device 10 shown in Fig. 32. The semiconductor device 10 shown in Fig. 33 differs from the semiconductor device 10 shown in Fig. 32 in that the pixel 80 does not have a pixel 82.

[0382] 33, a light source 82E that emits light to irradiate an object to be detected is provided outside a pixel section 84. For example, an LED that emits high-intensity near-infrared light can be used as the light source 82E. Because the light source 82E is provided outside the pixel section 84, it can be turned on by a control separate from that of the semiconductor device 10.

[0383] 33 are merely an example and are not limited to these. The light source 82E may be an element of a device in which the semiconductor device 10 is installed. Alternatively, the light source 82E may be a device separate from the semiconductor device 10.

[0384] The configuration of the pixels 80 is not limited to the configurations shown in FIGS. 32 and 33, and various arrangements can be adopted.

[0385] <Pixel configuration example 2> 34A is a circuit diagram showing an example configuration of a pixel circuit PIX1 that can be used for pixel 81 and pixel 82. The pixel circuit PIX1 has a light-emitting element EL1, transistors M1, M2, and M3, and a capacitor C101. Here, an example is shown in which a light-emitting diode is used as the light-emitting element EL1. It is preferable to use an organic EL element that emits visible light or an organic EL element that emits infrared light as the light-emitting element EL1.

[0386] One of the source and the drain of the transistor M1 is electrically connected to the wiring S1. The other of the source and the drain of the transistor M1 is electrically connected to the gate of the transistor M2 and one electrode of the capacitor C101. The gate of the transistor M1 is electrically connected to the wiring G1. The other of the source and the drain of the transistor M2 is electrically connected to the wiring V2. The other of the source and the drain of the transistor M2 is electrically connected to the anode of the light-emitting element EL1 and one of the source and the drain of the transistor M3. The other of the source and the drain of the transistor M3 is electrically connected to the wiring V0. The gate of the transistor M3 is electrically connected to the wiring G2. The cathode of the light-emitting element EL1 is electrically connected to the wiring V1.

[0387] The wirings G1 and G2 can be electrically connected to the gate driver circuit 83 shown in Figures 32 and 33. The wiring S1 can be electrically connected to the data driver circuit 86 shown in Figures 32 and 33.

[0388] A constant potential is supplied to the wiring V1 and the wiring V2. Light can be emitted by setting the anode side of the light-emitting element EL1 at a high potential and the cathode side at a low potential. The transistor M1 is controlled by a signal supplied to the wiring G1 and functions as a selection transistor for controlling the selection state of the pixel circuit PIX1. The transistor M2 also functions as a drive transistor for controlling the current flowing through the light-emitting element EL1 according to the potential supplied to its gate.

[0389] When the transistor M1 is on, the potential supplied to the wiring S1 is supplied to the gate of the transistor M2, and the light emission luminance of the light-emitting element EL1 can be controlled according to the potential. The transistor M3 is controlled by a signal supplied to the wiring G2. By turning on the transistor M3, the potential between the transistor M3 and the light-emitting element EL1 can be reset to a constant potential supplied from the wiring V0. This allows a potential to be written to the gate of the transistor M2 while the source potential of the transistor M2 is stabilized.

[0390] Figure 34B shows an example of a pixel circuit PIX2, which is different from the pixel circuit PIX1. The pixel circuit PIX2 has a boost function. The pixel circuit PIX2 includes a light-emitting element EL2, a transistor M4, a transistor M5, a transistor M6, a transistor M7, a capacitor C102, and a capacitor C103. Here, an example is shown in which a light-emitting diode is used as the light-emitting element EL2.

[0391] One of the source or drain of the transistor M4 is electrically connected to a wiring S4. The other of the source or drain of the transistor M4 is electrically connected to a gate of a transistor M6, one electrode of a capacitor C102, and one electrode of a capacitor C103. The gate of the transistor M4 is electrically connected to a wiring G1. One of the source or drain of the transistor M5 is electrically connected to a wiring S5. The other of the source or drain of the transistor M5 is electrically connected to the other electrode of the capacitor C103. The gate of the transistor M5 is electrically connected to a wiring G3.

[0392] One of the source and the drain of the transistor M6 is electrically connected to the wiring V2. The other of the source and the drain of the transistor M6 is electrically connected to one of the source and the drain of the transistor M7 and the anode of the light-emitting element EL2. The other of the source and the drain of the transistor M7 is electrically connected to the wiring V0. The gate of the transistor M7 is electrically connected to the wiring G2. The cathode of the light-emitting element EL2 is electrically connected to the wiring V1.

[0393] The wirings G1 to G3 can be electrically connected to the gate driver circuit 83 shown in Figures 32 and 33. The wirings S4 and S5 can be electrically connected to the data driver circuit 86 shown in Figures 32 and 33.

[0394] The transistor M4 is controlled by a signal supplied to the wiring G1, and the transistor M5 is controlled by a signal supplied to the wiring G3. The transistor M6 functions as a drive transistor that controls the current flowing through the light-emitting element EL2 in accordance with the potential supplied to the gate.

[0395] The light emission luminance of the light-emitting element EL2 can be controlled according to the potential supplied to the gate of the transistor M6. The transistor M7 is controlled by a signal supplied to the wiring G2. By turning on the transistor M7, the potential between the transistor M6 and the light-emitting element EL2 can be reset to a constant potential supplied from the wiring V0. This allows a potential to be written to the gate of the transistor M6 while the source potential of the transistor M6 is stabilized. Furthermore, by setting the potential supplied from the wiring V0 to the same potential as or lower than the wiring V1, the light emission of the light-emitting element EL2 can be suppressed.

[0396] The boosting function of the pixel circuit PIX2 will be described below.

[0397] First, the potential "D1" of the wiring S4 is supplied to the gate of the transistor M6 via the transistor M4, and at the same time, the reference potential "V ref At this time, the capacitor C103 is supplied with "D1-V ref Next, the gate of the transistor M6 is set to a floating state, and the potential "D2" of the wiring S5 is supplied to the other electrode of the capacitor C103 via the transistor M5. Here, the potential "D2" is a potential for addition.

[0398] At this time, the capacitance value of the capacitor C103 is C3, the capacitance value of the capacitor C102 is C2, and the capacitance value of the gate of the transistor M6 is C M6 Then, the potential of the gate of transistor M6 is D1+(C3 / (C3+C2+C M6 ))×(D2-V ref )) where the value of C3 is C2+C M6 Assuming that the value is sufficiently larger than the value of C3 / (C3+C2+C M6 ) is close to 1. Therefore, the potential at the gate of transistor M6 is "D1 + (D2 - V ref )” and D1=D2, and V ref If =0, then "D1+(D2-V ref ))”="2D1".

[0399] In other words, if the circuit is designed appropriately, a potential that is approximately twice the potential that can be input from the wiring S4 or the wiring S5 can be supplied to the gate of the transistor M6.

[0400] This effect allows a high voltage to be generated even when a general-purpose driver IC is used, thereby lowering the input voltage and reducing power consumption.

[0401] The pixel circuit PIX2 may also have the configuration shown in FIG. 34C. The pixel circuit PIX2 shown in FIG. 34C differs from the pixel circuit PIX2 shown in FIG. 34B in that it includes a transistor M8. In the pixel circuit PIX2 shown in FIG. 34C, one of the source and the drain of the transistor M8 is electrically connected to the other of the source and the drain of the transistor M5 and the other electrode of the capacitor C103. The other of the source and the drain of the transistor M8 is electrically connected to a wiring V0. The gate of the transistor M8 is electrically connected to a wiring G1. In addition, one of the source and the drain of the transistor M5 is electrically connected to a wiring S4.

[0402] 34B, as described above, the pixel circuit PIX2 performs the operation of supplying the reference potential and the potential for addition to the other electrode of the capacitor C103 via the transistor M5. In this case, two lines S4 and S5 are required, and the reference potential and the potential for addition must be rewritten alternately on the line S5.

[0403] In the pixel circuit PIX2 shown in Figure 34C, although the number of transistors M8 is increased, a dedicated path for supplying the reference potential is provided, thereby reducing the number of wires S5. Also, the gate of transistor M8 can be connected to wire G1, and wire V0 can be used for supplying the reference potential, so the number of wires connected to transistor M8 does not increase. Furthermore, because the reference potential and the potential for addition are not alternately rewritten on a single wire, high-speed operation with low power consumption is possible.

[0404] In addition, in FIG. 34B and FIG. 34C, the reference potential "V ref In this case, a potential approximately three times the potential that can be input from the wiring S4 or the wiring S5 can be supplied to the gate of the transistor M6. Note that the inverted potential means a potential whose absolute value of the difference from a certain reference potential is the same (or approximately the same) but which is different from the original potential. When the original potential is "D1", the inverted potential is "D1B", and the reference potential is V0, the relationship V0 = (D1 + D1B) / 2 should be satisfied.

[0405] In the semiconductor device according to one embodiment of the present invention, an image may be displayed by emitting pulsed light from a light-emitting element. By shortening the driving time of the light-emitting element, the power consumption and heat generation of the semiconductor device can be reduced. Organic EL elements are particularly suitable because of their excellent frequency characteristics. The frequency can be, for example, from 1 kHz to 100 MHz.

[0406] <Configuration example 3 of semiconductor device> 35 is a cross-sectional view showing an example of the configuration of the semiconductor device 10. The semiconductor device 10 has a light receiving element 110, a light emitting element 190, and a light emitting element 180. The light receiving element 110 corresponds to the organic photodiode of the pixel 31. The light emitting element 190 corresponds to the organic EL element (emitting infrared light) of the pixel 82. The light emitting element 180 corresponds to the organic EL element (emitting visible light) of the pixel 81.

[0407] The organic EL element (light-emitting element 180) of pixel 81 and the organic EL element (light-emitting element 190) of pixel 82 can have the same configuration except for the light-emitting layer. Therefore, here, the details of light-emitting element 190 will be described, and a description of light-emitting element 180 will be omitted.

[0408] The light receiving element 110 has a pixel electrode 111, a common layer 112, a photoelectric conversion layer 113, a common layer 114, and a common electrode 115. The light emitting element 190 has a pixel electrode 191, a common layer 112, a light emitting layer 193, a common layer 114, and a common electrode 115. The light emitting element 180 has a light emitting layer 183 that is different from the light emitting layer 193.

[0409] The pixel electrode 111, the pixel electrode 191, the common layer 112, the photoelectric conversion layer 113, the light-emitting layer 193, the common layer 114, and the common electrode 115 may each have a single-layer structure or a multilayer structure.

[0410] The pixel electrode 111 and the pixel electrode 191 are located on the insulating layer 214. The pixel electrode 111 and the pixel electrode 191 can be formed using the same material and in the same process.

[0411] The common layer 112 is located on the pixel electrode 111 and the pixel electrode 191. The common layer 112 is a layer that is used in common by the light receiving element 110 and the light emitting element 190.

[0412] The photoelectric conversion layer 113 has a region overlapping with the pixel electrode 111 via the common layer 112. The light-emitting layer 193 has a region overlapping with the pixel electrode 191 via the common layer 112. The photoelectric conversion layer 113 includes a first organic compound. The light-emitting layer 193 includes a second organic compound different from the first organic compound.

[0413] The common layer 114 is located on the common layer 112, the photoelectric conversion layer 113, and the light-emitting layer 193. The common layer 114 is a layer that is used in common by the light-receiving element 110 and the light-emitting element 190.

[0414] The common electrode 115 has an area overlapping with the pixel electrode 111 via the common layer 112, the photoelectric conversion layer 113, and the common layer 114. The common electrode 115 also has an area overlapping with the pixel electrode 191 via the common layer 112, the light-emitting layer 193, and the common layer 114. The common electrode 115 is a layer used in common by the light-receiving element 110 and the light-emitting element 190.

[0415] In the semiconductor device 10, an organic compound is used for the photoelectric conversion layer 113 of the light-receiving element 110. The layers of the light-receiving element 110 other than the photoelectric conversion layer 113 can have a common configuration with the light-emitting element 190 (organic EL element). Therefore, the light-receiving element 110 can be formed in parallel with the formation of the light-emitting element 190 by simply adding a step of forming the photoelectric conversion layer 113 to the manufacturing process of the light-emitting element 190. Furthermore, the light-emitting element 190 and the light-receiving element 110 can be formed on the same substrate. Therefore, the light-receiving element 110 can be built into a display device without significantly increasing the number of manufacturing steps. Note that the light-receiving element 110 and the light-emitting element 190 may have layers that are manufactured separately from each other in addition to the photoelectric conversion layer 113 and the light-emitting layer 193.

[0416] The semiconductor device 10 has a light receiving element 110, a light emitting element 190, a transistor 141, a transistor 142, and the like between a pair of substrates (substrate 151 and substrate 152). Here, the transistor 141 can be, for example, the transistor 51 shown in FIG. 2B1. The transistor 142 can be, for example, the transistor M2 or the transistor M3 shown in FIG. 34A, or the transistor M6 or the transistor M7 shown in FIGS. 34B and 34C.

[0417] In the light-receiving element 110, the common layer 112, photoelectric conversion layer 113, and common layer 114, which are respectively located between the pixel electrode 111 and the common electrode 115, may be organic layers (layers containing an organic compound). The pixel electrode 111 preferably has a function of reflecting visible light and infrared light. The common electrode 115 has a function of transmitting visible light and infrared light.

[0418] The light receiving element 110 has a function of detecting light. Specifically, the light receiving element 110 is a photoelectric conversion element that converts incident light 25 (visible light, infrared light, or light including both visible light and infrared light) into an electrical signal.

[0419] A light-shielding layer 148 is provided on the surface of the substrate 152 facing the substrate 151. The light-shielding layer 148 has openings at positions overlapping the light receiving element 110 and the light emitting element 190. By providing the light-shielding layer 148, the range in which the light receiving element 110 detects light can be controlled.

[0420] The light-shielding layer 148 can be made of a material that blocks light emitted by the light-emitting element 190. The light-shielding layer 148 preferably absorbs visible light and infrared light. The light-shielding layer 148 can be made of, for example, a metal material, or a resin material containing a pigment (e.g., carbon black) or a dye. The light-shielding layer 148 may have a laminated structure of a red color filter, a green color filter, and a blue color filter.

[0421] Furthermore, a filter 149 that cuts off light with wavelengths shorter than visible light may be provided in an opening of the light-shielding layer 148 that is provided at a position overlapping the light-receiving element 110. As the filter 149, for example, a long-pass filter that cuts off light with wavelengths shorter than visible light (ultraviolet light) can be used. As a filter that cuts off ultraviolet light, for example, a resin film or an inorganic insulating film can be used. By providing the filter 149, it is possible to suppress the incidence of ultraviolet light on the light-receiving element 110, and it is possible to detect visible light and infrared light with low noise.

[0422] As shown in FIG. 36A, the filter 149 may be stacked on the light receiving element 110.

[0423] 36B, filter 149 may be lenticular. Lens-shaped filter 149 is a convex lens having a convex surface facing substrate 151. Alternatively, filter 149 may be arranged so that the convex surface faces substrate 152.

[0424] When both the light-shielding layer 148 and the lens-type filter 149 are formed on the same surface of the substrate 152, the order of formation does not matter. Although Fig. 36B shows an example in which the lens-type filter 149 is formed first, the light-shielding layer 148 may also be formed first. In Fig. 36B, the edge of the lens-type filter 149 is covered with the light-shielding layer 148.

[0425] In the configuration shown in FIG. 36B, light 25 enters the light receiving element 110 via a lens-shaped filter 149. By making the filter 149 lens-shaped, the imaging range of the light receiving element 110 can be narrowed, and overlapping of the imaging ranges of adjacent light receiving elements 110 can be prevented. This makes it possible to capture a clear image with less blur. Furthermore, by making the filter 149 lens-shaped, it is possible to enlarge the opening of the light-shielding layer 148 above the light receiving element 110. Therefore, the amount of light incident on the light receiving element 110 can be increased, and the light detection sensitivity can be improved.

[0426] The lens-type filter 149 can be formed directly on the substrate 152 or on the light-receiving element 110. Alternatively, a separately manufactured microlens array or the like may be attached to the substrate 152.

[0427] 36C, a configuration may be adopted in which filter 149 is not provided. If light receiving element 110 has characteristics such as no sensitivity to ultraviolet light or sensitivity to visible light and infrared light is sufficiently higher than sensitivity to ultraviolet light, filter 149 can be omitted. In this case, a lens having a shape similar to lens-type filter 149 shown in FIG. 36B may be provided overlapping light receiving element 110.

[0428] Here, the light receiving element 110 can detect light 25 that is reflected by a detection object such as a finger, out of light 23 emitted by the light emitting element 190. However, there are cases where part of the light emitted by the light emitting element 190 is reflected within the semiconductor device 10 and enters the light receiving element 110 without passing through the detection object.

[0429] The light-shielding layer 148 can suppress the influence of such stray light. For example, if the light-shielding layer 148 is not provided, the light 24a emitted from the light-emitting element 190 shown in FIG. 35 may be reflected by the substrate 152 or the like, and the reflected light 24b may enter the light-receiving element 110. By providing the light-shielding layer 148, it is possible to prevent the reflected light 24b from entering the light-receiving element 110. This reduces noise and improves the light detection accuracy of the light-receiving element 110.

[0430] In the light-emitting element 190, the common layer 112, the light-emitting layer 193, and the common layer 114 located between the pixel electrode 191 and the common electrode 115 can also be called an EL layer. The pixel electrode 191 preferably has a function of reflecting at least infrared light.

[0431] The light-emitting element 190 has a function of emitting infrared light. Specifically, the light-emitting element 190 is an electroluminescent element that emits light 23 toward the substrate 152 by applying a voltage between the pixel electrode 191 and the common electrode 115.

[0432] The pixel electrode 111 is electrically connected to the source or drain of the transistor 141 through an opening provided in the insulating layer 214. An end of the pixel electrode 111 is covered with a partition wall 216.

[0433] The pixel electrode 191 is electrically connected to the source or drain of the transistor 142 through an opening provided in the insulating layer 214. An end of the pixel electrode 191 is covered with a partition wall 216.

[0434] The transistor 141 and the transistor 142 are adjacent to each other on the same layer (substrate 151 in FIG. 35).

[0435] At least a part of the circuit electrically connected to the light receiving element 110 is preferably formed using the same material and in the same process as the circuit electrically connected to the light emitting element 190. This allows the display device to be thinner and the manufacturing process to be simplified compared to when the two circuits are formed separately.

[0436] The light receiving element 110 and the light emitting element 190 are preferably covered with a protective layer 195. Fig. 35 shows an example in which the protective layer 195 is provided on and in contact with the common electrode 115. By providing the protective layer 195, impurities such as water are prevented from entering the light receiving element 110 and the light emitting element 190, and the reliability of the light receiving element 110 and the light emitting element 190 can be improved. In addition, the protective layer 195 and the substrate 152 are bonded together by an adhesive layer 242.

[0437] 37A, the protective layer 195 may not be provided on the light receiving element 110 and the light emitting element 190. In this case, the common electrode 115 and the substrate 152 are bonded together by the adhesive layer 242.

[0438] 37B, a configuration may be adopted in which the light-shielding layer 148 is not provided. This increases the amount of light emitted to the outside by the light-emitting element 190 and the amount of light received by the light-receiving element 110, thereby improving the detection sensitivity.

[0439] Fig. 38 shows a perspective view of the semiconductor device 10. The semiconductor device 10 has a configuration in which a substrate 151 and a substrate 152 are bonded together. In Fig. 38, the substrate 152 is indicated by a dashed line.

[0440] The semiconductor device 10 has a display unit 162, a circuit 164a, a circuit 164b, wiring 165a, wiring 165b, etc. Also, Fig. 38 shows an example in which an IC (integrated circuit) 173a, an FPC 172a, an IC 173b, and an FPC 172b are mounted on the semiconductor device 10. Therefore, the configuration shown in Fig. 38 can also be said to be a display module having the semiconductor device 10, an IC, and an FPC.

[0441] The circuit 164a may be a gate driver circuit for displaying, and the circuit 164b may be a row driver circuit for imaging (photodetection).

[0442] For example, signals and power can be supplied to the circuit 164a via wiring 165a. The signals and power can be input to the wiring 165a from outside the semiconductor device 10 via an FPC 172a. Alternatively, the signals and power can be generated by an IC 173a and output to the wiring 165a. Furthermore, signals and power can be supplied to the circuit 164b via wiring 165b.

[0443] 38 shows an example in which ICs 173a and 173b are provided on substrate 151 using a COG (Chip On Glass) method, but a TCP (Tape Carrier Package) method, a COF (Chip On Film) method, or the like may also be used. IC 173a may be, for example, an IC having the function of a data driver circuit electrically connected to the above-mentioned pixels 81 and 82. Furthermore, IC 173b may be, for example, an IC having the function of a signal processing circuit of a readout circuit electrically connected to the above-mentioned pixel 31.

[0444] The driver circuit may be provided on the substrate 151 in the same manner as the transistors that form the pixel circuits.

[0445] Figure 39 is a diagram showing an example of a cross section of a portion of the region including the FPC 172a, a portion of the region including the circuit 164a, a portion of the region including the display unit 162, and a portion of the region including the end portion in the semiconductor device 10 shown in Figure 38.

[0446] The semiconductor device 10 shown in FIG. 39 includes a transistor 201, a transistor 141, a transistor 142, a light-emitting element 190, a light-receiving element 110, and the like between a substrate 151 and a substrate 152.

[0447] The substrate 152 and the insulating layer 214 are bonded via an adhesive layer 242. A solid sealing structure, a hollow sealing structure, or the like can be applied to seal the light emitting element 190 and the light receiving element 110. A space 143 surrounded by the substrate 152, the adhesive layer 242, and the insulating layer 214 is filled with an inert gas (nitrogen, argon, or the like), and a hollow sealing structure is applied. The adhesive layer 242 may be provided so as to overlap the light receiving element 110 and the light emitting element 190. Furthermore, the area surrounded by the substrate 152, the adhesive layer 242, and the insulating layer 214 may be filled with a resin different from the adhesive layer 242.

[0448] The transistor 201, the transistor 141, and the transistor 142 are all formed over a substrate 151. These transistors can be manufactured using the same material and through the same process.

[0449] An insulating layer 211, an insulating layer 213, an insulating layer 215, and an insulating layer 214 are provided over the substrate 151 in this order. A part of the insulating layer 211 functions as a gate insulating layer for each transistor. A part of the insulating layer 213 functions as a gate insulating layer for each transistor. The insulating layer 215 is provided to cover the transistor. The insulating layer 214 is provided to cover the transistor and functions as a planarization layer. Note that the number of gate insulating layers and the number of insulating layers covering the transistors are not limited, and each may be a single layer or two or more layers.

[0450] At least one insulating layer covering the transistor is preferably made of a material that is resistant to the diffusion of impurities such as water or hydrogen. This allows the insulating layer to function as a barrier layer. With this structure, it is possible to effectively prevent impurities from diffusing into the transistor from the outside, thereby improving the reliability of the display device.

[0451] The insulating layer 211, the insulating layer 213, and the insulating layer 215 are preferably formed using an inorganic insulating film. Examples of the inorganic insulating film that can be used include a silicon nitride film, a silicon oxynitride film, a silicon oxide film, a silicon nitride oxide film, an aluminum oxide film, and an aluminum nitride film. Alternatively, a hafnium oxide film, an yttrium oxide film, a zirconium oxide film, a gallium oxide film, a tantalum oxide film, a magnesium oxide film, a lanthanum oxide film, a cerium oxide film, and a neodymium oxide film may be used. Two or more of the above insulating films may be stacked.

[0452] In this specification and the like, a silicon oxynitride film refers to a film whose composition contains more oxygen than nitrogen, and a silicon nitride oxide film refers to a film whose composition contains more nitrogen than oxygen.

[0453] An organic insulating film is preferably used for the insulating layer 214, which functions as a planarizing layer. Materials that can be used for the organic insulating film include acrylic resin, polyimide resin, epoxy resin, polyamide resin, polyimideamide resin, siloxane resin, benzocyclobutene resin, phenol resin, and precursors of these resins.

[0454] Here, organic insulating films often have a lower barrier property against impurities than inorganic insulating films. Therefore, it is preferable that the organic insulating film has an opening near the edge of the semiconductor device 10. This makes it possible to suppress the diffusion of impurities from the edge of the semiconductor device 10 through the organic insulating film. Alternatively, the organic insulating film may be formed so that the edge of the organic insulating film is located inside the edge of the semiconductor device 10, so that the organic insulating film is not exposed at the edge of the semiconductor device 10.

[0455] 39, an opening is formed in the insulating layer 214. This makes it possible to prevent impurities from diffusing from the outside into the display unit 162 through the insulating layer 214, even when an organic insulating film is used for the insulating layer 214. This makes it possible to improve the reliability of the semiconductor device 10.

[0456] The transistor 201, the transistor 141, and the transistor 142 each include a conductive layer 221 that functions as a gate, an insulating layer 211 that functions as a gate insulating layer, conductive layers 222a and 222b that function as a source and a drain, a semiconductor layer 231, an insulating layer 213 that functions as a gate insulating layer, and a conductive layer 223 that functions as a gate. Here, the same hatching pattern is applied to multiple layers obtained by processing the same conductive film. The insulating layer 211 is located between the conductive layer 221 and the semiconductor layer 231. The insulating layer 213 is located between the conductive layer 223 and the semiconductor layer 231.

[0457] The structure of the transistor included in the display device of this embodiment is not particularly limited. For example, a planar transistor, a staggered transistor, an inverted staggered transistor, or the like can be used. Furthermore, either a top-gate transistor or a bottom-gate transistor structure may be used. Alternatively, gates may be provided above and below a semiconductor layer in which a channel is formed.

[0458] The transistor 201, the transistor 141, and the transistor 142 each have a structure in which a semiconductor layer in which a channel is formed is sandwiched between two gates. The two gates may be connected and supplied with the same signal to drive the transistor. Alternatively, a potential for controlling the threshold voltage of the transistor may be applied to one of the two gates, and a potential for driving the transistor may be applied to the other gate.

[0459] The crystallinity of a semiconductor material used for a transistor is not particularly limited, and any of an amorphous semiconductor, a single-crystal semiconductor, and a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part) may be used. The use of a single-crystal semiconductor or a crystalline semiconductor is preferable because it can suppress deterioration of transistor characteristics.

[0460] The semiconductor layer of the transistor preferably contains a metal oxide (also referred to as an oxide semiconductor). Alternatively, the semiconductor layer of the transistor may contain silicon. Examples of silicon include amorphous silicon, crystalline silicon (low-temperature polysilicon, single-crystal silicon, or the like), and the like.

[0461] When the semiconductor layer contains a metal oxide, the metal oxide preferably contains at least indium or zinc, as described above. It is particularly preferable that the metal oxide contains indium and zinc. Furthermore, it is preferable that the metal oxide further contains aluminum, gallium, yttrium, tin, or the like. Furthermore, the metal oxide may contain one or more elements selected from boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, or the like.

[0462] The transistors included in the circuit 164a and the transistors included in the display portion 162 may have the same structure or different structures. The transistors included in the circuit 164a may all have the same structure or may have two or more types. Similarly, the transistors included in the display portion 162 may all have the same structure or may have two or more types.

[0463] A connection portion 204 is provided in an area on the substrate 151 where the substrate 152 does not overlap. In the connection portion 204, the wiring 165 is electrically connected to the FPC 172a via the conductive layer 166 and the connection layer 244. The conductive layer 166, which is obtained by processing the same conductive film as the pixel electrode 191, is exposed on the upper surface of the connection portion 204. This allows the connection portion 204 and the FPC 172a to be electrically connected via the connection layer 244.

[0464] Various optical members can be disposed on the outside of the substrate 152. Examples of optical members include a polarizing plate, a retardation plate, a light diffusion layer (e.g., a diffusion film), an anti-reflection layer, and a light collecting film. In addition, an antistatic film that suppresses the adhesion of dust, a water-repellent film that makes it difficult for dirt to adhere, a hard coat film that suppresses the occurrence of scratches during use, or an impact absorbing layer may be disposed on the outside of the substrate 152.

[0465] The substrate 151 and the substrate 152 may be made of glass, quartz, ceramic, sapphire, resin, or the like.

[0466] The adhesive layer can be made of various curable adhesives, such as photo-curable adhesives (e.g., ultraviolet curable), reactive curable adhesives, thermosetting adhesives, or anaerobic adhesives. Examples of such adhesives include epoxy resin, acrylic resin, silicone resin, phenolic resin, polyimide resin, imide resin, PVC (polyvinyl chloride) resin, PVB (polyvinyl butyral) resin, and EVA (ethylene vinyl acetate) resin. Materials with low moisture permeability, such as epoxy resin, are particularly preferred. Two-component resins may also be used. An adhesive sheet may also be used.

[0467] The connection layer 244 may be an anisotropic conductive film (ACF), an anisotropic conductive paste (ACP), or the like.

[0468] The light-emitting element 190 can be a top-emission type, a bottom-emission type, a dual-emission type, or the like. In one embodiment of the present invention, a top-emission type is preferable, but other configurations can also be applied by arranging the light-emitting surface of the light-emitting element 190 and the light-receiving surface of the light-receiving element 110 in the same direction.

[0469] The light-emitting element 190 has at least a light-emitting layer 193. The light-emitting element 190 may further have, in addition to the light-emitting layer 193, a layer containing a substance with a high hole-injection property, a substance with a high hole-transport property, a hole-blocking material, a substance with a high electron-transport property, a substance with a high electron-injection property, or a bipolar substance (a substance with high electron-transport property and high hole-transport property). For example, the common layer 112 preferably has one or both of a hole-injection layer and a hole-transport layer. For example, the common layer 114 preferably has one or both of an electron-transport layer and an electron-injection layer.

[0470] Both low molecular weight compounds and high molecular weight compounds may be used, and may contain inorganic compounds, for the common layer 112, the light emitting layer 193, and the common layer 114. The common layer 112, the light emitting layer 193, and the common layer 114 may be formed by a method such as a vapor deposition method (including a vacuum vapor deposition method), a transfer method, a printing method, an inkjet method, or a coating method.

[0471] The light-emitting layer 193 may contain an inorganic compound such as quantum dots as a light-emitting material.

[0472] The photoelectric conversion layer 113 of the light-receiving element 110 includes a semiconductor. As the semiconductor, an inorganic semiconductor such as silicon or an organic semiconductor including an organic compound can be used. In this embodiment, an example in which an organic semiconductor is used as the semiconductor included in the photoelectric conversion layer 113 is shown. By using an organic semiconductor, the light-emitting layer 193 of the light-emitting element 190 and the photoelectric conversion layer 113 of the light-receiving element 110 can be formed by the same method (for example, vacuum evaporation), which is preferable because a common manufacturing apparatus can be used.

[0473] The n-type semiconductor material of the photoelectric conversion layer 113 is fullerene (e.g., C 60 , or C 70 Examples of the p-type semiconductor material of the photoelectric conversion layer 113 include electron-accepting organic semiconductor materials such as copper(II) phthalocyanine (CuPc), tetraphenyldibenzoperiflanthene (DBP), and zinc phthalocyanine (ZnPc).

[0474] For example, the photoelectric conversion layer 113 can be formed by co-evaporating an n-type semiconductor and a p-type semiconductor.

[0475] Materials that can be used for the gate, source, and drain of a transistor as well as conductive layers such as various wirings and electrodes that constitute a display device include metals such as aluminum, titanium, chromium, nickel, copper, yttrium, zirconium, molybdenum, silver, tantalum, and tungsten, and alloys containing these metals as main components, etc. Films containing these materials can be used as a single-layer structure or a stacked-layer structure.

[0476] Examples of light-transmitting conductive materials include conductive oxides such as indium oxide, indium tin oxide, indium zinc oxide, zinc oxide, and zinc oxide containing gallium. Alternatively, graphene can be used. Metal materials such as gold, silver, platinum, magnesium, nickel, tungsten, chromium, molybdenum, iron, cobalt, copper, palladium, and titanium, as well as alloy materials containing these metal materials, can be used. Alternatively, nitrides of these metal materials (e.g., titanium nitride) can be used. When using metal materials or alloy materials (or their nitrides), it is preferable to thin them thin enough to have light-transmitting properties. A stacked film of the above materials can also be used as the conductive layer. For example, a stacked film of an alloy of silver and magnesium and indium tin oxide is preferable because it can increase conductivity. These can also be used for conductive layers such as various wirings or electrodes constituting a display device, and for conductive layers (conductive layers functioning as pixel electrodes or common electrodes) in display elements.

[0477] Examples of insulating materials that can be used for each insulating layer include resins such as acrylic resins or epoxy resins, and inorganic insulating materials such as silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, or aluminum oxide.

[0478] The structures shown in this embodiment mode can be combined as appropriate. For example, structures shown in different drawings can be combined as appropriate.

[0479] This embodiment mode can be appropriately combined with other embodiment modes or examples shown in this specification and the like.

[0480] (Embodiment 2) In this embodiment, a metal oxide (hereinafter also referred to as an oxide semiconductor) that can be used for the OS transistor described in the above embodiment will be described.

[0481] The metal oxide preferably contains at least indium or zinc. It is particularly preferable that it contains indium and zinc. In addition to these, it is preferable that it contains aluminum, gallium, yttrium, tin, or the like. It may also contain one or more elements selected from boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, or the like.

[0482] <Classification of crystal structures> First, classification of crystal structures in oxide semiconductors will be described with reference to Fig. 40A, which is a diagram for explaining classification of crystal structures of oxide semiconductors, typically IGZO (a metal oxide containing In, Ga, and Zn).

[0483] As shown in FIG. 40A, oxide semiconductors are broadly classified into "Amorphous," "Crystalline," and "Crystal." Also, "Amorphous" includes completely amorphous. Also, "Crystalline" includes c-axis-aligned crystalline (CAAC), nanocrystalline (nc), and CAC. The "Crystalline" classification excludes single crystal, polycrystal, and completely amorphous (excluding single crystal and polycrystal). Also, "Crystal" includes single crystal and polycrystal.

[0484] The structure within the bold frame shown in Figure 40A is an intermediate state between "Amorphous" and "Crystal" and belongs to a new boundary region (New crystalline phase). In other words, this structure can be said to be completely different from the energetically unstable "Amorphous" and "Crystal."

[0485] The crystalline structure of a film or substrate can be evaluated using X-ray diffraction (XRD) spectroscopy. Figures 40B and 40C show XRD spectra obtained by GIXD (Grazing-Incidence XRD) measurement of a quartz glass substrate and an IGZO (also called crystalline IGZO) film with a crystal structure classified as "Crystalline," respectively. The GIXD method is also known as the thin-film method or the Seemann-Bohlin method. Hereinafter, the XRD spectra obtained by GIXD measurement shown in Figures 40B and 40C will be simply referred to as XRD spectra. In Figures 40B and 40C, the vertical axis represents X-ray intensity, and the horizontal axis represents the diffraction angle (2θ) of the X-rays. Figure 40B shows the XRD spectrum of a quartz glass substrate, and Figure 40C shows the XRD spectrum of a crystalline IGZO film. The composition of the crystalline IGZO film shown in Fig. 40C is approximately In:Ga:Zn = 4:2:3 [atomic ratio], and the thickness of the crystalline IGZO film shown in Fig. 40C is 500 nm.

[0486] As shown by the arrows in Figure 40B, the peak shape of the XRD spectrum for the quartz glass substrate is nearly symmetrical. On the other hand, as shown by the arrows in Figure 40C, the peak shape of the XRD spectrum for the crystalline IGZO film is asymmetrical. The asymmetrical peak shape of the XRD spectrum clearly indicates the presence of crystals in the film or substrate. In other words, if the peak shape of the XRD spectrum is not symmetrical, the film or substrate cannot be said to be in an amorphous state. Note that Figure 40C clearly shows the crystalline phase (IGZO crystal phase) at or near 2θ = 31°. It is presumed that the asymmetrical peak shape in the XRD spectrum is due to the diffraction peak of the crystalline phase (microcrystals).

[0487] Specifically, it is believed that interference from X-rays scattered by atoms contained in IGZO contributes to the peak at or near 2θ=34°. It is also believed that minute crystals contribute to the peak at or near 2θ=31°. In the XRD spectrum of the crystalline IGZO film shown in Figure 40C, the peak width on the low-angle side of the peak at or near 2θ=34° is broad. This suggests that minute crystals resulting from the peak at or near 2θ=31° are present within the crystalline IGZO film.

[0488] The crystalline structure of a film or substrate can be evaluated by a diffraction pattern (also called a nanobeam electron diffraction pattern) observed using nanobeam electron diffraction (NBED). The diffraction patterns of a quartz glass substrate and an IGZO film deposited at room temperature are shown in Figures 40D and 40E, respectively. Figure 40D shows the diffraction pattern of the quartz glass substrate, and Figure 40E shows the diffraction pattern of the IGZO film. The IGZO film shown in Figure 40E was deposited by sputtering using an oxide target with an In:Ga:Zn=1:1:1 [atomic ratio]. In nanobeam electron diffraction, electron diffraction is performed using a probe diameter of 1 nm.

[0489] As shown in Figure 40D, a halo is observed in the diffraction pattern of the silica glass substrate, confirming that the silica glass is in an amorphous state. Furthermore, as shown in Figure 40E, a spot-like pattern is observed in the diffraction pattern of the IGZO film deposited at room temperature, rather than a halo. Therefore, it is presumed that the IGZO film deposited at room temperature is in an intermediate state, neither crystalline nor amorphous, and therefore cannot be concluded to be in an amorphous state.

[0490] <<Oxide semiconductor structure>> Note that oxide semiconductors may be classified differently from those shown in FIG. 40A when focusing on their crystal structures. For example, oxide semiconductors are divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include the above-mentioned CAAC-OS and nc-OS. Non-single-crystal oxide semiconductors include polycrystalline oxide semiconductors, amorphous-like oxide semiconductors (a-like OSs), and amorphous oxide semiconductors.

[0491] Here, the above-mentioned CAAC-OS, nc-OS, and a-like OS will be described in detail.

[0492] [CAAC-OS] CAAC-OS is an oxide semiconductor having multiple crystalline regions, each with its c-axis aligned in a specific direction. The specific direction can be the thickness direction of the CAAC-OS film, the normal direction to the surface on which the CAAC-OS film is formed, or the normal direction to the surface of the CAAC-OS film. A crystalline region is a region with periodic atomic arrangement. Considering an atomic arrangement as a lattice arrangement, a crystalline region can also be a region with a uniform lattice arrangement. Furthermore, CAAC-OS has a region where multiple crystalline regions are connected in the ab-plane direction, and the region may have distortion. The distortion refers to a location where the lattice orientation changes between a region with a uniform lattice arrangement and a region with a different uniform lattice arrangement in the region where multiple crystalline regions are connected. In other words, CAAC-OS is an oxide semiconductor with a c-axis aligned but no clear orientation in the ab-plane direction.

[0493] Each of the multiple crystalline regions is composed of one or more minute crystals (crystals with a maximum diameter of less than 10 nm). When a crystalline region is composed of one minute crystal, the maximum diameter of the crystalline region is less than 10 nm. When a crystalline region is composed of many minute crystals, the size of the crystalline region may be several tens of nm.

[0494] In addition, in an In-M-Zn oxide (wherein element M is one or more elements selected from aluminum, gallium, yttrium, tin, titanium, etc.), the CAAC-OS tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium (In) and oxygen (hereinafter referred to as an In layer) and a layer containing element M, zinc (Zn), and oxygen (hereinafter referred to as an (M, Zn) layer) are stacked. Note that indium and element M are mutually substituted. Therefore, the (M, Zn) layer may contain indium. Furthermore, the In layer may contain element M. Furthermore, the In layer may contain Zn. The layered structure is observed as a lattice image in a high-resolution TEM image, for example.

[0495] When the CAAC-OS film is subjected to structural analysis using, for example, an XRD apparatus, a peak indicating c-axis orientation is detected at or near 2θ=31° in out-of-plane XRD measurement using θ / 2θ scan. Note that the position of the peak indicating c-axis orientation (2θ value) may vary depending on the type or composition of the metal elements constituting the CAAC-OS.

[0496] Furthermore, for example, in the electron diffraction pattern of the CAAC-OS film, multiple bright spots are observed, and the spots are observed at positions that are point-symmetric with respect to the spot of the incident electron beam that has passed through the sample (also called the direct spot).

[0497] When the crystalline region is observed from the specific direction, the lattice arrangement in the crystalline region is basically a hexagonal lattice, but the unit cell is not necessarily a regular hexagon and may be non-regular hexagonal. The distortion may also have a pentagonal or heptagonal lattice arrangement. In the CAAC-OS, no clear grain boundaries can be identified even near the distortion. This indicates that the formation of grain boundaries is suppressed by the distortion of the lattice arrangement. This is thought to be because the CAAC-OS can tolerate distortion due to the lack of close-packed arrangement of oxygen atoms in the ab-plane direction or the change in interatomic bond distance caused by metal atom substitution.

[0498] A crystal structure with clear grain boundaries is called polycrystalline. Grain boundaries act as recombination centers, trapping carriers and potentially reducing the on-state current or field-effect mobility of a transistor. Therefore, CAAC-OS, which lacks clear grain boundaries, is one of the crystalline oxides with a crystal structure suitable for use in a transistor semiconductor layer. Zn is preferred for use in CAAC-OS. For example, In-Zn oxide and In-Ga-Zn oxide are suitable because they can suppress the generation of grain boundaries more effectively than In oxide.

[0499] The CAAC-OS is an oxide semiconductor with high crystallinity and no clear grain boundaries. Therefore, it can be said that the CAAC-OS is less susceptible to a decrease in electron mobility due to grain boundaries. Furthermore, since the crystallinity of an oxide semiconductor can be reduced by the inclusion of impurities or the generation of defects, the CAAC-OS can also be said to be an oxide semiconductor with few impurities and defects (e.g., oxygen vacancies). Therefore, oxide semiconductors with CAAC-OS have stable physical properties. Therefore, oxide semiconductors with CAAC-OS are heat-resistant and highly reliable. Furthermore, the CAAC-OS is stable even under high temperatures (so-called thermal budgets) during the manufacturing process. Therefore, using a CAAC-OS for an OS transistor enables greater flexibility in the manufacturing process.

[0500] [nc-OS] The nc-OS has periodic atomic arrangement in a microscopic region (e.g., a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In other words, the nc-OS has microcrystalline structures. The size of the microcrystalline structures is, for example, 1 nm to 10 nm, particularly 1 nm to 3 nm, and therefore these microcrystalline structures are also called nanocrystalline structures. Furthermore, the nc-OS exhibits no regularity in the crystal orientation between different nanocrystalline structures. Therefore, the entire film lacks orientation. Therefore, depending on the analytical method, the nc-OS may be indistinguishable from an a-like OS or an amorphous oxide semiconductor. For example, when a structural analysis of an nc-OS film is performed using an XRD apparatus, no peaks indicating crystallinity are detected in out-of-plane XRD measurements using θ / 2θ scanning. Furthermore, when an nc-OS film is subjected to electron diffraction (also known as selected-area electron diffraction) using an electron beam with a probe diameter larger than that of nanocrystalline structures (e.g., 50 nm or larger), a halo-like diffraction pattern is observed. On the other hand, when electron diffraction (also called nanobeam electron diffraction) is performed on an nc-OS film using an electron beam with a probe diameter close to or smaller than the size of the nanocrystals (for example, 1 nm to 30 nm), an electron diffraction pattern can be obtained in which multiple spots are observed within a ring-shaped region centered on the direct spot.

[0501] [a-like OS] The a-like OS is an oxide semiconductor having a structure between the nc-OS and the amorphous oxide semiconductor. The a-like OS has a pore or low-density region. That is, the a-like OS has lower crystallinity than the nc-OS and CAAC-OS. Furthermore, the a-like OS has a higher hydrogen concentration in the film than the nc-OS and CAAC-OS.

[0502] <<Oxide semiconductor structure>> Next, the above-mentioned CAC-OS will be described in detail, which relates to the material composition.

[0503] [CAC-OS] CAC-OS is a material structure in which elements constituting a metal oxide are unevenly distributed in a size range of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or in the vicinity thereof. Note that, hereinafter, a metal oxide in which one or more metal elements are unevenly distributed and the regions containing the metal elements are mixed in a size range of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or in the vicinity thereof, is also referred to as a mosaic or patch state.

[0504] Furthermore, CAC-OS has a mosaic structure in which the material is separated into first and second regions, and the first regions are distributed throughout the film (hereinafter also referred to as a cloud structure). That is, CAC-OS is a composite metal oxide having a structure in which the first and second regions are mixed.

[0505] Here, the atomic ratios of In, Ga, and Zn to the metal elements constituting the CAC-OS in the In-Ga-Zn oxide are denoted as [In], [Ga], and [Zn], respectively. For example, in the CAC-OS in the In-Ga-Zn oxide, the first region is a region where [In] is larger than [In] in the composition of the CAC-OS film. The second region is a region where [Ga] is larger than [Ga] in the composition of the CAC-OS film. Alternatively, for example, the first region is a region where [In] is larger than [In] in the second region and [Ga] is smaller than [Ga] in the second region. The second region is a region where [Ga] is larger than [Ga] in the first region and [In] is smaller than [In] in the first region.

[0506] Specifically, the first region is a region whose main component is indium oxide, indium zinc oxide, or the like. The second region is a region whose main component is gallium oxide, gallium zinc oxide, or the like. In other words, the first region can be rephrased as a region whose main component is In. The second region can be rephrased as a region whose main component is Ga.

[0507] It should be noted that there are cases where a clear boundary between the first region and the second region cannot be observed.

[0508] In addition, CAC-OS in In-Ga-Zn oxide refers to a material structure containing In, Ga, Zn, and O, in which some regions primarily composed of Ga and other regions primarily composed of In are randomly arranged in a mosaic pattern. Therefore, it is presumed that CAC-OS has a structure in which metal elements are distributed nonuniformly.

[0509] The CAC-OS can be formed, for example, by a sputtering method under conditions where the substrate is not intentionally heated. When the CAC-OS is formed by a sputtering method, one or more of an inert gas (typically argon), oxygen gas, and nitrogen gas may be used as the deposition gas. The lower the flow rate ratio of oxygen gas to the total flow rate of deposition gas during deposition, the better. For example, the flow rate ratio of oxygen gas to the total flow rate of deposition gas during deposition is preferably 0% or more and less than 30%, and more preferably 0% or more and 10% or less.

[0510] Furthermore, for example, in the case of CAC-OS in an In-Ga-Zn oxide, EDX mapping obtained using EDX (Energy Dispersive X-ray spectroscopy) confirms that the CAC-OS has a structure in which a region containing In as the main component (first region) and a region containing Ga as the main component (second region) are unevenly distributed and mixed.

[0511] Here, the first region has higher conductivity than the second region. That is, the flow of carriers through the first region causes the metal oxide to exhibit conductivity. Therefore, the first region is distributed in a cloud-like manner in the metal oxide, thereby achieving a high field-effect mobility (μ).

[0512] On the other hand, the second region has higher insulating properties than the first region. That is, the second region is distributed in the metal oxide, thereby suppressing leakage current.

[0513] Therefore, when CAC-OS is used in a transistor, the conductivity due to the first region and the insulating property due to the second region act complementarily, thereby providing the CAC-OS with a switching function (the ability to turn on and off). In other words, CAC-OS has a conductive function in part of the material and an insulating function in part of the material, and the material as a whole functions as a semiconductor. By separating the conductive function from the insulating function, both functions can be maximized. Therefore, by using CAC-OS in a transistor, a high on-current (I on ), high field-effect mobility (μ), and good switching behavior can be achieved.

[0514] Furthermore, transistors using CAC-OS have high reliability, making them ideal for various semiconductor devices such as displays.

[0515] Oxide semiconductors have a variety of structures, each with different characteristics. The oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, a CAC-OS, an nc-OS, and a CAAC-OS.

[0516] <Transistors containing oxide semiconductors> Next, a case where the oxide semiconductor is used in a transistor will be described.

[0517] By using the oxide semiconductor for a transistor, a transistor with high field-effect mobility and high reliability can be realized.

[0518] For the transistor, an oxide semiconductor with a low carrier concentration is preferably used. For example, the carrier concentration of the oxide semiconductor is 1×10 17 cm -3 Less than 1 × 10 15 cm -3 or less, more preferably 1 × 10 13 cm -3 Less than or equal to 1×10 11 cm -3 or less, more preferably 1 × 10 10 cm -3 Less than 1 x 10 -9 cm -3 The above is the case. Note that in order to reduce the carrier concentration of an oxide semiconductor film, the impurity concentration in the oxide semiconductor film may be reduced to reduce the density of defect states. In this specification and the like, a semiconductor having a low impurity concentration and a low density of defect states is referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor. Note that an oxide semiconductor having a low carrier concentration may also be referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor.

[0519] Furthermore, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a low density of defect states, and therefore the density of trap states may also be low.

[0520] Furthermore, charges trapped in the trap states of an oxide semiconductor take a long time to disappear and may behave like fixed charges. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high density of trap states may have unstable electrical characteristics.

[0521] Therefore, in order to stabilize the electrical characteristics of a transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. Furthermore, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in a nearby film. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon.

[0522] <Impurities> Here, the influence of each impurity in an oxide semiconductor will be described.

[0523] When an oxide semiconductor contains silicon or carbon, which is one of the Group 14 elements, defect levels are formed in the oxide semiconductor. Therefore, the concentration of silicon or carbon in the oxide semiconductor and the concentration of silicon or carbon near the interface with the oxide semiconductor (concentration obtained by secondary ion mass spectrometry (SIMS)) are calculated to be 2×10 18 atoms / cm 3 Less than or equal to 2 x 10 17 atoms / cm 3 The following applies.

[0524] Furthermore, when an oxide semiconductor contains an alkali metal or alkaline earth metal, defect levels may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or alkaline earth metal is likely to have normally-on characteristics. For this reason, when the concentration of the alkali metal or alkaline earth metal in the oxide semiconductor obtained by SIMS is 1×10 18 atoms / cm 3 Less than or equal to 2 x 10 16 atoms / cm 3 Do the following:

[0525] Furthermore, when nitrogen is contained in an oxide semiconductor, electrons serving as carriers are generated, the carrier concentration increases, and the semiconductor is likely to become n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor tends to have normally-on characteristics. Alternatively, when nitrogen is contained in an oxide semiconductor, trap states may be formed. As a result, the electrical characteristics of the transistor may become unstable. For this reason, the nitrogen concentration in the oxide semiconductor obtained by SIMS is set to 5×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 Less than or equal to 1×10 18 atoms / cm 3 Less than 5 × 10, more preferably 17 atoms / cm 3 Do the following:

[0526] Furthermore, hydrogen contained in an oxide semiconductor may react with oxygen bonded to a metal atom to form water, which may form an oxygen vacancy. When hydrogen enters the oxygen vacancy, electrons serving as carriers may be generated. Furthermore, some of the hydrogen may bond with oxygen bonded to a metal atom to generate electrons serving as carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen is likely to have normally-on characteristics. For this reason, it is preferable to reduce the amount of hydrogen in the oxide semiconductor as much as possible. Specifically, the hydrogen concentration in an oxide semiconductor measured by SIMS is 1×10 20 atoms / cm 3 Less than 1 x 10 19 atoms / cm 3 less than 5 × 10 18 atoms / cm 3 less than 1×10 18 atoms / cm 3 Make it less than.

[0527] When an oxide semiconductor with sufficiently reduced impurities is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0528] This embodiment mode can be combined as appropriate with other embodiment modes or examples shown in this specification and the like.

[0529] (Embodiment 3) In this embodiment, an electronic device including a semiconductor device according to one embodiment of the present invention will be described.

[0530] The semiconductor device of one embodiment of the present invention can be provided in various electronic devices. For example, the semiconductor device of one embodiment of the present invention can be provided in electronic devices with relatively large screens, such as television devices, desktop or notebook computers, tablet computers, computer monitors, digital signage, and pachinko machines, as well as digital cameras, digital video cameras, digital photo frames, portable game consoles, personal digital assistants, and sound players. Configuration examples of electronic devices that can include the semiconductor device of one embodiment of the present invention are described with reference to FIGS. 41A to 41D .

[0531] 41A is a diagram showing an example of a mobile information terminal 9100. The mobile information terminal 9100 includes a display unit 9110, a housing 9101, keys 9102, a speaker 9103, and the like. The mobile information terminal 9100 may be, for example, a tablet. Here, keys such as the key 9102 may be keys for turning a power source on and off, for example. That is, the keys such as the key 9102 may be, for example, a power switch. Furthermore, the keys such as the key 9102 may be, for example, operation keys used to cause an electronic device to perform a desired operation.

[0532] The display unit 9110 can display information 9104, operation buttons (also referred to as operation icons or simply icons) 9105, and the like.

[0533] By providing the semiconductor device of one embodiment of the present invention in the portable information terminal 9100, the portable information terminal 9100 can perform authentication such as fingerprint authentication in a short time with high accuracy.

[0534] 41B is a diagram showing an example of a digital signage 9200. The digital signage 9200 can have a configuration in which a display unit 9210 is attached to a pillar 9201.

[0535] By providing the digital signage 9200 with the semiconductor device of one embodiment of the present invention, the digital signage 9200 can perform authentication such as fingerprint authentication with high accuracy in a short time.

[0536] 41C is a diagram illustrating an example of a mobile information terminal 9300. The mobile information terminal 9300 includes a display portion 9310, a housing 9301, a speaker 9302, a camera 9303, keys 9304, a connection terminal 9305, and a connection terminal 9306. The mobile information terminal 9300 may be, for example, a smartphone. The connection terminal 9305 may be, for example, a microUSB, a lightning, or a Type-C. The connection terminal 9306 may be, for example, an earphone jack.

[0537] The display unit 9310 can display, for example, operation buttons 9307. The display unit 9310 can also display information 9308. Examples of the information 9308 include a display notifying of an incoming email, SNS (social networking service), or phone call, the title of the email or SNS, the name of the sender of the email or SNS, the date and time, the remaining battery level, or the strength of the antenna reception.

[0538] By providing the semiconductor device of one embodiment of the present invention in the portable information terminal 9300, the portable information terminal 9300 can perform authentication such as fingerprint authentication in a short time with high accuracy.

[0539] 41D is a diagram showing an example of a wristwatch-type mobile information terminal 9400. The mobile information terminal 9400 includes a display portion 9410, a housing 9401, a wristband 9402, keys 9403, and a connection terminal 9404. Note that the connection terminal 9404 can be, for example, a microUSB, a lightning, or a Type-C, similar to the connection terminal 9305.

[0540] 41D shows an example in which the time is displayed on the display unit 9410 as the information 9406.

[0541] By providing the semiconductor device of one embodiment of the present invention in the portable information terminal 9400, the portable information terminal 9400 can perform authentication such as fingerprint authentication in a short time with high accuracy.

[0542] This embodiment mode can be appropriately combined with other embodiment modes or examples shown in this specification and the like. [Example]

[0543] Example 1 In this example, the results of a simulation performed on a shift register circuit included in a semiconductor device of one embodiment of the present invention will be described.

[0544] In this example, assuming a shift register circuit configured as shown in FIG. 10, the operation shown in FIG. 13 was simulated, followed by the operation shown in FIG. 14. Also, assuming a shift register circuit configured as shown in FIG. 20, the operation shown in FIG. 21 was simulated, followed by the operation shown in FIG. 22. Furthermore, assuming a shift register circuit configured as shown in FIG. 23, the operation shown in FIG. 24 was simulated, followed by the operation shown in FIG. 25. Here, m was set to 8. That is, the shift register circuit assumed in this example had register circuits R[1] to R[8]. Also, p was set to 3, and q was set to 6.

[0545] 42A and 42B are graphs showing the change in potential of each terminal over time when the operation shown in FIG. 13 is simulated and then the operation shown in FIG. 14 is simulated, assuming a shift register circuit having the configuration shown in FIG. 10. Specifically, FIG. 42A shows the potential of terminals SP1, SMP, SP2, and OFFS, which are terminals electrically connected to the input terminal of register circuit R or the input terminal of latch circuit LAT. FIG. 42B shows the potential of terminals ROUT[1] to ROUT[8], which are terminals electrically connected to the output terminals of register circuits R[1] to R[8].

[0546] 43A and 43B are graphs showing the change over time in the potential of each terminal when the operation shown in Fig. 21 is simulated and then the operation shown in Fig. 22 is simulated, assuming a shift register circuit having the configuration shown in Fig. 20. Specifically, Fig. 43A shows the potential of terminal DSL(1), the potential of terminal DSL(2), the potential of terminal DSL(3), the potential of terminal SPI, and the potential of terminal OFFS, which are terminals electrically connected to the demultiplexer circuit DeMUX or the register circuit R. Fig. 43B shows the potential of terminals ROUT[1] to ROUT[8], which are terminals electrically connected to the output terminals of register circuits R[1] to R[8].

[0547] 44A and 44B are graphs showing the change in potential of each terminal over time when the operation shown in FIG. 24 is simulated and then the operation shown in FIG. 25 is simulated, assuming a shift register circuit having the configuration shown in FIG. 23. Specifically, FIG. 44A shows the potential of the terminal CCLK and the terminal CRS, which are terminals electrically connected to the input terminal of the counter circuit CNT. FIG. 44B shows the potential of the terminals OSS[1] to OSS[8], which are terminals electrically connected to the output terminals of the register circuits R[1] to R[8].

[0548] It was confirmed through simulation that signals are output from register circuits R[3] to R[6] after signals are output from register circuits R[1] to R[8], regardless of the configuration of the shift register circuit shown in Fig. 10, Fig. 20, or Fig. 23. Therefore, it was confirmed through simulation that the shift register circuit shown in Fig. 10, the shift register circuit shown in Fig. 20, and the shift register circuit shown in Fig. 23 can all perform the desired operation.

[0549] This embodiment can be combined as appropriate with other embodiment modes or embodiments shown in this specification and the like. [Example]

[0550] Example 1 In this example, the results of a simulation performed on a shift register circuit included in a semiconductor device of one embodiment of the present invention will be described.

[0551] Fig. 45 is a schematic diagram of a shift register circuit used in the simulation in this example. The shift register circuit shown in Fig. 45 corresponds to the shift register circuit shown in Fig. 26 of the first embodiment.

[0552] As shown in FIG. 45, the shift register circuit according to this embodiment includes a register circuit R <1> to register circuit R <36> a register circuit RD, a switch SW1a, a switch SW1b, a switch SW2a, a switch SW2b, and a signal supply circuit SS <1> ~Signal supply circuit SS <36> The configuration has the following.

[0553] Resistor circuit R <1> The terminal SP is electrically connected to the input terminal of the register circuit R <1> to register circuit R <36> The nine register circuits R are connected in series with each other, with a switch SW1a sandwiched between them. <1> , register circuit R <10> , register circuit R <19> , and a register circuit R <28> are connected in series with each other via the switch SW1b. <36> The output terminal of the register circuit RD is electrically connected to the input terminal of the register circuit RD.

[0554] Resistor circuit R <10> The output terminal of the resistor circuit R <9> is electrically connected to the input terminal of the resistor circuit R <1> The resistor circuit R <19> The output terminal of the resistor circuit R <18> is electrically connected to the input terminal of the resistor circuit R <10> The resistor circuit R <28> The output terminal of the resistor circuit R <27> is electrically connected to the input terminal of the resistor circuit R <19> The output terminal of the register circuit RD is electrically connected to the input terminal of the register circuit R via the switch SW2a. <36> is electrically connected to the input terminal of the resistor circuit R <28> It is assumed that the input terminal is electrically connected to the

[0555] Signal supply circuit SS <1> ~Signal supply circuit SS <36> Among these, the input terminals of the odd-numbered signal supply circuits SS are electrically connected to terminals SL_PWC(1) to SL_PWC(4) and terminals RS_PWC(1) to RS_PWC(4), respectively. On the other hand, the input terminals of the even-numbered signal supply circuits SS are electrically connected to terminals SL_PWC(5) to SL_PWC(8) and terminals RS_PWC(5) to RS_PWC(8), respectively.

[0556] The output terminals of the signal supply circuit SS are electrically connected to four terminals SL and four terminals RS. <1> The terminals SL[1:4] and RS[1:4] are electrically connected to the output terminals of the signal supply circuit SS. <36> The output terminals are electrically connected to the terminals SL[141:144] and the terminals RS[141:144], respectively.

[0557] 45, in this example, the switches SW1a and SW2a were set to the off state, and the switches SW1b and SW2b were set to the on state. Then, an operation corresponding to the operation shown in FIG. 31 of the first embodiment was performed in a simulation.

[0558] Figures 46A to 46C are graphs showing the change over time in the potential of a terminal electrically connected to the input terminal of the register circuit R or the input terminal of the signal supply circuit SS. Specifically, Figure 46A is a graph showing the change over time in the potential of terminal SP. Also, Figure 46B is a graph showing the change over time in the potential of terminals SL_PWC(1) to SL_PWC(4) and terminals RS_PWC(1) to RS_PWC(4), and Figure 46C is a graph showing the change over time in the potential of terminals SL_PWC(5) to SL_PWC(8) and terminals RS_PWC(5) to RS_PWC(8).

[0559] In this example, as shown in Figures 46A to 46C, a high potential start pulse signal was first input to terminal SP. Then, a high potential selection signal was input to terminals SL_PWC(1) to SL_PWC(4), a high potential reset signal was input to terminals RS_PWC(1) to RS_PWC(4), and a high potential selection signal was input to terminals SL_PWC(5) to SL_PWC(8), and a high potential reset signal was input to terminals RS_PWC(5) to RS_PWC(8). In this example, the high potential was 6V.

[0560] 47A to 47D are graphs showing the time-dependent changes in the potentials of terminals SL and RS. Specifically, FIG. 47A is a graph showing the time-dependent changes in the potentials of terminals SL[1] to SL[4] and terminals RS[1] to RS[4]. FIG. 47B is a graph showing the time-dependent changes in the potentials of terminals SL

[37] to SL

[40] and terminals RS

[37] to RS

[40] . FIG. 47C is a graph showing the time-dependent changes in the potentials of terminals SL

[73] to SL

[76] and terminals RS

[73] to RS

[76] . FIG. 47D is a graph showing the time-dependent changes in the potentials of terminals SL

[0109] to SL

[0112] and terminals RS

[0109] to RS

[0112] .

[0561] 47A to 47D, it was confirmed by simulation that high-potential selection signals were sequentially output to terminals SL[1] to SL[4], terminals SL

[37] to SL

[40] , terminals SL

[73] to SL

[76] , and terminals SL

[0109] to SL

[0112] . It was also confirmed by simulation that high-potential reset signals were sequentially output to terminals RS[1] to RS[4], terminals RS

[37] to RS

[40] , terminals RS

[73] to RS

[76] , and terminals RS

[0109] to RS

[0112] . Here, among terminals SL[1] to SL

[0144] and terminals RS[1] to RS

[0144] , terminals not shown in any of FIGS. 47A to 47D did not output high-potential signals in the simulation of this embodiment.

[0562] From the above, it was confirmed that the shift register circuit shown in FIG. 45 can perform the desired operation in simulation.

[0563] This embodiment can be combined as appropriate with other embodiment modes or embodiments shown in this specification and the like. [Explanation of symbols]

[0564] 10: semiconductor device, 11: substrate, 12: substrate, 13: light-emitting device, 15: imaging device, 23: light, 24a: light, 24b: reflected light, 25: light, 27: finger, 29: fingerprint, 30: pixel unit, 30R: pixel unit, 31: pixel, 32: control circuit, 33: low driver circuit, 34: CDS circuit, 36: circuit, 37: detection circuit, 41: wiring, 43: wiring, 44: wiring, 45: wiring, 46: wiring, 47: wiring, 48: wiring, 49: wiring, 50: light-receiving element, 51: transistor, 52: transistor, 53: transistor, 54: transistor, 56: capacitor, 57: Capacitor, 60: Circuit, 70: Finger, 71: Fingerprint, 80: Pixel, 81: Pixel, 82: Pixel, 82E: Light Source, 83: Gate Driver Circuit, 84: Pixel Unit, 86: Data Driver Circuit, 110: Light Receiving Element, 111: Pixel Electrode, 112: Common Layer, 113: Photoelectric Conversion Layer, 114: Common Layer, 115: Common Electrode, 141: Transistor, 142: Transistor, 143: Space, 148: Light-Shielding Layer, 149: Filter, 151: Substrate, 152: Substrate, 162: Display Unit, 164a: Circuit, 164b: Circuit, 165: Wiring, 165a: Wiring, 165b: Wiring Wire, 166: Conductive layer, 172a: FPC, 172b: FPC, 173a: IC, 173b: IC, 180: Light-emitting element, 183: Light-emitting layer, 190: Light-emitting element, 191: Pixel electrode, 193: Light-emitting layer, 195: Protective layer, 201: Transistor, 204: Connection portion, 211: Insulating layer, 213: Insulating layer, 214: Insulating layer, 215: Insulating layer, 216: Partition, 221: Conductive layer, 222a: Conductive layer, 222b: Conductive layer, 223: Conductive layer, 228: Region, 231: Semiconductor layer, 242: Adhesive layer, 244: Connection layer, 9100: Portable information terminal, 9101: Housing , 9102: Key, 9103: Speaker, 9104: Information, 9110: Display, 9200: Digital signage, 9201: Pillar, 9210: Display, 9300: Mobile information terminal, 9301: Housing, 9302: Speaker, 9303: Camera, 9304: Key, 9305: Connection terminal, 9306: Connection terminal, 9307: Operation button, 9308: Information, 9310: Display, 9400: Mobile information terminal, 9401: Housing, 9402: Wristband, 9403: Key, 9404: Connection terminal, 9406: Information, 9407: Operation button, 9410: Display< / m> < / m> < / m> < / m> < / r> < / r> < / r> < / m> < / r> < / r> < / r> < / r> < / m> < / r> < / r> < / r> < / m> < / r> < / r> < / r> < / m> < / m>

Claims

1. A row driver circuit is provided. the row driver circuit has a function of driving pixels arranged in a matrix of m rows and n columns (n ​​is an integer of 2 or more), and includes first to m-th latch circuits and first to m-th register circuits; a first start pulse signal is input to the first latch circuit; a second start pulse signal is input to the first latch circuit to the mth latch circuit; The scanning signal output from the rth register circuit (r is an integer of 1 or more and m-1 or less) is input to the (r+1)th latch circuit, the first latch circuit has a function of outputting the first start pulse signal to the first register circuit when the data held in the first latch circuit is 0, and outputting the second start pulse signal to the first register circuit when the data held in the first latch circuit is 1; an imaging device having a function in which the s (s is an integer of 2 or more and m or less) latch circuit outputs a scanning signal output from the (s-1) register circuit to the s register circuit when data held in the s latch circuit is 0, and outputs the second start pulse signal to the s register circuit when data held in the s latch circuit is 1, In the first mode, the first start pulse signal is input to the row driver circuit, but the second start pulse signal is not input to the row driver circuit; the first register circuit to the mth register circuit sequentially output a first scanning signal as the scanning signal; the row driver circuit sequentially selects the first row to the m-th row of the pixels arranged in the m rows and n columns in accordance with the first scanning signal; An image of an object is captured at the pixels in the m rows and n columns; In the second mode, when the region in which the object is imaged corresponds to pixels in rows p (p is an integer greater than 1) to q (q is an integer greater than or equal to p and less than or equal to m) among the pixels in m rows and n columns, Among the first latch circuit to the m latch circuit, the p latch circuit holds data of 1, and the first latch circuit to the (p-1) latch circuit and the (p+1) latch circuit to the m latch circuit hold data of 0, In a third mode, the second start pulse signal is input to the row driver circuit, and the first start pulse signal is not input to the row driver circuit; the pth register circuit to the qth register circuit among the first register circuit to the mth register circuit sequentially output a second scanning signal as the scanning signal, and then a scanning stop signal is input to the first register circuit to the mth register circuit, and the (q+1)th register circuit to the mth register circuit do not output a scanning signal; the row driver circuit sequentially selects only the p-th row through the q-th row of the pixels in the m rows and n columns in accordance with the second scanning signal; An imaging device that captures an image of the object only at pixels in rows p to q.

2. In claim 1, a transistor having a metal oxide in a channel formation region, The imaging device, wherein the metal oxide comprises indium.

Images