Selective deposition process on semiconductor substrates

Abstract

Embodiments of this disclosure relate to a method for selectively depositing polysilicon after forming a fluid polymer film to protect a substrate surface within a feature. A first silicon (Si) layer is deposited by physical vapor deposition (PVD). A fluid polymer film is formed on the first silicon (Si) layer on the bottom. A portion of the first silicon (Si) layer is selectively removed from the top surface and at least one side wall. The fluid polymer film is removed. In some embodiments, a second silicon (Si) layer is selectively deposited on the first silicon (Si) layer to fill the feature. In some embodiments, the remaining portion of the first silicon (Si) layer on the bottom is oxidized to form a first silicon oxide (SiO₂) on the bottom. x ) forms a layer, and a silicon (Si) layer or a second silicon oxide (SiO) layer x The ) layer is the first silicon oxide (SiO x It is deposited on top of layers.

Description

[Technical Field]

[0001]

[0001] Embodiments of the present disclosure relate to a selective deposition method facilitated by a fluid polymer. More specifically, embodiments of the present disclosure relate to a method for selectively depositing polysilicon after the use of a fluid polymer to protect a substrate surface within a feature. [Background technology]

[0002]

[0002] Gap-filling processes are integrated with several semiconductor manufacturing processes. Gap-filling processes can be used to fill gaps (or features) with insulating or conductive materials. For example, shallow trench isolation, intermetallic insulating layers, passivation layers, and dummy gates are all typically implemented by gap-filling processes.

[0003]

[0003] As device dimensions continue to shrink (e.g., limit dimensions less than 20 nm, less than 10 nm, and even less) and the thermal balance decreases, the limitations of conventional deposition processes make it increasingly difficult to fill the space without defects.

[0004]

[0004] Due to its unique electronic properties, polysilicon can be used in a variety of semiconductor applications, such as thin-film transistors. However, selective deposition of high-quality silicon (Si) remains a challenge. Known physical vapor deposition (PVD) processes can provide high-quality silicon (Si), but they lack selectivity. In addition, there are no known processes for selectively depositing silicon (Si) on a metal or metal silicide substrate without damaging the metal or metal silicide substrate.

[0005]

[0005] Therefore, a method is needed to protect the metal or metal silicide within the feature in order to enable bottom-up filling by a selective polysilicon deposition process. [Overview of the Initiative]

[0006]

[0006] One or more embodiments of the present disclosure relate to methods for selectively depositing polysilicon. The method comprises depositing a first silicon (Si) layer on the surface of a semiconductor substrate on which at least one feature is formed by physical vapor deposition (PVD), wherein the at least one feature has at least one opening with an opening width on its top surface, at least one side wall, and a bottom, and the feature depth of the at least one feature extends from the top surface to the bottom, and the first silicon (Si) layer is formed on the top surface and along at least one side wall and the bottom; forming a fluid polymer film on the first silicon (Si) layer within the at least one feature, wherein the fluid polymer film is formed on the first silicon (Si) layer on the bottom and has a polymer depth less than or equal to the feature depth; selectively removing at least a portion of the first silicon (Si) layer from the top surface and at least one side wall; and removing the fluid polymer film in order to expose the first silicon (Si) layer on the bottom of the at least one feature.

[0007]

[0007] Further embodiments of the present disclosure relate to a method for selectively depositing polysilicon. The method involves depositing a first silicon (Si) layer on the surface of a semiconductor substrate having at least one feature formed thereon by physical vapor deposition (PVD), wherein the at least one feature has at least one opening having an opening width on its top surface, at least one sidewall, and a bottom, the feature depth of the at least one feature extends from the top surface to the bottom, and the first silicon (Si) layer is formed on the top surface and along the at least one sidewall and the bottom, and depositing the first silicon (Si) layer within the at least one feature The method involves forming a fluid polymer film on a first silicon (Si) layer, wherein the fluid polymer film is formed on the bottom of the first silicon (Si) layer and has a polymer depth less than or equal to the feature depth; selectively removing at least a portion of the first silicon (Si) layer from the top surface and at least one side wall without substantially affecting any material beneath the fluid polymer film; removing the fluid polymer film to expose the bottom of the first silicon (Si) layer; and forming a first silicon oxide (SiO) layer at the bottom. x This includes oxidizing the remaining portion of the first silicon (Si) layer in order to form a new layer.

[0008]

[0008] To enable a detailed understanding of the above-described features of the Disclosure, a more specific description of the Disclosure, which has been briefly summarized above, can be obtained by referring to embodiments. Some of these embodiments are shown in the accompanying drawings. However, it should be noted that the accompanying drawings illustrate only typical embodiments of the Disclosure, as the Disclosure may also permit other equally valid embodiments, and therefore should not be considered to limit the scope of the Disclosure.

[0009]

[0009] In the following attached drawings in which the same elements are indicated by the same reference numerals, the embodiments described herein are merely examples and not limiting. [Brief explanation of the drawing]

[0010] [Figure 1]

[0010] Shows the process flow diagram of a method according to one or more embodiments. [Figure 2]

[0011] Shows a cross-sectional view of a semiconductor substrate according to one or more embodiments. [Figure 3]

[0012] Shows a cross-sectional view of a semiconductor substrate according to one or more embodiments. [Figure 4]

[0013] Shows a cross-sectional view of a semiconductor substrate according to one or more embodiments. [Figure 5]

[0014] Shows a cross-sectional view of a semiconductor substrate according to one or more embodiments. [Figure 6]

[0015] Shows a cross-sectional view of a semiconductor substrate according to one or more embodiments. [Figure 7]

[0016] Shows a cross-sectional view of a semiconductor substrate according to one or more embodiments. [Figure 8A]

[0017] Shows a cross-sectional view of a semiconductor substrate according to one or more embodiments. [Figure 8B]

[0018] Shows a cross-sectional view of a semiconductor substrate according to one or more embodiments. [Figure 8C]

[0019] Shows a cross-sectional view of a semiconductor substrate according to one or more embodiments. [Figure 9]

[0020] Is a schematic top view of an exemplary multi-chamber processing system according to one or more embodiments.

Embodiments for Carrying Out the Invention

[0011]

[0021] Before describing some exemplary embodiments of the present disclosure, it should be understood that the present disclosure is not limited to the details of the configurations or process steps presented in the following description. The present disclosure is capable of other embodiments and can be practiced or carried out in various ways.

[0012]

[0022] As used in this book, the term "approximately" means "about" or "almost," and refers to a variation of no more than ±15% of a given number or range. For example, values ​​differing by ±14%, ±10%, ±5%, ±2%, ±1%, ±0.5%, or ±0.1% satisfy the definition of "approximately."

[0013]

[0023] As used in this document and the attached claims, the terms “substrate” or “wafer” refer to the surface or portion of the surface on which the process operates. Furthermore, unless otherwise clearly indicated by the context, a reference to a substrate may refer only to a portion of the substrate. In addition, a reference to deposition on a substrate may mean both a bare substrate and a substrate having one or more films or features deposited or formed thereon.

[0014]

[0024] As used in this document, “substrate” refers to any substrate or material surface formed on a substrate that is subjected to a film treatment during the manufacturing process. For example, substrate surfaces that can be treated include, depending on the application, materials such as silicon, silicon oxide, strained silicon, silicon-on-insulator (SOI), carbon-doped silicon oxide, amorphous silicon, doped silicon, germanium, and gallium arsenide, as well as any other materials such as metals, metal nitrides, metal alloys, and other conductive materials. A substrate includes, but is not limited to, a semiconductor wafer. A substrate can be exposed to a pretreatment process to polish, etch, reduce, oxidize, hydroxylate, anneal, and / or bake the substrate surface. In addition to direct film treatment on the surface of the substrate itself, any of the film treatment steps disclosed in this disclosure may be performed on an underlying layer formed on the substrate, as disclosed in more detail below, and the term “substrate surface” is intended to include such underlying layers as indicated in the context. Therefore, for example, when a film / layer, or a partial film / layer, is deposited on the substrate surface, the exposed surface of the newly deposited film / layer becomes the substrate surface.

[0015]

[0025] As used in this book, the term “substrate surface” refers to any substrate surface on which layers may be formed. A substrate surface may have one or more features formed therein, one or more layers formed on them, or a combination thereof. The shape of a feature may be any suitable shape, including but not limited to protrusions, grooves, holes, and vias (circular or polygonal). The term “feature” as used in this context refers to any intentional irregularity on a surface. Suitable examples of features include, but are not limited to, grooves with a top, two sidewalls, and a bottom extending into the substrate, vias with one or more sidewalls extending into the substrate and reaching a bottom, and slot vias.

[0016]

[0026] As used in this document and the attached claims, the term “selectively” refers to a process that acts on the first surface with a greater effect than another second surface. Such a process is described as acting "selectively" on the first surface rather than the second. The term "over" used in this way does not refer to the physical orientation of one surface over the other, but rather to the relationship between the thermodynamic or mechanical properties of the chemical reaction on one surface and the other.

[0017]

[0027] The term "on" indicates direct contact between elements. The term "direct" indicates direct contact between elements without an intervening element.

[0018]

[0028] As used in this document and the attached claims, terms such as “precursor,” “reactant,” and “reactive gas” are interchangeable and refer to any gas species that can react with the substrate surface.

[0019]

[0029] Embodiments of this disclosure advantageously provide a method for selectively depositing polysilicon after using a fluid polymer to protect the substrate surface within a feature. One or more embodiments advantageously provide a method for removing metallic material from the fields and sidewalls of a feature without removing the fluid polymer from the bottom surface of the substrate. The remaining fluid polymer has a smooth surface. Further embodiments advantageously provide a method for selectively depositing metallic gap filler in a bottom-up manner.

[0020]

[0030] Embodiments of this disclosure are illustrated by drawings showing processes and substrates according to one or more embodiments of this disclosure. The processes, schemes, and resulting substrates shown are merely illustrative of the disclosed processes, and those skilled in the art will understand that the disclosed processes are not limited to the illustrated applications.

[0021]

[0031] The following description provides numerous specific details to give a comprehensive understanding of the embodiments. Those skilled in the art will see that the embodiments can be carried out without these specific details. In other cases, well-known embodiments are not described in detail to avoid unnecessarily obscuring the embodiments. Furthermore, please understand that the various embodiments shown in the accompanying drawings are illustrative and not necessarily drawn to scale.

[0022]

[0032] Referring to the drawings, this disclosure relates to a selective deposition method 100 for gap-filling material. Figure 1 shows a process flow diagram of the selective deposition method 100 according to one or more embodiments of this disclosure. Figures 2 to 8C show a device 200 having a substrate surface with at least one feature formed internally during processing according to one or more embodiments of this disclosure. Figure 9 is a schematic top view of an exemplary multi-chamber processing system for performing the method according to one or more embodiments.

[0023]

[0033] Figure 2 shows a semiconductor device 200 having a substrate surface 205. The aforementioned substrate surface refers to the exposed surface of the substrate on which a process can be performed. The substrate surface 205 has at least one feature 210 formed inside. Although only three features are shown in the drawing, those skilled in the art will understand that multiple features are each similarly affected by the disclosed method.

[0024]

[0034] At least one feature 210 has an opening 212 having an opening width 202. The opening 212 is formed on the top surface 215 of the device 200. Feature 210 also has one or more sidewalls 214, with a feature depth D extending from the top surface 215 to the bottom 216. Although the drawings show straight and vertical sidewalls, the disclosed methods may also be inclined sidewalls, irregular sidewalls, or inwardly recessed reentrant sidewalls.

[0025]

[0035] In one or more embodiments, the device 200 shown in Figure 2 consists of a material 220 on a feature 210. Those skilled in the art will understand that the top surface 215, sidewalls 214, and bottom 216 may each consist of one or more similar or different materials. For example, the lower part of a sidewall 214 may be formed from a first material, while the upper part of the same sidewall 214 may consist of a second material. Similarly, a thin layer may be deposited on the top surface 215 without forming an obvious portion of the sidewall 214. In one or more embodiments, the bottom 216 may consist of a different material from the sidewalls 214. In one or more embodiments, the material on the bottom 216 includes silicon (Si). In one or more embodiments, the sidewalls 214 include a dielectric material. The dielectric material may be any suitable dielectric material known to those skilled in the art.

[0026]

[0036] In one or more embodiments, the aperture width 202 of the aperture 212 is approximately 50 nm or less, approximately 30 nm or less, approximately 20 nm or less, approximately 10 nm or less, or approximately 7 nm or less. In one or more embodiments, the aperture width 202 is in the range of approximately 8 nm to approximately 20 nm.

[0027]

[0037] In one or more embodiments, the feature depth D of feature 210 is approximately 5 nm or more, approximately 10 nm or more, approximately 20 nm or more, approximately 50 nm or more, approximately 60 nm or more, approximately 75 nm or more, approximately 100 nm or more, approximately 200 nm or more, approximately 300 nm or more, approximately 400 nm or more, or approximately 450 nm or more. In one or more embodiments, the feature depth D is in the range of approximately 5 nm to approximately 500 nm. In one or more embodiments, the feature depth D is in the range of approximately 10 nm to approximately 300 nm. In one or more embodiments, the feature depth D is in the range of approximately 60 nm to approximately 100 nm.

[0028]

[0038] As used in this document, the term “feature” refers to any intentional irregularity of a surface. Suitable examples of features include, but are not limited to, trenches or vias with a top, two sidewalls, and a bottom, and peaks with a top and two sidewalls. Features can have any suitable aspect ratio (the ratio of the depth of a feature to the width of a feature). In one or more embodiments, the aspect ratio of at least one feature 210 is approximately 5:1, 10:1, 15:1, 20:1, 25:1, 30:1, 35:1, or 40:1 or greater.

[0029]

[0039] For simplicity, when referring to Figures 3-8C, we will be referring to the portion of feature 210 shown in Figure 2. For example, device 200 shown in Figure 3 is referred to as having a bottom 216. For clarity in the presented figures, the reference numbers for the portion of feature 210 are not shown in Figures 3-8C.

[0030]

[0040] Referring to Figures 1 and 2-8C, in one or more embodiments, Method 100 begins with an optional step 105 for pre-treating the substrate. The pre-treating in step 105 may be any suitable pre-treating known to those skilled in the art. Suitable pre-treating includes, but is not limited to, preheating, washing, immersion, removal of native oxides, or deposition of a contact layer (e.g., titanium silicide (TiSi)) or a capping layer (e.g., TiSiN). In one or more embodiments, a layer such as titanium silicide or titanium silicon nitride (TiSiN), or another metal silicide, is deposited in step 105 to form a silicide contact.

[0031]

[0041] Those skilled in the art will understand that the disclosed processes are not limited to silicide contact and liner / gap filling applications. Generally, front-end of line (FEOL) refers to the first part of integrated circuit manufacturing, including transistor manufacturing; middle-of-line (MOL) refers to connecting the transistor-to-chip interconnection portion using a series of contact structures; and back-end of line (BEOL) refers to the series of process steps from after transistor manufacturing to wafer completion. One or more embodiments of this disclosure relate to methods for forming devices useful for one or more FEOL, MOL, and / or BEOL processes known to those skilled in the art.

[0032]

[0042] Figure 3 shows an exemplary device 200 after an optional step 105. The device 200 includes a bottom formed from at least one feature 210, as well as side walls and a top formed from a layer 220. In one or more embodiments, at least one feature 210 includes a conductive material, and the layer 220 includes a dielectric. Those skilled in the art will understand that the disclosed process may be performed for different materials, and / or the illustrated layers may be arranged in different ways.

[0033]

[0043] Method 100 continues to cycle 110. In cycle 110, a first silicon (Si) layer 240 is formed at the bottom 216 of at least one feature 210 of the device 200. Cycle 110 includes a series of steps, each of which may be performed sequentially and repeated. Some of the steps are optional within each cycle. A given optional step may be performed periodically (every other cycle, every 5 cycles, or every 100 cycles) as needed based on predetermined parameters, or it may not be performed at all during each cycle.

[0034]

[0044] As shown in Figure 3, cycle 110 begins with step 112. In step 112, the first silicon (Si) layer 240 is deposited on the substrate surface 205 of the device 200. The first silicon (Si) layer 240 has a bottom thickness at the bottom 216, a top thickness at the top 215, and / or a sidewall thickness at the sidewall 214. In some embodiments, the first silicon (Si) layer 240 is formed at the bottom of at least one feature 210.

[0035]

[0045] The first silicon (Si) layer 240 can be deposited by any suitable method. In one or more embodiments, the first silicon (Si) layer 240 can be deposited by physical vapor deposition (PVD). In these embodiments, as shown in Figure 3, the thickness of the sidewalls is smaller than the thickness of the top and bottom. In one or more embodiments, the thickness of the top is greater than the thickness of the bottom.

[0036]

[0046] Those skilled in the art will understand that the disclosed method may begin with a first silicon (Si) layer 240 already formed on the substrate surface 205 of the device 200, after which the device 200 is provided. As used herein and in the appended claims, the term “provided” means that the substrate is made available for processing (e.g., placed in a processing chamber).

[0037]

[0047] Cycle 110 continues to step 114. As shown in Figure 4, in step 114, the fluid polymer film 250 is formed on the first silicon (Si) layer 240 within the feature 210 of the device 200. The polymer film 250 has a polymer thickness less than or equal to the feature depth D. In other words, as a fluid film (described later), the polymer film is entirely contained within the feature 210 and is not present on the top surface 215 of the device 200. Thus, in this respect, the polymer may be described as having “thickness” or, interchangeably, as having “depth”. In other words, the “thickness” of the polymer is measured in the Z direction within the feature 210 of the device 200, and its thickness / depth is less than or equal to the feature depth D. In one or more embodiments, the polymer film 250 has a thickness in the range of approximately 1 nm to approximately 50 nm, approximately 1 nm to approximately 10 nm, or approximately 2 nm to approximately 5 nm. In some embodiments, the thickness of the polymer film 250 is in the range of 1% to 99%, 1% to 80%, or 2% to 20% of the depth D of at least one feature 210.

[0038]

[0048] In the disclosed method, processing parameters and reactants may be selected to limit the conformality of the deposited material, thereby enabling the deposited material to better fill features on the substrate. A fluid material is a material that, under appropriate conditions, will flow by gravity to lower parts of the substrate surface and / or by capillary action into narrow CD spaces of grooves or other features.

[0039]

[0049] In one or more embodiments, forming a polymer film involves exposing a surface to one or more monomers.

[0040]

[0050] In some embodiments, the one or more monomers comprise, consist essentially of, or consist of a single monomer selected from the group consisting of a methyl group, a methacrylate group, a styrene group, a benzyl alcohol group, a benzyl chloride group, an aldehyde group, and an amine group. In some embodiments, the one or more monomers consist of a single monomer selected from the group consisting of a methyl group, a methacrylate group, a styrene group, a benzyl alcohol group, a benzyl chloride group, an aldehyde group, and an amine group.

[0041]

[0051] In one or more embodiments, the monomer comprises, consists essentially of, or consists of a single difunctional monomer, wherein each functional group within the difunctional monomer is different. In this way, one functional group of a monomer molecule will react with another functional group of a different monomer molecule. One skilled in the art can recognize this as an "A" polymer.

[0042]

[0052] In one or more embodiments, the one or more monomers comprise, consist essentially of, or consist of one or more of an amine having two functional groups, an aldehyde having two functional groups, a ketone having two functional groups, and an alcohol having two functional groups.

[0043]

[0053] In one or more embodiments, the amine has the formula H2N-(CH x ) n -NH2, where n is an integer in the range of 1 to 20 and x is 1 or 2. In one or more embodiments, the aldehyde has the formula OHC-(CH x ) m -CHO, where m is an integer in the range of 2 to 20 and x is 1 or 2. In one or more embodiments, the ketone has the formula ROC-(CH x ) q -COR, where q is an integer in the range of 2 to 20, x is 1 or 2, and R is an alkyl group. In one or more embodiments, the formula ROC-(CH x ) qIn -COR, each R is the same alkyl group. In one or more embodiments, the formula ROC-(CH x ) q In -COR, each R is a different alkyl group. In one or more embodiments, the alcohol is of the formula HOC-(CH x ) r -COH has a function where r is an integer between 2 and 20, and x is 1 or 2.

[0044]

[0054] In one or more embodiments, amines, aldehydes, ketones, and alcohols contain carbon atoms. In one or more embodiments, the monomers described herein may be linear, branched, cyclic, saturated, or unsaturated. The monomers described herein do not contain reactive groups in the chemical polymerization processes described herein.

[0045]

[0055] In certain embodiments, the monomer may be selected from one or more of the following: TIFF2026523063000002.tif105170

[0046]

[0056] In one or more embodiments, the monomer comprises, substantially consists of, or is composed of two monomers (e.g., two bifunctional monomers having identical functional groups). In this way, the functional groups of one monomer react with the functional groups of the second monomer. Those skilled in the art can recognize this as an "AB" polymer.

[0047]

[0057] In one or more embodiments, one or more monomers comprise, substantially consist of, or consist of three monomers, wherein two of the monomers independently comprise one or more of amines having a single functional group, aldehydes having a single functional group, ketones having a single functional group, or alcohols having a single functional group, and at least one of the monomers is independently selected from the group consisting of amines having a difunctional group, aldehydes having a difunctional group, ketones having a difunctional group, and alcohols having a difunctional group. Those skilled in the art can recognize this as an "ABC" polymer.

[0048]

[0058] In one or more embodiments, flexible monomers used to produce the selective protective polymer film 250 can form oligomers at a higher rate during polymerization compared to rigid monomers. Therefore, in one or more embodiments, the polymerization process proceeds through monomer, oligomer, and polymer stages. Polymer formation depends on the local concentration of the monomers. In one or more embodiments, monomers A and B are used, which can only bond with A and B, and not with A and with B. Therefore, during the purging and pumping stages, the concentration of A decreases significantly, especially in the field / wall regions 214, 215. In this case, when monomer B is introduced, only oligomers are formed on the field / wall regions 214, 215 where the concentration of monomer A is very low. Due to the difference in pumping and purging efficiency between the field / walls 214, 215 and the bottom 216 of feature 210, the concentration of monomer A at the bottom 216 of feature 210 is higher than the concentration at the field / walls 214, 215. The higher concentration of A monomer at the bottom 216 of feature 210 leads to the formation of oligomers or polymers with a higher molecular weight, together with the introduced B monomer. These oligomers and polymers will continue to grow at the bottom 216 of feature 210 throughout the process cycle. In one or more embodiments, when a B monomer with a lower molecular weight is used, even if the BAB oligomer is formed in the fields / walls 214, 215 where the concentration of A is low, it will be more volatile compared to the higher oligomer (BABAB, etc.) formed at the bottom 216 of feature 210. This minimizes the amount of polymer residue in the fields / walls 214, 215.

[0049]

[0059] The benzene ring has an electrical advantage in activating aldehyde functional groups during bonding with amines. When two aldehyde groups are located at the 1,4 positions of the benzene ring, the monomer is a hard or rigid monomer. When the monomer reacts with 1,4-diaminobenzene, a hard polymer with a rough surface within the features is formed.

[0050]

[0060] Therefore, in one or more embodiments, when two aldehyde groups are located at the 1,3 positions of benzene, it is a flexible monomer, and a flexible polymer film 250 is formed. The flexible polymer film 250 has a lower glass transition temperature compared to films formed from rigid polymers. Therefore, in one or more embodiments, particularly T g When the temperature is lower than the process temperature, a smooth polymer surface, flexibility, and a lower glass transition temperature (T) are obtained. g A polymer film 250 having ) is advantageously formed.

[0051]

[0061] In one or more embodiments, the use of flexible monomers increases the chances of oligomer formation (e.g., ABAB or ABABAB). Flexible monomers also enable smooth surfaces with easy packing and packing density within feature 210. Flexible monomers also reduce polymer residue in the field / wall 214,215 region due to the volatility of the oligomer and its fluidity within the feature. This improvement eliminates polymer residue in field 215 and sidewall 214, improving process efficiency. In one or more embodiments, the quality of the semiconductor device is improved when there is little to no residue in the field 215 and wall 214 region.

[0052]

[0062] While not intended to be theoretically restrictive, the polymer formed and deposited as a polymer film 250 is considered to have the flexibility to fill the bottom 216 of the feature 210. In one or more embodiments, the polymer is fluid during deposition and further processing.

[0053]

[0063] As mentioned above, the polymer film 250 is fluid. It has been found that controlling the size of the obtained oligomers is necessary to control the "fluidity" of the obtained polymer film 250.

[0054]

[0064] Therefore, in one or more embodiments, the polymer film 250 is formed on a substrate maintained at a temperature in the range of 0°C to 400°C. In some embodiments, the substrate is maintained at a temperature in the range of 30°C to 400°C.

[0055]

[0065] Furthermore, other process parameters can be controlled during the formation of the polymer film 250. Examples of controllable parameters include, but are not limited to, the pressure of the processing chamber, the selection of monomers, the use of an inert diluent or carrier gas, the partial pressure of the monomers, the pulse sequence of the monomers, and the pause period that allows the polymer material to flow.

[0056]

[0066] After forming the fluid polymer film 250 in step 114, cycle 110 continues to step 116. As shown in Figure 5, in step 116, at least a portion of the first silicon (Si) layer 240 is selectively removed. The first silicon (Si) layer 240 is removed from the top surface 215 without substantially affecting any material beneath the polymer film 250. Processes used in this manner that do not "substantially affect" the material layers do not cause any reduction in volume, thickness, or composition. Those skilled in the art will understand that the polymer film 250 acts as an etching stop layer while a portion of the first silicon (Si) layer 240 is removed.

[0057]

[0067] In one or more embodiments, step 116 also removes a portion of the first silicon (Si) layer 240 from the sidewall 214. In one or more embodiments, some portion of the first silicon (Si) layer 240 present on the sidewall 214 below the upper surface of the polymer film 250 may remain without being removed.

[0058]

[0068] In one or more embodiments, the selective removal of the portion of the first silicon (Si) layer in step 116 is performed on a substrate maintained at a temperature in the range of 100°C to 400°C.

[0059]

[0069] In one or more embodiments, selective removal of the first silicon (Si) layer 240 is performed by exposing the substrate surface 205 to a fluorine-based plasma or a chlorine-based plasma. Any suitable fluorine-based plasma or chlorine-based plasma known to those skilled in the art for selectively removing the first silicon (Si) layer 240 may be used.

[0060]

[0070] In one or more embodiments, the selective removal of the first silicon (Si) layer 240 in step 116 is performed by exposing the substrate surface 205 of the device 200 to NF3 radicals. In one or more embodiments, the substrate is maintained at a temperature in the range of 80°C to 150°C.

[0061]

[0071] In one or more embodiments, the selective removal of the first silicon (Si) layer 240 in step 116 is performed by exposing the substrate surface 205 of the device 200 to a chlorine-containing gas or an alkyl chloride gas. In some embodiments, the alkyl chloride gas includes, but is not limited to, methyl chloride, 2-chloropropane, or 1,2-dichloroethane. In one or more embodiments, the substrate is maintained at a temperature in the range of 80°C to 150°C.

[0062]

[0072] Cycle 110 continues to step 118. As shown in Figure 6, in step 118, the polymer film 250 is removed, exposing the remaining portion of the first silicon (Si) layer 240 (for example, a portion of the first silicon (Si) layer above the bottom 216 beneath the polymer film 250). In one or more embodiments, the removal of the polymer film 250 is complete, with little or no residue remaining.

[0063]

[0073] In one or more embodiments, the polymer film 250 is removed by exposing the substrate surface 205 of the device 200 to hydrogen (H2) plasma treatment. In one or more embodiments, the polymer film 250 is removed by exposure to a high-temperature, thermal O2 atmosphere.

[0064]

[0074] In one or more embodiments, the removal of the polymer film 250 is performed by exposing the substrate surface 205 of the device 200 to one or more heat treatments or hydrogen (H2) plasma treatments. In one or more embodiments, after removing the first silicon (Si) layer 240 from the top surface 215 and side walls 214, the polymer film 250 may be thermally removed by heating to 350°C to 500°C under vacuum. In other embodiments, after removing the first silicon (Si) layer 240 from the top surface 215 and side walls 214, the polymer film 250 may also be removed by hydrogen (H2) plasma at a temperature in the range of 100°C to 300°C for a time in the range of 2 to 30 seconds.

[0065]

[0075] In one or more embodiments, the removal of the polymer film 250 in step 118 includes a first step of exposing the substrate surface to hydrogen (H2) plasma and oxygen (O2) plasma, and a second step of exposing the substrate surface to hydrogen (H2) plasma only.

[0066]

[0076] The first step may be carried out with a chamber pressure in the range of approximately 1 Torr to approximately 10 Torr (e.g., approximately 5 Torr), a hydrogen (H2) plasma flow rate in the range of approximately 1000 sccm to approximately 10000 sccm (e.g., 6000 sccm), and an oxygen (O2) flow rate in the range of approximately 100 sccm to approximately 1000 sccm (e.g., 300 sccm).

[0067]

[0077] The second step can be carried out at a chamber pressure in the range of approximately 10 Torr to approximately 50 Torr (e.g., approximately 20 Torr) and a hydrogen (H2) plasma flow rate in the range of approximately 10 sccm to approximately 10,000 sccm.

[0068]

[0078] The polymer removal process in step 118 can be carried out in a processing chamber, such as a Volta® CVD / ALD chamber, which is available from Applied Materials, Inc. in Santa Clara, California.

[0069]

[0079] After removing the polymer film 250 in step 118 shown in Figure 6, cycle 110 optionally continues to step 119. In step 119, the remaining portion of the first silicon (Si) layer 240 is oxidized, leaving the first silicon oxide (SiO) on the bottom 216. x A layer is formed. In one or more embodiments, in step 119, oxidizing the remainder of the first silicon (Si) layer 240 includes a thermal oxidation process and / or a plasma oxidation process. In one or more embodiments, the thermal oxidation process includes oxidizing the remainder of the first silicon (Si) layer 240 in a process chamber or furnace at a temperature in the range of about 500°C to about 900°C. In one or more embodiments, the plasma oxidation process includes exposing the remainder of the first silicon (Si) layer 240 to an oxygen-containing plasma at a temperature in the range of about 200°C to about 500°C. The oxygen-containing plasma may include any suitable oxygen-containing plasma known to those skilled in the art.

[0070]

[0080] After removing the polymer film 250 in step 118 shown in Figure 6, cycle 110 oxidizes the remaining portion of the first silicon (Si) layer 240 to form the first silicon oxide (SiO) on the bottom 216. x In the embodiment where layer 242 is formed (step 119), cycle 110 continues to step 130, which will be described in more detail below.

[0071]

[0081] In one or more embodiments, at the end of cycle 110, the surface of the first silicon (Si) layer 240 is free of contaminants or residues from the polymer layer 250. More specifically, in one or more embodiments, the surface of the first silicon (Si) layer 240 is free of carbon or oxygen residues. In one or more embodiments, if method 100 includes repeated cycles 110 (see below), there are no contaminants or residues between the first silicon (Si) layer 240 deposited in subsequent cycles. In one or more embodiments, if method 100 includes the deposition of a second silicon (Si) layer 260 (see below), there are no contaminants or residues between the first silicon (Si) layer 240 and the second silicon (Si) layer 260.

[0072]

[0082] In one or more embodiments, during the removal of the polymer layer 250, the monomer is selected such that it does not contain any oxygen atoms that could oxidize the surface of the first silicon (Si) layer 240.

[0073]

[0083] Method 100 proceeds to measurement point 120. At point 120, the substrate is evaluated to determine whether the first silicon (Si) layer 240 has reached a predetermined thickness or whether a predetermined number of cycles 110 have been performed. If the conditions are met, Method 100 proceeds to step 130. If the conditions are not met, Method 100 returns to step 112, which is the beginning of cycle 110. In these embodiments, where cycle 110 is repeated to form additional material, those skilled in the art will understand that step 112 is often performed to deposit the required additional metallic material (e.g., silicon (Si)). In one or more embodiments, the predetermined thickness is in the range of about 2 nm to about 10 nm.

[0074]

[0084] In one or more embodiments not shown, the first silicon (Si) layer 240 can be optionally etched. In one or more embodiments, the first silicon (Si) layer 240 is etched to remove the portion of the first silicon (Si) layer 240 that extends to the sidewall 214. When etched, the first silicon (Si) layer 240 is also thinned on the bottom 216 of the feature 210. Thus, it will be understood by those skilled in the art that the first silicon (Si) layer 240 can be deposited to a bottom thickness greater than desired in the final product in order to provide sacrificial material that will be removed when etching the metallic material from the sidewall 214.

[0075]

[0085] Method 100 includes an optional step 130. As shown in Figure 7, in some embodiments, the optional step 130 is performed after the removal of the polymer film 250 in step 118 shown in Figure 6.

[0076]

[0086] In step 130 of Figure 7, the second silicon (Si) layer 260 is selectively deposited on the first silicon (Si) layer 240. The second silicon (Si) layer 260 may be deposited by any suitable deposition process known to those skilled in the art. In this case, the second silicon (Si) layer 260 is selectively formed on the surface of the first silicon (Si) layer 240 rather than on other substrate surface materials (e.g., layer 220). In one or more embodiments, selective deposition of the second silicon (Si) layer 260 involves chemical vapor deposition (CVD). The selective deposition process provides a gap-filling material comprising a second silicon (Si) layer 260 formed in a bottom-up manner without lateral deposition from the sidewalls 214. In one or more embodiments, the second silicon (Si) layer 260 is deposited without forming any voids or seams within the second silicon (Si) layer 260.

[0077]

[0087] As shown in Figure 8B, in some embodiments, the optional step 130 is performed after the removal of the polymer film 250 in step 118 shown in Figure 6, and the remaining portion of the first silicon (Si) layer 240 is oxidized in cycle 110 to form the first silicon oxide (SiO) on the bottom 216. x After forming layer 242 (step 119), cycle 110 then proceeds to step 130. In one or more embodiments not shown, a second silicon (Si) layer 260 is formed from the first silicon oxide (SiO x ) is selectively deposited on top of layer 242. Although not shown, those skilled in the art will know that the second silicon (Si) layer 260 is deposited on top of the first silicon oxide (SiO) in step 130. x Before being selectively deposited on layer 242, the remaining portion of the first silicon (Si) layer 240 is oxidized, and in step 119 shown in Figure 8A, the first silicon oxide (SiO) is deposited on the bottom 216. x It will be understood that this will result in the formation of layer 242. In certain embodiments, the deposition process will be carried out on the first silicon oxide (SiO) rather than other substrate surface materials (e.g., layer 220). x The selective deposition process is selective to the surface of layer 242. The selective deposition process provides a gap-filling material including a second silicon (Si) layer 260 formed in a bottom-up manner without lateral deposition from the sidewalls 214. In one or more embodiments, the second silicon (Si) layer 260 is deposited without forming any voids or seams within the second silicon (Si) layer 260.

[0078]

[0088] In step 130 of Figure 7, the second silicon (Si) layer 260 is selectively deposited on the first silicon (Si) layer 240. The deposition process is selective to the surface of the first silicon (Si) layer 240 rather than to other substrate surface materials (e.g., layer 220). The selective deposition process provides a gap-filling material including the second silicon (Si) layer 260, which is formed in a bottom-up manner without lateral deposition from the sidewalls 214. In one or more embodiments, the second silicon (Si) layer 260 is deposited without forming any voids or seams within the second silicon (Si) layer 260.

[0079]

[0089] Figure 8B shows step 130 of cycle 110. In step 130 of Figure 8B, the second silicon (Si) layer 260 is formed from the first silicon oxide (SiO) layer. x The second silicon (Si) layer 260 is selectively deposited on top of layer 242. The second silicon (Si) layer 260 can be deposited by any suitable deposition process known to those skilled in the art. In this case, the second silicon (Si) layer 260 is deposited on top of the first silicon oxide (SiO) rather than other substrate surface materials (e.g., layer 220). x The second silicon (Si) layer 260 is selectively formed on the surface of layer 242. In one or more embodiments, selective deposition of the second silicon (Si) layer 260 involves chemical vapor deposition (CVD). The selective deposition process provides a gap-filling material comprising a second silicon (Si) layer 260 formed in a bottom-up manner without lateral deposition from the sidewalls 214. In one or more embodiments, the second silicon (Si) layer 260 is deposited without forming any voids or seams within the second silicon (Si) layer 260.

[0080]

[0090] Figure 8C shows the process of producing the first silicon oxide (SiO2) in step 130 of Figure 8B. x The image shows step 119 after selectively depositing a second silicon (Si) layer 260 on top of the first silicon oxide (SiO) layer 242. In one or more embodiments, the second silicon (Si) layer 260 is selectively oxidized in step 119 to form the first silicon oxide (SiO) layer. x ) A second silicon oxide (SiO2) is placed on top of layer 242. x ) layer 262 is formed. In one or more embodiments, a second silicon oxide (SiO x The ) layer is removed by an etching process, thereby removing the first silicon oxide (SiO x ) is selectively deposited on top of the layer, and as a result of the etching process, a second silicon oxide (SiO) is formed. x A layer is formed. The etching process may be any suitable etching process known to those skilled in the art.

[0081]

[0091] Method 100 is performed after step 130 (selectively depositing the second silicon (Si) layer 260), or in step 130 of Figure 8B, on the first silicon oxide (SiO x After step 119, in which a second silicon (Si) layer 260 is selectively deposited on layer 242, the process may be terminated or may continue to an optional post-processing step 140. The optional post-processing step 140 may be, for example, a process to change the properties of the film (e.g., annealing or plasma treatment), a further film deposition process to grow an additional film (e.g., an additional ALD or CVD process), or a further etching process to form a desired predetermined device structure. In one or more embodiments, the optional post-processing step 140 may be a process to change the properties of the deposited film. In one or more embodiments, the optional post-processing step 140 includes annealing the device 200. In one or more embodiments, the annealing is performed at a temperature of about 300°C or higher, about 400°C or higher, about 500°C or higher, about 600°C or higher, about 700°C or higher, about 800°C or higher, about 900°C or higher, or about 1000°C or higher. The annealing environment of one or more embodiments includes one or more of the following: an inert gas (e.g., molecular nitrogen (N2), argon (Ar)), a reducing gas (e.g., molecular hydrogen (H2) or ammonia (NH3)), or an oxidizing agent, but not limited to oxygen (O2), ozone (O3), or a peroxide. Annealing can be performed for any suitable length of time. In one or more embodiments, the substrate is annealed for a predetermined time in the range of about 15 seconds to about 90 minutes, or about 1 minute to about 60 minutes.

[0082]

[0092] Additional embodiments of this disclosure include dielectric materials (e.g., hafnium oxide (HfO)), but are not limited to these. x ) or zirconium oxide (ZrO x This invention relates to a method for selectively depositing high dielectric materials (including ) with high dielectric constants. Protecting the substrate surface within a feature using a fluid polymer is possible for metallic materials such as silicon and polysilicon, as well as hafnium oxide (HfO). xIt has been advantageously found that it can be used to selectively deposit dielectric materials such as ) or zirconium oxide (ZrOx).

[0083]

[0093] In one or more embodiments, hafnium oxide (HfO x ) can be deposited by method 100, which includes cycle 110. In some embodiments, hafnium oxide (HfO x The hafnium oxide (HfO) is deposited directly onto the substrate surface 205 of the device 200 by atomic layer deposition (ALD) or chemical vapor deposition (CVD). x A method for selectively depositing dielectric material after the deposition of ) is as follows: hafnium oxide (HfO) on the bottom x ) protects the hafnium oxide (HfO) of field 215 and wall 214. x To remove hafnium oxide (HfO) in at least one feature, x The method includes forming a fluid polymer film on top of the first dielectric layer (e.g., hafnium oxide (HfO)). Therefore, in one or more embodiments, the method 100 for selectively depositing dielectric material optionally includes pre-treating the substrate (step 105) and forming a first dielectric layer (e.g., hafnium oxide (HfO)). x A cycle 110 including depositing (for example, hafnium oxide (HfO)) or zirconium oxide (ZrOx) (step 112), forming a fluid polymer film (step 114), selectively removing a portion of the first dielectric layer (step 116), and removing the polymer film (step 118), a measurement point (step 120), and optionally a second dielectric layer (for example, hafnium oxide (HfO)) x The process includes selectively depositing (or zirconium oxide (ZrOx)) onto the remaining portion of the first dielectric layer, and optionally performing post-treatment (step 140).

[0084]

[0094] Figure 9 shows a schematic top view of an example of a multi-chamber processing system 400 according to an embodiment of the present disclosure. The processing system 400 generally includes a factory interface 402, load lock chambers 404, 406, transfer chambers 408, 410 with their respective transfer robots 412, 414, holding chambers 416, 418, and processing chambers 420, 422, 424, 426, 428, 430. As will be described in detail herein, wafers in the processing system 400 can be processed in various chambers and transferred between various chambers without exposing the wafers to the ambient environment outside the processing system 400 (e.g., the ambient air environment that may be present in the factory). For example, wafers can be processed in various chambers and transferred between various chambers in a low-pressure (e.g., about 300 Torr or less) or vacuum environment without disrupting the low-pressure or vacuum environment during various processes performed on the wafers in the processing system 400. Thus, the processing system 400 can provide an integrated solution for processing a portion of wafers.

[0085]

[0095] Examples of processing systems that can be appropriately modified in accordance with the instructions provided in this book include the Endura®, Producer®, or Centura® integrated processing systems, commercially available from Applied Materials, Inc. in Santa Clara, California, or other suitable processing systems. Other processing systems (including those from other manufacturers) may be adapted to benefit from the embodiments described herein.

[0086]

[0096] In the example shown in Figure 9, the factory interface 402 includes a docking station 440 and a factory interface robot 442 to facilitate wafer transfer. The docking station 440 is configured to receive one or more forward-opening unified pods (FOUPs) 444. In some examples, each factory interface robot 442 generally includes a blade 448 located at one end of the factory interface robot 442, configured to transfer wafers from the factory interface 402 to load lock chambers 404, 406.

[0087]

[0097] The load lock chambers 404 and 406 have ports 450 and 452 connected to the factory interface 402, respectively, and ports 454 and 456 connected to the transfer chamber 408, respectively. The transfer chamber 408 further has ports 458 and 460 connected to the holding chambers 416 and 418, respectively, and ports 462 and 464 connected to the processing chambers 420 and 422, respectively. Similarly, the transfer chamber 410 has ports 466 and 468 connected to the holding chambers 416 and 418, respectively, and ports 470, 472, 474, and 476 connected to the processing chambers 424, 426, 428, and 430, respectively. Ports 454, 456, 458, 460, 462, 464, 466, 468, 470, 472, 474, and 476 may be slit valve openings equipped with slit valves to allow wafers to pass through, for example, by transfer robots 412 and 414, and to provide a seal between each chamber to prevent gas from passing between them. Generally, any port is open for wafer transfer; otherwise, the port is closed.

[0088]

[0098] The load lock chambers 404, 406, transfer chambers 408, 410, holding chambers 416, 418, and processing chambers 420, 422, 424, 426, 428, 430 may be fluidically coupled to a gas and pressure control system (not shown). The gas and pressure control system may include one or more gas pumps (e.g., turbopumps, cryopumps, roughing pumps), a gas source, various valves, and conduits fluidly coupled to the various chambers. During operation, the factory interface robot 442 transfers wafers from the FOUP 444 to the load lock chamber 404 or 406 via port 450 or 452. The gas and pressure control system then pumps down the load lock chamber 404 or 406. The gas and pressure control system further maintains the transfer chambers 408, 410 and the holding chambers 416, 418 in an internal low-pressure or vacuum environment (which may include an inert gas). Therefore, pumping down the load lock chamber 404 or 406 facilitates the passage of the wafer between, for example, the atmospheric environment of the factory interface 402 and the low-pressure or vacuum environment of the transfer chamber 408.

[0089]

[0099] With the wafer in load lock chamber 404 or 406 being pumped down, the transfer robot 412 transfers the wafer from load lock chamber 404 or 406 to transfer chamber 408 via port 454 or 456. The transfer robot 412 can then transfer the wafer to either processing chamber 420 or 422 via ports 462 or 464 for processing, or to holding chambers 416 or 418 via ports 458 or 460 to hold for further transfer. Similarly, the transfer robot 414 can access the wafer in holding chamber 416 or 418 via port 466 or 468 and transfer the wafer to either processing chamber 424, 426, 428 or 430 via ports 470, 472, 474 or 476 for processing, or to holding chambers 416 or 418 via ports 466 or 468 to hold for further transfer. Wafer transfer and holding within and between various chambers can be performed in a low-pressure or vacuum environment provided by a gas and pressure control system.

[0090]

[0100] Processing chambers 420, 422, 424, 426, 428, and 430 may be any suitable chamber for processing wafers. In some embodiments, processing chamber 420 can perform an annealing process, processing chamber 422 can perform a cleaning process, and processing chambers 424, 426, 428, and 430 can perform an epitaxial growth process. In some embodiments, processing chamber 422 can perform a cleaning process, processing chamber 420 can perform an etching process, and processing chambers 424, 426, 428, and 430 can perform their respective epitaxial growth processes. Processing chamber 422 may be a SiCoNi® pre-clean chamber available from Applied Materials, Inc., Santa Clara, California. Processing chamber 420 may be a Selectra® etching chamber available from Applied Materials, Inc., Santa Clara, California. Processing chamber 422 may be a Volta® CVD / ALD chamber available from Applied Materials, Inc., Santa Clara, California.

[0091]

[0101] The system controller 490 is connected to the processing system 400 to control the processing system 400 or its components. For example, the system controller 490 can control the operation of the processing system 400 by using direct control of the chambers 404, 406, 408, 416, 418, 410, 420, 422, 424, 426, 428, and 430 of the processing system 400, or by controlling controllers associated with the chambers 404, 406, 408, 416, 418, 410, 420, 422, 424, 426, 428, and 430. During operation, the system controller 490 enables data acquisition and feedback from each chamber to adjust the performance of the processing system 400.

[0092]

[0102] The system controller 490 generally includes a central processing unit (CPU) 492, memory 494, and support circuitry 496. The CPU 492 may be any form of general-purpose processor available for use in an industrial environment. Memory 494, or non-temporary computer-readable media, is accessible by the CPU 492 and may be one or more types of memory, such as random access memory (RAM), read-only memory (ROM), floppy disks, hard disks, or other forms of local or remote digital storage. Support circuitry 496 is coupled to the CPU 492 and may include a cache, clock circuitry, input / output subsystems, power supply, etc. The various methods disclosed herein can generally be implemented by the CPU 492 executing computer instruction code stored in memory 494 (or the memory of a particular process chamber) under the control of the CPU 492, for example, as software routines. Once the computer instruction code is executed by the CPU 492, the CPU 492 controls each chamber to execute processes according to various schemes.

[0093]

[0103] Other processing systems can also be configured in other ways. For example, more or fewer processing chambers can be connected to the transfer device. In the illustrated example, the transfer device includes transfer chambers 408, 410 and holding chambers 416, 418. In other examples, more or fewer transfer chambers (e.g., one transfer chamber) and / or more or fewer holding chambers (e.g., no holding chambers) may be implemented as transfer devices within the processing system.

[0094]

[0104] The process may generally be stored as a software routine in the memory of the system controller 1190, and when executed by the processor, causes the process chamber to execute the process of the present disclosure. The software routine may also be stored and / or executed by a second processor (not shown) located remotely from the hardware controlled by the processor. Furthermore, some or all of the methods of the present disclosure can be performed in hardware. Thus, the process may be implemented in software and executed using a computer system in hardware (e.g., application-specific integrated circuits or other types of hardware implementations), or in a combination of software and hardware. When executed by the processor, the software routine transforms a general-purpose computer into a dedicated computer (controller) that controls the chamber operation so that the process can be executed.

[0095]

[0105] Embodiments of this disclosure relate to non-temporary computer-readable media. In one or more embodiments, the non-temporary computer-readable media includes instructions that, when executed by a controller of a processing chamber, cause the processing chamber to perform a step of any of the methods described herein (e.g., Method 100).

[0096]

[0106] To describe the relationship between one element or feature and another as shown in the drawings, spatially relative terms such as “beneath,” “below,” “lower,” “above,” and “upper” may be used in this document for ease of explanation. These spatially relative terms are intended to encompass different orientations of the device in use or operation, in addition to the orientation shown in the drawing. Therefore, for example, if the device in the drawing is upside down, an element described as “below” or “beneath” another element or feature would be located “above” that other element or feature. Thus, the exemplary term “below” can encompass both above and below directions. Devices may be oriented in other ways (rotated 90 degrees or in other directions), and the spatially relative descriptions used in this document should be interpreted accordingly.

[0097]

[0107] In the context of describing the materials and methods discussed in this book (particularly in the context of the claims below), the use of “a” and “an,” “the,” and similar referents should be interpreted as encompassing both singular and plural, unless otherwise indicated in this book or unless the context clearly contradicts this interpretation. Enumerations of numerical ranges in this book are merely intended as abbreviations to refer individually to each specific value within that range, unless otherwise indicated in this book, and each specific value is incorporated in this book as if it were individually listed. All methods described in this book may be performed in any appropriate order, unless otherwise indicated in this book or unless the context clearly contradicts this interpretation. Any and all examples or exemplary language provided in this book (e.g., “such as”) are merely intended to better describe the materials and methods and do not limit their scope unless otherwise specified in the claims. Nothing in this document should be interpreted as indicating that any element not specified in the claims is essential for carrying out the disclosed materials and methods.

[0098]

[0108] Throughout this document, any reference to “one embodiment,” “a particular embodiment,” “one or more embodiments,” or “embodiments” means that the specific features, structures, materials, or properties described in relation to an embodiment are included in at least one embodiment of this disclosure. Therefore, phrases such as “in one or more embodiments,” “a particular embodiment,” “in one embodiment,” or “in an embodiment” appearing in various parts of this document do not necessarily refer to the same embodiment of this disclosure. In one or more embodiments, the specific features, structures, materials, or properties are combined in any and appropriate manner.

[0099]

[0109] While the disclosures in this book are described with reference to specific embodiments, it should be understood that these embodiments are merely illustrative of the principles and applications of the disclosure. Those skilled in the art will see that various modifications and variations can be made to the methods and apparatus of the disclosure without departing from the spirit and scope of the disclosure. Therefore, the disclosure is intended to include modifications and variations that fall within the scope of the appended claims and their equivalents.

Claims

1. A method for selectively depositing polysilicon, A first silicon (Si) layer is deposited on the surface of a semiconductor substrate having at least one feature formed thereon by physical vapor deposition (PVD), wherein the at least one feature has at least one opening with an opening width on its upper surface, at least one side wall, and a bottom, the feature depth of the at least one feature extends from the upper surface to the bottom, and the first silicon (Si) layer is deposited on the upper surface and along the at least one side wall and the bottom. Forming a fluid polymer film on the first silicon (Si) layer within at least one feature, wherein the fluid polymer film is formed on the first silicon (Si) layer on the bottom and has a polymer depth less than or equal to the feature depth. Selectively removing at least a portion of the first silicon (Si) layer from the upper surface and the at least one side wall, and To expose the first silicon (Si) layer on the bottom of the at least one feature, the fluid polymer film is removed. Methods that include...

2. The method according to claim 1, comprising forming the fluid polymer film at a temperature in the range of 30°C to 400°C.

3. The method according to claim 1, wherein forming the fluid polymer film comprises exposing the surface of the semiconductor substrate to one or more monomers.

4. The method according to claim 3, wherein the one or more monomers include a single monomer selected from the group consisting of a methyl group, a methacrylate group, a styrene group, a benzyl alcohol group, a benzyl chloride group, and an aldehyde group.

5. The method according to claim 3, wherein the one or more monomers comprise two monomers, each monomer independently selected from the group consisting of amines having a difunctional group, aldehydes having a difunctional group, ketones having a difunctional group, and alcohols having a difunctional group.

6. The method according to claim 5, wherein the one or more monomers comprise three monomers, two of which independently comprise one or more of the following: an amine having a single functional group, an aldehyde having a single functional group, a ketone having a single functional group, or an alcohol having a single functional group, and at least one of the monomers is independently selected from the group consisting of an amine having a difunctional group, an aldehyde having a difunctional group, a ketone having a difunctional group, and an alcohol having a difunctional group.

7. The method according to claim 1, comprising selectively removing the portion of the first silicon (Si) layer at a temperature in the range of 100°C to 400°C.

8. The method according to claim 7, wherein selectively removing the portion of the first silicon (Si) layer includes exposing the semiconductor substrate surface to a fluorine-based plasma or a chlorine-based plasma.

9. The surface of the semiconductor substrate is heat-treated or hydrogen (H ２ The method according to claim 1, wherein the fluid polymer film is removed by exposure to one or more of the plasma treatments.

10. The method according to claim 9, wherein the fluid polymer film is removed without substantially affecting any material located beneath the fluid polymer film.

11. The method according to claim 1, comprising repeating the steps of forming a fluid polymer film on the first silicon (Si) layer, selectively removing at least a portion of the first silicon (Si) layer from the top surface and the at least one side wall, and removing the fluid polymer film.

12. The method according to claim 1, wherein the feature depth is in the range of about 10 nm to about 300 nm.

13. The method according to claim 1, wherein the polymer depth is in the range of about 1 nm to about 50 nm.

14. A method for selectively depositing polysilicon, A first silicon (Si) layer is deposited on the surface of a semiconductor substrate having at least one feature formed thereon by physical vapor deposition (PVD), wherein the at least one feature has at least one opening with an opening width on its upper surface, at least one side wall, and a bottom, the feature depth of the at least one feature extends from the upper surface to the bottom, and the first silicon (Si) layer is deposited on the upper surface and along the at least one side wall and the bottom. Forming a fluid polymer film on the first silicon (Si) layer within at least one feature, wherein the fluid polymer film is formed on the first silicon (Si) layer on the bottom and has a polymer depth less than or equal to the feature depth. To selectively remove at least a portion of the first silicon (Si) layer from the top surface and the at least one side wall without substantially affecting any material beneath the fluid polymer film, In order to expose the first silicon (Si) layer on the bottom, the fluid polymer film is removed, and On the bottom portion, the first silicon oxide (SiO ｘ To form the layer, the remaining portion of the first silicon (Si) layer is oxidized. Methods that include...

15. The method according to claim 14, wherein forming the fluid polymer film comprises exposing the surface of the semiconductor substrate to one or more monomers.

16. The surface of the semiconductor substrate is heat-treated or hydrogen (H ２ The method according to claim 14, wherein the fluid polymer film is removed by exposure to one or more of the plasma treatments.

17. The method according to claim 16, wherein the fluid polymer film is removed without substantially affecting any material located beneath the fluid polymer film.

18. The method according to claim 14, comprising repeating the steps of forming the fluid polymer film on the first silicon (Si) layer, selectively removing at least a portion of the first silicon (Si) layer from the top surface and the at least one side wall, removing the fluid polymer film, and oxidizing the remaining portion of the first silicon (Si) layer.

19. After removing the fluid polymer film, the first silicon oxide (SiO) is used to fill the feature depth. ｘ The method according to claim 14, further comprising selectively depositing a second silicon (Si) layer on the ) layer.

20. Second silicon oxide (SiO ｘ The method according to claim 19, further comprising oxidizing the second silicon (Si) layer in order to form a layer.

Images