Selective deposition of silicon-containing dielectrics on patterned substrates in specific areas.

Abstract

A method is disclosed for the selective formation of silicon-containing films on various substrates, comprising the use of a precursor containing at least one oxygen atom and at least one silicon-nitrogen bond, and a non-oxidizing plasma.

Description

[Technical Field]

[0001] Cross-reference of related applications This application claims priority to U.S. Provisional Patent Application No. 63 / 527,857, filed on 20 July 2023, the disclosure of which is incorporated herein by reference in its entirety. [Background technology]

[0002] For over half a century, the pursuit of faster and more powerful electronic devices has driven remarkable progress in fabrication methods for creating complex structures at the micron and nanometer scales. However, current nanoelectronics fabrication relies on increasingly sophisticated and costly patterning techniques, which presents significant challenges. For example, variations between fabrication steps can lead to misalignment errors that weaken device performance and reliability, particularly in the back-end-of-line (BEOL) phase of the line. This production phase faces increasing challenges in matching metal lines and vias as device dimensions shrink, leading to short circuits or high resistance. To mitigate this problem, fully self-aligned via (FSAV) fabrication designs have been proposed that do not require a photolithography mask matching process.

[0003] One strategy for achieving FSAV is to introduce topographic height differences in the metal / low dielectric constant (low k) material pattern before depositing the next layer. This approach can be achieved by increasing the spacing between vias and metal lines, either through metal recess etching or area-selective deposition (ASD) of additional dielectric material on the top surface of existing dielectric areas on the substrate. However, metal recessing has several disadvantages, including multiple process steps, poor uniformity, and surface roughness. On the other hand, ASD is preferred due to its precise thickness control and excellent surface uniformity. To minimize the influence on the interconnect dielectric capacitance that determines the RC delay of the device, low k materials such as carbosiloxane (SiOC) or silicon dioxide (SiO2) are desired to create the topography at the BEOL of this FSAV approach. While ASD is a promising strategy for implementing FSAV structures, selective deposition of low-k dielectrics using common deposition techniques such as atomic layer deposition (ALD) or chemical vapor deposition (CVD) presents significant challenges, leading to complex process schemes for the selective deposition of such films.

[0004] Several ASD processes for the selective deposition of oxides on oxides have been reported in the literature, including U.S. Patent Nos. 9,895,715, 10,047,435, 10,460,930, 10,510,529, 9,786,491, 9,786,492, 9,425,038, U.S. Patent Application Publication No. 2022 / 0238323, 11,898,240, WO2022 / 104226, and Yu et al. (Chem. Mater., 33, 902-909 (2021)). In many cases, the reports involve the deposition of high-k dielectrics such as ZnO, Al2O3, ZrO2, or HfO2, which have limited practical applications. Conversely, ASD processes targeting low-k dielectric films such as SiOC or SiO2 are hindered by the harsh conditions typically required to form silicon-based films, such as oxygen plasma or ozone, which degrade self-assembling monolayers or small molecule inhibitors typically used to inhibit growth in off-target areas of the substrate. A few reports have addressed this problem by using water-reactive silicon precursors such as chlorosilane or isocyanatosilane in combination with chemical barriers to passivate non-growing metal surfaces. However, the reaction kinetics of these precursors with water are slow, making the practical implementation of these processes difficult. In addition, the use of chemical barriers requires additional processing steps to deposit and remove the barriers. Furthermore, many semiconductor device layers feature multiple metal surfaces that may require unique barrier chemistry, adding further process complexity to passivation schemes. While specific processes for depositing SiOCN films at suitable temperatures using plasma and reduction of oxygen-containing precursors are known, the growth rates of the disclosed examples are low and decrease with increasing temperature, limiting the range of film compositions and thicknesses that can be prepared by such methods. [Prior art documents] [Patent Documents]

[0005] [Patent Document 1] U.S. Patent No. 9,895,715 [Patent Document 2] U.S. Patent No. 10,047,435 [Patent Document 3] U.S. Patent No. 10,460,930 [Patent Document 4] U.S. Patent No. 10,510,529 [Patent Document 5] U.S. Patent No. 9,786,491 [Patent Document 6] U.S. Patent No. 9,786,492 [Patent Document 7] U.S. Patent No. 9,425,038 [Patent Document 8] U.S. Patent Application Publication No. 2022 / 0238323 [Patent Document 9] U.S. Patent No. 11,898,240 [Patent Document 10] WO2022 / 104226 [Non-patent literature]

[0006] [Non-Patent Document 1] Yu et al., (Chem. Mater., 33, 902-909 (2021)) [Overview of the project] [Problems that the invention aims to solve]

[0007] Therefore, a proprietary process that operates at sufficiently high temperatures for the growth of low-carbon silicon films, which is desirable for many applications, is still required.

[0008] Specifically, what is desirable is a simple process with a minimum number of steps, most preferably only two in each ALD cycle, and with the absence or minimization of blocking, blocking material removal, and post-deposition cleaning or etching steps, in particular, which must be repeated with each ALD cycle or every few cycles. [Means for solving the problem]

[0009] Aspects of the present disclosure are methods for selectively depositing a silicon-containing dielectric layer on a patterned substrate, comprising: (a) introducing the patterned substrate into a reaction zone of a deposition chamber, the patterned substrate comprising at least one metal region and at least one insulated non-metal region, and the temperature of the reaction zone being between about 25 °C and about 500 °C; (b) forming a silicon-containing dielectric layer that only covers at least one non-metal region of the patterned substrate via an atomic layer deposition process or a chemical vapor deposition process, the patterned substrate being exposed to a compound having Formula 1, Formula 2, Formula 3, or Formula 4:

[0010]

Chemical formula

[0011] and the patterned substrate being exposed to a non-oxidizing plasma; relating to a method comprising.

[0012] In Formulas 1 to 4, n and m are each independently an integer from 1 to about 4, and R1, R2, and R3 are each independently hydrogen or a linear, branched, or cyclic, optionally substituted, alkoxy, alkyl, aryl, alkyne, alkene, ether, ester, ketone, alkylamino, dialkylamino, alkyl(alkylamino) or alkyl(dialkylamino) group having from 1 to about 12 carbon atoms, or a linear, branched, or cyclic, optionally substituted, general formula SiR 11 R 12 R 13 、OSiR 11 R 12 R 13 、or R 14 SiR 11 R 12 R 13 (wherein R 11 、R 12 、and R 13Each is independently hydrogen or an alkyl or alkoxy group having about 1 to about 12 carbon atoms (preferably about 1 to about 4 carbon atoms), R 14 R4 is a silyl group having a linear or branched alkyl group having 1 to about 12 carbon atoms (preferably about 1 to 4 carbon atoms), and R4 and R5 are each independently hydrogen, or a linear, branched, or cyclic, optionally substituted alkyl, aryl, alkyne, alkene, ether, ester, ketone, dialkylamino, alkylamino, alkyl(alkylamino) or alkyl(dialkylamino) group having 1 to about 12 carbon atoms, or a linear, branched, or cyclic, optionally substituted group of the general formula SiR 11 R 12 R 13 , or R 14 SiR 11 R 12 R 13 (In the formula, R 11 , R 12 , and R 13 Each is independently hydrogen or an alkyl or alkoxy group having about 1 to about 12 carbon atoms (preferably about 1 to about 4 carbon atoms), R 14 R6, R7, R8, R9 and R 10 Each is independently a hydrogen atom, or a linear, branched, or cyclic, optionally substituted alkoxy, alkyl, aryl, alkyne, alkene, ether, ester, ketone, alkylamino, dialkylamino, alkyl(alkylamino) or alkyl(dialkylamino) group having 1 to about 12 carbon atoms, or a linear, branched, or cyclic, optionally substituted group of the general formula SiR 11 R 12 R 13 OSiR 11 R 12 R 13 , or R 14 SiR11 R 12 R 13 (In the formula, R 11 , R 12 , and R 13 Each is independently hydrogen or an alkyl or alkoxy group having about 1 to about 12 carbon atoms (preferably about 1 to about 4 carbon atoms), R 14 R1 is a silyl group having a linear or branched alkyl group having 1 to about 12 carbon atoms (preferably about 1 to 4 carbon atoms), and at least one of R1, R2 and R3 contains at least one oxygen atom.

[0013] Advantageous improvements to the present invention, which can be implemented individually or in combination, are specified in the dependent claims.

[0014] In summary, the following embodiments are proposed as particularly preferred within the scope of the present invention.

[0015] Embodiment 1: A method for selectively depositing a silicon-containing dielectric layer on a patterned substrate, (a) A step of introducing a patterned substrate into the reaction zone of a deposition chamber, wherein the patterned substrate comprises at least one metallic region and at least one insulated nonmetallic region, and the temperature of the reaction zone is between approximately 25°C and approximately 500°C. (b) A step of forming a silicon-containing dielectric layer that covers only at least one nonmetallic region of a patterned substrate via an atomic layer deposition process or a chemical vapor deposition process, wherein the patterned substrate is a material of formula 1, formula 2, formula 3, or formula 4:

[0016] [ka]

[0017] [wherein n and m are each independently integers from 1 to about 4, and R1, R2, and R3 are each independently hydrogen, or a linear, branched, or cyclic, optionally substituted, alkoxy, alkyl, aryl, alkyne, alkene, ether, ester, ketone, alkylamino, dialkylamino, alkyl(alkylamino) or alkyl(dialkylamino) group having 1 to about 12 carbon atoms, or a linear, branched, or cyclic, optionally substituted, general formula SiR 11 R 12 R 13 OSiR 11 R 12 R 13 , or R 14 SiR 11 R 12 R 13 (In the formula, R 11 , R 12 , and R 13 Each is independently either hydrogen or an alkyl or alkoxy group having about 1 to about 12 carbon atoms, R 14 R4 is a silyl group having a linear or branched alkyl group having 1 to about 12 carbon atoms, and R4 and R5 are each independently hydrogen, or a linear, branched, or cyclic, optionally substituted alkyl, aryl, alkyne, alkene, ether, ester, ketone, alkylamino, dialkylamino, alkyl(alkylamino) or alkyl(dialkylamino) group having 1 to about 12 carbon atoms, or a linear, branched, or cyclic, optionally substituted group of the general formula SiR 11 R 12 R 13 Or R 14 SiR 11 R 12 R 13 (In the formula, R 11 , R 12 , and R 13 Each is independently either hydrogen or an alkyl or alkoxy group having about 1 to about 12 carbon atoms, R 14R6, R7, R8, R9 and R 10 Each is independently a hydrogen atom, or a linear, branched, or cyclic, optionally substituted alkoxy, alkyl, aryl, alkyne, alkene, ether, ester, ketone, alkylamino, dialkylamino, alkyl(alkylamino) or alkyl(dialkylamino) group having 1 to about 12 carbon atoms, or a linear, branched, or cyclic, optionally substituted group of the general formula SiR 11 R 12 R 13 OSiR 11 R 12 R 13 , or R 14 SiR 11 R 12 R 13 (In the formula, R 11 , R 12 , and R 13 Each is independently either hydrogen or an alkyl or alkoxy group having about 1 to about 12 carbon atoms, R 14 R1 is a silyl group having a linear or branched alkyl group having 1 to about 12 carbon atoms, and at least one of R1, R2, and R3 contains at least one oxygen atom. The process involves exposing the patterned substrate to a compound containing and then to a non-oxidizing plasma. Methods that include...

[0018] Embodiment 2: A method according to Embodiment 1, wherein a patterned substrate is simultaneously exposed to a compound having formula 1, formula 2, formula 3, or formula 4 and to a non-oxidizing plasma.

[0019] Embodiment 3: A method according to Embodiment 1, wherein a patterned substrate is sequentially exposed to a compound having formula 1, formula 2, formula 3, or formula 4, and to a non-oxidizing plasma.

[0020] Embodiment 4: A method according to any one of Embodiments 1 to 3, further comprising the step of performing annealing, cleaning, etching, or plasma treatment on a patterned substrate prior to step (b).

[0021] Embodiment 5: A method according to any one of Embodiments 1 to 4, further comprising the step of exposing the patterned substrate to a chemical barrier for selectively passivating at least one region of the substrate, prior to step (b).

[0022] Embodiment 6: A method according to any one of Embodiments 1 to 5, wherein the source gas for the non-oxidizing plasma comprises hydrogen, nitrogen, ammonia, or hydrazine.

[0023] Embodiment 7: A method according to any of Embodiments 1 to 6, wherein the source gas for the non-oxidizing plasma contains less than about 1 volume percent of oxygen, hydrogen peroxide, carbon dioxide, water, or nitrous oxide.

[0024] Embodiment 8: The compound of Formula 1, Formula 2, Formula 3, or Formula 4 is N-ethyl-2,2-dimethoxy-4-methyl-1-aza-2-silacyclopentane, Nn-butyl-aza-2,2-dimethoxysilacyclopentane, Nt-butyl-aza-2,2-dimethoxysilacyclopentane, N-methyl-aza-2,2-dimethoxysilacyclopentane, 2,2-dimethoxy-1,3-dimethyl-1,3-diaza-2-silacyclopentane, 2,2-diethoxy-1,3-dimethyl-1,3- Diaza-2-silacyclopentane, (1-(3-triethoxysilyl)propyl)-2,2-diethoxy-1-aza-2-silacyclopentane, N-allyl-aza-2,2-dimethoxysilacyclopentane, 2,2-dimethoxy-1,6-diaza-2-silacyclooctane, aza-2-methyl-2-methoxysilacyclopentane, N-methyl-2-methyl-2-methoxy-4-methyl-1-aza-2-silacyclopentane, (dimethylamino)trimethoxysilane, (die Tris(dimethylamino)trimethoxysilane, (diethylamino)triethoxysilane, (dimethylamino)triethoxysilane, (diisopropoxyamino)trimethoxysilane, or (diisopropoxyamino)triethoxysilane, bis(dimethylamino)dimethoxysilane, bis(dimethylamino)diethoxysilane, tris(dimethylamino)methoxysilane, tris(dimethylamino)ethoxysilane, 3-[(dimethylamino)dimethylsilyl]propyl 2-methyl- A method according to any of Embodiments 1 to 7, wherein the compound is 2-propenoate, 2-(ethoxymethyl)-1-(trimethylsilyl)-1-aza-2-silacyclopentane, 1-(3-methoxypropyl)-N,N,1,1-tetramethylsilanamine, or N-methyl-2,2-dimethoxy-4-trimethylsilyl-1-aza-2-silacyclopentane, or 2-methoxy-1-(trimethylsilyl)-2-[(trimethylsilyl)oxy]-1-aza-2-silacyclopentane.

[0025] Embodiment 9: A method according to any of Embodiments 1 to 8, wherein the silicon-containing dielectric layer has a thickness of about 1 nm to about 20 nm.

[0026] Embodiment 10: A method according to Embodiment 9, wherein the silicon-containing dielectric layer has a thickness of about 3 nm to about 10 nm.

[0027] Embodiment 11: A method according to any of Embodiments 1 to 10, wherein the temperature of the reaction chamber is approximately 275°C to approximately 425°C.

[0028] Embodiment 12: A method according to any one of Embodiments 1 to 11, wherein the patterned substrate comprises silicon dioxide, silicon oxycarbide, silicon oxynitride, silicon carboxynitride, silicon oxyfluoride, or a borosilicate.

[0029] Embodiment 13: A method according to any one of Embodiments 1 to 12, wherein the silicon-containing dielectric layer has a film thickness of less than about 1 nm in at least one area of ​​a patterned substrate containing copper, cobalt, ruthenium, molybdenum, tungsten, and / or gold.

[0030] Embodiment 14: A method according to any of Embodiments 1 to 13 for forming a silicon-containing dielectric layer using an atomic layer deposition process.

[0031] Embodiment 15: The atomic layer deposition process is (b1) A step of exposing a patterned substrate to a pulse of a compound of formula 1, formula 2, formula 3, or formula 4, (b2) A process of purging the deposition chamber, (b3) A step of exposing the patterned substrate to a non-oxidizing plasma, (b4) A process of purging the deposition chamber, (b5) A process of repeating steps (b1) to (b4) until the desired layer thickness is reached. A method according to Embodiment 14, including the following:

[0032] Embodiment 16: Before step (b1), the following steps: (b0.1) A process of performing annealing, cleaning, etching, or plasma treatment on a patterned substrate. (b0.2) A step of exposing the patterned substrate to an oxidizing agent, and (b0.3) A step of exposing the patterned substrate to a chemical barrier to selectively passivate at least one region of the substrate. A method according to embodiment 15, further comprising performing at least one of the following.

[0033] Embodiment 17: After step (b4), (b4.1) A step of exposing the patterned substrate to pulses of an oxidizing agent, (b4.2) The process of purging the deposition chamber and A method according to Embodiment 15, further including the following.

[0034] Embodiment 18: The method of Embodiment 17, wherein the oxidizing agent is selected from water, carbon dioxide, nitrous oxide, oxygen, ozone, hydrogen peroxide, alcohol, mixtures thereof, and plasma thereof.

[0035] Embodiment 19: After step (b5), the following steps (b5.1) to (b5.3): (b5.1) A process of performing annealing, cleaning, etching, or plasma treatment on a patterned substrate. (b5.2) Step of exposing the patterned substrate to an oxidizing agent, (b5.3) A step of exposing a patterned substrate to a chemical barrier to selectively passivate at least one region of the substrate. To implement at least one of the following, and then, (b5.4) Depending on the circumstances, a step of purging the reaction chamber, (b6) A process that repeats steps (b1) to (b5) at least once. A method according to Embodiment 15, further including the following.

[0036] Embodiment 20: A method according to any of Embodiments 14 to 19, wherein a pulse of the compound of Formula 1, Formula 2, Formula 3, or Formula 4 has a duration of about 0.05 seconds to about 30 seconds.

[0037] Embodiment 21: A method according to Embodiment 20, wherein a pulse of the compound of Formula 1, Formula 2, Formula 3, or Formula 4 has a duration of about 5 to about 10 seconds.

[0038] Embodiment 22: A method according to any of Embodiments 14 to 21, wherein a patterned substrate is exposed to a non-oxidizing plasma for a period of about 1 second to about 60 seconds.

[0039] Embodiment 23: A method according to Embodiment 22, wherein the patterned substrate is exposed to a non-oxidizing plasma for about 10 to about 20 seconds.

[0040] Embodiment 24: A method according to any of Embodiments 1 to 13, wherein a silicon-containing dielectric layer is formed using a chemical deposition process or a pulsed chemical deposition process.

[0041] Embodiment 25: A chemical deposition or pulsed chemical deposition process, (b7) A step of exposing the patterned substrate to a compound of formula 1, formula 2, formula 3, or formula 4 while simultaneously exposing the patterned substrate to a non-oxidizing plasma until a desired layer thickness is reached, (b8) Depending on the circumstances, the process of purging the deposition chamber, (b9) Repeat steps (b7) and (b8) until a second desired layer thickness is reached. A method according to Embodiment 24, including the following:

[0042] Embodiment 26: After step (b8), the following steps: (b8.1) A process of performing annealing, cleaning, etching, or plasma treatment on a patterned substrate. (b8.2) Step of exposing the patterned substrate to an oxidizing agent, (b8.3) A step of exposing a patterned substrate to a chemical barrier to selectively passivate at least one region of the substrate. To implement at least one of the following, and then, (b8.4) A step to purge the reaction chamber, if applicable. A method according to embodiment 25, further including the following.

[0043] Embodiment 27: Before step (b7), the following steps: (b0.l) A process of performing annealing, cleaning, etching, or plasma treatment on a patterned substrate. (b0.2) A step of exposing the patterned substrate to an oxidizing agent, (b0.3) A step of exposing the patterned substrate to a chemical barrier to selectively passivate at least one region of the substrate. A method according to embodiment 25 or 26, further comprising carrying out at least one of the following.

[0044] The following detailed description of preferred embodiments of the present invention will be better understood in conjunction with the accompanying drawings. For the purpose of illustrating the present invention, currently preferred embodiments are shown in the drawings. However, it should be understood that the present invention is not limited to the exact arrangements and means shown. [Brief explanation of the drawing]

[0045] [Figure 1] These are graphs of in-situ polarization analysis for the films prepared in Example 1, Comparative Example 1, and Comparative Example 2. [Figure 2] This figure shows the X-ray photoelectron spectroscopy (XPS) data of the silicon 2s peak for the films prepared in Example 1, Example 2, and Example 3. [Figure 3] This figure shows the XPS depth profile data for the film of Comparative Example 3. [Figure 4] This figure shows the XPS depth profile data for the film of Comparative Example 4. [Figure 5] This figure shows the XPS depth profile data for the film of Example 5. [Figure 6] This graph shows the growth rate of the precursors of the present invention and comparative precursors. [Modes for carrying out the invention]

[0046] Aspects of this disclosure relate to the use of atomic layer deposition (ALD) or chemical vapor deposition (CVD) processes for selectively depositing silicon-based dielectric layers on dielectric regions of patterned substrates. Specifically, described herein are processes for selective intrinsic deposition of silicon-based dielectrics on the same or other silicon-based or metallic dielectrics, utilizing a silicon-based precursor containing both an oxygen-containing ligand and silicon-bound nitrogen in combination with a non-oxidizing plasma.

[0047] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art in which the present invention pertains. Otherwise, certain terms used herein have the meaning as explicitly stated herein. All patents, published patent applications and publications cited herein are incorporated by reference as if they were fully explicitly stated herein.

[0048] It should be noted that, as used herein and in the appended claims, the singular forms "a," "an," and "the" refer to multiple references unless the context clearly indicates otherwise.

[0049] Unless otherwise stated, all numerical values ​​should be understood to be modified by the term “approximately” in all cases. Therefore, numerical values ​​typically include ±10% of the listed value. For example, a list of temperatures such as “10°C” includes 9°C and 11°C. When used in a specification, the use of a numerical range explicitly includes all individual numerical values ​​within that range, including all conceivable subranges, integers and fractions of values ​​within such ranges, unless the context clearly indicates otherwise.

[0050] For the purposes of this disclosure, with respect to a silicon-containing dielectric layer that overlaps only one nonmetallic region of a patterned substrate, the term “overlying” may be understood to be synonymous with “covering” or “on top of,” that is, the silicon-containing dielectric layer overlaps / covers / is positioned on at least one nonmetallic region of the patterned substrate without overlapping / covering / positioning on at least one metallic region of the patterned substrate. The terms “insulated” and “isolated” are synonymous. The terms “overlying” and its synonyms may be understood to mean directly or indirectly, that is, with or without at least one layer between them. With respect to the formation of the silicon-containing dielectric layer, the terms “on top of” and “on top of” are synonymous.

[0051] In one embodiment, the present disclosure is a method for selectively depositing a silicon-containing dielectric layer on a patterned substrate, (a) A step of introducing a patterned substrate into the reaction zone of a deposition chamber, wherein the patterned substrate comprises at least one metallic region and at least one insulated nonmetallic region, and the temperature of the reaction zone is between approximately 25°C and approximately 500°C. (b) A step of forming a silicon-containing dielectric layer that covers only at least one nonmetallic region of a patterned substrate via an atomic layer deposition process or a chemical vapor deposition process, wherein the patterned substrate is a material of formula 1, formula 2, formula 3, or formula 4:

[0052] [ka]

[0053] The process involves exposing the patterned substrate to a compound containing and then to a non-oxidizing plasma. This includes methods.

[0054] As described in more detail below, in Formulas 1 to 4, n and m are each independently an integer from 1 to about 4, and R1, R2, and R3 are each independently hydrogen or a linear, branched, or cyclic, optionally substituted, alkoxy, alkyl, aryl, alkyne, alkene, ether, ester, ketone, alkylamino, dialkylamino, alkyl(alkylamino) or alkyl(dialkylamino) group having from 1 to about 12 carbon atoms, or a linear, branched, or cyclic, optionally substituted, general formula SiR 11 R 12 R 13 、OSiR 11 R 12 R 13 、or R 14 SiR 11 R<000\089>R 13 (wherein R 11 、R 12 、and R<000009\3> are each independently hydrogen or an alkyl or alkoxy group having from about 1 to about 12 carbon atoms (preferably from about 1 to about 4 carbon atoms), and R 14 is a linear or branched alkyl group having from 1 to about 12 carbon atoms (preferably from about 1 to 4 carbon atoms)) is a silyl group, and R4 and R5 are each independently hydrogen or a linear, branched, or cyclic, optionally substituted, alkyl, aryl, alkyne, alkene, ether, ester, ketone, alkylamino, dialkylamino, alkyl(alkylamino) or alkyl(dialkylamino) group having from 1 to about 12 carbon atoms, or a linear, branched, or cyclic, optionally substituted, general formula SiR 11 R 12 R 13 or R 14 SiR[[ID=…]] 11 R 12 R 13 (wherein R 11 、R 12 、and R 13Each is independently hydrogen or an alkyl or alkoxy group having about 1 to about 12 carbon atoms (preferably about 1 to about 4 carbon atoms), R 14 R6, R7, R8, R9 and R 10 Each is independently a hydrogen atom, or a linear, branched, or cyclic, optionally substituted alkoxy, alkyl, aryl, alkyne, alkene, ether, ester, ketone, alkylamino, dialkylamino, alkyl(alkylamino), or alkyl(dialkylamino) group having 1 to about 12 carbon atoms, or a linear, branched, or cyclic, optionally substituted group of the general formula SiR 11 R 12 R 13 OSiR 11 R 12 R 13 , or R 14 SiR 11 R 12 R 13 (In the formula, R 11 , R 12 , and R 13 Each is independently hydrogen or an alkyl or alkoxy group having about 1 to about 12 carbon atoms (preferably about 1 to about 4 carbon atoms), R 14 R1 is a silyl group having a linear or branched alkyl group having 1 to about 12 carbon atoms (preferably about 1 to 4 carbon atoms), and at least one of R1, R2, and R3 contains at least one oxygen atom. Notably, each compound having formula 1, 2, 3, or 4 has a silicon-nitrogen bond, and there are no hydrocarbons or other spacer or linker groups between silicon and nitrogen.

[0055] In one embodiment, the present disclosure specifically relates to a method for selectively depositing a dielectric layer on an existing nonmetallic layer of a patterned substrate using an atomic layer deposition process, (a) A step of introducing a patterned substrate into the reaction zone of a deposition chamber, wherein the patterned substrate comprises at least one metallic region and at least one insulated nonmetallic region, and the temperature of the reaction zone is between approximately 25°C and approximately 500°C. (b0.l) Depending on the case, a step of performing annealing, cleaning, etching, or plasma treatment on the patterned substrate, (b0.2) Depending on the case, a step of exposing the patterned substrate to an oxidizing agent, (b0.3) Depending on the case, the patterned substrate is exposed to a chemical barrier that selectively passivates at least one region of the substrate, (b1) A step of exposing a patterned substrate to a pulse of a compound having formula 1, formula 2, formula 3, or formula 4, (b2) A process of purging the deposition chamber, (b3) A step of exposing the patterned substrate to a non-oxidizing plasma, (b4) A process of purging the deposition chamber, (b4.1) Depending on the case, a step of exposing the patterned substrate to an oxidizing agent, (b4.2) Depending on the circumstances, the process of purging the deposition chamber, (b5) A process of repeating steps (b1) to (b4.2) until the desired film thickness is reached, (b5.1) Depending on the case, a step of performing annealing, cleaning, etching, or plasma treatment on the patterned substrate, (b5.2) Depending on the case, a step of exposing the patterned substrate to an oxidizing agent, (b5.3) Depending on the case, the step of exposing the patterned substrate to a chemical barrier for selectively passivating at least one region (regio) of the substrate, (b5.4) Depending on the circumstances, a step of purging the reaction chamber, (b.6) Depending on the case, the process of repeating steps (b1) to (b5.4) until the desired thickness of the silicon-containing dielectric layer is reached. The present invention relates to a method including the silicon-containing dielectric layer covering only at least one non-metallic region of the patterned substrate.

[0056] Each of these steps is described in more detail below. In this method, steps (a) to (b0.3) represent pre-deposition surface preparation, steps (b1) to (b5) represent the ALD deposition process, and steps (b5.1) to (b6) represent the supercycle ALD process, which periodically includes additional surface cleaning or modification processes to enhance selectivity by re-establishing suitable growing and non-growing surfaces or removing undesirable growth on non-growing surfaces, or to modify the properties of the interface between the growing film or its adjacent layers.

[0057] [ka]

[0058] In formulas 1 to 4, n and m are each independently integers from 1 to about 4, and R1, R2, and R3 are each independently hydrogen, or a linear, branched, or cyclic, optionally substituted alkoxy, alkyl, aryl, alkyne, alkene, ether, ester, ketone, alkylamino, dialkylamino, alkyl(alkylamino) or alkyl(dialkylamino) group having 1 to about 12 carbon atoms (preferably about 1 to about 4 carbon atoms), or a linear, branched, or cyclic, optionally substituted general formula SiR 11 R 12 R 13 OSiR 11 R 12 R 13 , or R 14 SiR 11 R 12 R 13 (In the formula, R 11 , R 12 , and R 13 Each is independently hydrogen or an alkyl or alkoxy group having about 1 to about 12 carbon atoms (preferably about 1 to about 4 carbon atoms), R 14R4 is a silyl group having a linear or branched alkyl group having 1 to about 12 carbon atoms (preferably about 1 to about 4 carbon atoms), and R4 and R5 are each independently hydrogen, or a linear, branched, or cyclic, optionally substituted alkyl, aryl, alkyne, alkene, ether, ester, ketone, alkylamino, dialkylamino, alkyl(alkylamino) or alkyl(dialkylamino) group having 1 to about 12 carbon atoms (preferably about 1 to about 4 carbon atoms), or a linear, branched, or cyclic, optionally substituted group of the general formula SiR 11 R 12 R 13 Or R 14 SiR 11 R 12 R 13 (In the formula, R 11 , R 12 , and R 13 Each is independently either hydrogen or an alkyl or alkoxy group having about 1 to about 12 carbon atoms (preferably about 1 to about 4 carbon atoms), R 14 R6, R7, R8, R9 and R 10 Each is independently a hydrogen atom, or a linear, branched, or cyclic, optionally substituted alkoxy, alkyl, aryl, alkyne, alkene, ether, ester, ketone, alkylamino, dialkylamino, alkyl(alkylamino) or alkyl(dialkylamino) group having 1 to about 12 carbon atoms (preferably about 1 to about 4 carbon atoms), or a linear, branched, or cyclic, optionally substituted group of the general formula SiR 11 R 12 R 13 OSiR 11 R 12 R 13 , or R 14 SiR 11 R 12 R 13 (In the formula, R11 , R 12 , and R 13 Each is independently hydrogen or an alkyl or alkoxy group having about 1 to about 12 carbon atoms (preferably about 1 to about 4 carbon atoms), R 14 R1 is a silyl group having a linear or branched alkyl group having 1 to about 12 carbon atoms (preferably about 1 to 4 carbon atoms), and at least one of R1, R2, and R3 contains at least one oxygen atom. Preferably, at least one of R1, R2, and R3 is an alkoxy group. If substituted, any of the R groups may be substituted with any known substituents, not limited to halogens, aminos, alkylaminos, dialkylaminos, alkyl(alkylaminos), and alkyl(dialkylaminos), and silyl groups, as described above, and each of these may be optionally substituted.

[0059] In a preferred embodiment, n and m are each 1, R1, R2, and R3 are alkyl, alkoxy, ester, ether, or dialkylamino groups, R4 is alkyl, alkenyl, alkyl (dialkylamino), or silyl, R5 is hydrogen or alkyl, R6, R7, and R8 are hydrogen or alkyl, and R9 and R 10 It is hydrogen.

[0060] A method according to this disclosure comprises the steps of introducing a patterned substrate into a reaction zone of a deposition chamber, wherein the patterned substrate comprises at least one metallic region and at least one insulated nonmetallic region, and the temperature of the reaction zone is between about 25°C and about 500°C; and exposing the patterned substrate to a series of steps repeated as many times as necessary to achieve a desired film thickness: exposing the patterned substrate to pulses of a compound having formula 1, formula 2, formula 3, or formula 4; purging the deposition chamber; exposing the patterned substrate to a non-oxidizing plasma; and purging the deposition chamber. The resulting silicon-based dielectric layer is selectively formed on nonmetallic regions or areas of the patterned substrate such that it covers only the nonmetallic regions of the patterned substrate. For the purposes of this disclosure, the terms “layer” and “film” may be understood to be synonymous.

[0061] Various different types of patterned substrates are suitable for use in the methods described herein, provided that they contain both nonmetallic and metallic regions. The term “patterned substrate” should be understood to refer to a substrate having at least two insulated or separated surface regions of different materials. Suitable nonmetallic substrate regions include, but are not limited to, currently preferred silicon dioxide, silicon oxycarbide, silicon oxynitride, silicon carboxynitride, silicon oxyfluoride, and borosilicates. Other possible substrates that would be suitable include, but are not limited to, substrates containing nonmetallic regions of silicon, germanium, silicon-germanium alloys, silicon nitride, titanium nitride, tantalum nitride, aluminum oxide, hafnium dioxide, titanium dioxide, and / or zinc oxide. Suitable metallic substrate regions include, but are not limited to, currently preferred copper and cobalt, as well as tungsten, ruthenium, gold, and / or molybdenum.

[0062] The term “substrate,” as used herein, is used to describe the material surface on which film processing is carried out during the manufacturing process. For example, a substrate may include, depending on the application, a bulk layer of silicon, silicon dioxide, silicon-on-insulator, strained silicon, doped silicon, germanium, gallium arsenide, silicon carbide, glass, alumina, metal, or metal nitride. In addition to the bulk layer, the substrate may include multiple layers of patterned thin films that form the device. The outermost exposed surface includes the substrate, which, according to the present invention, must include at least one non-metallic grown surface and at least one metallic non-grown surface.

[0063] In the first step, the reaction zone of the deposition chamber, including the boundary, is heated or cooled to about 25°C to about 500°C, including all temperatures within this range. The reaction zone may be heated before or after the introduction of the substrate into the reaction chamber. The preferred temperature for the reaction zone is about 275°C to about 425°C, including all intervening temperatures, such as about 275°C, about 300°C, about 325°C, about 350°C, about 375°C, about 400°C, and about 425°C.

[0064] The parameters of the purge cycle are not particularly limited and may be optimized based on the specific reaction conditions, apparatus, and reactants. Generally, any inert gas such as argon or nitrogen may be used, and a typical purge cycle is at least about 2 seconds long. In a preferred embodiment, the purge is about 10 seconds long.

[0065] The temperature of the reaction zones in the substrate and deposition chamber is important for generating the desired silicon-based dielectric layer on the patterned substrate. Specifically, the temperature of the reaction zones in the substrate and deposition chamber is preferably about 25°C to about 500°C, more preferably about 275°C to about 425°C, during exposure to pulses of a compound having formula 1, 2, 3, or 4 and any choice of water as described below. The substrate temperature range includes all temperatures within the range, and therefore the temperature range of about 275°C to about 425°C includes about 300°C, about 325°C, about 350°C, about 375°C, and about 400°C, and, without limitation, about 275°C, about 280°C, about 285°C, about 290°C, about 295°C, about 300°C, about 305°C, about 310°C, about 315°C, about 320°C, about 325°C, about It can be understood that this includes temperatures such as 330°C, approximately 335°C, approximately 340°C, approximately 345°C, approximately 350°C, approximately 355°C, approximately 360°C, approximately 365°C, approximately 370°C, approximately 375°C, approximately 380°C, approximately 385°C, approximately 390°C, approximately 395°C, approximately 400°C, approximately 405°C, approximately 410°C, approximately 415°C, approximately 420°C, and approximately 425°C, as well as all intervening temperatures.

[0066] It is within the scope of this disclosure that the temperatures of the reaction zones of the substrate and the deposition chamber may be the same or different. That is, the substrate chuck or platen can be heated independently of the chamber, and these temperatures may be controlled independently by the deposition tool. The substrate temperature can be raised higher than that of the main part of the chamber, although the difference is typically small (about 10°C to about 30°C). Thus, the ranges described above are applicable to both the substrate and the reaction zones. In ALD, it is understood in the art that these are effectively the same as the desired reaction occurring on the substrate surface. However, in CVD, the reaction occurs both in the gas phase within the main chamber space and on the substrate surface. In that case, a temperature difference between the gas phase reaction and the surface reaction can be introduced.

[0067] The pulse length for each reactant may be optimized based on specific reaction conditions and apparatus, and is generally kept as short as practically feasible. The pulse length for compounds having formulas 1, 2, 3, or 4 is about 0.05 to about 30 seconds, preferably 2 to about 15 seconds, more preferably at least about 3 seconds and more preferably about 5 to about 10 seconds. The pulse length for an optional water pulse is about 2 to about 15 seconds, preferably about 5 to about 10 seconds. Longer pulse times may be effective for all compounds, but they are not practical in terms of material consumption or tool utilization.

[0068] In some cases, it is within the scope of this disclosure to perform annealing, cleaning, etching, or plasma treatment of the patterned substrate before exposing it to a compound having formula 1, 2, 3, or 4. For example, the substrate may be washed with ethanol for 5 minutes before being placed in a deposition chamber at a desired deposition temperature, and then treated with nitrogen plasma for about 1 minute over 60 seconds at a power of 2500 W via a remote ICP before the start of the deposition process. Other examples of wet pretreatment protocols that may be appropriate depending on the properties of the grown and ungrown surfaces of the patterned substrate include, but are not limited to, cleaning or etching solutions using organic solvents such as isopropanol or tetrahydrofuran, organic acids such as citric acid or acetic acid, mineral acids such as hydrogen fluoride, hydrogen chloride, or sulfuric acid, bases such as ammonia, or oxidizing agents such as hydrogen peroxide, either alone, in mixtures, or in sequential combinations, as is well known in the art. Dry processes that may be used as pretreatment include an annealing step in the same or different chambers, which may include any of the following: reducing or oxidizing conditions, reactive ion etching, or plasma treatment. Depending on the specific area of ​​the patterned substrate, it may be understood that more than one pretreatment may be applied to the same patterned substrate. Other similar substrate pretreatment processes known in the art may also be applicable. Such treatments may improve the selectivity of the process of the present invention or the performance of the resulting film, but the appropriate pretreatment method and conditions may be determined on a case-by-case basis depending on the specific substrate, apparatus, reactants, and reaction conditions.

[0069] In some cases, before exposing the patterned substrate to pulses of a compound having formula 1, 2, 3, or 4, the patterned substrate is exposed to a chemical barrier that selectively passivates one or more regions of the substrate. If such an optional step is performed, the chemical barrier can be removed once the desired dielectric film thickness is achieved. Possible inhibitor compounds include, but are not limited to, polymers, N-heterocyclic carbenes, silanes, or organic or organosilantiols, amines, aldehydes, ketones, phenols, and phosphonic acids, which can be removed by dry processes, not limited to plasma etching, reactive ion etching, corona treatment, ozonolysis, UV / ozone, thermal decomposition, or thermal desorption, or by wet etching processes using formulations containing organic solvents, acids, bases, or hydrogen peroxide.

[0070] For the purposes of this disclosure, the phrase “non-oxidizing plasma” may be understood to mean plasma generated using a gas mixture containing no more than 1 volume percent of oxygen-containing species, excluding the silicon precursor. Examples of such oxygen-containing species that may be intentionally or unintentionally added to the plasma stream include oxygen, water, carbon dioxide, or nitrous oxide, preferably in amounts of less than about 1 volume percent. In preferred embodiments, the plasma contains hydrogen, nitrogen, ammonia, or hydrazine together with argon as a carrier gas, delivered by a remotely inductively coupled plasma (ICP) system. However, the use of other forms of plasma generation, such as capacitively coupled plasma or hollow cathode plasma, is within the scope of this disclosure. Most preferably, the plasma contains nitrogen together with argon as a carrier gas.

[0071] Exposure of a patterned substrate to a non-oxidizing plasma may occur sequentially or simultaneously with respect to exposure to a silicon-containing compound of formula 1, 2, 3, or 4. In the case of alternating exposure of silicon compounds and plasma, commonly referred to as plasma-assisted atomic layer deposition (PEALD), the duration of plasma exposure is preferably about 1 to 60 seconds, most preferably about 10 to 20 seconds. Additional or extended pulses of plasma may be added before the deposition process to clean or otherwise prepare the surface, or after the deposition process to clean or otherwise prepare the surface for subsequent processes in the manufacture of a desired semiconductor device. Within the scope of this disclosure, the term “pulse” may be understood to include both temporal and spatial methods of sequentially exposing a patterned substrate to a chemical compound of formula 1, 2, 3, or 4 and a non-oxidizing plasma. Examples of suitable methods for pulsed chemical compounds of the present invention according to Equations 1, 2, 3, and 4 include, but are not limited to, an open vacuum system in which a precursor vessel, a reaction chamber, and a pumping system are connected throughout the entire pulse; a closed vacuum system in which the pumping system is isolated from the reaction chamber for part or all of the duration of the pulse, thereby inducing the residence time of the chemical precursor in the reaction chamber; or a system that creates exposure to the chemical compounds of Equation 1, 2, 3, or 4 by physically moving a patterned substrate from a region of space in which the chemical compounds are present to an area in which they are not present, commonly referred to as a “spatial ALD”. It should also be understood that pulses of non-oxidizing plasma can be implemented either by temporal or spatial methods.

[0072] In the case of simultaneous exposure of a substrate to a precursor and plasma, generally referred to as plasma-assisted chemical deposition (PECVD), the duration of the process is determined by the process growth rate and the desired thickness of the deposited film under the specific conditions being used. It can be understood that PECVD processes involving both simultaneous initiation and termination of plasma and precursor introduction, as well as cases where one starts before or terminates after the other, are within the scope of this disclosure. In addition, PECVD processes within the scope of this disclosure may consist of a series of shorter exposures, referred to as "pulsed PECVD," which are divided into single exposures to the precursor and plasma, or by purging the reaction zone of the patterned substrate with an inert gas, or by cleaning, etching, annealing, or additional plasma treatment.

[0073] The duration of plasma exposure is preferably about 1 to about 300 seconds per nanometer of film growth, more preferably about 5 to about 100 seconds. Unlike ALD, where film thickness is controlled by the number of repeated cycles, in CVD, thickness is controlled by time, and therefore, it is well understood in the art that "per nanometer of film growth" is important in the CVD process. Since CVD is generally a linear process, the film thickness can be doubled by doubling the process length.

[0074] In some embodiments, after exposure to a non-oxidizing plasma and purging, the patterned substrate is exposed to an oxidizing agent pulse, followed by a purging step as previously described. For the purposes of this disclosure, the term “oxidizing agent” may be understood to include water, carbon dioxide, nitrous oxide, oxygen, ozone, hydrogen peroxide, alcohols, mixtures thereof, and plasmas thereof. Although not limited by theory, the optional addition of an oxidizing agent pulse between the pulse of the non-oxidizing plasma and the pulse of the chemical compound of Formula 1, Formula 2, Formula 3, or Formula 4 can increase the concentration of hydroxide groups on the surface of the deposited dielectric film, thereby causing greater adsorption of the chemical compound of Formula 1, Formula 2, Formula 3, or Formula 4 during the duration of the subsequent pulse. The pulse length of the optional oxidizing agent pulse is about 0.5 to about 15 seconds, preferably about 5 to about 10 seconds.

[0075] In some embodiments, after a number of Formula 1, 2, 3, or 4 compound exposure / purging / non-oxidizing plasma exposure / purging sequences (optionally including oxidizing agent exposure / purging steps) (approximately 1 to 50 sequences, etc.) have been completed, the substrate is subjected to annealing, cleaning, etching, or plasma treatment as described above, and optional exposure to chemical barriers as described above.

[0076] The preparation of silicon-containing dielectric films having thicknesses of approximately 1 to 20 nm, particularly approximately 3 nm to 10 nm, is within the scope of this disclosure, and these thicknesses are currently desirable in the microelectronics industry. The desired film or layer thickness can be achieved by repeatedly repeating the method steps described herein.

[0077] Transferring the chemical compounds of Formulas 1, 2, 3, and 4 into a carrier gas is further within the scope of this disclosure. Suitable, but not limited to, any noble gas such as argon, or an inert gas such as nitrogen, would be appropriate. However, omitting the use of a carrier gas is also within the scope of this disclosure. Diluting a reactive plasma gas such as nitrogen, hydrogen, ammonia, or hydrazine with a carrier gas such as argon or helium is also within the scope of this disclosure.

[0078] Compounds having formulas 1, 2, 3, and 4 are silicon compounds containing at least one silicon-nitrogen (Si-N) bond that provides the rapid surface reactivity required for ALD processes, and at least one oxygen-containing ligand bonded to a silicon atom, such as a currently preferred alkoxy group that acts as an oxygen source. Exemplary compounds, though not limited to those described, include mixed alkoxy-aminosilanes or cyclic azasilanes or diazasilanes having at least one alkoxy group bonded to silicon.

[0079] Specific examples of silicon compounds within the scope of this disclosure include N-ethyl-2,2-dimethoxy-4-methyl-1-aza-2-silacyclopentane, Nn-butyl-aza-2,2-dimethoxysilacyclopentane, Nt-butyl-aza-2,2-dimethoxysilacyclopentane, N-methyl-aza-2,2-dimethoxysilacyclopentane, 2,2-dimethoxy-1,3-dimethyl-1,3-diaza-2-silacyclopentane, and 2,2-diethoxy-1,3-dimethyl-1,3-dia Za-2-silacyclopentane, (1-(3-triethoxysilyl)propyl)-2,2-diethoxy-1-aza-2-silacyclopentane, N-allyl-aza-2,2-dimethoxysilacyclopentane, 2,2-dimethoxy-1,6-diaza-2-silacyclooctane, aza-2-methyl-2-methoxysilacyclopentane, N-methyl-2-methyl-2-methoxy-4-methyl-1-aza-2-silacyclopentane, (dimethylamino)trimethoxysilane, (die (Diethylamino)trimethoxysilane, (Diethylamino)triethoxysilane, (Dimethylamino)triethoxysilane, (Diisopropoxyamino)trimethoxysilane, or (Diisopropoxyamino)triethoxysilane, bis(dimethylamino)dimethoxysilane, bis(dimethylamino)diethoxysilane, tris(dimethylamino)methoxysilane, tris(dimethylamino)ethoxysilane, 3-[(dimethylamino)dimethylsilyl]propyl2-methyl The chemical structures of the following compounds are included: ru-2-propenoate, 2-(ethoxymethyl)-1-(trimethylsilyl)-1-aza-2-silacyclopentane, 1-(3-methoxypropyl)-N,N,1,1-tetramethylsilanamine, or N-methyl-2,2-dimethoxy-4-trimethylsilyl-1-aza-2-silacyclopentane, or 2-methoxy-1-(trimethylsilyl)-2-[(trimethylsilyl)oxy]-1-aza-2-silacyclopentane.

[0080] [ka]

[0081] Silicon compounds according to this disclosure are preferably substantially free of halides, metals, and metal ions. “Substantially free” as used herein with respect to halides, such as chlorides, bromides, iodides, or fluorides, means less than about 3 ppm by weight of halides, more preferably less than about 1 ppm, as determined by inductively coupled plasma mass spectrometry (ICP-MS) or ion chromatography. With respect to metals and metal ions, “substantially free” is used herein to mean less than about 1 ppm of ionic or neutral forms of lithium, sodium, magnesium, potassium, calcium, scandium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, copper, zinc, or other higher molecular weight transition metals, more preferably less than about 0.1 ppm of ionic or neutral metals.

[0082] The processes described herein are inherently selective processes. “Inherently,” as used herein, means that modification of non-growing metal surfaces with organic molecules is not required to inhibit growth on at least one metal surface during the deposition process. However, it is within the scope of this disclosure that the selectivity of the process can be further enhanced by inhibiting growth on one or more non-growing surfaces using low molecular weight molecules, self-assembling monolayers, or polymers known in the art. Such molecules known in the art include C1-C153 18 Thiols, dodecylsilanes, etc. C1-C 18 Silanes, benzimidazolium N-heterocyclic carbenes, imidazolium N-heterocyclic carbenes, ketones such as acetylacetone, phenols such as catechol, and C1-C2 carbenes such as octadecylphosphonic acid. 18 It includes amines such as phosphonic acid and aniline, and cyclic azasilanes such as N-methyl-aza-2,2,4-trimethylsilacyclopentane. Such polymers known in the art include, but are not limited to, polyimides, polynorbornene, and polyacrylates.

[0083] In a further aspect of this disclosure, a method for selectively depositing a dielectric layer on an existing nonmetallic layer of a patterned substrate by using a chemical vapor deposition (CVD) process or a pulsed chemical vapor deposition process is provided. (a) A step of introducing a patterned substrate into the reaction zone of a deposition chamber, wherein the patterned substrate comprises at least one metallic region and at least one insulated nonmetallic region, and the temperature of the reaction zone is between approximately 25°C and approximately 500°C. (b0.l) Depending on the case, a step of performing annealing, cleaning, etching, or plasma treatment on the substrate, (b0.2) Depending on the case, a step of exposing the patterned substrate to an oxidizing agent, (b0.3) Depending on the case, the step of exposing the patterned substrate to a chemical barrier for selective passivation in at least one region of the substrate, (b7) A step of exposing the patterned substrate to a compound of formula 1, formula 2, formula 3, or formula 4 while simultaneously exposing the patterned substrate to a non-oxidizing plasma, (b8) Depending on the circumstances, the process of purging the deposition chamber, (b8.1) Depending on the case, a step of performing annealing, cleaning, etching, or plasma treatment on the patterned substrate, (b8.2) Depending on the case, a step of exposing the patterned substrate to an oxidizing agent, (b8.3) Depending on the case, the step of exposing the patterned substrate to a chemical barrier for selective passivation in at least one region of the substrate, (b8.4) Depending on the circumstances, a step of purging the reaction chamber, (b9) Repeat steps (b7) through (b8.4) until the desired film thickness is reached. Includes. The silicon-containing dielectric layer covers only at least one region of the patterned substrate. Compounds having formulas 1, 2, 3, and 4 were described previously.

[0084] Most of the steps in this method are as previously described, with the exception of step (d), which involves exposure to the compound of Formula 1, 2, 3, or 4 and a non-oxidizing plasma. This simultaneous exposure to the chemical compound of Formula 1, 2, 3, or 4 and the plasma may be continued without interruption until the desired layer / film thickness is reached, or it may be stopped and restarted multiple times to include cleaning, annealing, etching, or plasma treatment of the patterned substrate with the film deposited thereon in the process of growing the target film. Although the exposure to the compound of Formula 1, 2, 3, or 4 and the plasma is simultaneous, it should be understood that it is within the scope of this disclosure that one exposure may start before the other or end after the other.

[0085] In this method, steps (a) to (b0.3) represent pre-deposition surface preparation, steps (b7) to (b8) represent CVD or pulsed CVD deposition processes, and steps (b8.1) to (b9) represent supercycle CVD or supercycle pulsed CVD processes, which periodically include additional surface cleaning or modification processes to enhance selectivity by re-establishing suitable growing and non-growing surfaces or removing undesirable growth on non-growing surfaces, or to modify the properties of the interface between the growing film or its adjacent layers.

[0086] In some embodiments, the precursor compounds of the present invention may be used in ALD or CVD processes for forming a dielectric layer on a patterned substrate in an inherently selective manner. In some embodiments, the term “selectively” means that the film deposited on the target growth surface is formed at a rate at least 5 times, preferably 10 times or more, or even more preferably 20 times or more, than it is deposited on a non-growth surface that is not targeted. As used herein, an “inherently” selective process is one in which modification of some or all of the non-growth surface by growth-inhibiting small molecule inhibitors, self-assembling monolayers, or polymeric films is not required to achieve selective growth on the dielectric layer. However, modification of one or more non-growth areas by such blockers, such as small molecule inhibitors, self-assembling monolayers, or polymeric films, in order to achieve enhanced selectivity is within the scope of the present invention. Examples of such materials known in the art include chlorosilanes, alkoxysilanes, aminosilanes, cyclic azasilanes, alkanethiols, alkanephosphonic acids, phenols, organic acids, alkynes, alkenes, aldehydes, and ketones. The blocking agent may be applied before the ALD or CVD process is initiated, or once or multiple times during the ALD or CVD process, or both, to optimize selectivity with respect to all grown and non-grown surfaces observed on the substrate.

[0087] As used herein, the terms “growth” and “non-growth” are understood to refer to areas of a patterned substrate where dielectric film growth is desired and undesired, respectively, for the fabrication of a device structure. According to the present invention, at least one growth surface must be nonmetallic. Non-limiting examples of growth surfaces include silicon dioxide, silicon, silicon-germanium, alumina, germanium, SiOC low-k dielectric, silicon nitride, and silicon carbide. Non-limiting examples of exemplary materials that may be non-growth surfaces include copper, cobalt, ruthenium, molybdenum, and tungsten.

[0088] The term "atomic layer deposition" or "ALD" can be understood as a temporal process in which a compound of formula 1, 2, 3, or 4 is introduced into a reaction chamber containing a substrate over a set period of time, the reaction chamber is purged with an inert gas such as nitrogen, argon, or helium, the substrate is exposed to a second reactant or plasma over a set period of time, and the reaction chamber is purged again with an inert gas. This cycle of the four steps is then repeated until a desired film thickness is achieved. Alternatively, "atomic layer deposition" or "ALD" can be understood as a spatial process in which the substrate is moved alternately between a position containing the compound of formula 1, 2, 3, or 4 and a position containing the second reactant or plasma, and this process is repeated until a desired film thickness is achieved.

[0089] The term "chemical vapor deposition" or "CVD" shall be understood to mean a process, in accordance with the present invention, in which a compound of formula 1, 2, 3, or 4 is introduced into a reaction chamber simultaneously with a second reactant or plasma and continued until a desired film thickness is reached.

[0090] According to the present invention, both ALD and CVD processes are understood to involve the substrate being exposed to one or more pretreatment processes with the same or different tools before the commencement of the ALD or CVD process. These pretreatment processes may include wet or plasma etching, polishing, solvent cleaning, hydroxylation, oxidation, reduction, annealing, or UV or e-beam exposure. The pretreatment processes may optionally include the use of barriers such as low molecular weight inhibitors, self-assembling monolayers, or polymeric films to suppress growth on one or more non-growing surfaces.

[0091] The ALD and CVD processes according to the present invention may occur once or more than once. If more than one, processes including wet or plasma etching, polishing, solvent cleaning, hydroxylation, oxidation, reduction, annealing, and UV or e-beam exposure may be performed between the ALD and CVD processes. Furthermore, processes including wet or plasma etching, polishing, solvent cleaning, hydroxylation, oxidation, reduction, annealing, and UV or e-beam exposure may be implemented after the final ALD or CVD process to remove undesirable film growth on non-growth surfaces, particles, or contaminants, to chemically or physically transform deposited materials, or to prepare the substrate surface for further device fabrication processes.

[0092] The precursors described herein contain two essential elements: the presence of at least one oxygen atom in the chemical structure of the precursor, which is necessary to provide an oxygen source for the formation of a silicon-containing dielectric film; and a silicon-nitrogen bond, which enables rapid and strong bonding with the growing film surface for the required period of time at temperatures up to 500°C.

[0093] The high growth rates and general applicability of these precursors at temperatures above approximately 200°C enable the formation of films with low carbon and nitrogen content. While SiOC(N) films are desirable in some applications, in many other cases, films with little to no carbon or nitrogen content (e.g., silicon dioxide) are preferred.

[0094] Herein, the present invention will be described in relation to the following non-limiting examples.

[0095] The chemical precursors used in Examples 1, 3, 4, Comparative Example 2, Comparative Example 3, and Comparative Example 4 have the following structure:

[0096] [ka]

[0097] It was N-ethyl-2,2-dimethoxy-4-methyl-1-aza-2-silacyclopentane, which contained [the specified compound].

[0098] The chemical precursor used in Comparative Example 1 has the following structure:

[0099] [ka]

[0100] It was N-methyl-aza-2,2,4-trimethylsilacyclopentane containing [a specific compound].

[0101] The chemical precursors used in Examples 2, 5, 6, and 7 have the following structure:

[0102] [ka]

[0103] It was (dimethylamino)trimethoxysilane having [a specific characteristic]. [Examples]

[0104] Selective growth of SiO2 on SiO2 using N-ethyl-2,2-dimethoxy-4-methyl-1-aza-2-silacyclopentane A silicon wafer with a 1000 nm thermal oxide layer was placed in a reaction chamber at 400°C. The wafer was subjected to 125 ALD cycles of sequential exposure to nitrogen plasma for 1 minute, followed by a 10-second purge of N-ethyl-2,2-dimethoxy-4-methyl-1-aza-2-silacyclopentane (10 seconds), nitrogen plasma (10 seconds), and water (10 seconds). A 2.0 nm silicon dioxide film, determined by polarization analysis, grew on the top surface of the underlying thermal oxide layer (see Figure 1). [Examples]

[0105] Selective growth of SiO2 on SiO2 using (dimethylamino)trimethoxysilane A silicon wafer with a 1000 nm thermal oxide layer was placed in a reaction chamber at 300°C. The wafer was subjected to 25 ALD cycles of sequential exposure to nitrogen plasma for 1 minute, followed by (dimethylamino)trimethoxysilane (5 seconds) and nitrogen plasma (10 seconds), separated by a 10-second purge. A 0.6 nm silicon dioxide film, determined by polarization analysis, grew on the top surface of the underlying thermal oxide layer (see Figure 1). [Examples]

[0106] Selective non-growth of SiO2 on copper using N-ethyl-2,2-dimethoxy-4-methyl-1-aza-2-silacyclopentane A silicon wafer with 500 nm physically deposited (PVD) copper was washed with ethanol for 5 minutes and then placed in a reaction chamber at 400°C. The wafer was subjected to 125 ALD cycles of sequential exposure to nitrogen plasma for 1 minute, followed by a 10-second purge of separated N-ethyl-2,2-dimethoxy-4-methyl-1-aza-2-silacyclopentane (10 seconds), nitrogen plasma (10 seconds), and water (10 seconds). No silicon signal was detected by X-ray photoelectron spectroscopy (XPS) (see Figure 2). [Examples]

[0107] Selective non-growth of SiO2 on cobalt using N-ethyl-2,2-dimethoxy-4-methyl-1-aza-2-silacyclopentane A silicon wafer with 50 nm physically deposited (PVD) cobalt was placed in a reaction chamber at 400°C. The wafer was subjected to 125 ALD cycles, sequentially exposing it to nitrogen plasma for 1 minute, followed by a 10-second purge of separated N-ethyl 2,2-dimethoxy-4-methyl-1-aza-2-silacyclopentane (10 seconds), nitrogen plasma (10 seconds), and water (10 seconds). No silicon signal was detected by XPS (see Figure 2). [Examples]

[0108] Selective non-growth of SiO2 on copper using (dimethylamino)trimethoxysilane A silicon wafer with 500 nm physically deposited (PVD) copper was washed with ethanol for 5 minutes and then placed in a reaction chamber at 300°C. The wafer was subjected to 25 ALD cycles of sequential exposure to nitrogen plasma for 1 minute, followed by a 10-second purge of (dimethylamino)trimethoxysilane (5 seconds) and nitrogen plasma (10 seconds). Minimal silicon was detected on the copper surface by XPS (see Figure 5). [Examples]

[0109] Selective growth of SiO2 on SiO2 using (dimethylamino)trimethoxysilane A silicon wafer with a 1.7 nm thick natural silicon dioxide layer was placed in a reaction chamber at 400°C. The wafer was subjected to 125 ALD cycles of sequential exposure to nitrogen plasma for 1 minute, followed by (dimethylamino)trimethoxysilane (10 seconds), nitrogen plasma (10 seconds), and water (10 seconds), separated by a 10-second purge. For a total of 5.6 nanometers of silicon dioxide, the thickness of the additional silicon dioxide film was determined to be 3.9 nanometers by polarization analysis. [Examples]

[0110] Selective non-growth of SiO2 on cobalt using (dimethylamino)trimethoxysilane A silicon wafer with 50 nm of physically deposited (PVD) cobalt was placed in a reaction chamber at 400°C. The wafer was subjected to 125 ALD cycles, sequentially exposing it to (dimethylamino)trimethoxysilane (10 seconds), nitrogen plasma (10 seconds), and water (10 seconds), followed by a 10-second purge. The thickness of the resulting silicon dioxide film was determined to be 1.0 nanometer by XPS.

[0111] Comparative Example 1 Non-growth of comparative compound (N-methyl-aza-2,2,4-trimethylsilacyclopentane) under the conditions of the present invention A silicon wafer with a 1000 nm thermal oxide layer was placed in a reaction chamber at 400°C. The wafer was subjected to 125 ALD cycles, sequentially exposing the wafer to a nitrogen plasma for 1 minute, followed by a 10-second purge, then to an oxygen-free non-inventive chemical compound (N-methyl-aza-2,2,4-trimethylsilacyclopentane, 10-second exposure) at positions R1, R2, or R3, nitrogen plasma (10 seconds), and water (10 seconds). Film growth of less than 0.6 nanometers was observed by polarization analysis (see Figure 1).

[0112] Comparative Example 2 Non-selective growth of N-ethyl-2,2-dimethoxy-4-methyl-1-aza-2-silacyclopentane on SiO2 under comparative conditions A silicon wafer with a 1000 nm thermal oxide layer was placed in a reaction chamber at 30°C. The wafer was subjected to 125 ALD cycles, sequentially exposing it to nitrogen plasma for 1 minute, followed by N-ethyl-2,2-dimethoxy-4-methyl-1-aza-2-silacyclopentane (5 seconds), and oxygen plasma (10 seconds), separated by a 10-second purge. An 8.2 nm silicon dioxide film, determined by polarization analysis, grew on the top surface of the underlying thermal oxide layer (see Figure 1).

[0113] Comparative Example 3 Non-selective growth of N-ethyl-2,2-dimethoxy-4-methyl-1-aza-2-silacyclopentane on copper under comparative conditions A silicon wafer with 500 nm PVD copper added was washed with ethanol for 5 minutes and then placed in a reaction chamber at 30°C. The wafer was subjected to 125 ALD cycles of sequential exposure to nitrogen plasma for 1 minute, followed by N-ethyl-2,2-dimethoxy-4-methyl-1-aza-2-silacyclopentane (5 seconds) and oxygen plasma (10 seconds), separated by a 10-second purge. A silicon dioxide film of approximately 10 nm, determined by XPS depth profiling, grew on the top surface of the copper. The XPS depth profile data for the film of Comparative Example 3, shown in Figure 3, demonstrates that silicon dioxide is deposited on copper when an oxidizing plasma is used rather than the non-oxidizing plasma of the present invention.

[0114] Comparative Example 4 Non-selective growth of N-ethyl-2,2-dimethoxy-4-methyl-1-aza-2-silacyclopentane on cobalt under comparative conditions. A silicon wafer with 50 nm PVD cobalt added was washed with ethanol for 5 minutes and then placed in a reaction chamber at 30°C. The wafer was subjected to 125 ALD cycles of sequential exposure to nitrogen plasma for 1 minute, followed by a 10-second purge of N-ethyl-2,2-dimethoxy-4-methyl-1-aza-2-silacyclopentane (5 seconds) and oxygen plasma (10 seconds). A silicon dioxide film of approximately 9 nm, as determined by XPS depth profiling, grew on the cobalt apex. The XPS depth profile data for the film of Comparative Example 4, shown in Figure 4, demonstrates that silicon dioxide is deposited on cobalt when an oxidizing plasma is used rather than the non-oxidizing plasma of the present invention.

[0115] Comparative Example 5 Comparison of precursor and plasma One precursor of the present invention (N-ethyl-2,2-dimethoxy-4-methyl-1-aza-2-silacyclopentane) and two comparative precursors (methoxypropyltrimethoxysilane and aminopropyltrimethoxysilane) were used in a 25-cycle atomic layer deposition process at temperatures ranging from 30°C to 400°C, with each cycle including 5 seconds of exposure to the precursor, 10 seconds of nitrogen purging, 10 seconds of plasma exposure, and 10 seconds of purging. For the precursor of the present invention, experiments were conducted using both ammonia plasma and nitrogen plasma. For the comparative precursors, experiments were conducted using ammonia plasma. The results are shown in Figure 6.

[0116] Figure 1 shows graphs of in-situ polarization analysis for the films prepared in Example 1, Example 2, Comparative Example 1, and Comparative Example 2. The graphs of in-situ polarization analysis shown in Figure 1 demonstrate typical cyclic ALD growth for Examples 1 and 2. In addition, Comparative Example 1 is shown, which uses a comparative precursor that is structurally similar to the one used in Example 1 but lacks oxygen atoms, and Comparative Example 2 is shown, which uses the same precursor as in Example 1 under non-inventive oxidative plasma conditions.

[0117] Figure 2 depicts the X-ray photoelectron spectroscopy (XPS) data of the silicon 2s peak for Examples 1, 2, and 3. The X-ray photoelectron spectroscopy (XPS) data in Figure 2 demonstrates virtually complete selectivity for deposition on the thermal oxide surface compared to copper and cobalt surfaces.

[0118] Figure 3 depicts the X-ray photoelectron spectrum of Comparative Example 3, showing a thick layer of silicon dioxide growth on copper under non-inventive oxidizing plasma conditions.

[0119] Figure 4 depicts the X-ray photoelectron spectrum of Comparative Example 3, showing a thick layer of silicon dioxide growth on cobalt under non-inventive oxidizing plasma conditions.

[0120] Figure 5 depicts the X-ray photoelectron spectrum of Example 5, which shows virtually no silicon-related peaks, demonstrating the high selectivity of the process of the present invention on a cobalt substrate.

[0121] Figure 6 depicts the growth rate over 25 atomic layer deposition cycles for the precursor of the present invention (N-ethyl-2,2-dimethoxy-4-methyl-1-aza-2-silacyclopentane) and two comparative precursors (methoxypropyltrimethoxysilane and aminopropyltrimethoxysilane) as a function of temperature. A significant decrease in growth rate was observed using the comparative precursors and ammonia plasma as a co-reactant, with growth rates below 0.2 angstroms per cycle above 200°C. Using the precursor of the present invention, N-ethyl-2,2-dimethoxy-4-methyl-1-aza-2-silacyclopentane, and ammonia plasma under otherwise identical conditions, growth rates between 0.2 and 0.3 angstroms per cycle were observed. By using the same precursor of the present invention and nitrogen plasma, the growth rate was further increased to a height of 0.5 angstroms per cycle.

[0122] Those skilled in the art will see that modifications can be made to the embodiments described above without departing from the broad concept of the invention. Therefore, it is understood that the present invention is not limited to the specific embodiments disclosed, but is intended to encompass modifications within the spirit and scope of the invention as defined by the appended claims.

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