A computing device including a magnetic Josephson junction having an embedded magnetic field control element

Abstract

A computing device is provided that includes a magnetic Josephson junction with an embedded magnetic field control element. An on-chip magnetic field control device is formed adjacent to a Josephson junction (JJ) structure. The on-chip magnetic field control device includes a wiring structure disposed laterally adjacent to the JJ structure. In some embodiments, the magnetic field control device also includes, in addition to the wiring structure, a conductive plate connected to the wiring structure and disposed below the JJ structure. Using a current through the wiring structure directly or indirectly induces a magnetic field into the JJ structure. The strength of the field is modulated by the amount of current passing through the wiring structure. The magnetic field can be stopped as needed by not allowing current to flow through the wiring structure.

Description

Technical Field

[0001] The present invention relates to computing devices (i.e., neuromorphic or artificial intelligence (AI)), and more particularly, to a computing device including a magnetic field control structure within a chip disposed proximate to a Josephson junction (JJ) structure and a method of forming the same.

Background Art

[0002] Devices including magnetic JJs can be used for advanced low-power / high-performance neuromorphic applications. A JJ includes two superconducting materials separated by a non-superconducting barrier layer, and these barrier layers are thin enough so that electrons can pass through and traverse the barrier layer. JJs generally exhibit the Josephson effect of superconducting current, where current can flow across the JJ indefinitely without the application of a voltage.

[0003] In devices including JJs, a perpendicular external magnetic field of the device is sometimes necessary for their function. Toggle magnetic random access memory (MRAM) has been used with double wires arranged at 90° to adjust the function of the MRAM device. However, in devices including magnetic JJs, such an implementation has not been known at all. Therefore, there is a need to provide a thin-chip magnetic field control structure that can be integrated into devices including JJs.

Summary of the Invention

[0004] A magnetic field control device within a chip is formed in proximity (within 5 nm to 500 nm) to a Josephson junction (JJ) structure. The magnetic field control device within the chip includes a wiring structure disposed adjacent to the side of the JJ structure. In some embodiments, the magnetic field control device also includes, in addition to the wiring structure, a conductive plate connected to the wiring structure and disposed under the JJ structure. Using a current through the wiring structure directly or indirectly induces a magnetic field to the JJ structure. The strength of the field is modulated by the amount of current passing through the wiring structure. The magnetic field can be stopped as needed by not allowing current to flow through the wiring structure.

[0005] In one aspect of the present invention, a computing device is provided that includes a magnetic field control structure within a chip disposed in proximity to a JJ structure. In one embodiment of the present invention, the computing device includes a conductive plate embedded within a semiconductor substrate. At least one JJ structure is disposed on the conductive plate. A first wiring structure is disposed adjacent to the side of the at least one JJ structure. In an embodiment of the present invention, applying an electrical current to one of the conductive plate or the first wiring structure induces a magnetic field to the at least one JJ structure.

[0006] In another embodiment of the present invention, a method of forming such a computing device is provided. In one embodiment of the present invention, the method includes forming a conductive plate within a semiconductor substrate. Next, a first dielectric material is formed on the physically exposed surfaces of the semiconductor substrate and the conductive plate, where the first dielectric material layer includes via openings that physically expose the surface of the conductive plate. A metal-containing layer is then formed within each via opening and on the uppermost surface of the first dielectric material layer. The metal-containing layer is then patterned to provide first and second metal-containing wiring structures, where the first metal-containing wiring structure is connected to the conductive plate and the second metal-containing wiring structure is spaced apart from the conductive plate. The JJ structure is then formed on each second metal-containing wiring structure. Next, a second dielectric material layer is formed adjacent to and on the side of each JJ structure. The second dielectric material layer includes a wiring connection structure and a JJ connection structure embedded therein. The wiring connection structure is connected to the first metal-containing wiring structure and the JJ connection structure is connected to the JJ structure.

[0007] In another embodiment, the method includes forming a conductive plate within a semiconductor substrate. Next, at least one JJ structure is formed on the conductive plate. A first dielectric material layer is then formed adjacent to the side of at least one JJ structure, where the first dielectric material layer includes a wiring structure embedded therein and connected to the semiconductor substrate. Next, a second dielectric material layer is formed on the first dielectric material layer and on at least one JJ structure. The second dielectric material layer includes a wiring connection structure and a JJ connection structure embedded therein. The wiring connection structure is connected to the wiring structure and the JJ connection structure is connected to the JJ structure.

Brief Description of the Drawings

[0008]

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[0009] Embodiments of the present invention will now be described in more detail herein with reference to the following discussion and the accompanying drawings. It should be noted that the drawings are provided for illustrative purposes only and, as such, are not drawn to scale. Also, note that like and corresponding elements are referred to by like reference numerals.

[0010] In the following description, to provide an understanding of various embodiments of the present invention, many specific details such as specific structures, components, materials, dimensions, processing steps, and technologies are described. However, those skilled in the art will understand that various embodiments of the present invention can be implemented without these specific details. In other instances, well-known structures or processing steps are not described to avoid obscuring the present invention.

[0011] Also, when an element such as a layer, region, or substrate is referred to as "on" or "above" another element, it will be understood that it can be directly on the other element or intervening elements may be present. In contrast, when an element is referred to as "directly on" or "immediately above" another element, no intervening elements are present. Also, when an element is referred to as "connected" or "coupled" to another element, it will be understood that it can be directly bonded or coupled to other elements or intervening elements that may be present. In contrast, when an element is referred to as "directly connected" or "directly coupled" to another element, no intervening elements are present.

[0012] First, referring to FIGS. 1 - 13, these illustrate a first method of the present invention that can be used to provide a computing device including a magnetic control device within a chip disposed near a JJ structure. In this embodiment of the present invention, a conductive plate is embedded within a semiconductor structure. A wiring structure is then formed on the conductive plate. Some of the wiring structures are directly connected to the conductive plate, while other wiring structures are not directly connected to the conductive plate. The JJ structure is then formed on each of the wiring structures that are not directly connected to the conductive plate. Next, a connection structure is formed. Some of the connection structures are connected to the wiring structures that are directly connected to the conductive plate, while other connection structures are connected to the JJ structure. Collectively, and in this embodiment, the conductive plate and the wiring structures connected to the conductive plate function as timing control devices when disposed proximate to their respective JJ structures.

[0013] In this embodiment, the conductive plate can generate a magnetic field by passing an electric current through the wiring structure, and the magnetic field can also be generated by the wiring structures themselves, but such a magnetic field is negligible compared to the magnetic field generated by the conductive plate. The strength of the magnetic field can be varied by the amount of electric current flowing through the wiring structure. Also, the magnetic field can be stopped as needed by not allowing an electric current to flow through the wiring structure.

[0014] Referring to FIG. 1, an exemplary structure that can be used in an embodiment of the present invention is shown. The exemplary structure of FIG. 1 includes a conductive plate 12 embedded within a semiconductor substrate 10. In particular, since the conductive plate 12 is disposed within a trench formed within the semiconductor substrate 10, the semiconductor substrate 10 is disposed adjacent to the side of the conductive plate 12 and below it.

[0015] The semiconductor substrate 10 that can be used in an embodiment of the present invention includes at least one semiconductor material having semiconductor characteristics. Semiconductor materials that can provide the semiconductor substrate 10 include, for example, silicon (Si), germanium (Ge), silicon-germanium alloy (SiGe), silicon carbide (SiC), silicon-germanium-carbide (SiGeC), III-V group compound semiconductors, or II-VI group compound semiconductors. III-V group compound semiconductors include at least one element from Group III of the periodic table of elements and one element from Group V of the periodic table of elements. II-VI group compound semiconductors include at least one element from Group II of the periodic table of elements and one element from Group VI of the periodic table of elements.

[0016] The semiconductor substrate 10 can be a single crystal semiconductor material. The semiconductor substrate 10 can be used with any well-known crystal orientation. For example, the crystal orientation of the semiconductor substrate 10 can be {100}, {110}, or {111}. Despite these specifically pointed out ones, other crystallographic orientations can also be used in embodiments of the present invention.

[0017] In some embodiments, the semiconductor substrate 10 can be a bulk semiconductor substrate, i.e., a substrate entirely composed of at least one semiconductor material. In other embodiments, the semiconductor substrate 10 is a silicon-on-insulator (SOI) including a handle substrate, a buried insulator layer, and a top semiconductor material layer. In such embodiments, the conductive plate 12 can be formed only within the top semiconductor material layer, or can be formed within the top semiconductor material layer and the buried insulator layer, or can be formed within the top semiconductor material layer, the buried insulator layer, and the handle substrate.

[0018] As described above, the conductive plate 12 is present within a trench formed in the semiconductor substrate 10. The trench can be formed by a patterning process. In one embodiment, the patterning process includes lithography and etching. Lithography includes forming a photoresist material on the material to be patterned, or on a material stack (e.g., the semiconductor substrate 10), exposing the photoresist material to a desired radiation pattern, and developing the exposed photoresist using a conventional resist developer. The etching used to transfer the pattern from the developed photoresist material to the semiconductor substrate 10 can include isotropic etching or anisotropic etching. In one embodiment, the patterning process uses reactive ion etching (RIE). The developed resist is typically removed from the structure using a conventional resist stripping process, such as ashing, after the pattern transfer etching.

[0019] The trench can have many shapes. In one example, the trench can be cylindrical in shape. In some embodiments, the trench can have a depth of 100 nm to 500 nm as measured from the topmost surface of the semiconductor substrate 10 to the bottom wall of the trench, although other trench depths are possible and can be used in embodiments of the present invention.

[0020] In this specification, a single trench is described and shown, but a plurality of spaced trenches can be formed in the semiconductor substrate 10, and then the conductive plate 12 can be etched and formed into each trench of the plurality of trenches.

[0021] The conductive plate 12 is then formed in the trench. The conductive plate 12 can be formed by a deposition process such as, for example, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), physical vapor deposition (PVD), sputtering, or plating. For example, a planarization process such as chemical mechanical polishing (CMP) can follow the deposition of the conductive plate material.

[0022] In some embodiments, the conductive plate 12 can be composed of an electrically conductive metal-containing material. The electrically conductive metal-containing materials that can be used as the conductive plate 12 are not limited to these, and include copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), titanium nitride (TiN), or a copper-aluminum alloy. In some embodiments, the conductive plate 12 can be composed of a superconductor. A superconductor is an element or an alloy of metals in which, when cooled below a certain threshold temperature, the material dramatically loses all resistance. A superconductor allows current to flow without any significant energy loss. Examples of superconductors that can be used as the conductive plate 12 include, but are not limited to, molybdenum (Mo), niobium (N), osmium (Os), rhenium (Re), rhodium (Rh), ruthenium (Ru), Nb-Ti alloy, or zirconium nitride (ZrN).

[0023] The conductive plate 12 has the same shape as a trench. In one embodiment, the conductive plate 12 is cylindrical in shape. In some embodiments, the conductive plate 12 can have a top surface that is coplanar with the topmost surface of the semiconductor substrate 10. In other embodiments, the conductive plate 12 can have a top surface either above or below the topmost surface of the semiconductor substrate 10.

[0024] Referring now to FIG. 2, an exemplary structure of FIG. 1 is shown after a first dielectric material layer 14 has been formed on the physically exposed surfaces of the semiconductor substrate 10 and the conductive plate 12. The first dielectric material layer 14 is a continuous layer that completely covers the exemplary structure shown in FIG. 1. The first dielectric material layer 14 can be composed of any dielectric material such as, for example, silicon dioxide, silicon nitride, or silicon oxynitride. In some embodiments, the first dielectric material layer 14 is composed entirely of a single dielectric material. In other embodiments, the first dielectric material layer 14 is composed of a stack of two or more dielectric materials. The first dielectric material layer 14 can be formed using a deposition process such as, for example, CVD or PECVD. The first dielectric material layer 14 can have a thickness of 10 nm to 100 nm, although other thicknesses are possible and can be used as the thickness of the first dielectric material layer 14.

[0025] Referring now to FIG. 3, an exemplary structure of FIG. 2 is shown after the formation of via openings 16 that pass through the first dielectric material layer 14, where each via opening 16 physically exposes the surface of the conductive plate 12. In an exemplary embodiment, a pair of via openings 16 is shown for the purposes of one example. Each via opening 16 can be formed by lithography and etching as defined above. The resist used to taper the first dielectric material layer 14 is stripped from the exemplary structure after the pattern transfer etching has been performed.

[0026] Referring now to FIG. 4, an exemplary structure of FIG. 3 is shown after a metal-containing layer 18 is formed on each via opening 16 and on the topmost surface of the first dielectric material layer 14. The metal-containing layer 18 can be composed of one of the electrically conductive metal-containing materials or one of the superconducting materials described above for the conductive plate 12. In one embodiment, the metal-containing layer 18 is composed of the same material as the conductive plate 12 in terms of composition. For example, both the metal-containing layer 18 and the conductive plate 12 can be composed of Cu. In another embodiment, the metal-containing layer 16 is composed of a material that is compositionally different from the conductive plate 12. For example, the metal-containing layer 18 can be composed of Nb, and the conductive plate 12 can be composed of Cu.

[0027] The metal-containing layer 18 can be formed by a deposition process including, for example, CVD, PECVD, sputtering, or plating. The metal-containing layer 18 has a thickness sufficient to fill each via opening 16 and extends over the topmost surface of the first dielectric material layer 14.

[0028] Referring now to FIG. 5, an exemplary structure of FIG. 4 is shown after the metal-containing layer 18 is patterned to provide a metal-containing wiring structure 18P on the first dielectric material layer 14. As shown, the metal-containing wiring structure 18P includes a lower via portion 18V that directly connects to the surface of the underlying conductive plate 12, while other metal-containing structures 18P do not have the lower via portion 18V. The metal-containing wiring structure 18P including the lower via portion 18V can be referred to as a first wiring structure or a line-via combined wiring structure, while the metal-containing wiring structure 18P without the lower via portion 18V is referred to as a second wiring structure or a line wiring structure.

[0029] The patterning of the metal-containing layer 18 includes lithography and etching as described above. As shown in FIG. 5, a gap 19 exists between each metal-containing wiring structure 18P. Also, as shown in FIG. 5, each first wiring structure (18P / 18V) is disposed adjacent to the side of the region including the second wiring structure 18P.

[0030] Here, referring to FIG. 6, an exemplary structure of FIG. 5 is shown after a gap-fill dielectric layer 20 is formed in a gap 19 disposed between respective metal-containing wiring structures 18P. The gap-fill dielectric layer 20 can include any dielectric material including one of the dielectric materials described above for the first dielectric material layer 14. In one embodiment, the gap-fill dielectric material 20 is composed of a dielectric material that is compositionally identical to the dielectric material that provided the first dielectric material image 14. In another embodiment, the gap-fill dielectric material 20 is composed of a dielectric material that is compositionally different from the dielectric material that provided the first dielectric material layer 14.

[0031] The gap-fill dielectric material 20 can be formed by depositing a dielectric material in respective gaps 19 and optionally on top of respective metal-containing wiring structures 18P. The dielectric material providing the gap-fill dielectric material 20 can be deposited by CVD, PECVD, or PVD. In some embodiments, a planarization process such as CMP, for example, can follow the deposition of the dielectric material providing the gap-fill dielectric material 20.

[0032] The gap-fill dielectric material 20 completely fills respective gaps 19, and the gap-fill dielectric material 20 typically has a coplanar surface with the top surface of respective metal-containing wiring structures 18P.

[0033] Referring now to FIG. 7, an exemplary structure of FIG. 6 after forming the precursor JJ material stack MS1 thereon is shown. In some embodiments, as shown in FIG. 7, a metal-containing capping layer 28 can be formed on top of the top surface of the precursor JJ material stack MS1. The precursor JJ material MS1 is not an active JJ structure at this point. The precursor JJ material stack MS1 includes, from bottom to top, a first superconductor material layer 22, an amorphous silicon-manganese-containing layer 24 (aSi-Mn), and a second superconductor material layer 26. Although this specifically describes and shows aSi-Mn as layer 24, the present invention contemplates embodiments where layer 24 is an aX-M layer, where X is a semiconductor material such as Si, Ge, or SiGe, and M is a magnetic material such as Co, Ni, Fe, Mn, or any combination thereof.

[0034] The first superconductor material layer 22 can include one of the superconductor materials described above for the conductive plate 12. The first superconductor material layer 22 can be composed of a superconductor material that is compositionally the same as, or compositionally different from, the superconductor material used for the conductive plate 12, or can be composed of the metal-containing wiring structure 18P, or a combination thereof. The first superconducting material layer 22 can be formed, for example, by a deposition process including CVD, PECVD, sputtering, plating, or ALD. The first superconductor material layer 22 can have a thickness of 5 nm to 50 nm, although other thicknesses of the first superconductor material layer 22 are contemplated and can be used as the first superconductor material layer 22.

[0035] The aSi-Mn layer 24 is composed of amorphous silicon in which manganese (Mn) is incorporated. The Mn content in the aSi-Mn layer 24 can be 15 atomic % to 60 atomic %. The aSi-Mn layer 24 can be formed by first depositing a layer of amorphous silicon and then introducing Mn into the amorphous silicon layer using plasma doping or outward diffusion of Mn into the amorphous silicon layer. Alternatively, the aSi-Mn layer 24 can be formed using an in-situ deposition process. The aSi-Mn layer 24 is a thin layer having a thickness of 1 nm to 50 nm. This thickness enables the transfer of electrons from the first and second superconductor materials. If there is sufficient Mn present in the aSi-Mn layer 24 to form a normal conductor, the thickness of the aSi-Mn layer 24 can be greater than the range described above.

[0036] The second superconductor material layer 26 can include one of the superconductor materials described above for the conductive plate 12. The second superconductor material layer 26 can be composed of a superconductor material layer that is compositionally the same or compositionally different from the superconductor material used as the first superconductor material layer 22, or can be composed of the conductive plate 12, or the metal-containing wiring structure 18P, or a combination thereof. The second superconductor material layer 26 can be formed by a deposition process including, for example, CVD, PECVD, sputtering, plating, or ALD. The second superconductor material layer 26 can have a thickness of 5 nm to 50 nm, although other thicknesses of the second superconductor material layer 26 are envisioned and can be used as the second superconductor material layer 26.

[0037] The metal-containing capping layer 28 can optionally be formed on the precursor JJ material stack MS1. The metal-containing capping layer 28 can be composed of Ti, Ta, TiN, W, WN, or any other high melting point metal, or a conductive metal nitride. The metal-containing capping layer 28 can be composed of a single material, or it can be composed of a multi-layered material stack. The metal-containing capping layer 28 can be formed by a deposition process including, for example, CVD, PECVD, sputtering, or ALD. The metal-containing capping layer 28 can have a thickness of 5 nm to 50 nm, although other thicknesses of the metal-containing capping layer 28 are envisioned and can be used as the metal-containing capping layer 28.

[0038] Referring now to FIG. 8, an exemplary structure of FIG. 7 is shown after converting the precursor JJ material stack MS1 to the JJ material stack MS2. The JJ material stack MS2 is active after the conversion step. The conversion step converts the aSi-Mn layer 24 to a Mn nanoparticle-containing crystalline silicon layer 25 (i.e., in the description herein, the Mn nanoparticle-containing crystalline silicon layer); generally, the conversion step converts an aX-M material where X is a semiconductor material such as Si, Ge, or SiGe and M is a magnetic material such as Co, Ni, Fe, Mn, or any combination thereof, with M and X as described above. The conversion does not change the first and second superconducting material layers 22, 26. The conversion includes an annealing process with a low oxygen content (i.e., 10E-7 to 10E-19). The annealing process can be performed at a temperature of 300°C to 500°C. The pressure during the annealing process can be 2 Torr to 150 Torr. The annealing process is typically performed in hydrogen, H2. In some embodiments, an inert gas such as helium (He), argon (Ar), or nitrogen (N2) can be used. In still other embodiments, vacuum annealing can be used. The annealing process can include furnace annealing, laser annealing, or microwave annealing. The duration of the annealing varies depending on the type of annealing process used. Generally, furnace annealing is performed for a longer period than laser or microwave annealing.

[0039] In some embodiments, and if not already formed, the metal-containing capping layer 28 can be formed on the JJ material stack MS2 as defined above. Alternatively, the formation of the metal-containing capping layer 28 can be completely eliminated from the process flow.

[0040] Referring now to FIG. 9, an exemplary structure of FIG. 8 is shown after patterning the JJ material stack MS2 to form a plurality of JJ structures labeled as JJs in the drawing, with each JJ structure of the plurality of JJ structures being disposed on the surface of a metal-containing wiring structure 18P (e.g., a second wiring structure) that is not directly connected to the conductive plate 12. During the patterning of the JJ material stack MS2, if present, the metal-containing capping layer 28 is also patterned. Although a plurality of JJ structures are described and shown, the present invention operates even when a single JJ structure is formed on a single second metal-containing wiring structure 18P.

[0041] Patterning includes lithography and etching. The etching is typically anisotropic etching such as, for example, RIE, ion beam etching, or plasma etching. Each JJ structure includes the remaining (i.e., unetched) portion of the first superconductor material layer 22 (hereinafter referred to as the first superconductor material portion 22P), the remaining (i.e., unetched) portion of the Mn nanoparticle-containing crystalline silicon layer 25 (hereinafter referred to as the Mn-containing crystalline silicon portion 25P), and the remaining (i.e., unetched) portion of the second superconductor material layer 26 (hereinafter referred to as the second superconductor material portion 26P). When the metal-containing capping layer 28 is present, the remaining (i.e., unetched) portion of the metal-containing capping layer 28 (hereinafter referred to as the metal-containing cap 28P) is present at the top of each JJ structure.

[0042] Each JJ structure, and when present, the metal-containing cap 28P can have a cylindrical shape (although other shapes are possible) and typically has a critical dimension (CD) less than CD under the surface of the metal-containing wiring structure 18P that is not directly connected to the conductive plate 12, although this is not always necessary. As shown, the various elements (22P, 25P, 26P) of the JJ structure have outermost sidewalls aligned perpendicular to each other. When present, the metal-containing cap 28P has an outermost sidewall aligned perpendicular to the outermost sidewall of the JJ structure on the lower side. As shown, the first wiring structure (18P / 18V) is adjacent to the side of the region containing the JJ structure.

[0043] Referring now to FIG. 10, an exemplary structure of FIG. 9 is shown after forming a dielectric spacer 30 that encapsulates each JJ structure. The dielectric spacer 30 is composed of a dielectric material that is compositionally different from the gap-fill dielectric material 20. The dielectric material that can provide the dielectric spacer 30 provides passivation of the JJ structure in some embodiments.

[0044] In one embodiment, the dielectric spacer 30 is composed of silicon nitride. In another embodiment, the dielectric spacer 30 can be composed of a dielectric material containing atoms of silicon, carbon, and hydrogen. In some embodiments, in addition to atoms of carbon and hydrogen, the dielectric material providing the dielectric spacer 30 can include at least one atom of nitrogen or oxygen. In other embodiments, in addition to atoms of silicon, nitrogen, carbon, and hydrogen, the dielectric material providing the dielectric spacer 30 can include boron atoms. In one example, the dielectric spacer 30 can be composed of an nBLOK dielectric material containing atoms of silicon, carbon, hydrogen, nitrogen, and oxygen. In an alternative example, the dielectric spacer 30 can be composed of a SiBCN dielectric material containing atoms of silicon, boron, carbon, hydrogen, and nitrogen.

[0045] The dielectric spacer 30 can be formed by first forming a continuous layer of the dielectric material that provides the dielectric spacer 30. For example, spacer etching such as RIE follows the deposition of the dielectric material that provides the dielectric spacer 30. The dielectric spacer 30 can have a thickness of 10 nm to 200 nm. Other thicknesses are possible and can be used as the thickness of the dielectric spacer. The dielectric spacer 30 typically has a top surface coplanar with the top surface of the metal-containing cap 28P, or, in the absence of the metal-containing cap 28P, the top surface of the JJ structure. Although the dielectric spacer 30 is shown as having an I-shaped configuration, the dielectric spacer 30 can have an L-shaped configuration and extend over the exposed surfaces of the metal-containing wiring structure 18P, or the dielectric gap fill material 20, or both.

[0046] Referring now to FIG. 11, an exemplary structure of FIG. 10 is shown after forming a second dielectric material layer 32 adjacent to and over the side of the JJ structure encapsulated by each dielectric spacer 30. The second dielectric material layer 32 can be composed of one of the dielectric materials described above for the first dielectric material layer 14; the dielectric material providing the second dielectric material layer 32 is typically compositionally different from the dielectric material providing the dielectric spacer 30. The second dielectric material layer 32 can also be composed of an interlayer dielectric material such as, for example, undoped silicate glass (USG), fluorosilicate glass (FSG), borophosphosilicate glass (BPSG), spin-on low-k dielectric material, a chemically vapor deposited (CVD) low-k dielectric layer, or any combination thereof. The term "low-k" as used herein describes a dielectric material having a dielectric constant of less than 4.0, and all dielectric constants are measured under vacuum unless otherwise stated herein. In another embodiment, a self-planarizing material such as spin-on glass (SOG) or spin-on low-k dielectric material can be used as the dielectric material for the second dielectric material layer 32. The second dielectric material layer 32 can be formed using a deposition method such as, for example, CVD, PECVD, or spin-on coating.

[0047] Here, referring to FIG. 12, an exemplary structure of FIG. 11 after forming a plurality of connection openings (34Z, 34Y) in the second dielectric material layer 32 is shown. The plurality of connection openings can be formed by lithography and etching. Each connection opening 34Z physically exposes one surface of the metal-containing wiring structure 18P including the lower via portion 18V, while each connection opening 34Y physically exposes either the top surface of one metal-containing cap 28P or the top surface of one second superconductor material portion 26P. The connection opening 34Z can be referred to as a wiring connection opening, while the connection opening 34Y can be referred to as a JJ structure connection opening.

[0048] Here, referring to FIG. 13, an exemplary structure of FIG. 12 after forming metal-containing connection structures (36Y, 36Z) in each connection opening (34Y, 34Z) is shown. Each metal-containing connection structure (36Y, 36Z) can be composed of a connection metal or a connection metal alloy. Examples of connection metals are not limited to these and include tungsten (W), aluminum (Al), or copper (Cu). An example of a connection metal alloy is a Cu-Al alloy. In some embodiments, the above-described superconductor can be used in providing each metal-containing connection structure (36Y, 36Z). The superconductor may be a preferred material for the connection structures (36Y, 36Z) because they would reduce heat consumption and overheating of the chip. As shown, each metal-containing connection structure (36Y, 36Z) has a top surface coplanar with the top surface of the second dielectric material layer 32.

[0049] Each metal-containing connection structure (36Y, 36Z) can be formed by filling the connection opening with a conductive material that provides the metal-containing connection structure (36Y, 36Z). In some embodiments, a planarization process can follow the filling of the connection opening with the conductive metal that provides the metal-containing connection structure (36Y, 36Z).

[0050] In an embodiment of the present invention, each metal-containing connection structure 36Z is connected to one surface of a metal connection wiring structure 18P including a lower via portion 18V, and each metal-containing connection structure 36Y is connected to the uppermost surface of a metal-containing cap 28P or the uppermost surface of one of the second superconductor material portions 26P. The metal-containing connection structure 36Z can be referred to as a wiring connection structure, while each metal-containing connection structure 36Y can be referred to as a JJ connection structure.

[0051] Referring first to FIGS. 14 - 21, a second method of the present invention is shown that can be used to provide a computing device including an in-chip magnetic control device disposed proximate to a JJ structure. In this embodiment of the present invention, a conductive plate is embedded within a semiconductor substrate and at least one JJ structure is formed on the surface of the conductive plate. A wiring structure is then formed adjacent to and connected to the surface of the semiconductor substrate, laterally adjacent to at least one JJ structure. Next, connection structures are formed. Some connection structures connect to the wiring structure that is directly connected to the semiconductor substrate, while other connection structures connect to the JJ structures. In this embodiment, it is the wiring structure, rather than the conductive plate, that is useful as a magnetic control device disposed proximate to the JJ structure. In this embodiment, the conductive plate is a wiring structure for the JJ structure.

[0052] In this embodiment, the magnetic field is generated by the wiring structure, rather than the conductive plate, through which current flows. The strength of the magnetic field can be modulated by the amount of current flowing through the wiring structure. Also, the magnetic field can be stopped by not allowing current to flow through the wiring structure, if desired.

[0053] First, referring to FIG. 14, another exemplary structure that can be used in an embodiment of the present invention is shown. The exemplary structure of FIG. 14 includes a conductive plate 52 embedded within a semiconductor substrate 50. The semiconductor substrate 50 and the conductive plate 52 for this embodiment of the present invention are the same as the semiconductor substrate 10 and the conductive plate 12 for the embodiment shown above in FIG. 1. As described above, the conductive plate 52 of this embodiment is not used to generate a magnetic field, but is used as a wiring structure for the JJ structure.

[0054] Now, referring to FIG. 15, an exemplary structure of FIG. 14 after forming a JJ material stack MS2 on the semiconductor substrate 50 and the conductive plate 52 is shown. The JJ material stack MS2 of this embodiment includes a first superconducting material layer 22 as defined above, a Mn nanoparticle-containing crystalline silicon layer 25 as defined above, and a second superconducting material layer 26 as defined above. Note that other M nanoparticle-containing crystalline semiconductor materials as defined above can be used in place of the Mn nanoparticle-containing crystalline silicon. The JJ material stack MS2 of this embodiment can be formed using the processing steps described above in the formation of the JJ material stack (see, for example, the above description regarding FIGS. 7 - 8). In some embodiments, a metal-containing capping layer 28 is present on the JJ material stack MS2 as defined above. In other embodiments, the metal-containing capping layer 28 is not present on the JJ material stack MS2.

[0055] Referring now to FIG. 16, an exemplary structure of FIG. 15 is shown after patterning the JJ material stack MS2 to provide a JJ structure on the conductive plate 52. The patterning of the JJ material stack MS2 of the present embodiment is the same as the patterning of the JJ material stack MS2 in previous embodiments of the present invention (see FIGS. 9 and the above discussion related to FIG. 9). Each JJ structure includes the remaining (i.e., unetched) portion of the first superconducting material layer 22 (hereinafter referred to as the first superconducting material layer portion 22P), the remaining (i.e., unetched) portion of the Mn nanoparticle-containing crystalline silicon layer 25 (hereinafter referred to as the Mn nanoparticle-containing silicon portion 25P), and the remaining (i.e., unetched) portion of the second superconducting material layer 26 (hereinafter referred to as the second superconducting material layer portion 26P). When the metal-containing capping layer 28 is present, the remaining (i.e., unetched) portion of the metal-containing capping layer 28 (hereinafter referred to as the metal-containing capping layer portion 28P) is present at the top of each JJ structure.

[0056] Each JJ structure and, when present, the metal-containing cap 28P can have a cylindrical shape (although other shapes are possible) in shape and typically has a CD less than the CD below the surface of the conductive plate 52, although not always required. As shown, the various elements (22P, 25P, 26P) of the JJ structure have outermost sidewalls that are aligned perpendicular to each other. When present, the metal-containing cap 28P has an outermost sidewall that is aligned perpendicular to the outermost sidewall of the JJ structure below.

[0057] Referring now to FIG. 17, an exemplary structure of FIG. 16 is shown after forming a dielectric spacer 30 that encapsulates each JJ structure. The dielectric spacer 30 of the present embodiment is the same as the dielectric spacer 30 described above. See, for example, the discussion of FIG. 10 above.

[0058] Referring now to FIG. 18, there is shown an exemplary structure of FIG. 17 after forming a first dielectric material layer 54 adjacent to the side of the JJ structure encapsulated by each dielectric spacer. The first dielectric material layer 54 of the present embodiment of the present invention can be composed of one of the dielectric materials described above for the first dielectric material layer 14. Alternatively, the first dielectric material layer 54 of the present embodiment can also be composed of an interlayer dielectric material such as, for example, undoped silicate glass (USG), fluorosilicate glass (FSG), borophosphosilicate glass (BPSG), spin-on low-k dielectric material, a low-k dielectric layer by chemical vapor deposition (CVD), or any combination thereof. The term "low-k" herein describes a dielectric material having a dielectric constant less than 4.0, and all dielectric constants are measured under vacuum unless otherwise declared herein. In another embodiment, a self-planarizing material such as spin-on glass (SOG) or spin-on low-k dielectric material can be used as the dielectric material for the first dielectric material layer 54.

[0059] The first dielectric material layer 54 can be formed using a deposition process such as, for example, CVD, PECVD, or spin-on coating. A planarization process such as, for example, CMP, or an etch-back process can follow the deposition of the dielectric material providing the first dielectric material layer 54. The first dielectric material 54 has the top surface coplanar with either the top surface of the metal-containing cap 28P or, in the absence of the metal-containing cap 28P, the second superconducting material portion 26P.

[0060] Referring now to FIG. 19, there is shown an exemplary structure of FIG. 18 after forming an opening 56 in the first dielectric material layer 54, where each opening 56 physically exposes the surface of the semiconductor substrate 50. The opening 56 can be formed by lithography and etching as defined above.

[0061] Referring now to FIG. 20, an exemplary structure of FIG. 19 after forming a metal-containing connection structure 58 in each opening 56 is shown. Each metal-containing connection structure 58 can be composed of one of the electrically conductive metals, electrically conductive metal alloys, or superconducting materials described above for the conductive plate 12. Each metal-containing wiring structure 58 can be composed of a material that is compositionally identical or compositionally different from that providing the conductive plate 52. The paired metal-containing wiring structures 58 are shown for the purposes of one embodiment.

[0062] Each metal-containing connection structure 58 can be formed by depositing one of an electrically conductive metal, an electrically conductive metal alloy, or a superconducting material using one of the deposition processes described above for forming the conductive plate 12. A planarization process such as CMP can follow the deposition of the material providing the metal-containing wiring structure 58. Each metal-containing wiring structure 58 typically has a top surface that is coplanar with the top surface of the first dielectric material layer 54, although this is not always necessary. As shown, the metal-containing wiring structure 58 is adjacent to the side of the region including the JJ structure.

[0063] Referring now to FIG. 21, an exemplary structure of FIG. 20 after forming a second dielectric material layer 60 on the first dielectric material layer 54 is shown, where the second dielectric material layer 60 includes a plurality of buried connection structures (62Y, 62Z) therein.

[0064] The second dielectric material layer 60 of the present embodiment of the present invention can include one of the dielectric materials described above for the first dielectric material layer 54. The second dielectric material layer 60 can be composed of a material that is compositionally identical or compositionally different from the dielectric material providing the first dielectric material layer 54. The second dielectric material layer 60 can be formed using one of the deposition processes described above for the formation of the first dielectric material layer 54.

[0065] A plurality of connection structures (62Y, 62Z) embedded in the second dielectric material layer 60 can be formed by first providing connection openings in the second dielectric material layer 60, where some of the connection openings physically expose the metal-containing wiring structure 58, and other connection openings physically expose either the top surface of the metal-containing cap 28P or, in the absence of the metal-containing cap 28P, the top surface of the second superconductor material portion 26P of the JJ structure. The connection openings can be formed by lithography and etching.

[0066] Each of the metal-containing connection structures (62Y, 62Z) can be composed of a connection metal or a connection metal alloy. Examples of connection metals include, but are not limited to, tungsten (W), aluminum (Al), or copper (Cu). An example of a connection metal alloy is a Cu-Al alloy. In some embodiments, the superconductors described above can be used in providing the respective metal-containing connection structures. The superconductors may be a preferred material for the connection structures (62Y, 62Z) because they would reduce heat consumption and overheating of the chip. As shown, each of the metal-containing connection structures (62Y, 62Z) has a top surface coplanar with the top surface of the second dielectric material layer 60.

[0067] Each of the metal-containing connection structures (62Y, 62Z) can be formed by filling the connection openings with a conductive material that provides the metal-containing connection structures (62Y, 62Z). In some embodiments, a planarization process can follow the deposition of the material that provides the metal-containing wiring structures (62Y, 62Z).

[0068] In embodiments of the present invention, each of the metal-containing connection structures 62Z connects to one surface of the metal connection wiring structure 58, and each of the metal-containing connection structures 62Y connects to the top surface of the metal-containing cap 28P or the top surface of one of the second superconductor material portions 26P. The metal-containing connection structure 62Z can be referred to as a wiring connection structure, while each of the metal-containing connection structures 62Y can be referred to as a JJ connection structure.

[0069] While the present invention has been particularly shown and described with reference to its preferred embodiments, it will be understood by those skilled in the art that the above and other changes in form and detail may be made without departing from the scope of the present invention. Accordingly, the present invention is not intended to be limited to the exact forms and details described, but is intended to fall within the scope of the appended claims.

[0070] In a preferred embodiment of the present invention, there is provided a method of forming a computing device, the method comprising: forming a conductive plate in a semiconductor substrate; forming at least one Josephson junction (JJ) structure on the conductive plate; forming a first dielectric material layer adjacent to the at least one JJ structure laterally, the first dielectric material layer including a wiring structure embedded therein and connected to the semiconductor substrate; and forming a second dielectric material layer on the first dielectric material layer and on the at least one JJ structure, the second dielectric material layer including a wiring connection structure and a JJ connection structure, the wiring connection structure being connected to the wiring structure, and the JJ connection structure being connected to the JJ structure. Preferably, forming the JJ structure includes: forming a precursor JJ material stack including a first superconducting material layer, an amorphous silicon-containing manganese layer, and a second superconducting material layer; converting the precursor JJ material stack into a JJ material stack, the conversion including annealing to convert the amorphous silicon-containing manganese layer into a Mn nanoparticle-containing crystalline silicon layer, and patterning the JJ stack. The method preferably further includes forming a JJ structure encapsulated with a dielectric spacer before forming the second dielectric material layer.

Claims

1. A computing device, comprising: a conductive plate embedded in a surface of a semiconductor substrate; at least one magnetic Josephson junction (JJ) structure disposed on the conductive plate; and a first wiring structure laterally adjacent to the at least one magnetic JJ structure, wherein the strength of a magnetic field induced in the at least one magnetic JJ structure is controlled according to the amount of current flowing through the first wiring structure by one of the conductive plate or the first wiring structure.

2. The computing device according to claim 1, wherein the first wiring structure is directly connected to a surface of the conductive plate, the at least one magnetic JJ structure is separated from the conductive plate, and the conductive plate induces the magnetic field with respect to the at least one magnetic JJ structure.

3. The computing device according to claim 1, wherein the first wiring structure is directly connected to a surface of the semiconductor substrate, the at least one magnetic JJ structure is disposed on a surface of the conductive plate, and the first wiring structure induces the magnetic field.

4. The computing device according to claim 3, further comprising a wiring connection structure connected to each first wiring structure and a JJ connection structure connected to the at least one magnetic JJ structure.

5. The computing device according to any one of claims 1 to 4, wherein the conductive plate is made of an electrically conductive metal, an electrically conductive metal alloy, or a superconductor material.

6. The computing device according to any one of claims 1 to 5, wherein the first wiring structure is made of an electrically conductive metal, an electrically conductive metal alloy, or a superconductor material.

7. The computing device according to any one of claims 1 to 6, further comprising a dielectric spacer encapsulating the at least one magnetic JJ structure.

8. The computing device according to any one of claims 1 to 7, wherein the at least one magnetic JJ structure includes a first superconductor material portion, a Mn nanoparticle-containing crystalline silicon portion, and a second superconductor material portion.

9. 10. The computing device of claim 8, further comprising a metal-containing cap disposed on the second superconductor material portion of the at least one magnetic JJ structure.

10. The computing device of any preceding claim, wherein the at least one magnetic JJ structure is cylindrical in shape.

11. 1. A computing device comprising: a conductive plate embedded in the surface of a semiconductor substrate; at least one magnetic Josephson junction (JJ) structure disposed above and spaced apart from the conductive plate; a first wiring structure laterally adjacent to the at least one magnetic JJ structure and directly connected to a surface of the conductive plate; the conductive plate induces a magnetic field in the at least one magnetic JJ structure upon application of a current thereto, the at least one magnetic JJ structure being disposed on a surface of a second wiring structure that is laterally spaced apart from the first wiring structure and is vertically spaced apart from the conductive plate.

12. 12. The computing device of claim 11, wherein the at least one magnetic JJ structure has critical dimensions that are smaller than critical dimensions of the second wiring structure.

13. The computing device of claim 11 , further comprising a wire connection structure connecting to each first wire structure and a JJ connection connecting to the at least one magnetic JJ structure.

14. 1. A method of forming a computing device, the method comprising: forming a conductive plate in a semiconductor substrate; forming a first dielectric material layer over the semiconductor substrate and the physically exposed surface of the conductive plate, the first dielectric material layer including a via opening that physically exposes a surface of the conductive plate; forming a metal-containing layer within each of the via openings and on a top surface of the first dielectric material layer; patterning the metal-containing layer to provide first and second metal-containing wiring structures, the first metal-containing wiring structure connecting to the conductive plate and the second metal-containing wiring structure being separate and spaced apart from the conductive plate; forming a magnetic Josephson junction (JJ) structure on each second metal-containing wiring structure; and Forming a second dielectric material layer on top of the magnetic JJ structure adjacent to the side of each magnetic JJ structure, the second dielectric material layer including a wiring connection structure and a JJ connection structure embedded in the second dielectric material layer, and the wiring connection structure connecting to the first metal-containing wiring structure and the JJ connection structure connecting to the magnetic JJ structure Method **Claim 15** Forming the magnetic JJ structure includes Forming a precursor JJ material stack including a first superconducting material layer, an amorphous silicon-containing manganese layer, and a second superconducting material layer Converting the precursor JJ material stack into a JJ material stack, the conversion including annealing to convert the amorphous silicon-containing manganese layer into a crystalline silicon layer containing Mn nanoparticles, the converting and Patterning the JJ material stack The method according to claim 14, including **Claim 16** The method according to claim 14, further including forming a magnetically encapsulated JJ structure encapsulated with a dielectric spacer before forming the second dielectric material layer **Claim 17** The method according to claim 14, further including forming a gap filling dielectric material in a gap disposed between the first and second wiring structures respectively

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