Transmission / reception switching circuit and wireless communication terminal

Abstract

The present invention improves the performance of a wireless communication terminal in which an antenna is connected to a transmission circuit and a reception circuit.　This transmission-reception switching circuit comprises a first N-type transistor and a second N-type transistor. The drain of the first N-type transistor is connected to an antenna, and a certain voltage is applied to the gate of the first N-type transistor. In addition, the drain of the second N-type transistor is connected to the source of the first N-type transistor, and a transmission signal is inputted to the gate of the second N-type transistor. In addition, a reception signal is supplied from one of the source and drain of the second N-type transistor.

Description

[Technical Field]

[0001] The present technology relates to a transmission / reception switching circuit, and more particularly to a transmission / reception switching circuit that switches between transmission and reception, and a wireless communication terminal. [Background technology]

[0002] Conventionally, when connecting a single antenna to a transmitting circuit and a receiving circuit, a transmitting / receiving switching circuit that switches between transmitting and receiving has been placed in front of the antenna. For example, a transmitting / receiving switching circuit has been proposed in which a quarter-wave transmission line is inserted between the antenna and each of the transmitting circuit and the receiving circuit (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2014-49964 Summary of the Invention [Problem to be solved by the invention]

[0004] The above-mentioned conventional technology attempts to realize a low-loss transmission / reception system by inserting a quarter-wavelength transmission line. However, when a quarter-wavelength transmission line is implemented at a radio frequency of about 1 gigahertz (GHz), a line length of about 75 millimeters (mm) is required, making it impractical to configure it within an integrated circuit (IC). Furthermore, even if the transmission line is placed outside the IC, the size becomes significant. Furthermore, since the line length of the quarter-wavelength transmission line varies depending on the radio frequency, the bandwidth is essentially limited. As such, it is difficult to improve the performance of a wireless communication terminal equipped with the above-mentioned transmission / reception circuit.

[0005] The present technology was developed in light of these circumstances, and aims to improve the performance of a wireless communication terminal in which an antenna is connected to a transmitting circuit and a receiving circuit. [Means for solving the problem]

[0006] The present technology has been made to solve the above-mentioned problems, and a first aspect thereof relates to a first N-type transistor having a drain connected to an antenna and a gate to which a constant voltage is applied, and a second N-type transistor having a drain connected to a source of the first N-type transistor, a gate to which a transmission signal is input, and a reception signal supplied from one of the source and drain; This brings about an effect that the performance of the transmission / reception switching circuit is improved.

[0007] Moreover, in this first aspect, the power supply may further include a first P-type transistor, a second P-type transistor, a third P-type transistor, and a third N-type transistor, wherein the transmission signal includes first and second transmission signals of the same phase, a third inverter consisting of the third P-type transistor and the third N-type transistor, and a second inverter consisting of the second P-type transistor and the second N-type transistor are connected in series to a power supply terminal, the first transmission signal is input to an input terminal of the third inverter, an output terminal of the third inverter is connected to a source of the first P-type transistor, the second transmission signal is input to an input terminal of the second inverter, an output terminal of the second inverter is connected to the source of the first N-type transistor, an input terminal of the first inverter consisting of the first P-type transistor and the first N-type transistor is connected to a connection node of the second and third inverters, and an output terminal of the first inverter is connected to the antenna. This allows part of the power amplifier section, which consists of three inverters, to function as a switch.

[0008] In addition, in this first aspect, the power supply may further include a first internal amplifier capacitance inserted between the input terminal of the second inverter and the input terminal of the third inverter, and a second internal amplifier capacitance inserted between the output terminal of the second inverter and the output terminal of the third inverter, thereby ensuring the in-phase of the first and second transmission signals.

[0009] In addition, in this first aspect, the power supply may further include a DC (Direct Current) cut capacitor inserted between the output terminal of the first inverter and the antenna, thereby providing the effect of cutting DC components.

[0010] In addition, in this first aspect, the power supply may further include a matching circuit inserted between the output terminal of the first inverter and the antenna, thereby achieving impedance matching.

[0011] In addition, in this first aspect, the antenna may further include a filter circuit inserted between the output terminal of the first inverter and the antenna, thereby providing the effect of filtering the transmission signal.

[0012] In addition, in this first aspect, a switching unit may be further provided that opens and closes a path between the source of the second N-type transistor and a ground terminal in accordance with a predetermined enable signal, thereby providing an effect of short-circuiting between the source of the second N-type transistor and the ground terminal.

[0013] In this first aspect, the switching unit may open and close a path between the source of the second N-type transistor and the ground terminal in accordance with the enable signal, thereby providing an effect of isolating a receiving circuit.

[0014] In this first aspect, the switching unit may further include a predetermined number of fifth transistors that open and close a path between the source of the second N-type transistor and a receiving circuit that processes the received signal in accordance with the enable signal, thereby providing an effect of isolating the receiving circuit.

[0015] In this first aspect, the switching unit may further include a shunt switch that opens or closes a path between a connection node between the fifth transistor and the receiving circuit and a ground terminal in accordance with the enable signal, thereby improving insulation of the receiving circuit.

[0016] In addition, in this first aspect, an inductor may be further provided between a power supply terminal and the drain of the first N-type transistor, thereby causing the power amplifier section in which the cascode-connected transistors are arranged to function as a switch.

[0017] In addition, in this first aspect, the amplifier may further include a matching circuit inserted between the antenna and a connection node of the first N-type transistor and the inductor, thereby achieving impedance matching.

[0018] In addition, in this first aspect, the power amplifier may further include a filter circuit inserted between the antenna and a connection node between the first N-type transistor and the inductor, thereby achieving impedance matching.

[0019] In addition, in this first aspect, a predetermined number of fourth transistors may be further provided, which open and close a path between the source of the second N-type transistor and a ground terminal in accordance with the enable signal, thereby ensuring the withstand voltage of the second N-type transistor.

[0020] In addition, in this first aspect, a switching unit may be further provided that opens and closes a path between a connection node of the first and second N-type transistors and a receiving circuit that processes the received signal in accordance with a predetermined enable signal, thereby providing the effect of isolating the receiving circuit.

[0021] In this first aspect, the switching unit may include a predetermined number of fifth transistors that open and close a path between the connection node of the first and second N-type transistors and the receiving circuit in accordance with the enable signal, thereby providing an effect of isolating the receiving circuit.

[0022] A second aspect of the present technology is a wireless communication terminal including a first N-type transistor having a drain connected to an antenna and a gate to which a constant voltage is applied, a second N-type transistor having a drain connected to the source of the first N-type transistor, a gate to which a transmission signal is input, and a reception signal supplied from one of the source and drain, a transmission circuit that supplies the transmission signal, and a reception circuit that processes the reception signal, thereby improving the performance of the wireless communication terminal. [Brief explanation of the drawings]

[0023] [Figure 1] 1 is a block diagram showing an example of the configuration of a wireless communication terminal according to a first embodiment of the present technology. [Figure 2] 1 is a circuit diagram showing an example of the configuration of a transmission / reception switching circuit according to a first embodiment of the present technology. [Figure 3] 4A and 4B are diagrams for explaining the operation of the transmission / reception switching circuit according to the first embodiment of the present technology. [Figure 4] 10 is a circuit diagram showing a configuration example of a transmission / reception switching circuit according to a first modified example of the first embodiment of the present technology. FIG. [Figure 5] 10 is a circuit diagram showing a configuration example of a transmission / reception switching circuit according to a second modified example of the first embodiment of the present technology. FIG. [Figure 6]10 is a circuit diagram showing a configuration example of a transmission / reception switching circuit according to a third modified example of the first embodiment of the present technology. FIG. [Figure 7] FIG. 10 is a circuit diagram showing a configuration example of a transmission / reception switching circuit according to a fourth modified example of the first embodiment of the present technology. [Figure 8] FIG. 10 is a circuit diagram showing a configuration example of a transmission / reception switching circuit according to a fifth modified example of the first embodiment of the present technology. [Figure 9] FIG. 13 is a circuit diagram showing a configuration example of a transmission / reception switching circuit provided with a filter circuit according to a fifth modified example of the first embodiment of the present technology. [Figure 10] 10 is a circuit diagram showing an example of the configuration of a transmission / reception switching circuit according to a second embodiment of the present technology. FIG. [Figure 11] 10 is a circuit diagram showing a configuration example of a transmission / reception switching circuit according to a first modified example of the second embodiment of the present technology. FIG. [Figure 12] 13 is a circuit diagram showing a configuration example of a transmission / reception switching circuit provided with a filter circuit according to a first modified example of the second embodiment of the present technology. FIG. [Figure 13] FIG. 10 is a circuit diagram showing a configuration example of a transmission / reception switching circuit according to a second modified example of the second embodiment of the present technology. [Figure 14] FIG. 10 is a circuit diagram showing a configuration example of a transmission / reception switching circuit according to a third modified example of the second embodiment of the present technology. [Figure 15] FIG. 10 is a circuit diagram showing a configuration example of a transmission / reception switching circuit according to a fourth modified example of the second embodiment of the present technology. [Figure 16] FIG. 1 is a diagram illustrating an example of a schematic configuration of an IoT system to which the technology according to the present disclosure can be applied. DETAILED DESCRIPTION OF THE INVENTION

[0024] Hereinafter, modes for carrying out the present technology (hereinafter referred to as embodiments) will be described. The description will be made in the following order. 1. First embodiment (example in which three inverters are arranged in the power amplifier section) 2. Second embodiment (example in which a cascode transistor is arranged in the power amplifier section) 3. Application Examples

[0025] <1. First embodiment> [Example of wireless communication terminal configuration] 1 is a block diagram showing an example of a configuration of a wireless communication terminal 100 according to a first embodiment of the present technology. The wireless communication terminal 100 is a terminal that performs wireless communication, and includes a transceiver 110, an antenna 120, and a microcomputer .

[0026] The transceiver 110 is a circuit that performs transmission and reception, and includes a transmission circuit 111, a reception circuit 112, and a transmission / reception switching circuit 200.

[0027] The transmission circuit 111 generates an RF (Radio Frequency) signal as a transmission signal using a mixer, a DAC (Digital to Analog Converter), etc. The transmission circuit 111 supplies the transmission signal to the transmission / reception switching circuit 200 via a signal line 208.

[0028] The receiving circuit 112 acquires an RF signal from the antenna 120 as a received signal via the transmission / reception switching circuit 200 and processes the signal. The receiving circuit 112 performs demodulation processing and AD (Analog to Digital) conversion processing using a mixer, an ADC (Analog to Digital Converter), etc.

[0029] The transmission / reception switching circuit 200 switches between transmission and reception under the control of the microcomputer 130. The transmission / reception switching circuit 200 supplies a transmission signal from the transmission circuit 111 to the antenna 120, and supplies a reception signal from the antenna 120 to the reception circuit 112 via a signal line 209.

[0030] The antenna 120 converts a transmission signal into an electromagnetic wave and converts the electromagnetic wave into a reception signal. The antenna 120 exchanges the transmission signal and reception signal with the transmission / reception switching circuit 200 via a signal line 129.

[0031] The microcomputer 130 controls the operation of the transceiver 110 .

[0032] [Example of configuration of transmission / reception switching circuit] 2 is a circuit diagram showing an example of the configuration of the transmission / reception switching circuit 200 according to the first embodiment of the present technology. The transmission / reception switching circuit 200 includes a power amplifier unit 205 and a switching unit 250.

[0033] The power amplifier section 205 includes inverters 210, 220, and 230. The inverter 210 is composed of a pMOS (p-channel Metal Oxide Semiconductor) transistor 211 and an nMOS (n-channel MOS) transistor 212. The inverter 220 is composed of a pMOS transistor 221 and an nMOS transistor 222. The inverter 230 is composed of a pMOS transistor 231 and an nMOS transistor 232.

[0034] The inverter 210 is an example of a first inverter as defined in the claims, the inverter 220 is an example of a second inverter as defined in the claims, and the inverter 230 is an example of a third inverter as defined in the claims.

[0035] The inverters 230 and 220 are connected in series to a power supply terminal of the power supply voltage VDD. In other words, the pMOS transistor 231, the nMOS transistor 232, the pMOS transistor 221, and the nMOS transistor 222 are connected in series to the power supply terminal.

[0036] Furthermore, a transmission signal IN1 from the transmission circuit 111 is input to the gates of the pMOS transistor 231 and the nMOS transistor 232 (i.e., the input terminal of the inverter 230). A transmission signal IN2 from the transmission circuit 111 is input to the gates of the pMOS transistor 221 and the nMOS transistor 222 (i.e., the input terminal of the inverter 220). In-phase rectangular waves (in other words, pulse signals) are used as the transmission signals IN1 and IN2.

[0037] Furthermore, the connection node between the pMOS transistor 231 and the nMOS transistor 232 (i.e., the output terminal of the inverter 230) is connected to the source of the pMOS transistor 211. The connection node between the pMOS transistor 221 and the nMOS transistor 222 (i.e., the output terminal of the inverter 220) is connected to the source of the nMOS transistor 212.

[0038] The gates of the pMOS transistor 211 and the nMOS transistor 212 (i.e., the input terminal of the inverter 210) are connected to the connection node of the inverters 230 and 220. The connection node of the pMOS transistor 211 and the nMOS transistor 212 (i.e., the output terminal of the inverter 210) is connected to the antenna 120.

[0039] With the above-mentioned connections, the power amplifier unit 205 functions as a D-class power amplifier that amplifies and outputs a pulse signal.

[0040] The pMOS transistor 211 and the nMOS transistor 212 are examples of the first P-type transistor and the first N-type transistor set forth in the claims. The pMOS transistor 221 and the nMOS transistor 222 are examples of the second P-type transistor and the second N-type transistor set forth in the claims. The pMOS transistor 231 and the nMOS transistor 232 are examples of the third P-type transistor and the third N-type transistor set forth in the claims.

[0041] The switching unit 250 includes nMOS transistors 251 and 252. The nMOS transistor 251 opens and closes the path between the source of the nMOS transistor 222 and the ground terminal in accordance with an enable signal xEN_Rx input to the gate.

[0042] The nMOS transistor 252 opens and closes the path between the source of the nMOS transistor 222 and the receiving circuit 112 in accordance with the enable signal EN_Rx input to the gate.

[0043] Here, the enable signal xEN_Rx is an inverted signal of the enable signal EN_Rx. These enable signals EN_Rx and xEN_Rx are generated by the microcomputer 130 or the like. When the transceiver 110 receives, the microcomputer 130 sets the enable signal EN_Rx to a high level (enable). On the other hand, when the transceiver 110 transmits, the microcomputer 130 sets the enable signal EN_Rx to a low level (disable).

[0044] With the above-described connection, when the enable signal EN_Rx is at a low level (disabled), the nMOS transistor 251 transitions to a closed state (i.e., an on state), and the nMOS transistor 252 transitions to an open state (i.e., an off state). When the nMOS transistor 251 is turned on, the source of the nMOS transistor 222 on the receiving side of the power amplifier unit 205 is shorted to the ground terminal, and the potential of the source becomes 0 volts (V). When the nMOS transistor 252 is turned off, the receiving circuit 112 is isolated from the power amplifier unit 205.

[0045] On the other hand, when the enable signal EN_Rx is at a high level (enabled), the nMOS transistor 251 transitions to an open state (off state), and the nMOS transistor 252 transitions to a closed state (on state). As a result, the received signal OUT is supplied to the receiving circuit 112.

[0046] It is also possible to replace the nMOS transistors 251 and 252 with pMOS transistors, in which case a low level enable signal EN_Rx is input when enabled.

[0047] The nMOS transistor 251 is an example of a fourth transistor as defined in the claims, and the nMOS transistor 252 is an example of a fifth transistor as defined in the claims.

[0048] 3 is a diagram for explaining the operation of the transmission / reception switching circuit 200 according to the first embodiment of the present technology. The transmission signals IN1 and IN2 oscillate between 0 volts (V) and VDD. In the figure, "a" indicates the state of the power amplifier unit 205 when the transmission signals IN1 and IN2 are at VDD. "b" in the figure indicates the state of the power amplifier unit 205 when the transmission signals IN1 and IN2 are at 0 volts (V).

[0049] As shown in the diagram a, when the transmission signals IN1 and IN2 are VDD, the pMOS transistors 211, 221, and 231 transition to the OFF state, and the nMOS transistors 212, 222, and 232 transition to the ON state. The level of the output terminal of the inverter 230 becomes VDD / 2, and the level of the output terminal of the inverter 220 becomes 0 volts (V). The level of the input terminal of the inverter 220 becomes VDD / 2, and the level of its output terminal becomes 0 volts (V).

[0050] As shown in FIG. 1B, when the transmission signals IN1 and IN2 are 0 volts (V), the pMOS transistors 211, 221, and 231 transition to the ON state, and the nMOS transistors 212, 222, and 232 transition to the OFF state. The level of the output terminal of the inverter 230 becomes VDD, and the level of the output terminal of the inverter 220 becomes VDD / 2 volts (V). The level of the input terminal of the inverter 220 becomes VDD / 2, and the level of its output terminal becomes VDD.

[0051] As shown in the figure, by inputting in-phase transmission signals IN1 and IN2, the output of inverter 230 swings between VDD and VDD / 2, and the output of inverter 220 swings between VDD / 2 and 0. Furthermore, the input to inverter 210 is always VDD / 2 voltage. Although the output of inverter 210 is VDD or 0 volts (V), the maximum voltage applied to pMOS transistor 211 and nMOS transistor 212 is VDD / 2, so that transistors with a lower breakdown voltage can be used. This enables highly efficient operation.

[0052] As described above, when the transceiver 110 transmits, the microcomputer 130 sets the enable signal EN_Rx to low level (disables it). The switching unit 250 blocks the received signal, and the transmitting circuit 111 supplies in-phase transmission signals IN1 and IN2.

[0053] On the other hand, when the transceiver 110 performs reception, the microcomputer 130 sets the enable signal EN_Rx to high level (enable). The switching unit 250 supplies the reception signal OUT to the reception circuit 112. At this time, the transmission circuit 111 sets the transmission signals IN1 and IN2 to VDD during the reception period, and turns on the nMOS transistors 212 and 222, as illustrated in a in the figure.

[0054] In this way, part of the power amplifier section 205 (nMOS transistors 212 and 222) also functions as a switch to switch between transmission and reception. This reduces the area of ​​the integrated circuit compared to when a switch is inserted after the power amplifier section 205, and can reduce insertion loss caused by signals passing through the transmission / reception switching circuit 200 during signal transmission.

[0055] Furthermore, as will be described later in the second embodiment, a transmission / reception system can be configured in a compact size without impairing high efficiency characteristics even in a configuration using a versatile cascode power amplifier.A transmission / reception system can be configured in a compact size without impairing high efficiency characteristics even in a configuration using a class D power amplifier that can operate with thin film transistors with good characteristics.

[0056] These effects can improve the performance of the wireless communication terminal 100.

[0057] As described above, according to the first embodiment of the present technology, the nMOS transistors 212 and 222 in the power amplifier unit 205 function as a switch for switching between transmission and reception, thereby making it possible to reduce the area of ​​the integrated circuit, reduce loss, and improve efficiency, thereby improving the performance of the wireless communication terminal 100.

[0058] [First Modification] In the first embodiment described above, the nMOS transistors 251 and 252 are arranged in the switching unit 250, but because part of the power amplifier unit 205 functions as a switch, it is possible to eliminate the nMOS transistor 252. The transmission / reception switching circuit 200 in this first modification of the first embodiment differs from the first embodiment in that the nMOS transistor 252 is eliminated.

[0059] 4 is a circuit diagram showing an example configuration of a transmission / reception switching circuit 200 in a first modified example of the first embodiment of the present technology. The transmission / reception switching circuit 200 in this first modified example of the first embodiment differs from the first embodiment in that an nMOS transistor 252 is not arranged in the switching unit 250. The source of the nMOS transistor 252 is connected to the receiving circuit 112.

[0060] As described above, according to the first modification of the first embodiment of the present technology, the nMOS transistor 252 in the switching unit 250 is reduced, and therefore the circuit size can be reduced accordingly.

[0061] [Second Modification] In the first embodiment described above, in-phase transmission signals IN1 and IN2 are input to the power amplifier unit 205, but a phase shift between these signals can occur, resulting in a deterioration in communication quality. The transmission / reception switching circuit 200 in this second modification of the first embodiment differs from the first embodiment in that a capacitor is provided to ensure that the transmission signals IN1 and IN2 are in phase.

[0062] 5 is a circuit diagram showing a configuration example of a transmission / reception switching circuit 200 in a second modified example of the first embodiment of the present technology. The transmission / reception switching circuit 200 in the second modified example of the first embodiment differs from the first embodiment in that it further includes capacitors 241 and 242, an nMOS transistor 253, and a resistor 261.

[0063] The capacitor 241 is inserted between the input terminal of the inverter 230 and the input terminal of the inverter 220. For example, a feedthrough capacitor through which a signal line connected to the connection node of the inverters 230 and 220 passes is used as the capacitor 241.

[0064] The capacitor 242 is inserted between the output terminal of the inverter 230 and the output terminal of the inverter 220. For example, a feedthrough capacitor through which a signal line connected to the connection node of the inverters 230 and 220 passes is used as the capacitor 242.

[0065] The in-phase of the transmission signals IN1 and IN2 can be ensured by inserting the capacitors 241 and 242. The capacitors 241 and 242 are an example of the first and second amplifier internal capacitances set forth in the claims.

[0066] The nMOS transistors 252 and 253 are connected in series between the source of the nMOS transistor 222 and the receiving circuit 112. The enable signal EN_Rx is input to the gates of these nMOS transistors 252 and 253.

[0067] When the enable signal EN_Rx is at a low level (disabled), both nMOS transistors 252 and 253 are turned off, thereby improving insulation compared to the case where only nMOS transistor 252 is used. Note that, although two nMOS transistors are connected in series between the source of nMOS transistor 222 and receiving circuit 112, three or more nMOS transistors can also be connected in series.

[0068] Furthermore, each of the nMOS transistors 251 to 253 can be replaced with a pMOS transistor. In this case, a low-level enable signal EN_Rx is input when enabled.

[0069] The nMOS transistor 253 is an example of the fifth transistor described in the claims.

[0070] Furthermore, a resistor 261 is inserted between the connection node of the nMOS transistor 253 and the receiving circuit 112 and the ground terminal.

[0071] As described above, according to the second modification of the first embodiment of the present technology, the capacitors 241 and 242 are inserted between the input / output terminals of the inverters 230 and 220, thereby ensuring the in-phase of the transmission signals IN1 and IN2 and improving communication quality. Furthermore, the addition of the nMOS transistor 253 can improve insulation.

[0072] [Third Modification] In the second modification of the first embodiment described above, the receiving circuit 112 is insulated by the nMOS transistors 252 and 253, but a leakage current may flow through the nMOS transistors 252 and 253 in the off state, resulting in insufficient insulation. The transmit / receive switching circuit 200 in this third modification of the first embodiment differs from the second modification of the first embodiment in that the insulation is improved by adding nMOS transistors.

[0073] 6 is a circuit diagram showing a configuration example of a transmission / reception switching circuit 200 according to a third modified example of the first embodiment of the present technology. The transmission / reception switching circuit 200 according to the third modified example of the first embodiment differs from the second modified example of the first embodiment in that it further includes an nMOS transistor 254.

[0074] The nMOS transistor 254 opens and closes a path between the connection node between the nMOS transistor 254 and the receiving circuit 112 and the ground terminal in accordance with the enable signal xEN_Rx. The enable signal xEN_Rx is input to the gate of this nMOS transistor 254. The nMOS transistor 254 functions as a shunt switch that passes leakage current to the ground terminal when disabled. This can further improve insulation.

[0075] Furthermore, each of the nMOS transistors 251 to 254 can be replaced with a pMOS transistor. In this case, a low-level enable signal EN_Rx is input when enabled.

[0076] As described above, according to the third modified example of the first embodiment of the present technology, the nMOS transistor 254 (shunt switch) is added, so that the insulation of the receiving circuit 112 can be further improved.

[0077] [Fourth Variation] In the second modification of the first embodiment described above, the power amplifier unit 205 is directly connected to the antenna 120, but this configuration may cause a DC (Direct Current) component to occur in the transmission signal. The transmission / reception switching circuit 200 in this fourth modification of the first embodiment differs from the second modification of the first embodiment in that a capacitance is further arranged in a stage preceding the antenna 120.

[0078] 7 is a circuit diagram showing a configuration example of a transmission / reception switching circuit 200 according to a fourth modified example of the first embodiment of the present technology. The transmission / reception switching circuit 200 according to the fourth modified example of the first embodiment differs from the second modified example of the first embodiment in that it further includes an nMOS transistor 271.

[0079] The source and drain of the nMOS transistor 271 are connected to the output terminal of the inverter 210. The gate of the nMOS transistor 271 is connected to the antenna 120. In other words, the MOS capacitance of the nMOS transistor 271 is inserted between the output terminal of the inverter 210 and the antenna 120. By inserting this MOS capacitance, it is possible to cut off DC components. Note that a capacitor can also be inserted instead of the MOS capacitance of the nMOS transistor 271.

[0080] The MOS capacitance of the nMOS transistor 271 is an example of a DC cut capacitance as defined in the claims.

[0081] As described above, according to the fourth modified example of the first embodiment of the present technology, the MOS capacitance of the nMOS transistor 271 is inserted in the front stage of the antenna 120, so that the DC component can be cut.

[0082] [Fifth Modification] In the second modification of the first embodiment described above, the power amplifier unit 205 is directly connected to the antenna 120, but impedance matching may be required between them. The transmission / reception switching circuit 200 in this fifth modification of the first embodiment differs from the second modification of the first embodiment in that a circuit for matching impedance is further provided.

[0083] 8 is a circuit diagram showing a configuration example of a transmission / reception switching circuit 200 according to a fifth modified example of the first embodiment of the present technology. The transmission / reception switching circuit 200 according to the fifth modified example of the first embodiment differs from the second modified example of the first embodiment in that it further includes a capacitor 272 and a matching circuit 281.

[0084] Capacitor 272 and matching circuit 281 are inserted between power amplifier section 205 and antenna 120. Matching circuit 281 matches the impedance between power amplifier section 205 and antenna 120. Adding matching circuit 281 can improve transmission efficiency and suppress signal reflection.

[0085] 9, a filter circuit 282 can be arranged instead of the capacitor 272 and the matching circuit 281. A low-pass filter, a band-pass filter, or the like can be assumed as the filter circuit 282. Also, the matching circuit 281 can be arranged in the power amplifier unit 205 (for example, in the previous stage of the inverter 210).

[0086] 2 and 4 to 9 and the configurations of the other circuits (such as the switching unit 250 and the matching circuit 281) can be combined as needed. For example, the switching unit 250 in FIG. 4 can be combined with the power amplifier unit 205 in FIG. 5.

[0087] As described above, according to the fifth modification of the first embodiment of the present technology, the matching circuit 281 is added, so that it is possible to improve transmission efficiency and suppress signal reflection.

[0088] <2. Second embodiment> In the first embodiment described above, three inverters (inverters 210, 220, and 230) are arranged in the power amplifier unit 205, but instead of these inverters, a pair of cascode-connected transistors can also be arranged. The transmission / reception switching circuit 200 in this second embodiment differs from the first embodiment in that a pair of cascode-connected transistors is used.

[0089] 10 is a circuit diagram showing a configuration example of a transmission / reception switching circuit 200 according to a second embodiment of the present technology. In this second embodiment, an inductor 245 and nMOS transistors 212 and 222 are arranged in a power amplifier unit 205 instead of inverters 210, 220, and 230. Also, only an nMOS transistor 252 is arranged in a switching unit 250.

[0090] The inductor 245 and the nMOS transistors 212 and 222 are connected in series between a power supply terminal and a ground terminal. A constant bias voltage V_Bias is applied to the gate of the nMOS transistor 212. The transmission signal IN from the transmission circuit 111 is input to the gate of the nMOS transistor 222.

[0091] Furthermore, the nMOS transistor 252 in the switching unit 250 opens and closes the path between the connection node of the nMOS transistors 212 and 222 and the receiving circuit 112 in accordance with the enable signal EN_Rx. The nMOS transistor 252 can also be replaced with a pMOS transistor. In this case, a low-level enable signal EN_Rx is input when enabled.

[0092] Furthermore, in the second embodiment, when the transceiver 110 performs reception, the transmission circuit 111 sets the transmission signal IN to a low level during the reception period, and turns off the nMOS transistor 222.

[0093] As shown in the figure, by arranging an inductor 245 and nMOS transistors 212 and 222 instead of the inverters 210, 220 and 230, the number of transistors can be reduced compared to when three inverters are used.

[0094] As described above, according to the second embodiment of the present technology, the inductor 245 and the nMOS transistors 212 and 222 are used instead of three inverters, so that the number of transistors can be reduced.

[0095] [First Modification] In the second embodiment described above, the power amplifier unit 205 is directly connected to the antenna 120, but impedance matching may be required between them. The transmit / receive switching circuit 200 in the first modification of the second embodiment differs from the second embodiment in that a circuit for matching impedance is further provided.

[0096] 11 is a circuit diagram showing an example configuration of a transmission / reception switching circuit 200 in a first modified example of the second embodiment of the present technology. The transmission / reception switching circuit 200 in the first modified example of the second embodiment differs from the second embodiment in that it further includes a matching circuit 281. The matching circuit 281 is inserted between the power amplifier unit 205 and the antenna 120.

[0097] As shown in FIG. 12, a filter circuit 282 may be provided in place of the matching circuit 281.

[0098] As described above, according to the first modified example of the second embodiment of the present technology, the matching circuit 281 is added, so that it is possible to improve transmission efficiency and suppress signal reflection.

[0099] [Second Modification] In the second embodiment described above, the nMOS transistor 252 is arranged in the switching unit 250, but it is possible to eliminate the nMOS transistor 252. The transmission / reception switching circuit 200 in the second modification of the second embodiment differs from the second embodiment in that the nMOS transistor 252 is eliminated.

[0100] 13 is a circuit diagram showing a configuration example of a transmission / reception switching circuit 200 in a second modified example of the second embodiment of the present technology. The transmission / reception switching circuit 200 in the second modified example of the second embodiment differs from the second embodiment in that the nMOS transistor 252 is not provided. The connection node of the nMOS transistors 212 and 222 is connected to the receiving circuit 112.

[0101] As described above, according to the second modification of the second embodiment of the present technology, the nMOS transistor 252 in the switching unit 250 is reduced, and therefore the circuit size can be reduced accordingly.

[0102] [Third Modification] In the second embodiment described above, the receiving circuit 112 is insulated by the nMOS transistor 252, but a leakage current may flow through the nMOS transistor 252 in the off state, resulting in insufficient insulation. The transmit / receive switching circuit 200 in this third modification of the second embodiment differs from the second embodiment in that the insulation is improved by adding an nMOS transistor.

[0103] 14 is a circuit diagram showing a configuration example of a transmission / reception switching circuit 200 according to a third modified example of the second embodiment of the present technology. The transmission / reception switching circuit 200 according to the third modified example of the second embodiment differs from the second embodiment in that it further includes an nMOS transistor 253.

[0104] The nMOS transistors 252 and 253 are connected in series between the connection node of the nMOS transistors 212 and 222 and the receiving circuit 112. The enable signal EN_Rx is input to the gates of these nMOS transistors 252 and 253.

[0105] Although two nMOS transistors are connected in series between the connection node of the nMOS transistors 212 and 222 and the receiving circuit 112, three or more nMOS transistors can also be connected in series.

[0106] It is also possible to replace the nMOS transistors 252 and 253 with pMOS transistors, in which case a low level enable signal EN_Rx is input when enabled.

[0107] As described above, according to the third modification of the second embodiment of the present technology, the addition of the nMOS transistor 253 can improve insulation.

[0108] [Fourth Variation] In the third modification of the second embodiment described above, the nMOS transistors 212 and 222 are cascode-connected, but it may be difficult to ensure the withstand voltage of the nMOS transistor 212 on the ground side during reception. The transmit / receive switching circuit 200 in this fourth modification of the second embodiment differs from the third modification of the second embodiment in that the withstand voltage is ensured by connecting nMOS transistors in series.

[0109] 15 is a circuit diagram showing a configuration example of a transmission / reception switching circuit 200 according to a fourth modified example of the second embodiment of the present technology. The transmission / reception switching circuit 200 according to the fourth modified example of the second embodiment differs from the third modified example of the second embodiment in that it further includes an nMOS transistor 246.

[0110] The nMOS transistor 246 opens and closes the path between the source of the nMOS transistor 222 and the ground terminal in accordance with the enable signal xEN_Rx input to its gate. By connecting the nMOS transistors 246 in series, the voltage between the drain and source of each of the nMOS transistors 222 and 246 that are off during reception can be reduced, making it easier to lower and ensure the required breakdown voltage.

[0111] Although only the nMOS transistor 246 is inserted between the source of the nMOS transistor 222 and the ground terminal, two or more nMOS transistors may be disposed depending on the required breakdown voltage.

[0112] The nMOS transistor 246 is an example of the fourth transistor set forth in the claims.

[0113] 10 to 15 and the configurations of the other circuits (such as the switching unit 250 and the matching circuit 281) can be combined as needed. For example, the switching unit 250 in FIG. 10 can be combined with the power amplifier unit 205 in FIG. 15.

[0114] As described above, according to the fourth modification example of the present technology, the nMOS transistor 246 is disposed between the source of the nMOS transistor 222 and the ground terminal, so that the withstand voltage of the nMOS transistor 212 can be easily ensured.

[0115] <3. Application Examples> The technology disclosed herein can be applied to a technology called IoT (Internet of things), which is the so-called "Internet of Things." IoT is a system in which IoT devices 9100, which are "things," are connected to other IoT devices 9003, the Internet, the cloud 9005, etc., and mutually control each other by exchanging information. IoT can be used in various industries, such as agriculture, housing, automobiles, manufacturing, distribution, and energy.

[0116] FIG. 16 is a diagram illustrating an example of a schematic configuration of an IoT system 9000 to which the technology according to the present disclosure can be applied.

[0117] The IoT device 9001 includes various sensors such as a temperature sensor, humidity sensor, illuminance sensor, acceleration sensor, distance sensor, image sensor, gas sensor, and motion sensor. The IoT device 9001 may also include terminals such as smartphones, mobile phones, wearable devices, and game consoles. The IoT device 9001 is powered by an AC power source, a DC power source, a battery, contactless power supply, so-called energy harvesting, or the like. The IoT device 9001 can communicate via wired, wireless, or near-field wireless communication. Suitable communication methods include 3G / LTE, WiFi, IEEE802.15.4, Bluetooth, Zigbee (registered trademark), and Z-Wave. The IoT device 9001 may communicate by switching between multiple of these communication methods.

[0118] IoT devices 9001 may form one-to-one, star-shaped, tree-shaped, or mesh-shaped networks. The IoT devices 9001 may connect to an external cloud 9005 directly or through a gateway 9002. Addresses are assigned to the IoT devices 9001 using IPv4, IPv6, 6LoWPAN, or the like. Data collected from the IoT devices 9001 is transmitted to other IoT devices 9003, servers 9004, clouds 9005, or the like. The timing and frequency of data transmission from the IoT devices 9001 may be appropriately adjusted, and the data may be compressed before transmission. Such data may be used as is, or may be analyzed by a computer 9008 using various methods, such as statistical analysis, machine learning, data mining, cluster analysis, discriminant analysis, combinatorial analysis, and time series analysis. By utilizing such data, various services, such as control, warning, monitoring, visualization, automation, and optimization, can be provided.

[0119] The technology disclosed herein can also be applied to devices and services related to homes. IoT devices 9001 in homes include washing machines, dryers, microwave ovens, dishwashers, refrigerators, ovens, rice cookers, cooking appliances, gas appliances, fire alarms, thermostats, air conditioners, televisions, recorders, audio equipment, lighting equipment, water heaters, hot water heaters, vacuum cleaners, fans, air purifiers, security cameras, locks, door / shutter operating devices, sprinklers, toilets, thermometers, scales, blood pressure monitors, etc. IoT devices 9001 may also include solar cells, fuel cells, storage batteries, gas meters, power meters, and distribution boards.

[0120] A low-power communication method is desirable for the IoT device 9001 in the home. The IoT device 9001 may communicate via WiFi indoors and 3G / LTE outdoors. An external server 9006 for controlling the IoT device may be installed on the cloud 9005 to control the IoT device 9001. The IoT device 9001 transmits data such as the status of the home device, temperature, humidity, power usage, and the presence or absence of people and animals inside and outside the home. The data transmitted from the home device is stored in the external server 9006 via the cloud 9005. New services are provided based on this data. Such an IoT device 9001 can be controlled by voice using voice recognition technology.

[0121] In addition, by sending information directly from various home appliances to a television, the status of the appliances can be visualized. Furthermore, various sensors can determine whether an inhabitant is present and send data to air conditioners, lights, etc., so that their power can be turned on and off. Furthermore, advertisements can be displayed via the Internet on the displays attached to the various home appliances.

[0122] An example of an IoT system 9000 to which the technology according to the present disclosure can be applied has been described above. The technology according to the present disclosure can be suitably applied to the IoT device 9001 among the configurations described above. Specifically, the wireless communication terminal 100 in FIG. 1 can be applied to the IoT device 9001. By applying the technology according to the present disclosure to the IoT device 9001, the performance of the IoT device 9001 can be improved.

[0123] Note that the above-described embodiment shows an example for realizing the present technology, and the matters in the embodiment and the matters specifying the invention in the claims correspond to each other. Similarly, the matters specifying the invention in the claims and the matters in the embodiment of the present technology having the same name correspond to each other. However, the present technology is not limited to the embodiment, and can be realized by applying various modifications to the embodiment within the scope of the gist thereof.

[0124] The effects described in this specification are merely examples and are not limiting, and other effects may also be obtained.

[0125] The present technology can also be configured as follows. (1) a first N-type transistor whose drain is connected to the antenna and whose gate is applied with a constant voltage; a second N-type transistor whose drain is connected to the source of the first N-type transistor, whose gate receives a transmission signal, and whose source or drain supplies a reception signal; A transmission / reception switching circuit comprising: (2) a first P-type transistor; a second P-type transistor; and a third P-type transistor; and a third N-type transistor; Further comprising: the transmit signals include first and second transmit signals that are in phase; a third inverter consisting of the third P-type transistor and the third N-type transistor and a second inverter consisting of the second P-type transistor and the second N-type transistor are connected in series to a power supply terminal; the first transmission signal is input to an input terminal of the third inverter; an output terminal of the third inverter is connected to the source of the first P-type transistor; the second transmission signal is input to an input terminal of the second inverter; an output terminal of the second inverter is connected to a source of the first N-type transistor; an input terminal of a first inverter formed by the first P-type transistor and the first N-type transistor is connected to a connection node of the second and third inverters; The output terminal of the first inverter is connected to the antenna. The transmission / reception switching circuit according to (1) above. (3) a first amplifier internal capacitance inserted between the input terminal of the second inverter and the input terminal of the third inverter; The transmission / reception switching circuit according to (2) above, further comprising a second amplifier internal capacitance inserted between the output terminal of the second inverter and the output terminal of the third inverter. (4) The transmission / reception switching circuit according to (2) or (3), further comprising a DC (Direct Current) cut capacitor inserted between the output terminal of the first inverter and the antenna. (5) The transmission / reception switching circuit according to any one of (2) to (4), further comprising a matching circuit inserted between the output terminal of the first inverter and the antenna. (6) The transmission / reception switching circuit according to any one of (2) to (4), further comprising a filter circuit inserted between the output terminal of the first inverter and the antenna. (7) The transmission / reception switching circuit according to any one of (2) to (6), further comprising a switching unit that opens and closes a path between the source of the second N-type transistor and a ground terminal in accordance with a predetermined enable signal. (8) The transmission / reception switching circuit according to (7), wherein the switching unit includes a fourth transistor that opens and closes the path between the source of the second N-type transistor and the ground terminal in accordance with the enable signal. (9) The transmission / reception switching circuit described in (8) above, wherein the switching unit further includes a predetermined number of fifth transistors that open and close a path between the source of the second N-type transistor and a receiving circuit that processes the received signal in accordance with the enable signal. (10) The transmission / reception switching circuit according to (9), wherein the switching unit further includes a shunt switch that opens and closes a path between a connection node of the fifth transistor and the receiving circuit and a ground terminal in accordance with the enable signal. (11) The transmission / reception switching circuit according to (1), further comprising an inductor inserted between a power supply terminal and the drain of the first N-type transistor. (12) The transmission / reception switching circuit according to (11), further comprising a matching circuit inserted between the antenna and a connection node between the first N-type transistor and the inductor. (13) The transmission / reception switching circuit according to (11), further comprising a filter circuit inserted between the antenna and a connection node between the first N-type transistor and the inductor. (14) The transmission / reception switching circuit according to any one of (11) to (13), further comprising a predetermined number of fourth transistors that open and close a path between the source of the second N-type transistor and a ground terminal in accordance with the enable signal. (15) The transmission / reception switching circuit according to any one of (11) to (14), further comprising a switching unit that opens and closes a path between a connection node of the first and second N-type transistors and a receiving circuit that processes the received signal in accordance with a predetermined enable signal. (16) The transmission / reception switching circuit described in (15), wherein the switching unit includes a predetermined number of fifth transistors that open and close the path between the connection node of the first and second N-type transistors and the receiving circuit in accordance with the enable signal. (17) A first N-type transistor having a drain connected to the antenna and a gate to which a constant voltage is applied; a second N-type transistor whose drain is connected to the source of the first N-type transistor, whose gate receives a transmission signal, and whose source or drain supplies a reception signal; a transmission circuit for supplying the transmission signal; a receiving circuit for processing the received signal; A wireless communication terminal comprising: [Explanation of symbols]

[0126] 100 Wireless communication terminal 110 Walkie-Talkie 111 Transmitting circuit 112 receiving circuit 120 Antenna 130 Microcomputer 200 Transmit / receive switching circuit 205 Power amplifier section 210, 220, 230 inverter 211, 221, 231 pMOS transistors 212, 222, 232, 246, 251-254, 271 nMOS transistors 241, 242, 272 capacity 245 inductor 250 Switching section 261 Resistance 281 Matching circuit 282 Filter Circuit 9001 IoT devices

Claims

1. a first N-type transistor having a drain connected to the antenna and a gate to which a constant voltage is applied; a second N-type transistor whose drain is connected to the source of the first N-type transistor, whose gate receives a transmission signal, and whose source or drain supplies a reception signal; A transmission / reception switching circuit comprising:

2. a first P-type transistor; a second P-type transistor; and a third P-type transistor; and a third N-type transistor; and Further comprising: the transmit signals include first and second transmit signals that are in phase; a third inverter consisting of the third P-type transistor and the third N-type transistor and a second inverter consisting of the second P-type transistor and the second N-type transistor are connected in series to a power supply terminal; the first transmission signal is input to an input terminal of the third inverter; an output terminal of the third inverter is connected to the source of the first P-type transistor; the second transmission signal is input to an input terminal of the second inverter; an output terminal of the second inverter is connected to the source of the first N-type transistor; an input terminal of a first inverter formed by the first P-type transistor and the first N-type transistor is connected to a connection node of the second and third inverters; The output terminal of the first inverter is connected to the antenna.

2. The transmission / reception switching circuit according to claim 1.

3. a first amplifier internal capacitance inserted between the input terminal of the second inverter and the input terminal of the third inverter; 3. The transmission / reception switching circuit according to claim 2, further comprising a second amplifier internal capacitance inserted between the output terminal of said second inverter and the output terminal of said third inverter.

4. 3. The transmission / reception switching circuit according to claim 2, further comprising a DC (Direct Current) cut capacitor inserted between the output terminal of the first inverter and the antenna.

5. 3. The transmission / reception switching circuit according to claim 2, further comprising a matching circuit inserted between the output terminal of said first inverter and said antenna.

6. 3. The transmission / reception switching circuit according to claim 2, further comprising a filter circuit inserted between the output terminal of said first inverter and said antenna.

7. 3. The transmission / reception switching circuit according to claim 2, further comprising a switching section that opens and closes a path between the source of said second N-type transistor and a ground terminal in accordance with a predetermined enable signal.

8. 8. The transmission / reception switching circuit according to claim 7, wherein the switching section includes a fourth transistor that opens and closes a path between the source of the second N-type transistor and the ground terminal in accordance with the enable signal.

9. 9. The transmission / reception switching circuit according to claim 8, wherein the switching unit further comprises a predetermined number of fifth transistors that open and close a path between the source of the second N-type transistor and a receiving circuit that processes the received signal in accordance with the enable signal.

10. 10. The transmission / reception switching circuit according to claim 9, wherein the switching section further comprises a shunt switch that opens and closes a path between a connection node of the fifth transistor and the receiving circuit and a ground terminal in accordance with the enable signal.

11. 2. The transmission / reception switching circuit according to claim 1, further comprising an inductor inserted between a power supply terminal and the drain of said first N-type transistor.

12. 12. The transmission / reception switching circuit according to claim 11, further comprising a matching circuit inserted between the antenna and a connection node between the first N-type transistor and the inductor.

13. 12. The transmission / reception switching circuit according to claim 11, further comprising a filter circuit inserted between the antenna and a connection node between the first N-type transistor and the inductor.

14. 12. The transmission / reception switching circuit according to claim 11, further comprising a predetermined number of fourth transistors that open and close a path between the source of the second N-type transistor and a ground terminal in accordance with a predetermined enable signal.

15. 12. The transmission / reception switching circuit according to claim 11, further comprising a switching unit that opens and closes a path between a connection node of the first and second N-type transistors and a receiving circuit that processes the received signal in accordance with a predetermined enable signal.

16. 16. The transmission / reception switching circuit according to claim 15, wherein the switching section comprises a predetermined number of fifth transistors that open and close a path between the connection node of the first and second N-type transistors and the receiving circuit in accordance with the enable signal.

17. a first N-type transistor having a drain connected to the antenna and a gate to which a constant voltage is applied; a second N-type transistor having a drain connected to the source of the first N-type transistor, a gate to which a transmission signal is input, and a source or a drain to which a reception signal is supplied; a transmission circuit for supplying the transmission signal; a receiving circuit for processing the received signal; A wireless communication terminal comprising:

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